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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/cpufreq.h>
18#include <linux/delay.h>
19
20#include <asm/mach-types.h> /* for machine_is_* */
21
22#include "soc.h"
23
24#include <mach/hardware.h>
25#include <mach/usb.h> /* for OTG_BASE */
26
27#include "iomap.h"
28#include "clock.h"
29#include "sram.h"
30
31/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
32#define IDL_CLKOUT_ARM_SHIFT 12
33#define IDLTIM_ARM_SHIFT 9
34#define IDLAPI_ARM_SHIFT 8
35#define IDLIF_ARM_SHIFT 6
36#define IDLLB_ARM_SHIFT 4 /* undocumented? */
37#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
38#define IDLPER_ARM_SHIFT 2
39#define IDLXORP_ARM_SHIFT 1
40#define IDLWDT_ARM_SHIFT 0
41
42/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
43#define CONF_MOD_UART3_CLK_MODE_R 31
44#define CONF_MOD_UART2_CLK_MODE_R 30
45#define CONF_MOD_UART1_CLK_MODE_R 29
46#define CONF_MOD_MMC_SD_CLK_REQ_R 23
47#define CONF_MOD_MCBSP3_AUXON 20
48
49/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
50#define CONF_MOD_SOSSI_CLK_EN_R 16
51
52/* Some OTG_SYSCON_2-specific bit fields */
53#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
54
55/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
56#define SOFT_MMC2_DPLL_REQ_SHIFT 13
57#define SOFT_MMC_DPLL_REQ_SHIFT 12
58#define SOFT_UART3_DPLL_REQ_SHIFT 11
59#define SOFT_UART2_DPLL_REQ_SHIFT 10
60#define SOFT_UART1_DPLL_REQ_SHIFT 9
61#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
62#define SOFT_CAM_DPLL_REQ_SHIFT 7
63#define SOFT_COM_MCKO_REQ_SHIFT 6
64#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
65#define USB_REQ_EN_SHIFT 4
66#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
67#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
68#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
69#define SOFT_DPLL_REQ_SHIFT 0
70
71/*
72 * Omap1 clocks
73 */
74
75static struct clk ck_ref = {
76 .name = "ck_ref",
77 .ops = &clkops_null,
78 .rate = 12000000,
79};
80
81static struct clk ck_dpll1 = {
82 .name = "ck_dpll1",
83 .ops = &clkops_null,
84 .parent = &ck_ref,
85};
86
87/*
88 * FIXME: This clock seems to be necessary but no-one has asked for its
89 * activation. [ FIX: SoSSI, SSR ]
90 */
91static struct arm_idlect1_clk ck_dpll1out = {
92 .clk = {
93 .name = "ck_dpll1out",
94 .ops = &clkops_generic,
95 .parent = &ck_dpll1,
96 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
97 ENABLE_ON_INIT,
98 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
99 .enable_bit = EN_CKOUT_ARM,
100 .recalc = &followparent_recalc,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct clk sossi_ck = {
106 .name = "ck_sossi",
107 .ops = &clkops_generic,
108 .parent = &ck_dpll1out.clk,
109 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
110 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
111 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
112 .recalc = &omap1_sossi_recalc,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct clk arm_ck = {
117 .name = "arm_ck",
118 .ops = &clkops_null,
119 .parent = &ck_dpll1,
120 .rate_offset = CKCTL_ARMDIV_OFFSET,
121 .recalc = &omap1_ckctl_recalc,
122 .round_rate = omap1_clk_round_rate_ckctl_arm,
123 .set_rate = omap1_clk_set_rate_ckctl_arm,
124};
125
126static struct arm_idlect1_clk armper_ck = {
127 .clk = {
128 .name = "armper_ck",
129 .ops = &clkops_generic,
130 .parent = &ck_dpll1,
131 .flags = CLOCK_IDLE_CONTROL,
132 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
133 .enable_bit = EN_PERCK,
134 .rate_offset = CKCTL_PERDIV_OFFSET,
135 .recalc = &omap1_ckctl_recalc,
136 .round_rate = omap1_clk_round_rate_ckctl_arm,
137 .set_rate = omap1_clk_set_rate_ckctl_arm,
138 },
139 .idlect_shift = IDLPER_ARM_SHIFT,
140};
141
142/*
143 * FIXME: This clock seems to be necessary but no-one has asked for its
144 * activation. [ GPIO code for 1510 ]
145 */
146static struct clk arm_gpio_ck = {
147 .name = "ick",
148 .ops = &clkops_generic,
149 .parent = &ck_dpll1,
150 .flags = ENABLE_ON_INIT,
151 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
152 .enable_bit = EN_GPIOCK,
153 .recalc = &followparent_recalc,
154};
155
156static struct arm_idlect1_clk armxor_ck = {
157 .clk = {
158 .name = "armxor_ck",
159 .ops = &clkops_generic,
160 .parent = &ck_ref,
161 .flags = CLOCK_IDLE_CONTROL,
162 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
163 .enable_bit = EN_XORPCK,
164 .recalc = &followparent_recalc,
165 },
166 .idlect_shift = IDLXORP_ARM_SHIFT,
167};
168
169static struct arm_idlect1_clk armtim_ck = {
170 .clk = {
171 .name = "armtim_ck",
172 .ops = &clkops_generic,
173 .parent = &ck_ref,
174 .flags = CLOCK_IDLE_CONTROL,
175 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
176 .enable_bit = EN_TIMCK,
177 .recalc = &followparent_recalc,
178 },
179 .idlect_shift = IDLTIM_ARM_SHIFT,
180};
181
182static struct arm_idlect1_clk armwdt_ck = {
183 .clk = {
184 .name = "armwdt_ck",
185 .ops = &clkops_generic,
186 .parent = &ck_ref,
187 .flags = CLOCK_IDLE_CONTROL,
188 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
189 .enable_bit = EN_WDTCK,
190 .fixed_div = 14,
191 .recalc = &omap_fixed_divisor_recalc,
192 },
193 .idlect_shift = IDLWDT_ARM_SHIFT,
194};
195
196static struct clk arminth_ck16xx = {
197 .name = "arminth_ck",
198 .ops = &clkops_null,
199 .parent = &arm_ck,
200 .recalc = &followparent_recalc,
201 /* Note: On 16xx the frequency can be divided by 2 by programming
202 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
203 *
204 * 1510 version is in TC clocks.
205 */
206};
207
208static struct clk dsp_ck = {
209 .name = "dsp_ck",
210 .ops = &clkops_generic,
211 .parent = &ck_dpll1,
212 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
213 .enable_bit = EN_DSPCK,
214 .rate_offset = CKCTL_DSPDIV_OFFSET,
215 .recalc = &omap1_ckctl_recalc,
216 .round_rate = omap1_clk_round_rate_ckctl_arm,
217 .set_rate = omap1_clk_set_rate_ckctl_arm,
218};
219
220static struct clk dspmmu_ck = {
221 .name = "dspmmu_ck",
222 .ops = &clkops_null,
223 .parent = &ck_dpll1,
224 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
225 .recalc = &omap1_ckctl_recalc,
226 .round_rate = omap1_clk_round_rate_ckctl_arm,
227 .set_rate = omap1_clk_set_rate_ckctl_arm,
228};
229
230static struct clk dspper_ck = {
231 .name = "dspper_ck",
232 .ops = &clkops_dspck,
233 .parent = &ck_dpll1,
234 .enable_reg = DSP_IDLECT2,
235 .enable_bit = EN_PERCK,
236 .rate_offset = CKCTL_PERDIV_OFFSET,
237 .recalc = &omap1_ckctl_recalc_dsp_domain,
238 .round_rate = omap1_clk_round_rate_ckctl_arm,
239 .set_rate = &omap1_clk_set_rate_dsp_domain,
240};
241
242static struct clk dspxor_ck = {
243 .name = "dspxor_ck",
244 .ops = &clkops_dspck,
245 .parent = &ck_ref,
246 .enable_reg = DSP_IDLECT2,
247 .enable_bit = EN_XORPCK,
248 .recalc = &followparent_recalc,
249};
250
251static struct clk dsptim_ck = {
252 .name = "dsptim_ck",
253 .ops = &clkops_dspck,
254 .parent = &ck_ref,
255 .enable_reg = DSP_IDLECT2,
256 .enable_bit = EN_DSPTIMCK,
257 .recalc = &followparent_recalc,
258};
259
260static struct arm_idlect1_clk tc_ck = {
261 .clk = {
262 .name = "tc_ck",
263 .ops = &clkops_null,
264 .parent = &ck_dpll1,
265 .flags = CLOCK_IDLE_CONTROL,
266 .rate_offset = CKCTL_TCDIV_OFFSET,
267 .recalc = &omap1_ckctl_recalc,
268 .round_rate = omap1_clk_round_rate_ckctl_arm,
269 .set_rate = omap1_clk_set_rate_ckctl_arm,
270 },
271 .idlect_shift = IDLIF_ARM_SHIFT,
272};
273
274static struct clk arminth_ck1510 = {
275 .name = "arminth_ck",
276 .ops = &clkops_null,
277 .parent = &tc_ck.clk,
278 .recalc = &followparent_recalc,
279 /* Note: On 1510 the frequency follows TC_CK
280 *
281 * 16xx version is in MPU clocks.
282 */
283};
284
285static struct clk tipb_ck = {
286 /* No-idle controlled by "tc_ck" */
287 .name = "tipb_ck",
288 .ops = &clkops_null,
289 .parent = &tc_ck.clk,
290 .recalc = &followparent_recalc,
291};
292
293static struct clk l3_ocpi_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .name = "l3_ocpi_ck",
296 .ops = &clkops_generic,
297 .parent = &tc_ck.clk,
298 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
299 .enable_bit = EN_OCPI_CK,
300 .recalc = &followparent_recalc,
301};
302
303static struct clk tc1_ck = {
304 .name = "tc1_ck",
305 .ops = &clkops_generic,
306 .parent = &tc_ck.clk,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
308 .enable_bit = EN_TC1_CK,
309 .recalc = &followparent_recalc,
310};
311
312/*
313 * FIXME: This clock seems to be necessary but no-one has asked for its
314 * activation. [ pm.c (SRAM), CCP, Camera ]
315 */
316static struct clk tc2_ck = {
317 .name = "tc2_ck",
318 .ops = &clkops_generic,
319 .parent = &tc_ck.clk,
320 .flags = ENABLE_ON_INIT,
321 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
322 .enable_bit = EN_TC2_CK,
323 .recalc = &followparent_recalc,
324};
325
326static struct clk dma_ck = {
327 /* No-idle controlled by "tc_ck" */
328 .name = "dma_ck",
329 .ops = &clkops_null,
330 .parent = &tc_ck.clk,
331 .recalc = &followparent_recalc,
332};
333
334static struct clk dma_lcdfree_ck = {
335 .name = "dma_lcdfree_ck",
336 .ops = &clkops_null,
337 .parent = &tc_ck.clk,
338 .recalc = &followparent_recalc,
339};
340
341static struct arm_idlect1_clk api_ck = {
342 .clk = {
343 .name = "api_ck",
344 .ops = &clkops_generic,
345 .parent = &tc_ck.clk,
346 .flags = CLOCK_IDLE_CONTROL,
347 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
348 .enable_bit = EN_APICK,
349 .recalc = &followparent_recalc,
350 },
351 .idlect_shift = IDLAPI_ARM_SHIFT,
352};
353
354static struct arm_idlect1_clk lb_ck = {
355 .clk = {
356 .name = "lb_ck",
357 .ops = &clkops_generic,
358 .parent = &tc_ck.clk,
359 .flags = CLOCK_IDLE_CONTROL,
360 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
361 .enable_bit = EN_LBCK,
362 .recalc = &followparent_recalc,
363 },
364 .idlect_shift = IDLLB_ARM_SHIFT,
365};
366
367static struct clk rhea1_ck = {
368 .name = "rhea1_ck",
369 .ops = &clkops_null,
370 .parent = &tc_ck.clk,
371 .recalc = &followparent_recalc,
372};
373
374static struct clk rhea2_ck = {
375 .name = "rhea2_ck",
376 .ops = &clkops_null,
377 .parent = &tc_ck.clk,
378 .recalc = &followparent_recalc,
379};
380
381static struct clk lcd_ck_16xx = {
382 .name = "lcd_ck",
383 .ops = &clkops_generic,
384 .parent = &ck_dpll1,
385 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
386 .enable_bit = EN_LCDCK,
387 .rate_offset = CKCTL_LCDDIV_OFFSET,
388 .recalc = &omap1_ckctl_recalc,
389 .round_rate = omap1_clk_round_rate_ckctl_arm,
390 .set_rate = omap1_clk_set_rate_ckctl_arm,
391};
392
393static struct arm_idlect1_clk lcd_ck_1510 = {
394 .clk = {
395 .name = "lcd_ck",
396 .ops = &clkops_generic,
397 .parent = &ck_dpll1,
398 .flags = CLOCK_IDLE_CONTROL,
399 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
400 .enable_bit = EN_LCDCK,
401 .rate_offset = CKCTL_LCDDIV_OFFSET,
402 .recalc = &omap1_ckctl_recalc,
403 .round_rate = omap1_clk_round_rate_ckctl_arm,
404 .set_rate = omap1_clk_set_rate_ckctl_arm,
405 },
406 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
407};
408
409/*
410 * XXX The enable_bit here is misused - it simply switches between 12MHz
411 * and 48MHz. Reimplement with clksel.
412 *
413 * XXX does this need SYSC register handling?
414 */
415static struct clk uart1_1510 = {
416 .name = "uart1_ck",
417 .ops = &clkops_null,
418 /* Direct from ULPD, no real parent */
419 .parent = &armper_ck.clk,
420 .rate = 12000000,
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
424 .set_rate = &omap1_set_uart_rate,
425 .recalc = &omap1_uart_recalc,
426};
427
428/*
429 * XXX The enable_bit here is misused - it simply switches between 12MHz
430 * and 48MHz. Reimplement with clksel.
431 *
432 * XXX SYSC register handling does not belong in the clock framework
433 */
434static struct uart_clk uart1_16xx = {
435 .clk = {
436 .name = "uart1_ck",
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .parent = &armper_ck.clk,
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb0054,
446};
447
448/*
449 * XXX The enable_bit here is misused - it simply switches between 12MHz
450 * and 48MHz. Reimplement with clksel.
451 *
452 * XXX does this need SYSC register handling?
453 */
454static struct clk uart2_ck = {
455 .name = "uart2_ck",
456 .ops = &clkops_null,
457 /* Direct from ULPD, no real parent */
458 .parent = &armper_ck.clk,
459 .rate = 12000000,
460 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
461 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
462 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
463 .set_rate = &omap1_set_uart_rate,
464 .recalc = &omap1_uart_recalc,
465};
466
467/*
468 * XXX The enable_bit here is misused - it simply switches between 12MHz
469 * and 48MHz. Reimplement with clksel.
470 *
471 * XXX does this need SYSC register handling?
472 */
473static struct clk uart3_1510 = {
474 .name = "uart3_ck",
475 .ops = &clkops_null,
476 /* Direct from ULPD, no real parent */
477 .parent = &armper_ck.clk,
478 .rate = 12000000,
479 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
480 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
481 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
482 .set_rate = &omap1_set_uart_rate,
483 .recalc = &omap1_uart_recalc,
484};
485
486/*
487 * XXX The enable_bit here is misused - it simply switches between 12MHz
488 * and 48MHz. Reimplement with clksel.
489 *
490 * XXX SYSC register handling does not belong in the clock framework
491 */
492static struct uart_clk uart3_16xx = {
493 .clk = {
494 .name = "uart3_ck",
495 .ops = &clkops_uart_16xx,
496 /* Direct from ULPD, no real parent */
497 .parent = &armper_ck.clk,
498 .rate = 48000000,
499 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
500 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
501 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
502 },
503 .sysc_addr = 0xfffb9854,
504};
505
506static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
507 .name = "usb_clko",
508 .ops = &clkops_generic,
509 /* Direct from ULPD, no parent */
510 .rate = 6000000,
511 .flags = ENABLE_REG_32BIT,
512 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
513 .enable_bit = USB_MCLK_EN_BIT,
514};
515
516static struct clk usb_hhc_ck1510 = {
517 .name = "usb_hhc_ck",
518 .ops = &clkops_generic,
519 /* Direct from ULPD, no parent */
520 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
521 .flags = ENABLE_REG_32BIT,
522 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
523 .enable_bit = USB_HOST_HHC_UHOST_EN,
524};
525
526static struct clk usb_hhc_ck16xx = {
527 .name = "usb_hhc_ck",
528 .ops = &clkops_generic,
529 /* Direct from ULPD, no parent */
530 .rate = 48000000,
531 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
532 .flags = ENABLE_REG_32BIT,
533 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
534 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
535};
536
537static struct clk usb_dc_ck = {
538 .name = "usb_dc_ck",
539 .ops = &clkops_generic,
540 /* Direct from ULPD, no parent */
541 .rate = 48000000,
542 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
543 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
544};
545
546static struct clk uart1_7xx = {
547 .name = "uart1_ck",
548 .ops = &clkops_generic,
549 /* Direct from ULPD, no parent */
550 .rate = 12000000,
551 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
552 .enable_bit = 9,
553};
554
555static struct clk uart2_7xx = {
556 .name = "uart2_ck",
557 .ops = &clkops_generic,
558 /* Direct from ULPD, no parent */
559 .rate = 12000000,
560 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
561 .enable_bit = 11,
562};
563
564static struct clk mclk_1510 = {
565 .name = "mclk",
566 .ops = &clkops_generic,
567 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
568 .rate = 12000000,
569 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
570 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
571};
572
573static struct clk mclk_16xx = {
574 .name = "mclk",
575 .ops = &clkops_generic,
576 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
577 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
578 .enable_bit = COM_ULPD_PLL_CLK_REQ,
579 .set_rate = &omap1_set_ext_clk_rate,
580 .round_rate = &omap1_round_ext_clk_rate,
581 .init = &omap1_init_ext_clk,
582};
583
584static struct clk bclk_1510 = {
585 .name = "bclk",
586 .ops = &clkops_generic,
587 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
588 .rate = 12000000,
589};
590
591static struct clk bclk_16xx = {
592 .name = "bclk",
593 .ops = &clkops_generic,
594 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
595 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
596 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
597 .set_rate = &omap1_set_ext_clk_rate,
598 .round_rate = &omap1_round_ext_clk_rate,
599 .init = &omap1_init_ext_clk,
600};
601
602static struct clk mmc1_ck = {
603 .name = "mmc1_ck",
604 .ops = &clkops_generic,
605 /* Functional clock is direct from ULPD, interface clock is ARMPER */
606 .parent = &armper_ck.clk,
607 .rate = 48000000,
608 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
609 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
610 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
611};
612
613/*
614 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
615 * CONF_MOD_MCBSP3_AUXON ??
616 */
617static struct clk mmc2_ck = {
618 .name = "mmc2_ck",
619 .ops = &clkops_generic,
620 /* Functional clock is direct from ULPD, interface clock is ARMPER */
621 .parent = &armper_ck.clk,
622 .rate = 48000000,
623 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
624 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
625 .enable_bit = 20,
626};
627
628static struct clk mmc3_ck = {
629 .name = "mmc3_ck",
630 .ops = &clkops_generic,
631 /* Functional clock is direct from ULPD, interface clock is ARMPER */
632 .parent = &armper_ck.clk,
633 .rate = 48000000,
634 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
635 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
636 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
637};
638
639static struct clk virtual_ck_mpu = {
640 .name = "mpu",
641 .ops = &clkops_null,
642 .parent = &arm_ck, /* Is smarter alias for */
643 .recalc = &followparent_recalc,
644 .set_rate = &omap1_select_table_rate,
645 .round_rate = &omap1_round_to_table_rate,
646};
647
648/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
649remains active during MPU idle whenever this is enabled */
650static struct clk i2c_fck = {
651 .name = "i2c_fck",
652 .ops = &clkops_null,
653 .flags = CLOCK_NO_IDLE_PARENT,
654 .parent = &armxor_ck.clk,
655 .recalc = &followparent_recalc,
656};
657
658static struct clk i2c_ick = {
659 .name = "i2c_ick",
660 .ops = &clkops_null,
661 .flags = CLOCK_NO_IDLE_PARENT,
662 .parent = &armper_ck.clk,
663 .recalc = &followparent_recalc,
664};
665
666/*
667 * clkdev integration
668 */
669
670static struct omap_clk omap_clks[] = {
671 /* non-ULPD clocks */
672 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
673 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
674 /* CK_GEN1 clocks */
675 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
676 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
677 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
678 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
679 CLK("omap_gpio.0", "ick", &arm_gpio_ck, CK_1510 | CK_310),
680 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
681 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
682 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
683 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
684 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
685 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
686 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
687 /* CK_GEN2 clocks */
688 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
689 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
690 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
691 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
692 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
693 /* CK_GEN3 clocks */
694 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
695 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
696 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
697 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
698 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
699 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
700 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
701 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
702 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
703 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
704 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
705 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
706 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
707 /* ULPD clocks */
708 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
709 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
710 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
711 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
712 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
713 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
714 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
715 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
716 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
717 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
718 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX | CK_7XX),
719 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
720 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
721 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
722 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
723 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
724 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
725 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
726 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
727 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
728 /* Virtual clocks */
729 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
730 CLK("omap_i2c.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
731 CLK("omap_i2c.1", "ick", &i2c_ick, CK_16XX),
732 CLK("omap_i2c.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
733 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
734 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
735 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
736 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
737 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
738 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
739 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
740 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
741 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
742 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
743 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
744 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
745 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
746 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
747};
748
749/*
750 * init
751 */
752
753static void __init omap1_show_rates(void)
754{
755 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
756 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
757 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
758 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
759}
760
761u32 cpu_mask;
762
763int __init omap1_clk_init(void)
764{
765 struct omap_clk *c;
766 int crystal_type = 0; /* Default 12 MHz */
767 u32 reg;
768
769#ifdef CONFIG_DEBUG_LL
770 /*
771 * Resets some clocks that may be left on from bootloader,
772 * but leaves serial clocks on.
773 */
774 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
775#endif
776
777 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
778 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
779 omap_writew(reg, SOFT_REQ_REG);
780 if (!cpu_is_omap15xx())
781 omap_writew(0, SOFT_REQ_REG2);
782
783 /* By default all idlect1 clocks are allowed to idle */
784 arm_idlect1_mask = ~0;
785
786 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
787 clk_preinit(c->lk.clk);
788
789 cpu_mask = 0;
790 if (cpu_is_omap1710())
791 cpu_mask |= CK_1710;
792 if (cpu_is_omap16xx())
793 cpu_mask |= CK_16XX;
794 if (cpu_is_omap1510())
795 cpu_mask |= CK_1510;
796 if (cpu_is_omap7xx())
797 cpu_mask |= CK_7XX;
798 if (cpu_is_omap310())
799 cpu_mask |= CK_310;
800
801 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
802 if (c->cpu & cpu_mask) {
803 clkdev_add(&c->lk);
804 clk_register(c->lk.clk);
805 }
806
807 /* Pointers to these clocks are needed by code in clock.c */
808 api_ck_p = clk_get(NULL, "api_ck");
809 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
810 ck_ref_p = clk_get(NULL, "ck_ref");
811
812 if (cpu_is_omap7xx())
813 ck_ref.rate = 13000000;
814 if (cpu_is_omap16xx() && crystal_type == 2)
815 ck_ref.rate = 19200000;
816
817 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
818 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
819 omap_readw(ARM_CKCTL));
820
821 /* We want to be in syncronous scalable mode */
822 omap_writew(0x1000, ARM_SYSST);
823
824
825 /*
826 * Initially use the values set by bootloader. Determine PLL rate and
827 * recalculate dependent clocks as if kernel had changed PLL or
828 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
829 * after the SRAM is initialized.
830 */
831 {
832 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
833
834 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
835 if (pll_ctl_val & 0x10) {
836 /* PLL enabled, apply multiplier and divisor */
837 if (pll_ctl_val & 0xf80)
838 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
839 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
840 } else {
841 /* PLL disabled, apply bypass divisor */
842 switch (pll_ctl_val & 0xc) {
843 case 0:
844 break;
845 case 0x4:
846 ck_dpll1.rate /= 2;
847 break;
848 default:
849 ck_dpll1.rate /= 4;
850 break;
851 }
852 }
853 }
854 propagate_rate(&ck_dpll1);
855 /* Cache rates for clocks connected to ck_ref (not dpll1) */
856 propagate_rate(&ck_ref);
857 omap1_show_rates();
858 if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
859 /* Select slicer output as OMAP input clock */
860 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1,
861 OMAP7XX_PCC_UPLD_CTRL);
862 }
863
864 /* Amstrad Delta wants BCLK high when inactive */
865 if (machine_is_ams_delta())
866 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
867 (1 << SDW_MCLK_INV_BIT),
868 ULPD_CLOCK_CTRL);
869
870 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
871 /* (on 730, bit 13 must not be cleared) */
872 if (cpu_is_omap7xx())
873 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
874 else
875 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
876
877 /* Put DSP/MPUI into reset until needed */
878 omap_writew(0, ARM_RSTCT1);
879 omap_writew(1, ARM_RSTCT2);
880 omap_writew(0x400, ARM_IDLECT1);
881
882 /*
883 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
884 * of the ARM_IDLECT2 register must be set to zero. The power-on
885 * default value of this bit is one.
886 */
887 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
888
889 /*
890 * Only enable those clocks we will need, let the drivers
891 * enable other clocks as necessary
892 */
893 clk_enable(&armper_ck.clk);
894 clk_enable(&armxor_ck.clk);
895 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
896
897 if (cpu_is_omap15xx())
898 clk_enable(&arm_gpio_ck);
899
900 return 0;
901}
902
903#define OMAP1_DPLL1_SANE_VALUE 60000000
904
905void __init omap1_clk_late_init(void)
906{
907 unsigned long rate = ck_dpll1.rate;
908
909 /* Find the highest supported frequency and enable it */
910 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
911 pr_err("System frequencies not set, using default. Check your config.\n");
912 /*
913 * Reprogramming the DPLL is tricky, it must be done from SRAM.
914 */
915 omap_sram_reprogram_clock(0x2290, 0x0005);
916 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
917 }
918 propagate_rate(&ck_dpll1);
919 omap1_show_rates();
920 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
921}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/arch/arm/mach-omap1/clock_data.c
4 *
5 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
6 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
7 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 *
9 * To do:
10 * - Clocks that are only available on some chips should be marked with the
11 * chips that they are present on.
12 */
13
14#include <linux/kernel.h>
15#include <linux/io.h>
16#include <linux/clk.h>
17#include <linux/clkdev.h>
18#include <linux/clk-provider.h>
19#include <linux/cpufreq.h>
20#include <linux/delay.h>
21#include <linux/soc/ti/omap1-io.h>
22
23#include <asm/mach-types.h> /* for machine_is_* */
24
25#include "soc.h"
26#include "hardware.h"
27#include "usb.h" /* for OTG_BASE */
28#include "iomap.h"
29#include "clock.h"
30#include "sram.h"
31
32/* Some ARM_IDLECT1 bit shifts - used in struct arm_idlect1_clk */
33#define IDL_CLKOUT_ARM_SHIFT 12
34#define IDLTIM_ARM_SHIFT 9
35#define IDLAPI_ARM_SHIFT 8
36#define IDLIF_ARM_SHIFT 6
37#define IDLLB_ARM_SHIFT 4 /* undocumented? */
38#define OMAP1510_IDLLCD_ARM_SHIFT 3 /* undocumented? */
39#define IDLPER_ARM_SHIFT 2
40#define IDLXORP_ARM_SHIFT 1
41#define IDLWDT_ARM_SHIFT 0
42
43/* Some MOD_CONF_CTRL_0 bit shifts - used in struct clk.enable_bit */
44#define CONF_MOD_UART3_CLK_MODE_R 31
45#define CONF_MOD_UART2_CLK_MODE_R 30
46#define CONF_MOD_UART1_CLK_MODE_R 29
47#define CONF_MOD_MMC_SD_CLK_REQ_R 23
48#define CONF_MOD_MCBSP3_AUXON 20
49
50/* Some MOD_CONF_CTRL_1 bit shifts - used in struct clk.enable_bit */
51#define CONF_MOD_SOSSI_CLK_EN_R 16
52
53/* Some OTG_SYSCON_2-specific bit fields */
54#define OTG_SYSCON_2_UHOST_EN_SHIFT 8
55
56/* Some SOFT_REQ_REG bit fields - used in struct clk.enable_bit */
57#define SOFT_MMC2_DPLL_REQ_SHIFT 13
58#define SOFT_MMC_DPLL_REQ_SHIFT 12
59#define SOFT_UART3_DPLL_REQ_SHIFT 11
60#define SOFT_UART2_DPLL_REQ_SHIFT 10
61#define SOFT_UART1_DPLL_REQ_SHIFT 9
62#define SOFT_USB_OTG_DPLL_REQ_SHIFT 8
63#define SOFT_CAM_DPLL_REQ_SHIFT 7
64#define SOFT_COM_MCKO_REQ_SHIFT 6
65#define SOFT_PERIPH_REQ_SHIFT 5 /* sys_ck gate for UART2 ? */
66#define USB_REQ_EN_SHIFT 4
67#define SOFT_USB_REQ_SHIFT 3 /* sys_ck gate for USB host? */
68#define SOFT_SDW_REQ_SHIFT 2 /* sys_ck gate for Bluetooth? */
69#define SOFT_COM_REQ_SHIFT 1 /* sys_ck gate for com proc? */
70#define SOFT_DPLL_REQ_SHIFT 0
71
72/*
73 * Omap1 clocks
74 */
75
76static struct omap1_clk ck_ref = {
77 .hw.init = CLK_HW_INIT_NO_PARENT("ck_ref", &omap1_clk_rate_ops, 0),
78 .rate = 12000000,
79};
80
81static struct omap1_clk ck_dpll1 = {
82 .hw.init = CLK_HW_INIT("ck_dpll1", "ck_ref", &omap1_clk_rate_ops,
83 /*
84 * force recursive refresh of rates of the clock
85 * and its children when clk_get_rate() is called
86 */
87 CLK_GET_RATE_NOCACHE),
88};
89
90/*
91 * FIXME: This clock seems to be necessary but no-one has asked for its
92 * activation. [ FIX: SoSSI, SSR ]
93 */
94static struct arm_idlect1_clk ck_dpll1out = {
95 .clk = {
96 .hw.init = CLK_HW_INIT("ck_dpll1out", "ck_dpll1", &omap1_clk_gate_ops, 0),
97 .ops = &clkops_generic,
98 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT,
99 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
100 .enable_bit = EN_CKOUT_ARM,
101 },
102 .idlect_shift = IDL_CLKOUT_ARM_SHIFT,
103};
104
105static struct omap1_clk sossi_ck = {
106 .hw.init = CLK_HW_INIT("ck_sossi", "ck_dpll1out", &omap1_clk_full_ops, 0),
107 .ops = &clkops_generic,
108 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
109 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
111 .recalc = &omap1_sossi_recalc,
112 .round_rate = &omap1_round_sossi_rate,
113 .set_rate = &omap1_set_sossi_rate,
114};
115
116static struct omap1_clk arm_ck = {
117 .hw.init = CLK_HW_INIT("arm_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
118 .rate_offset = CKCTL_ARMDIV_OFFSET,
119 .recalc = &omap1_ckctl_recalc,
120 .round_rate = omap1_clk_round_rate_ckctl_arm,
121 .set_rate = omap1_clk_set_rate_ckctl_arm,
122};
123
124static struct arm_idlect1_clk armper_ck = {
125 .clk = {
126 .hw.init = CLK_HW_INIT("armper_ck", "ck_dpll1", &omap1_clk_full_ops,
127 CLK_IS_CRITICAL),
128 .ops = &clkops_generic,
129 .flags = CLOCK_IDLE_CONTROL,
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
131 .enable_bit = EN_PERCK,
132 .rate_offset = CKCTL_PERDIV_OFFSET,
133 .recalc = &omap1_ckctl_recalc,
134 .round_rate = omap1_clk_round_rate_ckctl_arm,
135 .set_rate = omap1_clk_set_rate_ckctl_arm,
136 },
137 .idlect_shift = IDLPER_ARM_SHIFT,
138};
139
140/*
141 * FIXME: This clock seems to be necessary but no-one has asked for its
142 * activation. [ GPIO code for 1510 ]
143 */
144static struct omap1_clk arm_gpio_ck = {
145 .hw.init = CLK_HW_INIT("ick", "ck_dpll1", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
146 .ops = &clkops_generic,
147 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
148 .enable_bit = EN_GPIOCK,
149};
150
151static struct arm_idlect1_clk armxor_ck = {
152 .clk = {
153 .hw.init = CLK_HW_INIT("armxor_ck", "ck_ref", &omap1_clk_gate_ops,
154 CLK_IS_CRITICAL),
155 .ops = &clkops_generic,
156 .flags = CLOCK_IDLE_CONTROL,
157 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
158 .enable_bit = EN_XORPCK,
159 },
160 .idlect_shift = IDLXORP_ARM_SHIFT,
161};
162
163static struct arm_idlect1_clk armtim_ck = {
164 .clk = {
165 .hw.init = CLK_HW_INIT("armtim_ck", "ck_ref", &omap1_clk_gate_ops,
166 CLK_IS_CRITICAL),
167 .ops = &clkops_generic,
168 .flags = CLOCK_IDLE_CONTROL,
169 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
170 .enable_bit = EN_TIMCK,
171 },
172 .idlect_shift = IDLTIM_ARM_SHIFT,
173};
174
175static struct arm_idlect1_clk armwdt_ck = {
176 .clk = {
177 .hw.init = CLK_HW_INIT("armwdt_ck", "ck_ref", &omap1_clk_full_ops, 0),
178 .ops = &clkops_generic,
179 .flags = CLOCK_IDLE_CONTROL,
180 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
181 .enable_bit = EN_WDTCK,
182 .fixed_div = 14,
183 .recalc = &omap_fixed_divisor_recalc,
184 },
185 .idlect_shift = IDLWDT_ARM_SHIFT,
186};
187
188static struct omap1_clk arminth_ck16xx = {
189 .hw.init = CLK_HW_INIT("arminth_ck", "arm_ck", &omap1_clk_null_ops, 0),
190 /* Note: On 16xx the frequency can be divided by 2 by programming
191 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
192 *
193 * 1510 version is in TC clocks.
194 */
195};
196
197static struct omap1_clk dsp_ck = {
198 .hw.init = CLK_HW_INIT("dsp_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
199 .ops = &clkops_generic,
200 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
201 .enable_bit = EN_DSPCK,
202 .rate_offset = CKCTL_DSPDIV_OFFSET,
203 .recalc = &omap1_ckctl_recalc,
204 .round_rate = omap1_clk_round_rate_ckctl_arm,
205 .set_rate = omap1_clk_set_rate_ckctl_arm,
206};
207
208static struct omap1_clk dspmmu_ck = {
209 .hw.init = CLK_HW_INIT("dspmmu_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
210 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
211 .recalc = &omap1_ckctl_recalc,
212 .round_rate = omap1_clk_round_rate_ckctl_arm,
213 .set_rate = omap1_clk_set_rate_ckctl_arm,
214};
215
216static struct omap1_clk dspper_ck = {
217 .hw.init = CLK_HW_INIT("dspper_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
218 .ops = &clkops_dspck,
219 .enable_reg = DSP_IDLECT2,
220 .enable_bit = EN_PERCK,
221 .rate_offset = CKCTL_PERDIV_OFFSET,
222 .recalc = &omap1_ckctl_recalc_dsp_domain,
223 .round_rate = omap1_clk_round_rate_ckctl_arm,
224 .set_rate = &omap1_clk_set_rate_dsp_domain,
225};
226
227static struct omap1_clk dspxor_ck = {
228 .hw.init = CLK_HW_INIT("dspxor_ck", "ck_ref", &omap1_clk_gate_ops, 0),
229 .ops = &clkops_dspck,
230 .enable_reg = DSP_IDLECT2,
231 .enable_bit = EN_XORPCK,
232};
233
234static struct omap1_clk dsptim_ck = {
235 .hw.init = CLK_HW_INIT("dsptim_ck", "ck_ref", &omap1_clk_gate_ops, 0),
236 .ops = &clkops_dspck,
237 .enable_reg = DSP_IDLECT2,
238 .enable_bit = EN_DSPTIMCK,
239};
240
241static struct arm_idlect1_clk tc_ck = {
242 .clk = {
243 .hw.init = CLK_HW_INIT("tc_ck", "ck_dpll1", &omap1_clk_rate_ops, 0),
244 .flags = CLOCK_IDLE_CONTROL,
245 .rate_offset = CKCTL_TCDIV_OFFSET,
246 .recalc = &omap1_ckctl_recalc,
247 .round_rate = omap1_clk_round_rate_ckctl_arm,
248 .set_rate = omap1_clk_set_rate_ckctl_arm,
249 },
250 .idlect_shift = IDLIF_ARM_SHIFT,
251};
252
253static struct omap1_clk arminth_ck1510 = {
254 .hw.init = CLK_HW_INIT("arminth_ck", "tc_ck", &omap1_clk_null_ops, 0),
255 /* Note: On 1510 the frequency follows TC_CK
256 *
257 * 16xx version is in MPU clocks.
258 */
259};
260
261static struct omap1_clk tipb_ck = {
262 /* No-idle controlled by "tc_ck" */
263 .hw.init = CLK_HW_INIT("tipb_ck", "tc_ck", &omap1_clk_null_ops, 0),
264};
265
266static struct omap1_clk l3_ocpi_ck = {
267 /* No-idle controlled by "tc_ck" */
268 .hw.init = CLK_HW_INIT("l3_ocpi_ck", "tc_ck", &omap1_clk_gate_ops, 0),
269 .ops = &clkops_generic,
270 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
271 .enable_bit = EN_OCPI_CK,
272};
273
274static struct omap1_clk tc1_ck = {
275 .hw.init = CLK_HW_INIT("tc1_ck", "tc_ck", &omap1_clk_gate_ops, 0),
276 .ops = &clkops_generic,
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
278 .enable_bit = EN_TC1_CK,
279};
280
281/*
282 * FIXME: This clock seems to be necessary but no-one has asked for its
283 * activation. [ pm.c (SRAM), CCP, Camera ]
284 */
285
286static struct omap1_clk tc2_ck = {
287 .hw.init = CLK_HW_INIT("tc2_ck", "tc_ck", &omap1_clk_gate_ops, CLK_IS_CRITICAL),
288 .ops = &clkops_generic,
289 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
290 .enable_bit = EN_TC2_CK,
291};
292
293static struct omap1_clk dma_ck = {
294 /* No-idle controlled by "tc_ck" */
295 .hw.init = CLK_HW_INIT("dma_ck", "tc_ck", &omap1_clk_null_ops, 0),
296};
297
298static struct omap1_clk dma_lcdfree_ck = {
299 .hw.init = CLK_HW_INIT("dma_lcdfree_ck", "tc_ck", &omap1_clk_null_ops, 0),
300};
301
302static struct arm_idlect1_clk api_ck = {
303 .clk = {
304 .hw.init = CLK_HW_INIT("api_ck", "tc_ck", &omap1_clk_gate_ops, 0),
305 .ops = &clkops_generic,
306 .flags = CLOCK_IDLE_CONTROL,
307 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
308 .enable_bit = EN_APICK,
309 },
310 .idlect_shift = IDLAPI_ARM_SHIFT,
311};
312
313static struct arm_idlect1_clk lb_ck = {
314 .clk = {
315 .hw.init = CLK_HW_INIT("lb_ck", "tc_ck", &omap1_clk_gate_ops, 0),
316 .ops = &clkops_generic,
317 .flags = CLOCK_IDLE_CONTROL,
318 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
319 .enable_bit = EN_LBCK,
320 },
321 .idlect_shift = IDLLB_ARM_SHIFT,
322};
323
324static struct omap1_clk rhea1_ck = {
325 .hw.init = CLK_HW_INIT("rhea1_ck", "tc_ck", &omap1_clk_null_ops, 0),
326};
327
328static struct omap1_clk rhea2_ck = {
329 .hw.init = CLK_HW_INIT("rhea2_ck", "tc_ck", &omap1_clk_null_ops, 0),
330};
331
332static struct omap1_clk lcd_ck_16xx = {
333 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
334 .ops = &clkops_generic,
335 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
336 .enable_bit = EN_LCDCK,
337 .rate_offset = CKCTL_LCDDIV_OFFSET,
338 .recalc = &omap1_ckctl_recalc,
339 .round_rate = omap1_clk_round_rate_ckctl_arm,
340 .set_rate = omap1_clk_set_rate_ckctl_arm,
341};
342
343static struct arm_idlect1_clk lcd_ck_1510 = {
344 .clk = {
345 .hw.init = CLK_HW_INIT("lcd_ck", "ck_dpll1", &omap1_clk_full_ops, 0),
346 .ops = &clkops_generic,
347 .flags = CLOCK_IDLE_CONTROL,
348 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
349 .enable_bit = EN_LCDCK,
350 .rate_offset = CKCTL_LCDDIV_OFFSET,
351 .recalc = &omap1_ckctl_recalc,
352 .round_rate = omap1_clk_round_rate_ckctl_arm,
353 .set_rate = omap1_clk_set_rate_ckctl_arm,
354 },
355 .idlect_shift = OMAP1510_IDLLCD_ARM_SHIFT,
356};
357
358
359/*
360 * XXX The enable_bit here is misused - it simply switches between 12MHz
361 * and 48MHz. Reimplement with clk_mux.
362 *
363 * XXX does this need SYSC register handling?
364 */
365static struct omap1_clk uart1_1510 = {
366 /* Direct from ULPD, no real parent */
367 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
368 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
369 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
370 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
371 .round_rate = &omap1_round_uart_rate,
372 .set_rate = &omap1_set_uart_rate,
373 .recalc = &omap1_uart_recalc,
374};
375
376/*
377 * XXX The enable_bit here is misused - it simply switches between 12MHz
378 * and 48MHz. Reimplement with clk_mux.
379 *
380 * XXX SYSC register handling does not belong in the clock framework
381 */
382static struct uart_clk uart1_16xx = {
383 .clk = {
384 .ops = &clkops_uart_16xx,
385 /* Direct from ULPD, no real parent */
386 .hw.init = CLK_HW_INIT("uart1_ck", "armper_ck", &omap1_clk_full_ops, 0),
387 .rate = 48000000,
388 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
389 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
390 .enable_bit = CONF_MOD_UART1_CLK_MODE_R,
391 },
392 .sysc_addr = 0xfffb0054,
393};
394
395/*
396 * XXX The enable_bit here is misused - it simply switches between 12MHz
397 * and 48MHz. Reimplement with clk_mux.
398 *
399 * XXX does this need SYSC register handling?
400 */
401static struct omap1_clk uart2_ck = {
402 /* Direct from ULPD, no real parent */
403 .hw.init = CLK_HW_INIT("uart2_ck", "armper_ck", &omap1_clk_full_ops, 0),
404 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
405 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
406 .enable_bit = CONF_MOD_UART2_CLK_MODE_R,
407 .round_rate = &omap1_round_uart_rate,
408 .set_rate = &omap1_set_uart_rate,
409 .recalc = &omap1_uart_recalc,
410};
411
412/*
413 * XXX The enable_bit here is misused - it simply switches between 12MHz
414 * and 48MHz. Reimplement with clk_mux.
415 *
416 * XXX does this need SYSC register handling?
417 */
418static struct omap1_clk uart3_1510 = {
419 /* Direct from ULPD, no real parent */
420 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
421 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
422 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
423 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
424 .round_rate = &omap1_round_uart_rate,
425 .set_rate = &omap1_set_uart_rate,
426 .recalc = &omap1_uart_recalc,
427};
428
429/*
430 * XXX The enable_bit here is misused - it simply switches between 12MHz
431 * and 48MHz. Reimplement with clk_mux.
432 *
433 * XXX SYSC register handling does not belong in the clock framework
434 */
435static struct uart_clk uart3_16xx = {
436 .clk = {
437 .ops = &clkops_uart_16xx,
438 /* Direct from ULPD, no real parent */
439 .hw.init = CLK_HW_INIT("uart3_ck", "armper_ck", &omap1_clk_full_ops, 0),
440 .rate = 48000000,
441 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
442 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
443 .enable_bit = CONF_MOD_UART3_CLK_MODE_R,
444 },
445 .sysc_addr = 0xfffb9854,
446};
447
448static struct omap1_clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
449 .ops = &clkops_generic,
450 /* Direct from ULPD, no parent */
451 .hw.init = CLK_HW_INIT_NO_PARENT("usb_clko", &omap1_clk_full_ops, 0),
452 .rate = 6000000,
453 .flags = ENABLE_REG_32BIT,
454 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
455 .enable_bit = USB_MCLK_EN_BIT,
456};
457
458static struct omap1_clk usb_hhc_ck1510 = {
459 .ops = &clkops_generic,
460 /* Direct from ULPD, no parent */
461 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
462 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
463 .flags = ENABLE_REG_32BIT,
464 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
465 .enable_bit = USB_HOST_HHC_UHOST_EN,
466};
467
468static struct omap1_clk usb_hhc_ck16xx = {
469 .ops = &clkops_generic,
470 /* Direct from ULPD, no parent */
471 .hw.init = CLK_HW_INIT_NO_PARENT("usb_hhc_ck", &omap1_clk_full_ops, 0),
472 .rate = 48000000,
473 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
474 .flags = ENABLE_REG_32BIT,
475 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
476 .enable_bit = OTG_SYSCON_2_UHOST_EN_SHIFT
477};
478
479static struct omap1_clk usb_dc_ck = {
480 .ops = &clkops_generic,
481 /* Direct from ULPD, no parent */
482 .hw.init = CLK_HW_INIT_NO_PARENT("usb_dc_ck", &omap1_clk_full_ops, 0),
483 .rate = 48000000,
484 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
485 .enable_bit = SOFT_USB_OTG_DPLL_REQ_SHIFT,
486};
487
488static struct omap1_clk uart1_7xx = {
489 .ops = &clkops_generic,
490 /* Direct from ULPD, no parent */
491 .hw.init = CLK_HW_INIT_NO_PARENT("uart1_ck", &omap1_clk_full_ops, 0),
492 .rate = 12000000,
493 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
494 .enable_bit = 9,
495};
496
497static struct omap1_clk uart2_7xx = {
498 .ops = &clkops_generic,
499 /* Direct from ULPD, no parent */
500 .hw.init = CLK_HW_INIT_NO_PARENT("uart2_ck", &omap1_clk_full_ops, 0),
501 .rate = 12000000,
502 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
503 .enable_bit = 11,
504};
505
506static struct omap1_clk mclk_1510 = {
507 .ops = &clkops_generic,
508 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
509 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
510 .rate = 12000000,
511 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
512 .enable_bit = SOFT_COM_MCKO_REQ_SHIFT,
513};
514
515static struct omap1_clk mclk_16xx = {
516 .ops = &clkops_generic,
517 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
518 .hw.init = CLK_HW_INIT_NO_PARENT("mclk", &omap1_clk_full_ops, 0),
519 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
520 .enable_bit = COM_ULPD_PLL_CLK_REQ,
521 .set_rate = &omap1_set_ext_clk_rate,
522 .round_rate = &omap1_round_ext_clk_rate,
523 .init = &omap1_init_ext_clk,
524};
525
526static struct omap1_clk bclk_1510 = {
527 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
528 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_rate_ops, 0),
529 .rate = 12000000,
530};
531
532static struct omap1_clk bclk_16xx = {
533 .ops = &clkops_generic,
534 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
535 .hw.init = CLK_HW_INIT_NO_PARENT("bclk", &omap1_clk_full_ops, 0),
536 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
537 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
538 .set_rate = &omap1_set_ext_clk_rate,
539 .round_rate = &omap1_round_ext_clk_rate,
540 .init = &omap1_init_ext_clk,
541};
542
543static struct omap1_clk mmc1_ck = {
544 .ops = &clkops_generic,
545 /* Functional clock is direct from ULPD, interface clock is ARMPER */
546 .hw.init = CLK_HW_INIT("mmc1_ck", "armper_ck", &omap1_clk_full_ops, 0),
547 .rate = 48000000,
548 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
549 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
550 .enable_bit = CONF_MOD_MMC_SD_CLK_REQ_R,
551};
552
553/*
554 * XXX MOD_CONF_CTRL_0 bit 20 is defined in the 1510 TRM as
555 * CONF_MOD_MCBSP3_AUXON ??
556 */
557static struct omap1_clk mmc2_ck = {
558 .ops = &clkops_generic,
559 /* Functional clock is direct from ULPD, interface clock is ARMPER */
560 .hw.init = CLK_HW_INIT("mmc2_ck", "armper_ck", &omap1_clk_full_ops, 0),
561 .rate = 48000000,
562 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
563 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
564 .enable_bit = 20,
565};
566
567static struct omap1_clk mmc3_ck = {
568 .ops = &clkops_generic,
569 /* Functional clock is direct from ULPD, interface clock is ARMPER */
570 .hw.init = CLK_HW_INIT("mmc3_ck", "armper_ck", &omap1_clk_full_ops, 0),
571 .rate = 48000000,
572 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
573 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
574 .enable_bit = SOFT_MMC_DPLL_REQ_SHIFT,
575};
576
577static struct omap1_clk virtual_ck_mpu = {
578 /* Is smarter alias for arm_ck */
579 .hw.init = CLK_HW_INIT("mpu", "arm_ck", &omap1_clk_rate_ops, 0),
580 .recalc = &followparent_recalc,
581 .set_rate = &omap1_select_table_rate,
582 .round_rate = &omap1_round_to_table_rate,
583};
584
585/* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
586remains active during MPU idle whenever this is enabled */
587static struct omap1_clk i2c_fck = {
588 .hw.init = CLK_HW_INIT("i2c_fck", "armxor_ck", &omap1_clk_gate_ops, 0),
589 .flags = CLOCK_NO_IDLE_PARENT,
590};
591
592static struct omap1_clk i2c_ick = {
593 .hw.init = CLK_HW_INIT("i2c_ick", "armper_ck", &omap1_clk_gate_ops, 0),
594 .flags = CLOCK_NO_IDLE_PARENT,
595};
596
597/*
598 * clkdev integration
599 */
600
601static struct omap_clk omap_clks[] = {
602 /* non-ULPD clocks */
603 CLK(NULL, "ck_ref", &ck_ref.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
604 CLK(NULL, "ck_dpll1", &ck_dpll1.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
605 /* CK_GEN1 clocks */
606 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk.hw, CK_16XX),
607 CLK(NULL, "ck_sossi", &sossi_ck.hw, CK_16XX),
608 CLK(NULL, "arm_ck", &arm_ck.hw, CK_16XX | CK_1510 | CK_310),
609 CLK(NULL, "armper_ck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
610 CLK("omap_gpio.0", "ick", &arm_gpio_ck.hw, CK_1510 | CK_310),
611 CLK(NULL, "armxor_ck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
612 CLK(NULL, "armtim_ck", &armtim_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
613 CLK("omap_wdt", "fck", &armwdt_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
614 CLK("omap_wdt", "ick", &armper_ck.clk.hw, CK_16XX),
615 CLK("omap_wdt", "ick", &dummy_ck.hw, CK_1510 | CK_310),
616 CLK(NULL, "arminth_ck", &arminth_ck1510.hw, CK_1510 | CK_310),
617 CLK(NULL, "arminth_ck", &arminth_ck16xx.hw, CK_16XX),
618 /* CK_GEN2 clocks */
619 CLK(NULL, "dsp_ck", &dsp_ck.hw, CK_16XX | CK_1510 | CK_310),
620 CLK(NULL, "dspmmu_ck", &dspmmu_ck.hw, CK_16XX | CK_1510 | CK_310),
621 CLK(NULL, "dspper_ck", &dspper_ck.hw, CK_16XX | CK_1510 | CK_310),
622 CLK(NULL, "dspxor_ck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
623 CLK(NULL, "dsptim_ck", &dsptim_ck.hw, CK_16XX | CK_1510 | CK_310),
624 /* CK_GEN3 clocks */
625 CLK(NULL, "tc_ck", &tc_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
626 CLK(NULL, "tipb_ck", &tipb_ck.hw, CK_1510 | CK_310),
627 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck.hw, CK_16XX | CK_7XX),
628 CLK(NULL, "tc1_ck", &tc1_ck.hw, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck.hw, CK_16XX),
630 CLK(NULL, "dma_ck", &dma_ck.hw, CK_16XX | CK_1510 | CK_310),
631 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck.hw, CK_16XX),
632 CLK(NULL, "api_ck", &api_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
633 CLK(NULL, "lb_ck", &lb_ck.clk.hw, CK_1510 | CK_310),
634 CLK(NULL, "rhea1_ck", &rhea1_ck.hw, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck.hw, CK_16XX),
636 CLK(NULL, "lcd_ck", &lcd_ck_16xx.hw, CK_16XX | CK_7XX),
637 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk.hw, CK_1510 | CK_310),
638 /* ULPD clocks */
639 CLK(NULL, "uart1_ck", &uart1_1510.hw, CK_1510 | CK_310),
640 CLK(NULL, "uart1_ck", &uart1_16xx.clk.hw, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx.hw, CK_7XX),
642 CLK(NULL, "uart2_ck", &uart2_ck.hw, CK_16XX | CK_1510 | CK_310),
643 CLK(NULL, "uart2_ck", &uart2_7xx.hw, CK_7XX),
644 CLK(NULL, "uart3_ck", &uart3_1510.hw, CK_1510 | CK_310),
645 CLK(NULL, "uart3_ck", &uart3_16xx.clk.hw, CK_16XX),
646 CLK(NULL, "usb_clko", &usb_clko.hw, CK_16XX | CK_1510 | CK_310),
647 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510.hw, CK_1510 | CK_310),
648 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx.hw, CK_16XX),
649 CLK(NULL, "usb_dc_ck", &usb_dc_ck.hw, CK_16XX | CK_7XX),
650 CLK(NULL, "mclk", &mclk_1510.hw, CK_1510 | CK_310),
651 CLK(NULL, "mclk", &mclk_16xx.hw, CK_16XX),
652 CLK(NULL, "bclk", &bclk_1510.hw, CK_1510 | CK_310),
653 CLK(NULL, "bclk", &bclk_16xx.hw, CK_16XX),
654 CLK("mmci-omap.0", "fck", &mmc1_ck.hw, CK_16XX | CK_1510 | CK_310),
655 CLK("mmci-omap.0", "fck", &mmc3_ck.hw, CK_7XX),
656 CLK("mmci-omap.0", "ick", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
657 CLK("mmci-omap.1", "fck", &mmc2_ck.hw, CK_16XX),
658 CLK("mmci-omap.1", "ick", &armper_ck.clk.hw, CK_16XX),
659 /* Virtual clocks */
660 CLK(NULL, "mpu", &virtual_ck_mpu.hw, CK_16XX | CK_1510 | CK_310),
661 CLK("omap_i2c.1", "fck", &i2c_fck.hw, CK_16XX | CK_1510 | CK_310 | CK_7XX),
662 CLK("omap_i2c.1", "ick", &i2c_ick.hw, CK_16XX),
663 CLK("omap_i2c.1", "ick", &dummy_ck.hw, CK_1510 | CK_310 | CK_7XX),
664 CLK("omap1_spi100k.1", "fck", &dummy_ck.hw, CK_7XX),
665 CLK("omap1_spi100k.1", "ick", &dummy_ck.hw, CK_7XX),
666 CLK("omap1_spi100k.2", "fck", &dummy_ck.hw, CK_7XX),
667 CLK("omap1_spi100k.2", "ick", &dummy_ck.hw, CK_7XX),
668 CLK("omap_uwire", "fck", &armxor_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
669 CLK("omap-mcbsp.1", "ick", &dspper_ck.hw, CK_16XX),
670 CLK("omap-mcbsp.1", "ick", &dummy_ck.hw, CK_1510 | CK_310),
671 CLK("omap-mcbsp.2", "ick", &armper_ck.clk.hw, CK_16XX),
672 CLK("omap-mcbsp.2", "ick", &dummy_ck.hw, CK_1510 | CK_310),
673 CLK("omap-mcbsp.3", "ick", &dspper_ck.hw, CK_16XX),
674 CLK("omap-mcbsp.3", "ick", &dummy_ck.hw, CK_1510 | CK_310),
675 CLK("omap-mcbsp.1", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
676 CLK("omap-mcbsp.2", "fck", &armper_ck.clk.hw, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.3", "fck", &dspxor_ck.hw, CK_16XX | CK_1510 | CK_310),
678};
679
680/*
681 * init
682 */
683
684static void __init omap1_show_rates(void)
685{
686 pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
687 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
688 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
689 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
690}
691
692u32 cpu_mask;
693
694int __init omap1_clk_init(void)
695{
696 struct omap_clk *c;
697 u32 reg;
698
699#ifdef CONFIG_DEBUG_LL
700 /* Make sure UART clocks are enabled early */
701 if (cpu_is_omap16xx())
702 omap_writel(omap_readl(MOD_CONF_CTRL_0) |
703 CONF_MOD_UART1_CLK_MODE_R |
704 CONF_MOD_UART3_CLK_MODE_R, MOD_CONF_CTRL_0);
705#endif
706
707 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
708 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
709 omap_writew(reg, SOFT_REQ_REG);
710 if (!cpu_is_omap15xx())
711 omap_writew(0, SOFT_REQ_REG2);
712
713 /* By default all idlect1 clocks are allowed to idle */
714 arm_idlect1_mask = ~0;
715
716 cpu_mask = 0;
717 if (cpu_is_omap1710())
718 cpu_mask |= CK_1710;
719 if (cpu_is_omap16xx())
720 cpu_mask |= CK_16XX;
721 if (cpu_is_omap1510())
722 cpu_mask |= CK_1510;
723 if (cpu_is_omap310())
724 cpu_mask |= CK_310;
725
726 /* Pointers to these clocks are needed by code in clock.c */
727 api_ck_p = &api_ck.clk;
728 ck_dpll1_p = &ck_dpll1;
729 ck_ref_p = &ck_ref;
730
731 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
732 omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
733 omap_readw(ARM_CKCTL));
734
735 /* We want to be in synchronous scalable mode */
736 omap_writew(0x1000, ARM_SYSST);
737
738
739 /*
740 * Initially use the values set by bootloader. Determine PLL rate and
741 * recalculate dependent clocks as if kernel had changed PLL or
742 * divisors. See also omap1_clk_late_init() that can reprogram dpll1
743 * after the SRAM is initialized.
744 */
745 {
746 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
747
748 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
749 if (pll_ctl_val & 0x10) {
750 /* PLL enabled, apply multiplier and divisor */
751 if (pll_ctl_val & 0xf80)
752 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
753 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
754 } else {
755 /* PLL disabled, apply bypass divisor */
756 switch (pll_ctl_val & 0xc) {
757 case 0:
758 break;
759 case 0x4:
760 ck_dpll1.rate /= 2;
761 break;
762 default:
763 ck_dpll1.rate /= 4;
764 break;
765 }
766 }
767 }
768
769 /* Amstrad Delta wants BCLK high when inactive */
770 if (machine_is_ams_delta())
771 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
772 (1 << SDW_MCLK_INV_BIT),
773 ULPD_CLOCK_CTRL);
774
775 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
776 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
777
778 /* Put DSP/MPUI into reset until needed */
779 omap_writew(0, ARM_RSTCT1);
780 omap_writew(1, ARM_RSTCT2);
781 omap_writew(0x400, ARM_IDLECT1);
782
783 /*
784 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
785 * of the ARM_IDLECT2 register must be set to zero. The power-on
786 * default value of this bit is one.
787 */
788 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
789
790 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++) {
791 if (!(c->cpu & cpu_mask))
792 continue;
793
794 if (c->lk.clk_hw->init) { /* NULL if provider already registered */
795 const struct clk_init_data *init = c->lk.clk_hw->init;
796 const char *name = c->lk.clk_hw->init->name;
797 int err;
798
799 err = clk_hw_register(NULL, c->lk.clk_hw);
800 if (err < 0) {
801 pr_err("failed to register clock \"%s\"! (%d)\n", name, err);
802 /* may be tried again, restore init data */
803 c->lk.clk_hw->init = init;
804 continue;
805 }
806 }
807
808 clk_hw_register_clkdev(c->lk.clk_hw, c->lk.con_id, c->lk.dev_id);
809 }
810
811 omap1_show_rates();
812
813 return 0;
814}
815
816#define OMAP1_DPLL1_SANE_VALUE 60000000
817
818void __init omap1_clk_late_init(void)
819{
820 unsigned long rate = ck_dpll1.rate;
821
822 /* Find the highest supported frequency and enable it */
823 if (omap1_select_table_rate(&virtual_ck_mpu, ~0, arm_ck.rate)) {
824 pr_err("System frequencies not set, using default. Check your config.\n");
825 /*
826 * Reprogramming the DPLL is tricky, it must be done from SRAM.
827 */
828 omap_sram_reprogram_clock(0x2290, 0x0005);
829 ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
830 }
831 propagate_rate(&ck_dpll1);
832 omap1_show_rates();
833 loops_per_jiffy = cpufreq_scale(loops_per_jiffy, rate, ck_dpll1.rate);
834}