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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 1999 ARM Limited
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
7 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
8 */
9
10#include <linux/kernel.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <asm/system_misc.h>
19#include <asm/proc-fns.h>
20#include <asm/mach-types.h>
21#include <asm/hardware/cache-l2x0.h>
22
23#include "common.h"
24#include "hardware.h"
25
26static void __iomem *wdog_base;
27static struct clk *wdog_clk;
28static int wcr_enable = (1 << 2);
29
30/*
31 * Reset the system. It is called by machine_restart().
32 */
33void mxc_restart(enum reboot_mode mode, const char *cmd)
34{
35 if (!wdog_base)
36 goto reset_fallback;
37
38 if (!IS_ERR(wdog_clk))
39 clk_enable(wdog_clk);
40
41 /* Assert SRS signal */
42 imx_writew(wcr_enable, wdog_base);
43 /*
44 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
45 * written twice), we add another two writes to ensure there must be at
46 * least two writes happen in the same one 32kHz clock period. We save
47 * the target check here, since the writes shouldn't be a huge burden
48 * for other platforms.
49 */
50 imx_writew(wcr_enable, wdog_base);
51 imx_writew(wcr_enable, wdog_base);
52
53 /* wait for reset to assert... */
54 mdelay(500);
55
56 pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
57
58 /* delay to allow the serial port to show the message */
59 mdelay(50);
60
61reset_fallback:
62 /* we'll take a jump through zero as a poor second */
63 soft_restart(0);
64}
65
66void __init mxc_arch_reset_init(void __iomem *base)
67{
68 wdog_base = base;
69
70 wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
71 if (IS_ERR(wdog_clk))
72 pr_warn("%s: failed to get wdog clock\n", __func__);
73 else
74 clk_prepare(wdog_clk);
75}
76
77#ifdef CONFIG_SOC_IMX1
78void __init imx1_reset_init(void __iomem *base)
79{
80 wcr_enable = (1 << 0);
81 mxc_arch_reset_init(base);
82}
83#endif
84
85#ifdef CONFIG_CACHE_L2X0
86void __init imx_init_l2cache(void)
87{
88 void __iomem *l2x0_base;
89 struct device_node *np;
90 unsigned int val;
91
92 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
93 if (!np)
94 return;
95
96 l2x0_base = of_iomap(np, 0);
97 if (!l2x0_base)
98 goto put_node;
99
100 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
101 /* Configure the L2 PREFETCH and POWER registers */
102 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
103 val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
104 L310_PREFETCH_CTRL_INSTR_PREFETCH |
105 L310_PREFETCH_CTRL_DATA_PREFETCH;
106
107 /* Set perfetch offset to improve performance */
108 val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
109 val |= 15;
110
111 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
112 }
113
114 iounmap(l2x0_base);
115put_node:
116 of_node_put(np);
117}
118#endif
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 1999 ARM Limited
4 * Copyright (C) 2000 Deep Blue Solutions Ltd
5 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
7 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
8 */
9
10#include <linux/kernel.h>
11#include <linux/clk.h>
12#include <linux/io.h>
13#include <linux/err.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17
18#include <asm/system_misc.h>
19#include <asm/proc-fns.h>
20#include <asm/mach-types.h>
21#include <asm/hardware/cache-l2x0.h>
22
23#include "common.h"
24#include "hardware.h"
25
26static void __iomem *wdog_base;
27static struct clk *wdog_clk;
28static int wcr_enable = (1 << 2);
29
30/*
31 * Reset the system. It is called by machine_restart().
32 */
33void mxc_restart(enum reboot_mode mode, const char *cmd)
34{
35 if (!wdog_base)
36 goto reset_fallback;
37
38 if (!IS_ERR(wdog_clk))
39 clk_enable(wdog_clk);
40
41 /* Assert SRS signal */
42 imx_writew(wcr_enable, wdog_base);
43 /*
44 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
45 * written twice), we add another two writes to ensure there must be at
46 * least two writes happen in the same one 32kHz clock period. We save
47 * the target check here, since the writes shouldn't be a huge burden
48 * for other platforms.
49 */
50 imx_writew(wcr_enable, wdog_base);
51 imx_writew(wcr_enable, wdog_base);
52
53 /* wait for reset to assert... */
54 mdelay(500);
55
56 pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
57
58 /* delay to allow the serial port to show the message */
59 mdelay(50);
60
61reset_fallback:
62 /* we'll take a jump through zero as a poor second */
63 soft_restart(0);
64}
65
66void __init mxc_arch_reset_init(void __iomem *base)
67{
68 wdog_base = base;
69
70 wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
71 if (IS_ERR(wdog_clk))
72 pr_warn("%s: failed to get wdog clock\n", __func__);
73 else
74 clk_prepare(wdog_clk);
75}
76
77#ifdef CONFIG_SOC_IMX1
78void __init imx1_reset_init(void __iomem *base)
79{
80 wcr_enable = (1 << 0);
81 mxc_arch_reset_init(base);
82}
83#endif
84
85#ifdef CONFIG_CACHE_L2X0
86void __init imx_init_l2cache(void)
87{
88 void __iomem *l2x0_base;
89 struct device_node *np;
90 unsigned int val;
91
92 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
93 if (!np)
94 return;
95
96 l2x0_base = of_iomap(np, 0);
97 if (!l2x0_base)
98 goto put_node;
99
100 if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
101 /* Configure the L2 PREFETCH and POWER registers */
102 val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
103 val |= L310_PREFETCH_CTRL_DBL_LINEFILL |
104 L310_PREFETCH_CTRL_INSTR_PREFETCH |
105 L310_PREFETCH_CTRL_DATA_PREFETCH;
106
107 /* Set perfetch offset to improve performance */
108 val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
109 val |= 15;
110
111 writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
112 }
113
114 iounmap(l2x0_base);
115put_node:
116 of_node_put(np);
117}
118#endif