1// SPDX-License-Identifier: GPL-2.0-or-later
 2/*
 3 * MX31 CPU type detection
 4 *
 5 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 6 */
 7
 8#include <linux/module.h>
 
 9#include <linux/io.h>
10
11#include "common.h"
12#include "hardware.h"
13#include "iim.h"
14
15static int mx31_cpu_rev = -1;
16
17static struct {
18	u8 srev;
19	const char *name;
20	unsigned int rev;
21} mx31_cpu_type[] = {
22	{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
23	{ .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
24	{ .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
25	{ .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
26	{ .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
27	{ .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
28	{ .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
29	{ .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
30	{ .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
31};
32
33static int mx31_read_cpu_rev(void)
34{
 
 
35	u32 i, srev;
36
 
 
 
 
 
37	/* read SREV register from IIM module */
38	srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
39	srev &= 0xff;
40
41	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
42		if (srev == mx31_cpu_type[i].srev) {
43			imx_print_silicon_rev(mx31_cpu_type[i].name,
44						mx31_cpu_type[i].rev);
45			return mx31_cpu_type[i].rev;
46		}
47
48	imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
49	return IMX_CHIP_REVISION_UNKNOWN;
50}
51
52int mx31_revision(void)
53{
54	if (mx31_cpu_rev == -1)
55		mx31_cpu_rev = mx31_read_cpu_rev();
56
57	return mx31_cpu_rev;
58}
59EXPORT_SYMBOL(mx31_revision);

 1// SPDX-License-Identifier: GPL-2.0-or-later
 2/*
 3 * MX31 CPU type detection
 4 *
 5 * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
 6 */
 7
 8#include <linux/module.h>
 9#include <linux/of_address.h>
10#include <linux/io.h>
11
12#include "common.h"
13#include "hardware.h"
14#include "iim.h"
15
16static int mx31_cpu_rev = -1;
17
18static struct {
19	u8 srev;
20	const char *name;
21	unsigned int rev;
22} mx31_cpu_type[] = {
23	{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
24	{ .srev = 0x10, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
25	{ .srev = 0x11, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
26	{ .srev = 0x12, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_1 },
27	{ .srev = 0x13, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_1 },
28	{ .srev = 0x14, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_1_2 },
29	{ .srev = 0x15, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_1_2 },
30	{ .srev = 0x28, .name = "i.MX31",    .rev = IMX_CHIP_REVISION_2_0 },
31	{ .srev = 0x29, .name = "i.MX31L",   .rev = IMX_CHIP_REVISION_2_0 },
32};
33
34static int mx31_read_cpu_rev(void)
35{
36	void __iomem *iim_base;
37	struct device_node *np;
38	u32 i, srev;
39
40	np = of_find_compatible_node(NULL, NULL, "fsl,imx31-iim");
41	iim_base = of_iomap(np, 0);
42	of_node_put(np);
43	BUG_ON(!iim_base);
44
45	/* read SREV register from IIM module */
46	srev = imx_readl(iim_base + MXC_IIMSREV);
47	srev &= 0xff;
48
49	for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
50		if (srev == mx31_cpu_type[i].srev) {
51			imx_print_silicon_rev(mx31_cpu_type[i].name,
52						mx31_cpu_type[i].rev);
53			return mx31_cpu_type[i].rev;
54		}
55
56	imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
57	return IMX_CHIP_REVISION_UNKNOWN;
58}
59
60int mx31_revision(void)
61{
62	if (mx31_cpu_rev == -1)
63		mx31_cpu_rev = mx31_read_cpu_rev();
64
65	return mx31_cpu_rev;
66}
67EXPORT_SYMBOL(mx31_revision);