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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3/*
4 * Device tree file for ZII's SPB4 board
5 *
6 * SPB - Seat Power Box
7 *
8 * Copyright (C) 2019 Zodiac Inflight Innovations
9 */
10
11/dts-v1/;
12#include "vf610.dtsi"
13
14/ {
15 model = "ZII VF610 SPB4 Board";
16 compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610";
17
18 chosen {
19 stdout-path = &uart0;
20 };
21
22 memory@80000000 {
23 device_type = "memory";
24 reg = <0x80000000 0x20000000>;
25 };
26
27 gpio-leds {
28 compatible = "gpio-leds";
29 pinctrl-0 = <&pinctrl_leds_debug>;
30 pinctrl-names = "default";
31
32 led-debug {
33 label = "zii:green:debug1";
34 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
35 linux,default-trigger = "heartbeat";
36 };
37 };
38
39 reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
40 compatible = "regulator-fixed";
41 regulator-name = "vcc_3v3_mcu";
42 regulator-min-microvolt = <3300000>;
43 regulator-max-microvolt = <3300000>;
44 };
45
46 supply-voltage-monitor {
47 compatible = "iio-hwmon";
48 io-channels = <&adc0 8>, /* 28V_SW */
49 <&adc0 9>, /* +3.3V */
50 <&adc1 8>, /* VCC_1V5 */
51 <&adc1 9>; /* VCC_1V2 */
52 };
53};
54
55&adc0 {
56 vref-supply = <®_vcc_3v3_mcu>;
57 status = "okay";
58};
59
60&adc1 {
61 vref-supply = <®_vcc_3v3_mcu>;
62 status = "okay";
63};
64
65&dspi1 {
66 bus-num = <1>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_dspi1>;
69 status = "okay";
70
71 flash@0 {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "m25p128", "jedec,spi-nor";
75 reg = <0>;
76 spi-max-frequency = <50000000>;
77 };
78};
79
80&edma0 {
81 status = "okay";
82};
83
84&edma1 {
85 status = "okay";
86};
87
88&esdhc0 {
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_esdhc0>;
91 bus-width = <8>;
92 non-removable;
93 no-1-8-v;
94 keep-power-in-suspend;
95 no-sdio;
96 no-sd;
97 status = "okay";
98};
99
100&esdhc1 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_esdhc1>;
103 bus-width = <4>;
104 no-sdio;
105 status = "okay";
106};
107
108&fec1 {
109 phy-mode = "rmii";
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_fec1>;
112 status = "okay";
113
114 fixed-link {
115 speed = <100>;
116 full-duplex;
117 };
118
119 mdio1: mdio {
120 #address-cells = <1>;
121 #size-cells = <0>;
122 clock-frequency = <12500000>;
123 suppress-preamble;
124 status = "okay";
125
126 switch0: switch0@0 {
127 compatible = "marvell,mv88e6190";
128 pinctrl-0 = <&pinctrl_gpio_switch0>;
129 pinctrl-names = "default";
130 reg = <0>;
131 eeprom-length = <65536>;
132 reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
133 interrupt-parent = <&gpio3>;
134 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
137
138 ports {
139 #address-cells = <1>;
140 #size-cells = <0>;
141
142 port@0 {
143 reg = <0>;
144 label = "cpu";
145 ethernet = <&fec1>;
146
147 fixed-link {
148 speed = <100>;
149 full-duplex;
150 };
151 };
152
153 port@1 {
154 reg = <1>;
155 label = "eth_cu_1000_1";
156 };
157
158 port@2 {
159 reg = <2>;
160 label = "eth_cu_1000_2";
161 };
162
163 port@3 {
164 reg = <3>;
165 label = "eth_cu_1000_3";
166 };
167
168 port@4 {
169 reg = <4>;
170 label = "eth_cu_1000_4";
171 };
172
173 port@5 {
174 reg = <5>;
175 label = "eth_cu_1000_5";
176 };
177
178 port@6 {
179 reg = <6>;
180 label = "eth_cu_1000_6";
181 };
182 };
183 };
184 };
185};
186
187&i2c0 {
188 clock-frequency = <100000>;
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_i2c0>;
191 status = "okay";
192
193 io-expander@22 {
194 compatible = "nxp,pca9554";
195 reg = <0x22>;
196 gpio-controller;
197 #gpio-cells = <2>;
198 };
199
200 eeprom@50 {
201 compatible = "atmel,24c04";
202 reg = <0x50>;
203 label = "nameplate";
204 };
205
206 eeprom@52 {
207 compatible = "atmel,24c04";
208 reg = <0x52>;
209 };
210};
211
212&i2c1 {
213 clock-frequency = <100000>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_i2c1>;
216 status = "okay";
217
218 watchdog@38 {
219 compatible = "zii,rave-wdt";
220 reg = <0x38>;
221 };
222};
223
224&snvsrtc {
225 status = "disabled";
226};
227
228&uart0 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_uart0>;
231 status = "okay";
232};
233
234&uart1 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_uart1>;
237 status = "okay";
238};
239
240&uart2 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pinctrl_uart2>;
243 status = "okay";
244
245 rave-sp {
246 compatible = "zii,rave-sp-rdu2";
247 current-speed = <1000000>;
248 #address-cells = <1>;
249 #size-cells = <1>;
250
251 watchdog {
252 compatible = "zii,rave-sp-watchdog";
253 };
254
255 eeprom@a3 {
256 compatible = "zii,rave-sp-eeprom";
257 reg = <0xa3 0x4000>;
258 #address-cells = <1>;
259 #size-cells = <1>;
260 zii,eeprom-name = "main-eeprom";
261 };
262 };
263};
264
265&uart3 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart3>;
268 status = "okay";
269};
270
271&wdoga5 {
272 status = "disabled";
273};
274
275&iomuxc {
276 pinctrl_dspi1: dspi1grp {
277 fsl,pins = <
278 VF610_PAD_PTD5__DSPI1_CS0 0x1182
279 VF610_PAD_PTD4__DSPI1_CS1 0x1182
280 VF610_PAD_PTC6__DSPI1_SIN 0x1181
281 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
282 VF610_PAD_PTC8__DSPI1_SCK 0x1182
283 >;
284 };
285
286 pinctrl_esdhc0: esdhc0grp {
287 fsl,pins = <
288 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
289 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
290 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
291 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
292 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
293 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
294 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
295 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
296 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
297 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
298 >;
299 };
300
301 pinctrl_esdhc1: esdhc1grp {
302 fsl,pins = <
303 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
304 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
305 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
306 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
307 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
308 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
309 >;
310 };
311
312 pinctrl_fec1: fec1grp {
313 fsl,pins = <
314 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
315 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
316 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
317 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
318 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
319 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
320 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
321 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
322 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
323 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
324 >;
325 };
326
327 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
328 fsl,pins = <
329 VF610_PAD_PTE2__GPIO_107 0x31c2
330 VF610_PAD_PTB28__GPIO_98 0x219d
331 >;
332 };
333
334 pinctrl_i2c0: i2c0grp {
335 fsl,pins = <
336 VF610_PAD_PTB14__I2C0_SCL 0x37ff
337 VF610_PAD_PTB15__I2C0_SDA 0x37ff
338 >;
339 };
340
341 pinctrl_i2c1: i2c1grp {
342 fsl,pins = <
343 VF610_PAD_PTB16__I2C1_SCL 0x37ff
344 VF610_PAD_PTB17__I2C1_SDA 0x37ff
345 >;
346 };
347
348 pinctrl_leds_debug: pinctrl-leds-debug {
349 fsl,pins = <
350 VF610_PAD_PTD3__GPIO_82 0x31c2
351 >;
352 };
353
354 pinctrl_uart0: uart0grp {
355 fsl,pins = <
356 VF610_PAD_PTB10__UART0_TX 0x21a2
357 VF610_PAD_PTB11__UART0_RX 0x21a1
358 >;
359 };
360
361 pinctrl_uart1: uart1grp {
362 fsl,pins = <
363 VF610_PAD_PTB23__UART1_TX 0x21a2
364 VF610_PAD_PTB24__UART1_RX 0x21a1
365 >;
366 };
367
368 pinctrl_uart2: uart2grp {
369 fsl,pins = <
370 VF610_PAD_PTD0__UART2_TX 0x21a2
371 VF610_PAD_PTD1__UART2_RX 0x21a1
372 >;
373 };
374
375 pinctrl_uart3: uart3grp {
376 fsl,pins = <
377 VF610_PAD_PTA30__UART3_TX 0x21a2
378 VF610_PAD_PTA31__UART3_RX 0x21a1
379 >;
380 };
381};