Loading...
Note: File does not exist in v6.13.7.
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/pinctrl/rockchip.h>
7#include <dt-bindings/clock/rk3036-cru.h>
8#include <dt-bindings/soc/rockchip,boot-mode.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 compatible = "rockchip,rk3036";
15
16 interrupt-parent = <&gic>;
17
18 aliases {
19 i2c0 = &i2c0;
20 i2c1 = &i2c1;
21 i2c2 = &i2c2;
22 mshc0 = &emmc;
23 mshc1 = &sdmmc;
24 mshc2 = &sdio;
25 serial0 = &uart0;
26 serial1 = &uart1;
27 serial2 = &uart2;
28 spi = &spi;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 enable-method = "rockchip,rk3036-smp";
35
36 cpu0: cpu@f00 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a7";
39 reg = <0xf00>;
40 resets = <&cru SRST_CORE0>;
41 operating-points = <
42 /* KHz uV */
43 816000 1000000
44 >;
45 clock-latency = <40000>;
46 clocks = <&cru ARMCLK>;
47 };
48
49 cpu1: cpu@f01 {
50 device_type = "cpu";
51 compatible = "arm,cortex-a7";
52 reg = <0xf01>;
53 resets = <&cru SRST_CORE1>;
54 };
55 };
56
57 amba: bus {
58 compatible = "simple-bus";
59 #address-cells = <1>;
60 #size-cells = <1>;
61 ranges;
62
63 pdma: pdma@20078000 {
64 compatible = "arm,pl330", "arm,primecell";
65 reg = <0x20078000 0x4000>;
66 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
68 #dma-cells = <1>;
69 arm,pl330-broken-no-flushp;
70 arm,pl330-periph-burst;
71 clocks = <&cru ACLK_DMAC2>;
72 clock-names = "apb_pclk";
73 };
74 };
75
76 arm-pmu {
77 compatible = "arm,cortex-a7-pmu";
78 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
80 interrupt-affinity = <&cpu0>, <&cpu1>;
81 };
82
83 display-subsystem {
84 compatible = "rockchip,display-subsystem";
85 ports = <&vop_out>;
86 };
87
88 timer {
89 compatible = "arm,armv7-timer";
90 arm,cpu-registers-not-fw-configured;
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
93 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
95 clock-frequency = <24000000>;
96 };
97
98 xin24m: oscillator {
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 clock-output-names = "xin24m";
102 #clock-cells = <0>;
103 };
104
105 bus_intmem: sram@10080000 {
106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
111
112 smp-sram@0 {
113 compatible = "rockchip,rk3066-smp-sram";
114 reg = <0x00 0x10>;
115 };
116 };
117
118 gpu: gpu@10090000 {
119 compatible = "rockchip,rk3036-mali", "arm,mali-400";
120 reg = <0x10090000 0x10000>;
121 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
122 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
124 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
125 interrupt-names = "gp",
126 "gpmmu",
127 "pp0",
128 "ppmmu0";
129 assigned-clocks = <&cru SCLK_GPU>;
130 assigned-clock-rates = <100000000>;
131 clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
132 clock-names = "bus", "core";
133 resets = <&cru SRST_GPU>;
134 status = "disabled";
135 };
136
137 vop: vop@10118000 {
138 compatible = "rockchip,rk3036-vop";
139 reg = <0x10118000 0x19c>;
140 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
142 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
143 resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
144 reset-names = "axi", "ahb", "dclk";
145 iommus = <&vop_mmu>;
146 status = "disabled";
147
148 vop_out: port {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 vop_out_hdmi: endpoint@0 {
152 reg = <0>;
153 remote-endpoint = <&hdmi_in_vop>;
154 };
155 };
156 };
157
158 vop_mmu: iommu@10118300 {
159 compatible = "rockchip,iommu";
160 reg = <0x10118300 0x100>;
161 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
162 interrupt-names = "vop_mmu";
163 clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
164 clock-names = "aclk", "iface";
165 #iommu-cells = <0>;
166 status = "disabled";
167 };
168
169 gic: interrupt-controller@10139000 {
170 compatible = "arm,gic-400";
171 interrupt-controller;
172 #interrupt-cells = <3>;
173 #address-cells = <0>;
174
175 reg = <0x10139000 0x1000>,
176 <0x1013a000 0x2000>,
177 <0x1013c000 0x2000>,
178 <0x1013e000 0x2000>;
179 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
180 };
181
182 usb_otg: usb@10180000 {
183 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
184 "snps,dwc2";
185 reg = <0x10180000 0x40000>;
186 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&cru HCLK_OTG0>;
188 clock-names = "otg";
189 dr_mode = "otg";
190 g-np-tx-fifo-size = <16>;
191 g-rx-fifo-size = <275>;
192 g-tx-fifo-size = <256 128 128 64 64 32>;
193 status = "disabled";
194 };
195
196 usb_host: usb@101c0000 {
197 compatible = "rockchip,rk3036-usb", "rockchip,rk3066-usb",
198 "snps,dwc2";
199 reg = <0x101c0000 0x40000>;
200 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
201 clocks = <&cru HCLK_OTG1>;
202 clock-names = "otg";
203 dr_mode = "host";
204 status = "disabled";
205 };
206
207 emac: ethernet@10200000 {
208 compatible = "rockchip,rk3036-emac", "snps,arc-emac";
209 reg = <0x10200000 0x4000>;
210 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
211 #address-cells = <1>;
212 #size-cells = <0>;
213 rockchip,grf = <&grf>;
214 clocks = <&cru HCLK_MAC>, <&cru SCLK_MACREF>, <&cru SCLK_MAC>;
215 clock-names = "hclk", "macref", "macclk";
216 /*
217 * Fix the emac parent clock is DPLL instead of APLL.
218 * since that will cause some unstable things if the cpufreq
219 * is working. (e.g: the accurate 50MHz what mac_ref need)
220 */
221 assigned-clocks = <&cru SCLK_MACPLL>;
222 assigned-clock-parents = <&cru PLL_DPLL>;
223 max-speed = <100>;
224 phy-mode = "rmii";
225 status = "disabled";
226 };
227
228 sdmmc: mmc@10214000 {
229 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
230 reg = <0x10214000 0x4000>;
231 clock-frequency = <37500000>;
232 max-frequency = <37500000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
234 clock-names = "biu", "ciu";
235 fifo-depth = <0x100>;
236 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
237 resets = <&cru SRST_MMC0>;
238 reset-names = "reset";
239 status = "disabled";
240 };
241
242 sdio: mmc@10218000 {
243 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
244 reg = <0x10218000 0x4000>;
245 max-frequency = <37500000>;
246 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
247 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
251 resets = <&cru SRST_SDIO>;
252 reset-names = "reset";
253 status = "disabled";
254 };
255
256 emmc: mmc@1021c000 {
257 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
258 reg = <0x1021c000 0x4000>;
259 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
260 bus-width = <8>;
261 cap-mmc-highspeed;
262 clock-frequency = <37500000>;
263 max-frequency = <37500000>;
264 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
265 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
266 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
267 rockchip,default-sample-phase = <158>;
268 disable-wp;
269 dmas = <&pdma 12>;
270 dma-names = "rx-tx";
271 fifo-depth = <0x100>;
272 mmc-ddr-1_8v;
273 non-removable;
274 pinctrl-names = "default";
275 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
276 resets = <&cru SRST_EMMC>;
277 reset-names = "reset";
278 status = "disabled";
279 };
280
281 i2s: i2s@10220000 {
282 compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
283 reg = <0x10220000 0x4000>;
284 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
285 clock-names = "i2s_clk", "i2s_hclk";
286 clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
287 dmas = <&pdma 0>, <&pdma 1>;
288 dma-names = "tx", "rx";
289 pinctrl-names = "default";
290 pinctrl-0 = <&i2s_bus>;
291 #sound-dai-cells = <0>;
292 status = "disabled";
293 };
294
295 cru: clock-controller@20000000 {
296 compatible = "rockchip,rk3036-cru";
297 reg = <0x20000000 0x1000>;
298 rockchip,grf = <&grf>;
299 #clock-cells = <1>;
300 #reset-cells = <1>;
301 assigned-clocks = <&cru PLL_GPLL>;
302 assigned-clock-rates = <594000000>;
303 };
304
305 grf: syscon@20008000 {
306 compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
307 reg = <0x20008000 0x1000>;
308
309 reboot-mode {
310 compatible = "syscon-reboot-mode";
311 offset = <0x1d8>;
312 mode-normal = <BOOT_NORMAL>;
313 mode-recovery = <BOOT_RECOVERY>;
314 mode-bootloader = <BOOT_FASTBOOT>;
315 mode-loader = <BOOT_BL_DOWNLOAD>;
316 };
317 };
318
319 acodec: acodec-ana@20030000 {
320 compatible = "rk3036-codec";
321 reg = <0x20030000 0x4000>;
322 rockchip,grf = <&grf>;
323 clock-names = "acodec_pclk";
324 clocks = <&cru PCLK_ACODEC>;
325 status = "disabled";
326 };
327
328 hdmi: hdmi@20034000 {
329 compatible = "rockchip,rk3036-inno-hdmi";
330 reg = <0x20034000 0x4000>;
331 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cru PCLK_HDMI>;
333 clock-names = "pclk";
334 rockchip,grf = <&grf>;
335 pinctrl-names = "default";
336 pinctrl-0 = <&hdmi_ctl>;
337 status = "disabled";
338
339 hdmi_in: port {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 hdmi_in_vop: endpoint@0 {
343 reg = <0>;
344 remote-endpoint = <&vop_out_hdmi>;
345 };
346 };
347 };
348
349 timer: timer@20044000 {
350 compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
351 reg = <0x20044000 0x20>;
352 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&xin24m>, <&cru PCLK_TIMER>;
354 clock-names = "timer", "pclk";
355 };
356
357 pwm0: pwm@20050000 {
358 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
359 reg = <0x20050000 0x10>;
360 #pwm-cells = <3>;
361 clocks = <&cru PCLK_PWM>;
362 clock-names = "pwm";
363 pinctrl-names = "default";
364 pinctrl-0 = <&pwm0_pin>;
365 status = "disabled";
366 };
367
368 pwm1: pwm@20050010 {
369 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
370 reg = <0x20050010 0x10>;
371 #pwm-cells = <3>;
372 clocks = <&cru PCLK_PWM>;
373 clock-names = "pwm";
374 pinctrl-names = "default";
375 pinctrl-0 = <&pwm1_pin>;
376 status = "disabled";
377 };
378
379 pwm2: pwm@20050020 {
380 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
381 reg = <0x20050020 0x10>;
382 #pwm-cells = <3>;
383 clocks = <&cru PCLK_PWM>;
384 clock-names = "pwm";
385 pinctrl-names = "default";
386 pinctrl-0 = <&pwm2_pin>;
387 status = "disabled";
388 };
389
390 pwm3: pwm@20050030 {
391 compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
392 reg = <0x20050030 0x10>;
393 #pwm-cells = <2>;
394 clocks = <&cru PCLK_PWM>;
395 clock-names = "pwm";
396 pinctrl-names = "default";
397 pinctrl-0 = <&pwm3_pin>;
398 status = "disabled";
399 };
400
401 i2c1: i2c@20056000 {
402 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
403 reg = <0x20056000 0x1000>;
404 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
405 #address-cells = <1>;
406 #size-cells = <0>;
407 clock-names = "i2c";
408 clocks = <&cru PCLK_I2C1>;
409 pinctrl-names = "default";
410 pinctrl-0 = <&i2c1_xfer>;
411 status = "disabled";
412 };
413
414 i2c2: i2c@2005a000 {
415 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
416 reg = <0x2005a000 0x1000>;
417 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
418 #address-cells = <1>;
419 #size-cells = <0>;
420 clock-names = "i2c";
421 clocks = <&cru PCLK_I2C2>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&i2c2_xfer>;
424 status = "disabled";
425 };
426
427 uart0: serial@20060000 {
428 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
429 reg = <0x20060000 0x100>;
430 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
431 reg-shift = <2>;
432 reg-io-width = <4>;
433 clock-frequency = <24000000>;
434 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
435 clock-names = "baudclk", "apb_pclk";
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
438 status = "disabled";
439 };
440
441 uart1: serial@20064000 {
442 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
443 reg = <0x20064000 0x100>;
444 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
445 reg-shift = <2>;
446 reg-io-width = <4>;
447 clock-frequency = <24000000>;
448 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
449 clock-names = "baudclk", "apb_pclk";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart1_xfer>;
452 status = "disabled";
453 };
454
455 uart2: serial@20068000 {
456 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
457 reg = <0x20068000 0x100>;
458 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
459 reg-shift = <2>;
460 reg-io-width = <4>;
461 clock-frequency = <24000000>;
462 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
463 clock-names = "baudclk", "apb_pclk";
464 pinctrl-names = "default";
465 pinctrl-0 = <&uart2_xfer>;
466 status = "disabled";
467 };
468
469 i2c0: i2c@20072000 {
470 compatible = "rockchip,rk3036-i2c", "rockchip,rk3288-i2c";
471 reg = <0x20072000 0x1000>;
472 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 clock-names = "i2c";
476 clocks = <&cru PCLK_I2C0>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c0_xfer>;
479 status = "disabled";
480 };
481
482 spi: spi@20074000 {
483 compatible = "rockchip,rockchip-spi";
484 reg = <0x20074000 0x1000>;
485 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
486 clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
487 clock-names = "apb-pclk","spi_pclk";
488 dmas = <&pdma 8>, <&pdma 9>;
489 dma-names = "tx", "rx";
490 pinctrl-names = "default";
491 pinctrl-0 = <&spi_txd &spi_rxd &spi_clk &spi_cs0>;
492 #address-cells = <1>;
493 #size-cells = <0>;
494 status = "disabled";
495 };
496
497 pinctrl: pinctrl {
498 compatible = "rockchip,rk3036-pinctrl";
499 rockchip,grf = <&grf>;
500 #address-cells = <1>;
501 #size-cells = <1>;
502 ranges;
503
504 gpio0: gpio0@2007c000 {
505 compatible = "rockchip,gpio-bank";
506 reg = <0x2007c000 0x100>;
507 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru PCLK_GPIO0>;
509
510 gpio-controller;
511 #gpio-cells = <2>;
512
513 interrupt-controller;
514 #interrupt-cells = <2>;
515 };
516
517 gpio1: gpio1@20080000 {
518 compatible = "rockchip,gpio-bank";
519 reg = <0x20080000 0x100>;
520 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&cru PCLK_GPIO1>;
522
523 gpio-controller;
524 #gpio-cells = <2>;
525
526 interrupt-controller;
527 #interrupt-cells = <2>;
528 };
529
530 gpio2: gpio2@20084000 {
531 compatible = "rockchip,gpio-bank";
532 reg = <0x20084000 0x100>;
533 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&cru PCLK_GPIO2>;
535
536 gpio-controller;
537 #gpio-cells = <2>;
538
539 interrupt-controller;
540 #interrupt-cells = <2>;
541 };
542
543 pcfg_pull_default: pcfg_pull_default {
544 bias-pull-pin-default;
545 };
546
547 pcfg_pull_none: pcfg-pull-none {
548 bias-disable;
549 };
550
551 pwm0 {
552 pwm0_pin: pwm0-pin {
553 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
554 };
555 };
556
557 pwm1 {
558 pwm1_pin: pwm1-pin {
559 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
560 };
561 };
562
563 pwm2 {
564 pwm2_pin: pwm2-pin {
565 rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
566 };
567 };
568
569 pwm3 {
570 pwm3_pin: pwm3-pin {
571 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
572 };
573 };
574
575 sdmmc {
576 sdmmc_clk: sdmmc-clk {
577 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
578 };
579
580 sdmmc_cmd: sdmmc-cmd {
581 rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>;
582 };
583
584 sdmmc_cd: sdmmc-cd {
585 rockchip,pins = <1 RK_PC1 1 &pcfg_pull_default>;
586 };
587
588 sdmmc_bus1: sdmmc-bus1 {
589 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>;
590 };
591
592 sdmmc_bus4: sdmmc-bus4 {
593 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>,
594 <1 RK_PC3 1 &pcfg_pull_default>,
595 <1 RK_PC4 1 &pcfg_pull_default>,
596 <1 RK_PC5 1 &pcfg_pull_default>;
597 };
598 };
599
600 sdio {
601 sdio_bus1: sdio-bus1 {
602 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>;
603 };
604
605 sdio_bus4: sdio-bus4 {
606 rockchip,pins = <0 RK_PB3 1 &pcfg_pull_default>,
607 <0 RK_PB4 1 &pcfg_pull_default>,
608 <0 RK_PB5 1 &pcfg_pull_default>,
609 <0 RK_PB6 1 &pcfg_pull_default>;
610 };
611
612 sdio_cmd: sdio-cmd {
613 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_default>;
614 };
615
616 sdio_clk: sdio-clk {
617 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none>;
618 };
619 };
620
621 emmc {
622 /*
623 * We run eMMC at max speed; bump up drive strength.
624 * We also have external pulls, so disable the internal ones.
625 */
626 emmc_clk: emmc-clk {
627 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
628 };
629
630 emmc_cmd: emmc-cmd {
631 rockchip,pins = <2 RK_PA1 2 &pcfg_pull_default>;
632 };
633
634 emmc_bus8: emmc-bus8 {
635 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>,
636 <1 RK_PD1 2 &pcfg_pull_default>,
637 <1 RK_PD2 2 &pcfg_pull_default>,
638 <1 RK_PD3 2 &pcfg_pull_default>,
639 <1 RK_PD4 2 &pcfg_pull_default>,
640 <1 RK_PD5 2 &pcfg_pull_default>,
641 <1 RK_PD6 2 &pcfg_pull_default>,
642 <1 RK_PD7 2 &pcfg_pull_default>;
643 };
644 };
645
646 emac {
647 emac_xfer: emac-xfer {
648 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
649 <2 RK_PB5 1 &pcfg_pull_default>, /* tx_en */
650 <2 RK_PB6 1 &pcfg_pull_default>, /* mac_clk */
651 <2 RK_PB7 1 &pcfg_pull_default>, /* rx_err */
652 <2 RK_PC0 1 &pcfg_pull_default>, /* rxd1 */
653 <2 RK_PC1 1 &pcfg_pull_default>, /* rxd0 */
654 <2 RK_PC2 1 &pcfg_pull_default>, /* txd1 */
655 <2 RK_PC3 1 &pcfg_pull_default>; /* txd0 */
656 };
657
658 emac_mdio: emac-mdio {
659 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_default>, /* mac_md */
660 <2 RK_PD1 1 &pcfg_pull_default>; /* mac_mdclk */
661 };
662 };
663
664 i2c0 {
665 i2c0_xfer: i2c0-xfer {
666 rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>,
667 <0 RK_PA1 1 &pcfg_pull_none>;
668 };
669 };
670
671 i2c1 {
672 i2c1_xfer: i2c1-xfer {
673 rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>,
674 <0 RK_PA3 1 &pcfg_pull_none>;
675 };
676 };
677
678 i2c2 {
679 i2c2_xfer: i2c2-xfer {
680 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>,
681 <2 RK_PC5 1 &pcfg_pull_none>;
682 };
683 };
684
685 i2s {
686 i2s_bus: i2s-bus {
687 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
688 <1 RK_PA1 1 &pcfg_pull_default>,
689 <1 RK_PA2 1 &pcfg_pull_default>,
690 <1 RK_PA3 1 &pcfg_pull_default>,
691 <1 RK_PA4 1 &pcfg_pull_default>,
692 <1 RK_PA5 1 &pcfg_pull_default>;
693 };
694 };
695
696 hdmi {
697 hdmi_ctl: hdmi-ctl {
698 rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
699 <1 RK_PB1 1 &pcfg_pull_none>,
700 <1 RK_PB2 1 &pcfg_pull_none>,
701 <1 RK_PB3 1 &pcfg_pull_none>;
702 };
703 };
704
705 uart0 {
706 uart0_xfer: uart0-xfer {
707 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
708 <0 RK_PC1 1 &pcfg_pull_none>;
709 };
710
711 uart0_cts: uart0-cts {
712 rockchip,pins = <0 RK_PC2 1 &pcfg_pull_default>;
713 };
714
715 uart0_rts: uart0-rts {
716 rockchip,pins = <0 RK_PC3 1 &pcfg_pull_none>;
717 };
718 };
719
720 uart1 {
721 uart1_xfer: uart1-xfer {
722 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
723 <2 RK_PC7 1 &pcfg_pull_none>;
724 };
725 /* no rts / cts for uart1 */
726 };
727
728 uart2 {
729 uart2_xfer: uart2-xfer {
730 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
731 <1 RK_PC3 2 &pcfg_pull_none>;
732 };
733 /* no rts / cts for uart2 */
734 };
735
736 spi-pins {
737 spi_txd:spi-txd {
738 rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
739 };
740
741 spi_rxd:spi-rxd {
742 rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
743 };
744
745 spi_clk:spi-clk {
746 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
747 };
748
749 spi_cs0:spi-cs0 {
750 rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
751
752 };
753
754 spi_cs1:spi-cs1 {
755 rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
756
757 };
758 };
759 };
760};