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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/reset/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7#include <dt-bindings/clock/qcom,rpmcc.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
25 no-map;
26 };
27
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
30 no-map;
31 };
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 CPU0: cpu@0 {
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CPU_SPC>;
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CPU_SPC>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CPU_SPC>;
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 };
86
87 idle-states {
88 CPU_SPC: spc {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
94 };
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x0 0x0>;
101 };
102
103 thermal-zones {
104 cpu-thermal0 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
107
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
131
132 trips {
133 cpu_alert1: trip0 {
134 temperature = <75000>;
135 hysteresis = <2000>;
136 type = "passive";
137 };
138 cpu_crit1: trip1 {
139 temperature = <110000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143 };
144 };
145
146 cpu-thermal2 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
149
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
152
153 trips {
154 cpu_alert2: trip0 {
155 temperature = <75000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159 cpu_crit2: trip1 {
160 temperature = <110000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164 };
165 };
166
167 cpu-thermal3 {
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
170
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
173
174 trips {
175 cpu_alert3: trip0 {
176 temperature = <75000>;
177 hysteresis = <2000>;
178 type = "passive";
179 };
180 cpu_crit3: trip1 {
181 temperature = <110000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186 };
187 };
188
189 cpu-pmu {
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
192 };
193
194 clocks {
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <19200000>;
199 };
200
201 pxo_board {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <27000000>;
205 };
206
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-frequency = <32768>;
211 };
212 };
213
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
217 #hwlock-cells = <1>;
218 };
219
220 smem {
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
223
224 hwlocks = <&sfpb_mutex 3>;
225 };
226
227 smd {
228 compatible = "qcom,smd";
229
230 modem@0 {
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
232
233 qcom,ipc = <&l2cc 8 3>;
234 qcom,smd-edge = <0>;
235
236 status = "disabled";
237 };
238
239 q6@1 {
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
241
242 qcom,ipc = <&l2cc 8 15>;
243 qcom,smd-edge = <1>;
244
245 status = "disabled";
246 };
247
248 dsps@3 {
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
250
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252 qcom,smd-edge = <3>;
253
254 status = "disabled";
255 };
256
257 riva@6 {
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
259
260 qcom,ipc = <&l2cc 8 25>;
261 qcom,smd-edge = <6>;
262
263 status = "disabled";
264 };
265 };
266
267 smsm {
268 compatible = "qcom,smsm";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
277
278 apps_smsm: apps@0 {
279 reg = <0>;
280 #qcom,smem-state-cells = <1>;
281 };
282
283 modem_smsm: modem@1 {
284 reg = <1>;
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
286
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 q6_smsm: q6@2 {
292 reg = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
294
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
298
299 wcnss_smsm: wcnss@3 {
300 reg = <3>;
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 dsps_smsm: dsps@4 {
308 reg = <4>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
310
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314 };
315
316 firmware {
317 scm {
318 compatible = "qcom,scm-apq8064";
319
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
322 };
323 };
324
325
326 /*
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
329 * ADC.
330 */
331 iio-hwmon {
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
340 };
341
342 soc: soc {
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346 compatible = "simple-bus";
347
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
351
352 gpio-controller;
353 gpio-ranges = <&tlmm_pinmux 0 0 90>;
354 #gpio-cells = <2>;
355 interrupt-controller;
356 #interrupt-cells = <2>;
357 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
358
359 pinctrl-names = "default";
360 pinctrl-0 = <&ps_hold>;
361 };
362
363 sfpb_wrapper_mutex: syscon@1200000 {
364 compatible = "syscon";
365 reg = <0x01200000 0x8000>;
366 };
367
368 intc: interrupt-controller@2000000 {
369 compatible = "qcom,msm-qgic2";
370 interrupt-controller;
371 #interrupt-cells = <3>;
372 reg = <0x02000000 0x1000>,
373 <0x02002000 0x1000>;
374 };
375
376 timer@200a000 {
377 compatible = "qcom,kpss-timer",
378 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
379 interrupts = <1 1 0x301>,
380 <1 2 0x301>,
381 <1 3 0x301>;
382 reg = <0x0200a000 0x100>;
383 clock-frequency = <27000000>,
384 <32768>;
385 cpu-offset = <0x80000>;
386 };
387
388 acc0: clock-controller@2088000 {
389 compatible = "qcom,kpss-acc-v1";
390 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
391 };
392
393 acc1: clock-controller@2098000 {
394 compatible = "qcom,kpss-acc-v1";
395 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
396 };
397
398 acc2: clock-controller@20a8000 {
399 compatible = "qcom,kpss-acc-v1";
400 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
401 };
402
403 acc3: clock-controller@20b8000 {
404 compatible = "qcom,kpss-acc-v1";
405 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
406 };
407
408 saw0: power-controller@2089000 {
409 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
410 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
411 regulator;
412 };
413
414 saw1: power-controller@2099000 {
415 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
416 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
417 regulator;
418 };
419
420 saw2: power-controller@20a9000 {
421 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
422 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
423 regulator;
424 };
425
426 saw3: power-controller@20b9000 {
427 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
428 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
429 regulator;
430 };
431
432 sps_sic_non_secure: sps-sic-non-secure@12100000 {
433 compatible = "syscon";
434 reg = <0x12100000 0x10000>;
435 };
436
437 gsbi1: gsbi@12440000 {
438 status = "disabled";
439 compatible = "qcom,gsbi-v1.0.0";
440 cell-index = <1>;
441 reg = <0x12440000 0x100>;
442 clocks = <&gcc GSBI1_H_CLK>;
443 clock-names = "iface";
444 #address-cells = <1>;
445 #size-cells = <1>;
446 ranges;
447
448 syscon-tcsr = <&tcsr>;
449
450 gsbi1_serial: serial@12450000 {
451 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
452 reg = <0x12450000 0x100>,
453 <0x12400000 0x03>;
454 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
456 clock-names = "core", "iface";
457 status = "disabled";
458 };
459
460 gsbi1_i2c: i2c@12460000 {
461 compatible = "qcom,i2c-qup-v1.1.1";
462 pinctrl-0 = <&i2c1_pins>;
463 pinctrl-1 = <&i2c1_pins_sleep>;
464 pinctrl-names = "default", "sleep";
465 reg = <0x12460000 0x1000>;
466 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
468 clock-names = "core", "iface";
469 #address-cells = <1>;
470 #size-cells = <0>;
471 status = "disabled";
472 };
473
474 };
475
476 gsbi2: gsbi@12480000 {
477 status = "disabled";
478 compatible = "qcom,gsbi-v1.0.0";
479 cell-index = <2>;
480 reg = <0x12480000 0x100>;
481 clocks = <&gcc GSBI2_H_CLK>;
482 clock-names = "iface";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges;
486
487 syscon-tcsr = <&tcsr>;
488
489 gsbi2_i2c: i2c@124a0000 {
490 compatible = "qcom,i2c-qup-v1.1.1";
491 reg = <0x124a0000 0x1000>;
492 pinctrl-0 = <&i2c2_pins>;
493 pinctrl-1 = <&i2c2_pins_sleep>;
494 pinctrl-names = "default", "sleep";
495 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
497 clock-names = "core", "iface";
498 #address-cells = <1>;
499 #size-cells = <0>;
500 status = "disabled";
501 };
502 };
503
504 gsbi3: gsbi@16200000 {
505 status = "disabled";
506 compatible = "qcom,gsbi-v1.0.0";
507 cell-index = <3>;
508 reg = <0x16200000 0x100>;
509 clocks = <&gcc GSBI3_H_CLK>;
510 clock-names = "iface";
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges;
514 gsbi3_i2c: i2c@16280000 {
515 compatible = "qcom,i2c-qup-v1.1.1";
516 pinctrl-0 = <&i2c3_pins>;
517 pinctrl-1 = <&i2c3_pins_sleep>;
518 pinctrl-names = "default", "sleep";
519 reg = <0x16280000 0x1000>;
520 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&gcc GSBI3_QUP_CLK>,
522 <&gcc GSBI3_H_CLK>;
523 clock-names = "core", "iface";
524 #address-cells = <1>;
525 #size-cells = <0>;
526 status = "disabled";
527 };
528 };
529
530 gsbi4: gsbi@16300000 {
531 status = "disabled";
532 compatible = "qcom,gsbi-v1.0.0";
533 cell-index = <4>;
534 reg = <0x16300000 0x03>;
535 clocks = <&gcc GSBI4_H_CLK>;
536 clock-names = "iface";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges;
540
541 gsbi4_i2c: i2c@16380000 {
542 compatible = "qcom,i2c-qup-v1.1.1";
543 pinctrl-0 = <&i2c4_pins>;
544 pinctrl-1 = <&i2c4_pins_sleep>;
545 pinctrl-names = "default", "sleep";
546 reg = <0x16380000 0x1000>;
547 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&gcc GSBI4_QUP_CLK>,
549 <&gcc GSBI4_H_CLK>;
550 clock-names = "core", "iface";
551 status = "disabled";
552 };
553 };
554
555 gsbi5: gsbi@1a200000 {
556 status = "disabled";
557 compatible = "qcom,gsbi-v1.0.0";
558 cell-index = <5>;
559 reg = <0x1a200000 0x03>;
560 clocks = <&gcc GSBI5_H_CLK>;
561 clock-names = "iface";
562 #address-cells = <1>;
563 #size-cells = <1>;
564 ranges;
565
566 gsbi5_serial: serial@1a240000 {
567 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
568 reg = <0x1a240000 0x100>,
569 <0x1a200000 0x03>;
570 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
572 clock-names = "core", "iface";
573 status = "disabled";
574 };
575
576 gsbi5_spi: spi@1a280000 {
577 compatible = "qcom,spi-qup-v1.1.1";
578 reg = <0x1a280000 0x1000>;
579 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-0 = <&spi5_default>;
581 pinctrl-1 = <&spi5_sleep>;
582 pinctrl-names = "default", "sleep";
583 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
584 clock-names = "core", "iface";
585 status = "disabled";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 };
589 };
590
591 gsbi6: gsbi@16500000 {
592 status = "disabled";
593 compatible = "qcom,gsbi-v1.0.0";
594 cell-index = <6>;
595 reg = <0x16500000 0x03>;
596 clocks = <&gcc GSBI6_H_CLK>;
597 clock-names = "iface";
598 #address-cells = <1>;
599 #size-cells = <1>;
600 ranges;
601
602 gsbi6_serial: serial@16540000 {
603 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
604 reg = <0x16540000 0x100>,
605 <0x16500000 0x03>;
606 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
608 clock-names = "core", "iface";
609 status = "disabled";
610 };
611
612 gsbi6_i2c: i2c@16580000 {
613 compatible = "qcom,i2c-qup-v1.1.1";
614 pinctrl-0 = <&i2c6_pins>;
615 pinctrl-1 = <&i2c6_pins_sleep>;
616 pinctrl-names = "default", "sleep";
617 reg = <0x16580000 0x1000>;
618 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&gcc GSBI6_QUP_CLK>,
620 <&gcc GSBI6_H_CLK>;
621 clock-names = "core", "iface";
622 status = "disabled";
623 };
624 };
625
626 gsbi7: gsbi@16600000 {
627 status = "disabled";
628 compatible = "qcom,gsbi-v1.0.0";
629 cell-index = <7>;
630 reg = <0x16600000 0x100>;
631 clocks = <&gcc GSBI7_H_CLK>;
632 clock-names = "iface";
633 #address-cells = <1>;
634 #size-cells = <1>;
635 ranges;
636 syscon-tcsr = <&tcsr>;
637
638 gsbi7_serial: serial@16640000 {
639 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
640 reg = <0x16640000 0x1000>,
641 <0x16600000 0x1000>;
642 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
644 clock-names = "core", "iface";
645 status = "disabled";
646 };
647
648 gsbi7_i2c: i2c@16680000 {
649 compatible = "qcom,i2c-qup-v1.1.1";
650 pinctrl-0 = <&i2c7_pins>;
651 pinctrl-1 = <&i2c7_pins_sleep>;
652 pinctrl-names = "default", "sleep";
653 reg = <0x16680000 0x1000>;
654 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&gcc GSBI7_QUP_CLK>,
656 <&gcc GSBI7_H_CLK>;
657 clock-names = "core", "iface";
658 status = "disabled";
659 };
660 };
661
662 rng@1a500000 {
663 compatible = "qcom,prng";
664 reg = <0x1a500000 0x200>;
665 clocks = <&gcc PRNG_CLK>;
666 clock-names = "core";
667 };
668
669 ssbi@c00000 {
670 compatible = "qcom,ssbi";
671 reg = <0x00c00000 0x1000>;
672 qcom,controller-type = "pmic-arbiter";
673
674 pm8821: pmic@1 {
675 compatible = "qcom,pm8821";
676 interrupt-parent = <&tlmm_pinmux>;
677 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
678 #interrupt-cells = <2>;
679 interrupt-controller;
680 #address-cells = <1>;
681 #size-cells = <0>;
682
683 pm8821_mpps: mpps@50 {
684 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
685 reg = <0x50>;
686 interrupts = <24 IRQ_TYPE_NONE>,
687 <25 IRQ_TYPE_NONE>,
688 <26 IRQ_TYPE_NONE>,
689 <27 IRQ_TYPE_NONE>;
690 gpio-controller;
691 #gpio-cells = <2>;
692 };
693 };
694 };
695
696 qcom,ssbi@500000 {
697 compatible = "qcom,ssbi";
698 reg = <0x00500000 0x1000>;
699 qcom,controller-type = "pmic-arbiter";
700
701 pmicintc: pmic@0 {
702 compatible = "qcom,pm8921";
703 interrupt-parent = <&tlmm_pinmux>;
704 interrupts = <74 8>;
705 #interrupt-cells = <2>;
706 interrupt-controller;
707 #address-cells = <1>;
708 #size-cells = <0>;
709
710 pm8921_gpio: gpio@150 {
711
712 compatible = "qcom,pm8921-gpio",
713 "qcom,ssbi-gpio";
714 reg = <0x150>;
715 interrupt-controller;
716 #interrupt-cells = <2>;
717 gpio-controller;
718 gpio-ranges = <&pm8921_gpio 0 0 44>;
719 #gpio-cells = <2>;
720
721 };
722
723 pm8921_mpps: mpps@50 {
724 compatible = "qcom,pm8921-mpp",
725 "qcom,ssbi-mpp";
726 reg = <0x50>;
727 gpio-controller;
728 #gpio-cells = <2>;
729 interrupts =
730 <128 IRQ_TYPE_NONE>,
731 <129 IRQ_TYPE_NONE>,
732 <130 IRQ_TYPE_NONE>,
733 <131 IRQ_TYPE_NONE>,
734 <132 IRQ_TYPE_NONE>,
735 <133 IRQ_TYPE_NONE>,
736 <134 IRQ_TYPE_NONE>,
737 <135 IRQ_TYPE_NONE>,
738 <136 IRQ_TYPE_NONE>,
739 <137 IRQ_TYPE_NONE>,
740 <138 IRQ_TYPE_NONE>,
741 <139 IRQ_TYPE_NONE>;
742 };
743
744 rtc@11d {
745 compatible = "qcom,pm8921-rtc";
746 interrupt-parent = <&pmicintc>;
747 interrupts = <39 1>;
748 reg = <0x11d>;
749 allow-set-time;
750 };
751
752 pwrkey@1c {
753 compatible = "qcom,pm8921-pwrkey";
754 reg = <0x1c>;
755 interrupt-parent = <&pmicintc>;
756 interrupts = <50 1>, <51 1>;
757 debounce = <15625>;
758 pull-up;
759 };
760
761 xoadc: xoadc@197 {
762 compatible = "qcom,pm8921-adc";
763 reg = <197>;
764 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
765 #address-cells = <2>;
766 #size-cells = <0>;
767 #io-channel-cells = <2>;
768
769 vcoin: adc-channel@00 {
770 reg = <0x00 0x00>;
771 };
772 vbat: adc-channel@01 {
773 reg = <0x00 0x01>;
774 };
775 dcin: adc-channel@02 {
776 reg = <0x00 0x02>;
777 };
778 vph_pwr: adc-channel@04 {
779 reg = <0x00 0x04>;
780 };
781 batt_therm: adc-channel@08 {
782 reg = <0x00 0x08>;
783 };
784 batt_id: adc-channel@09 {
785 reg = <0x00 0x09>;
786 };
787 usb_vbus: adc-channel@0a {
788 reg = <0x00 0x0a>;
789 };
790 die_temp: adc-channel@0b {
791 reg = <0x00 0x0b>;
792 };
793 ref_625mv: adc-channel@0c {
794 reg = <0x00 0x0c>;
795 };
796 ref_1250mv: adc-channel@0d {
797 reg = <0x00 0x0d>;
798 };
799 chg_temp: adc-channel@0e {
800 reg = <0x00 0x0e>;
801 };
802 ref_muxoff: adc-channel@0f {
803 reg = <0x00 0x0f>;
804 };
805 };
806 };
807 };
808
809 qfprom: qfprom@700000 {
810 compatible = "qcom,qfprom";
811 reg = <0x00700000 0x1000>;
812 #address-cells = <1>;
813 #size-cells = <1>;
814 ranges;
815 tsens_calib: calib {
816 reg = <0x404 0x10>;
817 };
818 tsens_backup: backup_calib {
819 reg = <0x414 0x10>;
820 };
821 };
822
823 gcc: clock-controller@900000 {
824 compatible = "qcom,gcc-apq8064";
825 reg = <0x00900000 0x4000>;
826 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
827 nvmem-cell-names = "calib", "calib_backup";
828 #clock-cells = <1>;
829 #reset-cells = <1>;
830 #thermal-sensor-cells = <1>;
831 };
832
833 lcc: clock-controller@28000000 {
834 compatible = "qcom,lcc-apq8064";
835 reg = <0x28000000 0x1000>;
836 #clock-cells = <1>;
837 #reset-cells = <1>;
838 };
839
840 mmcc: clock-controller@4000000 {
841 compatible = "qcom,mmcc-apq8064";
842 reg = <0x4000000 0x1000>;
843 #clock-cells = <1>;
844 #reset-cells = <1>;
845 };
846
847 l2cc: clock-controller@2011000 {
848 compatible = "syscon";
849 reg = <0x2011000 0x1000>;
850 };
851
852 rpm@108000 {
853 compatible = "qcom,rpm-apq8064";
854 reg = <0x108000 0x1000>;
855 qcom,ipc = <&l2cc 0x8 2>;
856
857 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
858 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
859 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
860 interrupt-names = "ack", "err", "wakeup";
861
862 rpmcc: clock-controller {
863 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
864 #clock-cells = <1>;
865 };
866
867 regulators {
868 compatible = "qcom,rpm-pm8921-regulators";
869
870 pm8921_s1: s1 {};
871 pm8921_s2: s2 {};
872 pm8921_s3: s3 {};
873 pm8921_s4: s4 {};
874 pm8921_s7: s7 {};
875 pm8921_s8: s8 {};
876
877 pm8921_l1: l1 {};
878 pm8921_l2: l2 {};
879 pm8921_l3: l3 {};
880 pm8921_l4: l4 {};
881 pm8921_l5: l5 {};
882 pm8921_l6: l6 {};
883 pm8921_l7: l7 {};
884 pm8921_l8: l8 {};
885 pm8921_l9: l9 {};
886 pm8921_l10: l10 {};
887 pm8921_l11: l11 {};
888 pm8921_l12: l12 {};
889 pm8921_l14: l14 {};
890 pm8921_l15: l15 {};
891 pm8921_l16: l16 {};
892 pm8921_l17: l17 {};
893 pm8921_l18: l18 {};
894 pm8921_l21: l21 {};
895 pm8921_l22: l22 {};
896 pm8921_l23: l23 {};
897 pm8921_l24: l24 {};
898 pm8921_l25: l25 {};
899 pm8921_l26: l26 {};
900 pm8921_l27: l27 {};
901 pm8921_l28: l28 {};
902 pm8921_l29: l29 {};
903
904 pm8921_lvs1: lvs1 {};
905 pm8921_lvs2: lvs2 {};
906 pm8921_lvs3: lvs3 {};
907 pm8921_lvs4: lvs4 {};
908 pm8921_lvs5: lvs5 {};
909 pm8921_lvs6: lvs6 {};
910 pm8921_lvs7: lvs7 {};
911
912 pm8921_usb_switch: usb-switch {};
913
914 pm8921_hdmi_switch: hdmi-switch {
915 bias-pull-down;
916 };
917
918 pm8921_ncp: ncp {};
919 };
920 };
921
922 usb1: usb@12500000 {
923 compatible = "qcom,ci-hdrc";
924 reg = <0x12500000 0x200>,
925 <0x12500200 0x200>;
926 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
927 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
928 clock-names = "core", "iface";
929 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
930 assigned-clock-rates = <60000000>;
931 resets = <&gcc USB_HS1_RESET>;
932 reset-names = "core";
933 phy_type = "ulpi";
934 ahb-burst-config = <0>;
935 phys = <&usb_hs1_phy>;
936 phy-names = "usb-phy";
937 status = "disabled";
938 #reset-cells = <1>;
939
940 ulpi {
941 usb_hs1_phy: phy {
942 compatible = "qcom,usb-hs-phy-apq8064",
943 "qcom,usb-hs-phy";
944 clocks = <&sleep_clk>, <&cxo_board>;
945 clock-names = "sleep", "ref";
946 resets = <&usb1 0>;
947 reset-names = "por";
948 #phy-cells = <0>;
949 };
950 };
951 };
952
953 usb3: usb@12520000 {
954 compatible = "qcom,ci-hdrc";
955 reg = <0x12520000 0x200>,
956 <0x12520200 0x200>;
957 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
959 clock-names = "core", "iface";
960 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
961 assigned-clock-rates = <60000000>;
962 resets = <&gcc USB_HS3_RESET>;
963 reset-names = "core";
964 phy_type = "ulpi";
965 ahb-burst-config = <0>;
966 phys = <&usb_hs3_phy>;
967 phy-names = "usb-phy";
968 status = "disabled";
969 #reset-cells = <1>;
970
971 ulpi {
972 usb_hs3_phy: phy {
973 compatible = "qcom,usb-hs-phy-apq8064",
974 "qcom,usb-hs-phy";
975 #phy-cells = <0>;
976 clocks = <&sleep_clk>, <&cxo_board>;
977 clock-names = "sleep", "ref";
978 resets = <&usb3 0>;
979 reset-names = "por";
980 };
981 };
982 };
983
984 usb4: usb@12530000 {
985 compatible = "qcom,ci-hdrc";
986 reg = <0x12530000 0x200>,
987 <0x12530200 0x200>;
988 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
990 clock-names = "core", "iface";
991 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
992 assigned-clock-rates = <60000000>;
993 resets = <&gcc USB_HS4_RESET>;
994 reset-names = "core";
995 phy_type = "ulpi";
996 ahb-burst-config = <0>;
997 phys = <&usb_hs4_phy>;
998 phy-names = "usb-phy";
999 status = "disabled";
1000 #reset-cells = <1>;
1001
1002 ulpi {
1003 usb_hs4_phy: phy {
1004 compatible = "qcom,usb-hs-phy-apq8064",
1005 "qcom,usb-hs-phy";
1006 #phy-cells = <0>;
1007 clocks = <&sleep_clk>, <&cxo_board>;
1008 clock-names = "sleep", "ref";
1009 resets = <&usb4 0>;
1010 reset-names = "por";
1011 };
1012 };
1013 };
1014
1015 sata_phy0: phy@1b400000 {
1016 compatible = "qcom,apq8064-sata-phy";
1017 status = "disabled";
1018 reg = <0x1b400000 0x200>;
1019 reg-names = "phy_mem";
1020 clocks = <&gcc SATA_PHY_CFG_CLK>;
1021 clock-names = "cfg";
1022 #phy-cells = <0>;
1023 };
1024
1025 sata0: sata@29000000 {
1026 compatible = "qcom,apq8064-ahci", "generic-ahci";
1027 status = "disabled";
1028 reg = <0x29000000 0x180>;
1029 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1030
1031 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1032 <&gcc SATA_H_CLK>,
1033 <&gcc SATA_A_CLK>,
1034 <&gcc SATA_RXOOB_CLK>,
1035 <&gcc SATA_PMALIVE_CLK>;
1036 clock-names = "slave_iface",
1037 "iface",
1038 "bus",
1039 "rxoob",
1040 "core_pmalive";
1041
1042 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1043 <&gcc SATA_PMALIVE_CLK>;
1044 assigned-clock-rates = <100000000>, <100000000>;
1045
1046 phys = <&sata_phy0>;
1047 phy-names = "sata-phy";
1048 ports-implemented = <0x1>;
1049 };
1050
1051 /* Temporary fixed regulator */
1052 sdcc1bam:dma@12402000{
1053 compatible = "qcom,bam-v1.3.0";
1054 reg = <0x12402000 0x8000>;
1055 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&gcc SDC1_H_CLK>;
1057 clock-names = "bam_clk";
1058 #dma-cells = <1>;
1059 qcom,ee = <0>;
1060 };
1061
1062 sdcc3bam:dma@12182000{
1063 compatible = "qcom,bam-v1.3.0";
1064 reg = <0x12182000 0x8000>;
1065 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&gcc SDC3_H_CLK>;
1067 clock-names = "bam_clk";
1068 #dma-cells = <1>;
1069 qcom,ee = <0>;
1070 };
1071
1072 sdcc4bam:dma@121c2000{
1073 compatible = "qcom,bam-v1.3.0";
1074 reg = <0x121c2000 0x8000>;
1075 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&gcc SDC4_H_CLK>;
1077 clock-names = "bam_clk";
1078 #dma-cells = <1>;
1079 qcom,ee = <0>;
1080 };
1081
1082 amba {
1083 compatible = "simple-bus";
1084 #address-cells = <1>;
1085 #size-cells = <1>;
1086 ranges;
1087 sdcc1: sdcc@12400000 {
1088 status = "disabled";
1089 compatible = "arm,pl18x", "arm,primecell";
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&sdcc1_pins>;
1092 arm,primecell-periphid = <0x00051180>;
1093 reg = <0x12400000 0x2000>;
1094 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1095 interrupt-names = "cmd_irq";
1096 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1097 clock-names = "mclk", "apb_pclk";
1098 bus-width = <8>;
1099 max-frequency = <96000000>;
1100 non-removable;
1101 cap-sd-highspeed;
1102 cap-mmc-highspeed;
1103 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1104 dma-names = "tx", "rx";
1105 };
1106
1107 sdcc3: sdcc@12180000 {
1108 compatible = "arm,pl18x", "arm,primecell";
1109 arm,primecell-periphid = <0x00051180>;
1110 status = "disabled";
1111 reg = <0x12180000 0x2000>;
1112 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1113 interrupt-names = "cmd_irq";
1114 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1115 clock-names = "mclk", "apb_pclk";
1116 bus-width = <4>;
1117 cap-sd-highspeed;
1118 cap-mmc-highspeed;
1119 max-frequency = <192000000>;
1120 no-1-8-v;
1121 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1122 dma-names = "tx", "rx";
1123 };
1124
1125 sdcc4: sdcc@121c0000 {
1126 compatible = "arm,pl18x", "arm,primecell";
1127 arm,primecell-periphid = <0x00051180>;
1128 status = "disabled";
1129 reg = <0x121c0000 0x2000>;
1130 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1131 interrupt-names = "cmd_irq";
1132 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1133 clock-names = "mclk", "apb_pclk";
1134 bus-width = <4>;
1135 cap-sd-highspeed;
1136 cap-mmc-highspeed;
1137 max-frequency = <48000000>;
1138 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1139 dma-names = "tx", "rx";
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&sdc4_gpios>;
1142 };
1143 };
1144
1145 tcsr: syscon@1a400000 {
1146 compatible = "qcom,tcsr-apq8064", "syscon";
1147 reg = <0x1a400000 0x100>;
1148 };
1149
1150 gpu: adreno-3xx@4300000 {
1151 compatible = "qcom,adreno-3xx";
1152 reg = <0x04300000 0x20000>;
1153 reg-names = "kgsl_3d0_reg_memory";
1154 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "kgsl_3d0_irq";
1156 clock-names =
1157 "core_clk",
1158 "iface_clk",
1159 "mem_clk",
1160 "mem_iface_clk";
1161 clocks =
1162 <&mmcc GFX3D_CLK>,
1163 <&mmcc GFX3D_AHB_CLK>,
1164 <&mmcc GFX3D_AXI_CLK>,
1165 <&mmcc MMSS_IMEM_AHB_CLK>;
1166 qcom,chipid = <0x03020002>;
1167
1168 iommus = <&gfx3d 0
1169 &gfx3d 1
1170 &gfx3d 2
1171 &gfx3d 3
1172 &gfx3d 4
1173 &gfx3d 5
1174 &gfx3d 6
1175 &gfx3d 7
1176 &gfx3d 8
1177 &gfx3d 9
1178 &gfx3d 10
1179 &gfx3d 11
1180 &gfx3d 12
1181 &gfx3d 13
1182 &gfx3d 14
1183 &gfx3d 15
1184 &gfx3d 16
1185 &gfx3d 17
1186 &gfx3d 18
1187 &gfx3d 19
1188 &gfx3d 20
1189 &gfx3d 21
1190 &gfx3d 22
1191 &gfx3d 23
1192 &gfx3d 24
1193 &gfx3d 25
1194 &gfx3d 26
1195 &gfx3d 27
1196 &gfx3d 28
1197 &gfx3d 29
1198 &gfx3d 30
1199 &gfx3d 31
1200 &gfx3d1 0
1201 &gfx3d1 1
1202 &gfx3d1 2
1203 &gfx3d1 3
1204 &gfx3d1 4
1205 &gfx3d1 5
1206 &gfx3d1 6
1207 &gfx3d1 7
1208 &gfx3d1 8
1209 &gfx3d1 9
1210 &gfx3d1 10
1211 &gfx3d1 11
1212 &gfx3d1 12
1213 &gfx3d1 13
1214 &gfx3d1 14
1215 &gfx3d1 15
1216 &gfx3d1 16
1217 &gfx3d1 17
1218 &gfx3d1 18
1219 &gfx3d1 19
1220 &gfx3d1 20
1221 &gfx3d1 21
1222 &gfx3d1 22
1223 &gfx3d1 23
1224 &gfx3d1 24
1225 &gfx3d1 25
1226 &gfx3d1 26
1227 &gfx3d1 27
1228 &gfx3d1 28
1229 &gfx3d1 29
1230 &gfx3d1 30
1231 &gfx3d1 31>;
1232
1233 qcom,gpu-pwrlevels {
1234 compatible = "qcom,gpu-pwrlevels";
1235 qcom,gpu-pwrlevel@0 {
1236 qcom,gpu-freq = <450000000>;
1237 };
1238 qcom,gpu-pwrlevel@1 {
1239 qcom,gpu-freq = <27000000>;
1240 };
1241 };
1242 };
1243
1244 mmss_sfpb: syscon@5700000 {
1245 compatible = "syscon";
1246 reg = <0x5700000 0x70>;
1247 };
1248
1249 dsi0: mdss_dsi@4700000 {
1250 compatible = "qcom,mdss-dsi-ctrl";
1251 label = "MDSS DSI CTRL->0";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1255 reg = <0x04700000 0x200>;
1256 reg-names = "dsi_ctrl";
1257
1258 clocks = <&mmcc DSI_M_AHB_CLK>,
1259 <&mmcc DSI_S_AHB_CLK>,
1260 <&mmcc AMP_AHB_CLK>,
1261 <&mmcc DSI_CLK>,
1262 <&mmcc DSI1_BYTE_CLK>,
1263 <&mmcc DSI_PIXEL_CLK>,
1264 <&mmcc DSI1_ESC_CLK>;
1265 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1266 "src_clk", "byte_clk", "pixel_clk",
1267 "core_clk";
1268
1269 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1270 <&mmcc DSI1_ESC_SRC>,
1271 <&mmcc DSI_SRC>,
1272 <&mmcc DSI_PIXEL_SRC>;
1273 assigned-clock-parents = <&dsi0_phy 0>,
1274 <&dsi0_phy 0>,
1275 <&dsi0_phy 1>,
1276 <&dsi0_phy 1>;
1277 syscon-sfpb = <&mmss_sfpb>;
1278 phys = <&dsi0_phy>;
1279 ports {
1280 #address-cells = <1>;
1281 #size-cells = <0>;
1282
1283 port@0 {
1284 reg = <0>;
1285 dsi0_in: endpoint {
1286 };
1287 };
1288
1289 port@1 {
1290 reg = <1>;
1291 dsi0_out: endpoint {
1292 };
1293 };
1294 };
1295 };
1296
1297
1298 dsi0_phy: dsi-phy@4700200 {
1299 compatible = "qcom,dsi-phy-28nm-8960";
1300 #clock-cells = <1>;
1301 #phy-cells = <0>;
1302
1303 reg = <0x04700200 0x100>,
1304 <0x04700300 0x200>,
1305 <0x04700500 0x5c>;
1306 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1307 clock-names = "iface_clk", "ref";
1308 clocks = <&mmcc DSI_M_AHB_CLK>,
1309 <&cxo_board>;
1310 };
1311
1312
1313 mdp_port0: iommu@7500000 {
1314 compatible = "qcom,apq8064-iommu";
1315 #iommu-cells = <1>;
1316 clock-names =
1317 "smmu_pclk",
1318 "iommu_clk";
1319 clocks =
1320 <&mmcc SMMU_AHB_CLK>,
1321 <&mmcc MDP_AXI_CLK>;
1322 reg = <0x07500000 0x100000>;
1323 interrupts =
1324 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1325 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1326 qcom,ncb = <2>;
1327 };
1328
1329 mdp_port1: iommu@7600000 {
1330 compatible = "qcom,apq8064-iommu";
1331 #iommu-cells = <1>;
1332 clock-names =
1333 "smmu_pclk",
1334 "iommu_clk";
1335 clocks =
1336 <&mmcc SMMU_AHB_CLK>,
1337 <&mmcc MDP_AXI_CLK>;
1338 reg = <0x07600000 0x100000>;
1339 interrupts =
1340 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1341 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1342 qcom,ncb = <2>;
1343 };
1344
1345 gfx3d: iommu@7c00000 {
1346 compatible = "qcom,apq8064-iommu";
1347 #iommu-cells = <1>;
1348 clock-names =
1349 "smmu_pclk",
1350 "iommu_clk";
1351 clocks =
1352 <&mmcc SMMU_AHB_CLK>,
1353 <&mmcc GFX3D_AXI_CLK>;
1354 reg = <0x07c00000 0x100000>;
1355 interrupts =
1356 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1358 qcom,ncb = <3>;
1359 };
1360
1361 gfx3d1: iommu@7d00000 {
1362 compatible = "qcom,apq8064-iommu";
1363 #iommu-cells = <1>;
1364 clock-names =
1365 "smmu_pclk",
1366 "iommu_clk";
1367 clocks =
1368 <&mmcc SMMU_AHB_CLK>,
1369 <&mmcc GFX3D_AXI_CLK>;
1370 reg = <0x07d00000 0x100000>;
1371 interrupts =
1372 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1374 qcom,ncb = <3>;
1375 };
1376
1377 pcie: pci@1b500000 {
1378 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1379 reg = <0x1b500000 0x1000
1380 0x1b502000 0x80
1381 0x1b600000 0x100
1382 0x0ff00000 0x100000>;
1383 reg-names = "dbi", "elbi", "parf", "config";
1384 device_type = "pci";
1385 linux,pci-domain = <0>;
1386 bus-range = <0x00 0xff>;
1387 num-lanes = <1>;
1388 #address-cells = <3>;
1389 #size-cells = <2>;
1390 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1391 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1392 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1393 interrupt-names = "msi";
1394 #interrupt-cells = <1>;
1395 interrupt-map-mask = <0 0 0 0x7>;
1396 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1397 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1398 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1399 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1400 clocks = <&gcc PCIE_A_CLK>,
1401 <&gcc PCIE_H_CLK>,
1402 <&gcc PCIE_PHY_REF_CLK>;
1403 clock-names = "core", "iface", "phy";
1404 resets = <&gcc PCIE_ACLK_RESET>,
1405 <&gcc PCIE_HCLK_RESET>,
1406 <&gcc PCIE_POR_RESET>,
1407 <&gcc PCIE_PCI_RESET>,
1408 <&gcc PCIE_PHY_RESET>;
1409 reset-names = "axi", "ahb", "por", "pci", "phy";
1410 status = "disabled";
1411 };
1412
1413 hdmi: hdmi-tx@4a00000 {
1414 compatible = "qcom,hdmi-tx-8960";
1415 pinctrl-names = "default";
1416 pinctrl-0 = <&hdmi_pinctrl>;
1417 reg = <0x04a00000 0x2f0>;
1418 reg-names = "core_physical";
1419 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1420 clocks = <&mmcc HDMI_APP_CLK>,
1421 <&mmcc HDMI_M_AHB_CLK>,
1422 <&mmcc HDMI_S_AHB_CLK>;
1423 clock-names = "core_clk",
1424 "master_iface_clk",
1425 "slave_iface_clk";
1426
1427 phys = <&hdmi_phy>;
1428 phy-names = "hdmi-phy";
1429
1430 ports {
1431 #address-cells = <1>;
1432 #size-cells = <0>;
1433
1434 port@0 {
1435 reg = <0>;
1436 hdmi_in: endpoint {
1437 };
1438 };
1439
1440 port@1 {
1441 reg = <1>;
1442 hdmi_out: endpoint {
1443 };
1444 };
1445 };
1446 };
1447
1448 hdmi_phy: hdmi-phy@4a00400 {
1449 compatible = "qcom,hdmi-phy-8960";
1450 reg = <0x4a00400 0x60>,
1451 <0x4a00500 0x100>;
1452 reg-names = "hdmi_phy",
1453 "hdmi_pll";
1454
1455 clocks = <&mmcc HDMI_S_AHB_CLK>;
1456 clock-names = "slave_iface_clk";
1457 #phy-cells = <0>;
1458 };
1459
1460 mdp: mdp@5100000 {
1461 compatible = "qcom,mdp4";
1462 reg = <0x05100000 0xf0000>;
1463 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&mmcc MDP_CLK>,
1465 <&mmcc MDP_AHB_CLK>,
1466 <&mmcc MDP_AXI_CLK>,
1467 <&mmcc MDP_LUT_CLK>,
1468 <&mmcc HDMI_TV_CLK>,
1469 <&mmcc MDP_TV_CLK>;
1470 clock-names = "core_clk",
1471 "iface_clk",
1472 "bus_clk",
1473 "lut_clk",
1474 "hdmi_clk",
1475 "tv_clk";
1476
1477 iommus = <&mdp_port0 0
1478 &mdp_port0 2
1479 &mdp_port1 0
1480 &mdp_port1 2>;
1481
1482 ports {
1483 #address-cells = <1>;
1484 #size-cells = <0>;
1485
1486 port@0 {
1487 reg = <0>;
1488 mdp_lvds_out: endpoint {
1489 };
1490 };
1491
1492 port@1 {
1493 reg = <1>;
1494 mdp_dsi1_out: endpoint {
1495 };
1496 };
1497
1498 port@2 {
1499 reg = <2>;
1500 mdp_dsi2_out: endpoint {
1501 };
1502 };
1503
1504 port@3 {
1505 reg = <3>;
1506 mdp_dtv_out: endpoint {
1507 };
1508 };
1509 };
1510 };
1511
1512 riva: riva-pil@3204000 {
1513 compatible = "qcom,riva-pil";
1514
1515 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1516 reg-names = "ccu", "dxe", "pmu";
1517
1518 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1519 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1520 interrupt-names = "wdog", "fatal";
1521
1522 memory-region = <&wcnss_mem>;
1523
1524 vddcx-supply = <&pm8921_s3>;
1525 vddmx-supply = <&pm8921_l24>;
1526 vddpx-supply = <&pm8921_s4>;
1527
1528 status = "disabled";
1529
1530 iris {
1531 compatible = "qcom,wcn3660";
1532
1533 clocks = <&cxo_board>;
1534 clock-names = "xo";
1535
1536 vddxo-supply = <&pm8921_l4>;
1537 vddrfa-supply = <&pm8921_s2>;
1538 vddpa-supply = <&pm8921_l10>;
1539 vdddig-supply = <&pm8921_lvs2>;
1540 };
1541
1542 smd-edge {
1543 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1544
1545 qcom,ipc = <&l2cc 8 25>;
1546 qcom,smd-edge = <6>;
1547
1548 label = "riva";
1549
1550 wcnss {
1551 compatible = "qcom,wcnss";
1552 qcom,smd-channels = "WCNSS_CTRL";
1553
1554 qcom,mmio = <&riva>;
1555
1556 bt {
1557 compatible = "qcom,wcnss-bt";
1558 };
1559
1560 wifi {
1561 compatible = "qcom,wcnss-wlan";
1562
1563 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1565 interrupt-names = "tx", "rx";
1566
1567 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1568 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1569 };
1570 };
1571 };
1572 };
1573
1574 etb@1a01000 {
1575 compatible = "coresight-etb10", "arm,primecell";
1576 reg = <0x1a01000 0x1000>;
1577
1578 clocks = <&rpmcc RPM_QDSS_CLK>;
1579 clock-names = "apb_pclk";
1580
1581 in-ports {
1582 port {
1583 etb_in: endpoint {
1584 remote-endpoint = <&replicator_out0>;
1585 };
1586 };
1587 };
1588 };
1589
1590 tpiu@1a03000 {
1591 compatible = "arm,coresight-tpiu", "arm,primecell";
1592 reg = <0x1a03000 0x1000>;
1593
1594 clocks = <&rpmcc RPM_QDSS_CLK>;
1595 clock-names = "apb_pclk";
1596
1597 in-ports {
1598 port {
1599 tpiu_in: endpoint {
1600 remote-endpoint = <&replicator_out1>;
1601 };
1602 };
1603 };
1604 };
1605
1606 replicator {
1607 compatible = "arm,coresight-static-replicator";
1608
1609 clocks = <&rpmcc RPM_QDSS_CLK>;
1610 clock-names = "apb_pclk";
1611
1612 out-ports {
1613 #address-cells = <1>;
1614 #size-cells = <0>;
1615
1616 port@0 {
1617 reg = <0>;
1618 replicator_out0: endpoint {
1619 remote-endpoint = <&etb_in>;
1620 };
1621 };
1622 port@1 {
1623 reg = <1>;
1624 replicator_out1: endpoint {
1625 remote-endpoint = <&tpiu_in>;
1626 };
1627 };
1628 };
1629
1630 in-ports {
1631 port {
1632 replicator_in: endpoint {
1633 remote-endpoint = <&funnel_out>;
1634 };
1635 };
1636 };
1637 };
1638
1639 funnel@1a04000 {
1640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1641 reg = <0x1a04000 0x1000>;
1642
1643 clocks = <&rpmcc RPM_QDSS_CLK>;
1644 clock-names = "apb_pclk";
1645
1646 in-ports {
1647 #address-cells = <1>;
1648 #size-cells = <0>;
1649
1650 /*
1651 * Not described input ports:
1652 * 2 - connected to STM component
1653 * 3 - not-connected
1654 * 6 - not-connected
1655 * 7 - not-connected
1656 */
1657 port@0 {
1658 reg = <0>;
1659 funnel_in0: endpoint {
1660 remote-endpoint = <&etm0_out>;
1661 };
1662 };
1663 port@1 {
1664 reg = <1>;
1665 funnel_in1: endpoint {
1666 remote-endpoint = <&etm1_out>;
1667 };
1668 };
1669 port@4 {
1670 reg = <4>;
1671 funnel_in4: endpoint {
1672 remote-endpoint = <&etm2_out>;
1673 };
1674 };
1675 port@5 {
1676 reg = <5>;
1677 funnel_in5: endpoint {
1678 remote-endpoint = <&etm3_out>;
1679 };
1680 };
1681 };
1682
1683 out-ports {
1684 port {
1685 funnel_out: endpoint {
1686 remote-endpoint = <&replicator_in>;
1687 };
1688 };
1689 };
1690 };
1691
1692 etm@1a1c000 {
1693 compatible = "arm,coresight-etm3x", "arm,primecell";
1694 reg = <0x1a1c000 0x1000>;
1695
1696 clocks = <&rpmcc RPM_QDSS_CLK>;
1697 clock-names = "apb_pclk";
1698
1699 cpu = <&CPU0>;
1700
1701 out-ports {
1702 port {
1703 etm0_out: endpoint {
1704 remote-endpoint = <&funnel_in0>;
1705 };
1706 };
1707 };
1708 };
1709
1710 etm@1a1d000 {
1711 compatible = "arm,coresight-etm3x", "arm,primecell";
1712 reg = <0x1a1d000 0x1000>;
1713
1714 clocks = <&rpmcc RPM_QDSS_CLK>;
1715 clock-names = "apb_pclk";
1716
1717 cpu = <&CPU1>;
1718
1719 out-ports {
1720 port {
1721 etm1_out: endpoint {
1722 remote-endpoint = <&funnel_in1>;
1723 };
1724 };
1725 };
1726 };
1727
1728 etm@1a1e000 {
1729 compatible = "arm,coresight-etm3x", "arm,primecell";
1730 reg = <0x1a1e000 0x1000>;
1731
1732 clocks = <&rpmcc RPM_QDSS_CLK>;
1733 clock-names = "apb_pclk";
1734
1735 cpu = <&CPU2>;
1736
1737 out-ports {
1738 port {
1739 etm2_out: endpoint {
1740 remote-endpoint = <&funnel_in4>;
1741 };
1742 };
1743 };
1744 };
1745
1746 etm@1a1f000 {
1747 compatible = "arm,coresight-etm3x", "arm,primecell";
1748 reg = <0x1a1f000 0x1000>;
1749
1750 clocks = <&rpmcc RPM_QDSS_CLK>;
1751 clock-names = "apb_pclk";
1752
1753 cpu = <&CPU3>;
1754
1755 out-ports {
1756 port {
1757 etm3_out: endpoint {
1758 remote-endpoint = <&funnel_in5>;
1759 };
1760 };
1761 };
1762 };
1763 };
1764};
1765#include "qcom-apq8064-pins.dtsi"