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1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6sl-pinfunc.h"
7#include <dt-bindings/clock/imx6sl-clock.h>
8
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12 /*
13 * The decompressor and also some bootloaders rely on a
14 * pre-existing /chosen node to be available to insert the
15 * command line and merge other ATAGS info.
16 */
17 chosen {};
18
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 mmc0 = &usdhc1;
30 mmc1 = &usdhc2;
31 mmc2 = &usdhc3;
32 mmc3 = &usdhc4;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 spi0 = &ecspi1;
39 spi1 = &ecspi2;
40 spi2 = &ecspi3;
41 spi3 = &ecspi4;
42 usbphy0 = &usbphy1;
43 usbphy1 = &usbphy2;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 compatible = "arm,cortex-a9";
52 device_type = "cpu";
53 reg = <0x0>;
54 next-level-cache = <&L2>;
55 operating-points = <
56 /* kHz uV */
57 996000 1275000
58 792000 1175000
59 396000 975000
60 >;
61 fsl,soc-operating-points = <
62 /* ARM kHz SOC-PU uV */
63 996000 1225000
64 792000 1175000
65 396000 1175000
66 >;
67 clock-latency = <61036>; /* two CLK32 periods */
68 #cooling-cells = <2>;
69 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
70 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
71 <&clks IMX6SL_CLK_PLL1_SYS>;
72 clock-names = "arm", "pll2_pfd2_396m", "step",
73 "pll1_sw", "pll1_sys";
74 arm-supply = <®_arm>;
75 pu-supply = <®_pu>;
76 soc-supply = <®_soc>;
77 nvmem-cells = <&cpu_speed_grade>;
78 nvmem-cell-names = "speed_grade";
79 };
80 };
81
82 clocks {
83 ckil {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <32768>;
87 };
88
89 osc {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <24000000>;
93 };
94 };
95
96 pmu {
97 compatible = "arm,cortex-a9-pmu";
98 interrupt-parent = <&gpc>;
99 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
100 };
101
102 usbphynop1: usbphynop1 {
103 compatible = "usb-nop-xceiv";
104 #phy-cells = <0>;
105 };
106
107 soc {
108 #address-cells = <1>;
109 #size-cells = <1>;
110 compatible = "simple-bus";
111 interrupt-parent = <&gpc>;
112 ranges;
113
114 ocram: sram@900000 {
115 compatible = "mmio-sram";
116 reg = <0x00900000 0x20000>;
117 clocks = <&clks IMX6SL_CLK_OCRAM>;
118 };
119
120 intc: interrupt-controller@a01000 {
121 compatible = "arm,cortex-a9-gic";
122 #interrupt-cells = <3>;
123 interrupt-controller;
124 reg = <0x00a01000 0x1000>,
125 <0x00a00100 0x100>;
126 interrupt-parent = <&intc>;
127 };
128
129 L2: cache-controller@a02000 {
130 compatible = "arm,pl310-cache";
131 reg = <0x00a02000 0x1000>;
132 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
133 cache-unified;
134 cache-level = <2>;
135 arm,tag-latency = <4 2 3>;
136 arm,data-latency = <4 2 3>;
137 };
138
139 aips1: bus@2000000 {
140 compatible = "fsl,aips-bus", "simple-bus";
141 #address-cells = <1>;
142 #size-cells = <1>;
143 reg = <0x02000000 0x100000>;
144 ranges;
145
146 spba: spba-bus@2000000 {
147 compatible = "fsl,spba-bus", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 reg = <0x02000000 0x40000>;
151 ranges;
152
153 spdif: spdif@2004000 {
154 compatible = "fsl,imx6sl-spdif",
155 "fsl,imx35-spdif";
156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
158 dmas = <&sdma 14 18 0>,
159 <&sdma 15 18 0>;
160 dma-names = "rx", "tx";
161 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
162 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
163 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
164 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
165 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
166 clock-names = "core", "rxtx0",
167 "rxtx1", "rxtx2",
168 "rxtx3", "rxtx4",
169 "rxtx5", "rxtx6",
170 "rxtx7", "spba";
171 status = "disabled";
172 };
173
174 ecspi1: spi@2008000 {
175 #address-cells = <1>;
176 #size-cells = <0>;
177 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
178 reg = <0x02008000 0x4000>;
179 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&clks IMX6SL_CLK_ECSPI1>,
181 <&clks IMX6SL_CLK_ECSPI1>;
182 clock-names = "ipg", "per";
183 status = "disabled";
184 };
185
186 ecspi2: spi@200c000 {
187 #address-cells = <1>;
188 #size-cells = <0>;
189 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
190 reg = <0x0200c000 0x4000>;
191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&clks IMX6SL_CLK_ECSPI2>,
193 <&clks IMX6SL_CLK_ECSPI2>;
194 clock-names = "ipg", "per";
195 status = "disabled";
196 };
197
198 ecspi3: spi@2010000 {
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
202 reg = <0x02010000 0x4000>;
203 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
204 clocks = <&clks IMX6SL_CLK_ECSPI3>,
205 <&clks IMX6SL_CLK_ECSPI3>;
206 clock-names = "ipg", "per";
207 status = "disabled";
208 };
209
210 ecspi4: spi@2014000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi";
214 reg = <0x02014000 0x4000>;
215 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6SL_CLK_ECSPI4>,
217 <&clks IMX6SL_CLK_ECSPI4>;
218 clock-names = "ipg", "per";
219 status = "disabled";
220 };
221
222 uart5: serial@2018000 {
223 compatible = "fsl,imx6sl-uart",
224 "fsl,imx6q-uart", "fsl,imx21-uart";
225 reg = <0x02018000 0x4000>;
226 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&clks IMX6SL_CLK_UART>,
228 <&clks IMX6SL_CLK_UART_SERIAL>;
229 clock-names = "ipg", "per";
230 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
231 dma-names = "rx", "tx";
232 status = "disabled";
233 };
234
235 uart1: serial@2020000 {
236 compatible = "fsl,imx6sl-uart",
237 "fsl,imx6q-uart", "fsl,imx21-uart";
238 reg = <0x02020000 0x4000>;
239 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
240 clocks = <&clks IMX6SL_CLK_UART>,
241 <&clks IMX6SL_CLK_UART_SERIAL>;
242 clock-names = "ipg", "per";
243 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
244 dma-names = "rx", "tx";
245 status = "disabled";
246 };
247
248 uart2: serial@2024000 {
249 compatible = "fsl,imx6sl-uart",
250 "fsl,imx6q-uart", "fsl,imx21-uart";
251 reg = <0x02024000 0x4000>;
252 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clks IMX6SL_CLK_UART>,
254 <&clks IMX6SL_CLK_UART_SERIAL>;
255 clock-names = "ipg", "per";
256 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
257 dma-names = "rx", "tx";
258 status = "disabled";
259 };
260
261 ssi1: ssi@2028000 {
262 #sound-dai-cells = <0>;
263 compatible = "fsl,imx6sl-ssi",
264 "fsl,imx51-ssi";
265 reg = <0x02028000 0x4000>;
266 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clks IMX6SL_CLK_SSI1_IPG>,
268 <&clks IMX6SL_CLK_SSI1>;
269 clock-names = "ipg", "baud";
270 dmas = <&sdma 37 1 0>,
271 <&sdma 38 1 0>;
272 dma-names = "rx", "tx";
273 fsl,fifo-depth = <15>;
274 status = "disabled";
275 };
276
277 ssi2: ssi@202c000 {
278 #sound-dai-cells = <0>;
279 compatible = "fsl,imx6sl-ssi",
280 "fsl,imx51-ssi";
281 reg = <0x0202c000 0x4000>;
282 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
283 clocks = <&clks IMX6SL_CLK_SSI2_IPG>,
284 <&clks IMX6SL_CLK_SSI2>;
285 clock-names = "ipg", "baud";
286 dmas = <&sdma 41 1 0>,
287 <&sdma 42 1 0>;
288 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>;
290 status = "disabled";
291 };
292
293 ssi3: ssi@2030000 {
294 #sound-dai-cells = <0>;
295 compatible = "fsl,imx6sl-ssi",
296 "fsl,imx51-ssi";
297 reg = <0x02030000 0x4000>;
298 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&clks IMX6SL_CLK_SSI3_IPG>,
300 <&clks IMX6SL_CLK_SSI3>;
301 clock-names = "ipg", "baud";
302 dmas = <&sdma 45 1 0>,
303 <&sdma 46 1 0>;
304 dma-names = "rx", "tx";
305 fsl,fifo-depth = <15>;
306 status = "disabled";
307 };
308
309 uart3: serial@2034000 {
310 compatible = "fsl,imx6sl-uart",
311 "fsl,imx6q-uart", "fsl,imx21-uart";
312 reg = <0x02034000 0x4000>;
313 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&clks IMX6SL_CLK_UART>,
315 <&clks IMX6SL_CLK_UART_SERIAL>;
316 clock-names = "ipg", "per";
317 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
318 dma-names = "rx", "tx";
319 status = "disabled";
320 };
321
322 uart4: serial@2038000 {
323 compatible = "fsl,imx6sl-uart",
324 "fsl,imx6q-uart", "fsl,imx21-uart";
325 reg = <0x02038000 0x4000>;
326 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clks IMX6SL_CLK_UART>,
328 <&clks IMX6SL_CLK_UART_SERIAL>;
329 clock-names = "ipg", "per";
330 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
331 dma-names = "rx", "tx";
332 status = "disabled";
333 };
334 };
335
336 pwm1: pwm@2080000 {
337 #pwm-cells = <3>;
338 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
339 reg = <0x02080000 0x4000>;
340 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
341 clocks = <&clks IMX6SL_CLK_PERCLK>,
342 <&clks IMX6SL_CLK_PWM1>;
343 clock-names = "ipg", "per";
344 };
345
346 pwm2: pwm@2084000 {
347 #pwm-cells = <3>;
348 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
349 reg = <0x02084000 0x4000>;
350 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&clks IMX6SL_CLK_PERCLK>,
352 <&clks IMX6SL_CLK_PWM2>;
353 clock-names = "ipg", "per";
354 };
355
356 pwm3: pwm@2088000 {
357 #pwm-cells = <3>;
358 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
359 reg = <0x02088000 0x4000>;
360 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks IMX6SL_CLK_PERCLK>,
362 <&clks IMX6SL_CLK_PWM3>;
363 clock-names = "ipg", "per";
364 };
365
366 pwm4: pwm@208c000 {
367 #pwm-cells = <3>;
368 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm";
369 reg = <0x0208c000 0x4000>;
370 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&clks IMX6SL_CLK_PERCLK>,
372 <&clks IMX6SL_CLK_PWM4>;
373 clock-names = "ipg", "per";
374 };
375
376 gpt: timer@2098000 {
377 compatible = "fsl,imx6sl-gpt";
378 reg = <0x02098000 0x4000>;
379 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6SL_CLK_GPT>,
381 <&clks IMX6SL_CLK_GPT_SERIAL>;
382 clock-names = "ipg", "per";
383 };
384
385 gpio1: gpio@209c000 {
386 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
387 reg = <0x0209c000 0x4000>;
388 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
389 <0 67 IRQ_TYPE_LEVEL_HIGH>;
390 gpio-controller;
391 #gpio-cells = <2>;
392 interrupt-controller;
393 #interrupt-cells = <2>;
394 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>,
395 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>,
396 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>,
397 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>,
398 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>,
399 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>;
400 };
401
402 gpio2: gpio@20a0000 {
403 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
404 reg = <0x020a0000 0x4000>;
405 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
406 <0 69 IRQ_TYPE_LEVEL_HIGH>;
407 gpio-controller;
408 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
411 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>,
412 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>,
413 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>,
414 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>,
415 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>,
416 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>,
417 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>;
418 };
419
420 gpio3: gpio@20a4000 {
421 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
422 reg = <0x020a4000 0x4000>;
423 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
424 <0 71 IRQ_TYPE_LEVEL_HIGH>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>,
430 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>,
431 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>,
432 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>,
433 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>,
434 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>,
435 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>,
436 <&iomuxc 31 102 1>;
437 };
438
439 gpio4: gpio@20a8000 {
440 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
441 reg = <0x020a8000 0x4000>;
442 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
443 <0 73 IRQ_TYPE_LEVEL_HIGH>;
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>,
449 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>,
450 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>,
451 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>,
452 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>,
453 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>,
454 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>,
455 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>,
456 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>,
457 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>,
458 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>,
459 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>,
460 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>,
461 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>,
462 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>;
463 };
464
465 gpio5: gpio@20ac000 {
466 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio";
467 reg = <0x020ac000 0x4000>;
468 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
469 <0 75 IRQ_TYPE_LEVEL_HIGH>;
470 gpio-controller;
471 #gpio-cells = <2>;
472 interrupt-controller;
473 #interrupt-cells = <2>;
474 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>,
475 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>,
476 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>,
477 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>,
478 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>,
479 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>,
480 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>,
481 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>,
482 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>,
483 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>,
484 <&iomuxc 21 161 1>;
485 };
486
487 kpp: keypad@20b8000 {
488 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp";
489 reg = <0x020b8000 0x4000>;
490 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clks IMX6SL_CLK_IPG>;
492 status = "disabled";
493 };
494
495 wdog1: watchdog@20bc000 {
496 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
497 reg = <0x020bc000 0x4000>;
498 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clks IMX6SL_CLK_IPG>;
500 };
501
502 wdog2: watchdog@20c0000 {
503 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt";
504 reg = <0x020c0000 0x4000>;
505 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6SL_CLK_IPG>;
507 status = "disabled";
508 };
509
510 clks: clock-controller@20c4000 {
511 compatible = "fsl,imx6sl-ccm";
512 reg = <0x020c4000 0x4000>;
513 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
514 <0 88 IRQ_TYPE_LEVEL_HIGH>;
515 #clock-cells = <1>;
516 };
517
518 anatop: anatop@20c8000 {
519 compatible = "fsl,imx6sl-anatop",
520 "fsl,imx6q-anatop",
521 "syscon", "simple-mfd";
522 reg = <0x020c8000 0x1000>;
523 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
524 <0 54 IRQ_TYPE_LEVEL_HIGH>,
525 <0 127 IRQ_TYPE_LEVEL_HIGH>;
526
527 reg_vdd1p1: regulator-1p1 {
528 compatible = "fsl,anatop-regulator";
529 regulator-name = "vdd1p1";
530 regulator-min-microvolt = <1000000>;
531 regulator-max-microvolt = <1200000>;
532 regulator-always-on;
533 anatop-reg-offset = <0x110>;
534 anatop-vol-bit-shift = <8>;
535 anatop-vol-bit-width = <5>;
536 anatop-min-bit-val = <4>;
537 anatop-min-voltage = <800000>;
538 anatop-max-voltage = <1375000>;
539 anatop-enable-bit = <0>;
540 };
541
542 reg_vdd3p0: regulator-3p0 {
543 compatible = "fsl,anatop-regulator";
544 regulator-name = "vdd3p0";
545 regulator-min-microvolt = <2800000>;
546 regulator-max-microvolt = <3150000>;
547 regulator-always-on;
548 anatop-reg-offset = <0x120>;
549 anatop-vol-bit-shift = <8>;
550 anatop-vol-bit-width = <5>;
551 anatop-min-bit-val = <0>;
552 anatop-min-voltage = <2625000>;
553 anatop-max-voltage = <3400000>;
554 anatop-enable-bit = <0>;
555 };
556
557 reg_vdd2p5: regulator-2p5 {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd2p5";
560 regulator-min-microvolt = <2250000>;
561 regulator-max-microvolt = <2750000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x130>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2100000>;
568 anatop-max-voltage = <2850000>;
569 anatop-enable-bit = <0>;
570 };
571
572 reg_arm: regulator-vddcore {
573 compatible = "fsl,anatop-regulator";
574 regulator-name = "vddarm";
575 regulator-min-microvolt = <725000>;
576 regulator-max-microvolt = <1450000>;
577 regulator-always-on;
578 anatop-reg-offset = <0x140>;
579 anatop-vol-bit-shift = <0>;
580 anatop-vol-bit-width = <5>;
581 anatop-delay-reg-offset = <0x170>;
582 anatop-delay-bit-shift = <24>;
583 anatop-delay-bit-width = <2>;
584 anatop-min-bit-val = <1>;
585 anatop-min-voltage = <725000>;
586 anatop-max-voltage = <1450000>;
587 };
588
589 reg_pu: regulator-vddpu {
590 compatible = "fsl,anatop-regulator";
591 regulator-name = "vddpu";
592 regulator-min-microvolt = <725000>;
593 regulator-max-microvolt = <1450000>;
594 anatop-reg-offset = <0x140>;
595 anatop-vol-bit-shift = <9>;
596 anatop-vol-bit-width = <5>;
597 anatop-delay-reg-offset = <0x170>;
598 anatop-delay-bit-shift = <26>;
599 anatop-delay-bit-width = <2>;
600 anatop-min-bit-val = <1>;
601 anatop-min-voltage = <725000>;
602 anatop-max-voltage = <1450000>;
603 };
604
605 reg_soc: regulator-vddsoc {
606 compatible = "fsl,anatop-regulator";
607 regulator-name = "vddsoc";
608 regulator-min-microvolt = <725000>;
609 regulator-max-microvolt = <1450000>;
610 regulator-always-on;
611 anatop-reg-offset = <0x140>;
612 anatop-vol-bit-shift = <18>;
613 anatop-vol-bit-width = <5>;
614 anatop-delay-reg-offset = <0x170>;
615 anatop-delay-bit-shift = <28>;
616 anatop-delay-bit-width = <2>;
617 anatop-min-bit-val = <1>;
618 anatop-min-voltage = <725000>;
619 anatop-max-voltage = <1450000>;
620 };
621
622 tempmon: tempmon {
623 compatible = "fsl,imx6q-tempmon";
624 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
625 interrupt-parent = <&gpc>;
626 fsl,tempmon = <&anatop>;
627 nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
628 nvmem-cell-names = "calib", "temp_grade";
629 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
630 };
631 };
632
633 usbphy1: usbphy@20c9000 {
634 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
635 reg = <0x020c9000 0x1000>;
636 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clks IMX6SL_CLK_USBPHY1>;
638 fsl,anatop = <&anatop>;
639 };
640
641 usbphy2: usbphy@20ca000 {
642 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy";
643 reg = <0x020ca000 0x1000>;
644 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
645 clocks = <&clks IMX6SL_CLK_USBPHY2>;
646 fsl,anatop = <&anatop>;
647 };
648
649 snvs: snvs@20cc000 {
650 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
651 reg = <0x020cc000 0x4000>;
652
653 snvs_rtc: snvs-rtc-lp {
654 compatible = "fsl,sec-v4.0-mon-rtc-lp";
655 regmap = <&snvs>;
656 offset = <0x34>;
657 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
658 <0 20 IRQ_TYPE_LEVEL_HIGH>;
659 };
660
661 snvs_poweroff: snvs-poweroff {
662 compatible = "syscon-poweroff";
663 regmap = <&snvs>;
664 offset = <0x38>;
665 value = <0x60>;
666 mask = <0x60>;
667 status = "disabled";
668 };
669 };
670
671 epit1: epit@20d0000 {
672 reg = <0x020d0000 0x4000>;
673 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
674 };
675
676 epit2: epit@20d4000 {
677 reg = <0x020d4000 0x4000>;
678 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
679 };
680
681 src: reset-controller@20d8000 {
682 compatible = "fsl,imx6sl-src", "fsl,imx51-src";
683 reg = <0x020d8000 0x4000>;
684 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
685 <0 96 IRQ_TYPE_LEVEL_HIGH>;
686 #reset-cells = <1>;
687 };
688
689 gpc: gpc@20dc000 {
690 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
691 reg = <0x020dc000 0x4000>;
692 interrupt-controller;
693 #interrupt-cells = <3>;
694 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
695 interrupt-parent = <&intc>;
696 clocks = <&clks IMX6SL_CLK_IPG>;
697 clock-names = "ipg";
698
699 pgc {
700 #address-cells = <1>;
701 #size-cells = <0>;
702
703 power-domain@0 {
704 reg = <0>;
705 #power-domain-cells = <0>;
706 };
707
708 pd_pu: power-domain@1 {
709 reg = <1>;
710 #power-domain-cells = <0>;
711 power-supply = <®_pu>;
712 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
713 <&clks IMX6SL_CLK_GPU2D_PODF>;
714 };
715
716 pd_disp: power-domain@2 {
717 reg = <2>;
718 #power-domain-cells = <0>;
719 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>,
720 <&clks IMX6SL_CLK_LCDIF_PIX>,
721 <&clks IMX6SL_CLK_EPDC_AXI>,
722 <&clks IMX6SL_CLK_EPDC_PIX>,
723 <&clks IMX6SL_CLK_PXP_AXI>;
724 };
725 };
726 };
727
728 gpr: iomuxc-gpr@20e0000 {
729 compatible = "fsl,imx6sl-iomuxc-gpr",
730 "fsl,imx6q-iomuxc-gpr", "syscon";
731 reg = <0x020e0000 0x38>;
732 };
733
734 iomuxc: pinctrl@20e0000 {
735 compatible = "fsl,imx6sl-iomuxc";
736 reg = <0x020e0000 0x4000>;
737 };
738
739 csi: csi@20e4000 {
740 reg = <0x020e4000 0x4000>;
741 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
742 };
743
744 spdc: spdc@20e8000 {
745 reg = <0x020e8000 0x4000>;
746 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
747 };
748
749 sdma: sdma@20ec000 {
750 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
751 reg = <0x020ec000 0x4000>;
752 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clks IMX6SL_CLK_SDMA>,
754 <&clks IMX6SL_CLK_AHB>;
755 clock-names = "ipg", "ahb";
756 #dma-cells = <3>;
757 /* imx6sl reuses imx6q sdma firmware */
758 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
759 };
760
761 pxp: pxp@20f0000 {
762 reg = <0x020f0000 0x4000>;
763 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
764 };
765
766 epdc: epdc@20f4000 {
767 reg = <0x020f4000 0x4000>;
768 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
769 };
770
771 lcdif: lcdif@20f8000 {
772 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif";
773 reg = <0x020f8000 0x4000>;
774 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>,
776 <&clks IMX6SL_CLK_LCDIF_AXI>,
777 <&clks IMX6SL_CLK_DUMMY>;
778 clock-names = "pix", "axi", "disp_axi";
779 status = "disabled";
780 power-domains = <&pd_disp>;
781 };
782
783 dcp: crypto@20fc000 {
784 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp";
785 reg = <0x020fc000 0x4000>;
786 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>,
787 <0 100 IRQ_TYPE_LEVEL_HIGH>,
788 <0 101 IRQ_TYPE_LEVEL_HIGH>;
789 };
790 };
791
792 aips2: bus@2100000 {
793 compatible = "fsl,aips-bus", "simple-bus";
794 #address-cells = <1>;
795 #size-cells = <1>;
796 reg = <0x02100000 0x100000>;
797 ranges;
798
799 usbotg1: usb@2184000 {
800 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
801 reg = <0x02184000 0x200>;
802 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks IMX6SL_CLK_USBOH3>;
804 fsl,usbphy = <&usbphy1>;
805 fsl,usbmisc = <&usbmisc 0>;
806 ahb-burst-config = <0x0>;
807 tx-burst-size-dword = <0x10>;
808 rx-burst-size-dword = <0x10>;
809 status = "disabled";
810 };
811
812 usbotg2: usb@2184200 {
813 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
814 reg = <0x02184200 0x200>;
815 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks IMX6SL_CLK_USBOH3>;
817 fsl,usbphy = <&usbphy2>;
818 fsl,usbmisc = <&usbmisc 1>;
819 ahb-burst-config = <0x0>;
820 tx-burst-size-dword = <0x10>;
821 rx-burst-size-dword = <0x10>;
822 status = "disabled";
823 };
824
825 usbh: usb@2184400 {
826 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb";
827 reg = <0x02184400 0x200>;
828 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clks IMX6SL_CLK_USBOH3>;
830 fsl,usbphy = <&usbphynop1>;
831 phy_type = "hsic";
832 fsl,usbmisc = <&usbmisc 2>;
833 dr_mode = "host";
834 ahb-burst-config = <0x0>;
835 tx-burst-size-dword = <0x10>;
836 rx-burst-size-dword = <0x10>;
837 status = "disabled";
838 };
839
840 usbmisc: usbmisc@2184800 {
841 #index-cells = <1>;
842 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc";
843 reg = <0x02184800 0x200>;
844 clocks = <&clks IMX6SL_CLK_USBOH3>;
845 };
846
847 fec: ethernet@2188000 {
848 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec";
849 reg = <0x02188000 0x4000>;
850 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
851 clocks = <&clks IMX6SL_CLK_ENET>,
852 <&clks IMX6SL_CLK_ENET_REF>;
853 clock-names = "ipg", "ahb";
854 status = "disabled";
855 };
856
857 usdhc1: mmc@2190000 {
858 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
859 reg = <0x02190000 0x4000>;
860 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&clks IMX6SL_CLK_USDHC1>,
862 <&clks IMX6SL_CLK_USDHC1>,
863 <&clks IMX6SL_CLK_USDHC1>;
864 clock-names = "ipg", "ahb", "per";
865 bus-width = <4>;
866 status = "disabled";
867 };
868
869 usdhc2: mmc@2194000 {
870 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
871 reg = <0x02194000 0x4000>;
872 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&clks IMX6SL_CLK_USDHC2>,
874 <&clks IMX6SL_CLK_USDHC2>,
875 <&clks IMX6SL_CLK_USDHC2>;
876 clock-names = "ipg", "ahb", "per";
877 bus-width = <4>;
878 status = "disabled";
879 };
880
881 usdhc3: mmc@2198000 {
882 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
883 reg = <0x02198000 0x4000>;
884 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&clks IMX6SL_CLK_USDHC3>,
886 <&clks IMX6SL_CLK_USDHC3>,
887 <&clks IMX6SL_CLK_USDHC3>;
888 clock-names = "ipg", "ahb", "per";
889 bus-width = <4>;
890 status = "disabled";
891 };
892
893 usdhc4: mmc@219c000 {
894 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc";
895 reg = <0x0219c000 0x4000>;
896 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&clks IMX6SL_CLK_USDHC4>,
898 <&clks IMX6SL_CLK_USDHC4>,
899 <&clks IMX6SL_CLK_USDHC4>;
900 clock-names = "ipg", "ahb", "per";
901 bus-width = <4>;
902 status = "disabled";
903 };
904
905 i2c1: i2c@21a0000 {
906 #address-cells = <1>;
907 #size-cells = <0>;
908 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
909 reg = <0x021a0000 0x4000>;
910 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
911 clocks = <&clks IMX6SL_CLK_I2C1>;
912 status = "disabled";
913 };
914
915 i2c2: i2c@21a4000 {
916 #address-cells = <1>;
917 #size-cells = <0>;
918 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
919 reg = <0x021a4000 0x4000>;
920 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clks IMX6SL_CLK_I2C2>;
922 status = "disabled";
923 };
924
925 i2c3: i2c@21a8000 {
926 #address-cells = <1>;
927 #size-cells = <0>;
928 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c";
929 reg = <0x021a8000 0x4000>;
930 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
931 clocks = <&clks IMX6SL_CLK_I2C3>;
932 status = "disabled";
933 };
934
935 memory-controller@21b0000 {
936 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";
937 reg = <0x021b0000 0x4000>;
938 clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;
939 };
940
941 rngb: rngb@21b4000 {
942 reg = <0x021b4000 0x4000>;
943 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
944 };
945
946 weim: weim@21b8000 {
947 #address-cells = <2>;
948 #size-cells = <1>;
949 reg = <0x021b8000 0x4000>;
950 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
951 fsl,weim-cs-gpr = <&gpr>;
952 status = "disabled";
953 };
954
955 ocotp: efuse@21bc000 {
956 compatible = "fsl,imx6sl-ocotp", "syscon";
957 reg = <0x021bc000 0x4000>;
958 clocks = <&clks IMX6SL_CLK_OCOTP>;
959 #address-cells = <1>;
960 #size-cells = <1>;
961
962 cpu_speed_grade: speed-grade@10 {
963 reg = <0x10 4>;
964 };
965
966 tempmon_calib: calib@38 {
967 reg = <0x38 4>;
968 };
969
970 tempmon_temp_grade: temp-grade@20 {
971 reg = <0x20 4>;
972 };
973 };
974
975 audmux: audmux@21d8000 {
976 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux";
977 reg = <0x021d8000 0x4000>;
978 status = "disabled";
979 };
980 };
981
982 gpu_2d: gpu@2200000 {
983 compatible = "vivante,gc";
984 reg = <0x02200000 0x4000>;
985 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
987 <&clks IMX6SL_CLK_GPU2D_OVG>;
988 clock-names = "bus", "core";
989 power-domains = <&pd_pu>;
990 };
991
992 gpu_vg: gpu@2204000 {
993 compatible = "vivante,gc";
994 reg = <0x02204000 0x4000>;
995 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>,
997 <&clks IMX6SL_CLK_GPU2D_OVG>;
998 clock-names = "bus", "core";
999 power-domains = <&pd_pu>;
1000 };
1001 };
1002};