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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8
9/ {
10 /* these are used by bootloader for disabling nodes */
11 aliases {
12 led0 = &led0;
13 led1 = &led1;
14 led2 = &led2;
15 nand = &gpmi;
16 ssi0 = &ssi1;
17 usb0 = &usbh1;
18 usb1 = &usbotg;
19 };
20
21 chosen {
22 bootargs = "console=ttymxc1,115200";
23 };
24
25 backlight {
26 compatible = "pwm-backlight";
27 pwms = <&pwm4 0 5000000>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <7>;
30 };
31
32 gpio-keys {
33 compatible = "gpio-keys";
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 user-pb {
38 label = "user_pb";
39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
40 linux,code = <BTN_0>;
41 };
42
43 user-pb1x {
44 label = "user_pb1x";
45 linux,code = <BTN_1>;
46 interrupt-parent = <&gsc>;
47 interrupts = <0>;
48 };
49
50 key-erased {
51 label = "key-erased";
52 linux,code = <BTN_2>;
53 interrupt-parent = <&gsc>;
54 interrupts = <1>;
55 };
56
57 eeprom-wp {
58 label = "eeprom_wp";
59 linux,code = <BTN_3>;
60 interrupt-parent = <&gsc>;
61 interrupts = <2>;
62 };
63
64 tamper {
65 label = "tamper";
66 linux,code = <BTN_4>;
67 interrupt-parent = <&gsc>;
68 interrupts = <5>;
69 };
70
71 switch-hold {
72 label = "switch_hold";
73 linux,code = <BTN_5>;
74 interrupt-parent = <&gsc>;
75 interrupts = <7>;
76 };
77 };
78
79 leds {
80 compatible = "gpio-leds";
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_gpio_leds>;
83
84 led0: user1 {
85 label = "user1";
86 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87 default-state = "on";
88 linux,default-trigger = "heartbeat";
89 };
90
91 led1: user2 {
92 label = "user2";
93 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
94 default-state = "off";
95 };
96
97 led2: user3 {
98 label = "user3";
99 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
100 default-state = "off";
101 };
102 };
103
104 memory@10000000 {
105 device_type = "memory";
106 reg = <0x10000000 0x40000000>;
107 };
108
109 pps {
110 compatible = "pps-gpio";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_pps>;
113 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
114 status = "okay";
115 };
116
117 reg_1p0v: regulator-1p0v {
118 compatible = "regulator-fixed";
119 regulator-name = "1P0V";
120 regulator-min-microvolt = <1000000>;
121 regulator-max-microvolt = <1000000>;
122 regulator-always-on;
123 };
124
125 reg_3p3v: regulator-3p3v {
126 compatible = "regulator-fixed";
127 regulator-name = "3P3V";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 regulator-always-on;
131 };
132
133 reg_usb_h1_vbus: regulator-usb-h1-vbus {
134 compatible = "regulator-fixed";
135 regulator-name = "usb_h1_vbus";
136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>;
138 regulator-always-on;
139 };
140
141 reg_usb_otg_vbus: regulator-usb-otg-vbus {
142 compatible = "regulator-fixed";
143 regulator-name = "usb_otg_vbus";
144 regulator-min-microvolt = <5000000>;
145 regulator-max-microvolt = <5000000>;
146 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
147 enable-active-high;
148 };
149
150 sound {
151 compatible = "fsl,imx6q-ventana-sgtl5000",
152 "fsl,imx-audio-sgtl5000";
153 model = "sgtl5000-audio";
154 ssi-controller = <&ssi1>;
155 audio-codec = <&codec>;
156 audio-routing =
157 "MIC_IN", "Mic Jack",
158 "Mic Jack", "Mic Bias",
159 "Headphone Jack", "HP_OUT";
160 mux-int-port = <1>;
161 mux-ext-port = <4>;
162 };
163};
164
165&audmux {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_audmux>;
168 status = "okay";
169};
170
171&can1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_flexcan1>;
174 status = "okay";
175};
176
177&clks {
178 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
179 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
180 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
181 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
182};
183
184&fec {
185 pinctrl-names = "default";
186 pinctrl-0 = <&pinctrl_enet>;
187 phy-mode = "rgmii-id";
188 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
189 status = "okay";
190};
191
192&gpmi {
193 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_gpmi_nand>;
195 status = "okay";
196};
197
198&hdmi {
199 ddc-i2c-bus = <&i2c3>;
200 status = "okay";
201};
202
203&i2c1 {
204 clock-frequency = <100000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c1>;
207 status = "okay";
208
209 gsc: gsc@20 {
210 compatible = "gw,gsc";
211 reg = <0x20>;
212 interrupt-parent = <&gpio1>;
213 interrupts = <4 GPIO_ACTIVE_LOW>;
214 interrupt-controller;
215 #interrupt-cells = <1>;
216 #size-cells = <0>;
217
218 adc {
219 compatible = "gw,gsc-adc";
220 #address-cells = <1>;
221 #size-cells = <0>;
222
223 channel@0 {
224 gw,mode = <0>;
225 reg = <0x00>;
226 label = "temp";
227 };
228
229 channel@2 {
230 gw,mode = <1>;
231 reg = <0x02>;
232 label = "vdd_vin";
233 };
234
235 channel@5 {
236 gw,mode = <1>;
237 reg = <0x05>;
238 label = "vdd_3p3";
239 };
240
241 channel@8 {
242 gw,mode = <1>;
243 reg = <0x08>;
244 label = "vdd_bat";
245 };
246
247 channel@b {
248 gw,mode = <1>;
249 reg = <0x0b>;
250 label = "vdd_5p0";
251 };
252
253 channel@e {
254 gw,mode = <1>;
255 reg = <0xe>;
256 label = "vdd_arm";
257 };
258
259 channel@11 {
260 gw,mode = <1>;
261 reg = <0x11>;
262 label = "vdd_soc";
263 };
264
265 channel@14 {
266 gw,mode = <1>;
267 reg = <0x14>;
268 label = "vdd_3p0";
269 };
270
271 channel@17 {
272 gw,mode = <1>;
273 reg = <0x17>;
274 label = "vdd_1p5";
275 };
276
277 channel@1d {
278 gw,mode = <1>;
279 reg = <0x1d>;
280 label = "vdd_1p8";
281 };
282
283 channel@20 {
284 gw,mode = <1>;
285 reg = <0x20>;
286 label = "vdd_1p0";
287 };
288
289 channel@23 {
290 gw,mode = <1>;
291 reg = <0x23>;
292 label = "vdd_2p5";
293 };
294
295 channel@26 {
296 gw,mode = <1>;
297 reg = <0x26>;
298 label = "vdd_gps";
299 };
300
301 channel@29 {
302 gw,mode = <1>;
303 reg = <0x29>;
304 label = "vdd_an1";
305 };
306 };
307 };
308
309 gsc_gpio: gpio@23 {
310 compatible = "nxp,pca9555";
311 reg = <0x23>;
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-parent = <&gsc>;
315 interrupts = <4>;
316 };
317
318 eeprom1: eeprom@50 {
319 compatible = "atmel,24c02";
320 reg = <0x50>;
321 pagesize = <16>;
322 };
323
324 eeprom2: eeprom@51 {
325 compatible = "atmel,24c02";
326 reg = <0x51>;
327 pagesize = <16>;
328 };
329
330 eeprom3: eeprom@52 {
331 compatible = "atmel,24c02";
332 reg = <0x52>;
333 pagesize = <16>;
334 };
335
336 eeprom4: eeprom@53 {
337 compatible = "atmel,24c02";
338 reg = <0x53>;
339 pagesize = <16>;
340 };
341
342 rtc: ds1672@68 {
343 compatible = "dallas,ds1672";
344 reg = <0x68>;
345 };
346};
347
348&i2c2 {
349 clock-frequency = <100000>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&pinctrl_i2c2>;
352 status = "okay";
353
354 ltc3676: pmic@3c {
355 compatible = "lltc,ltc3676";
356 reg = <0x3c>;
357 interrupt-parent = <&gpio1>;
358 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
359
360 regulators {
361 /* VDD_SOC (1+R1/R2 = 1.635) */
362 reg_vdd_soc: sw1 {
363 regulator-name = "vddsoc";
364 regulator-min-microvolt = <674400>;
365 regulator-max-microvolt = <1308000>;
366 lltc,fb-voltage-divider = <127000 200000>;
367 regulator-ramp-delay = <7000>;
368 regulator-boot-on;
369 regulator-always-on;
370 };
371
372 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
373 reg_1p8v: sw2 {
374 regulator-name = "vdd1p8";
375 regulator-min-microvolt = <1033310>;
376 regulator-max-microvolt = <2004000>;
377 lltc,fb-voltage-divider = <301000 200000>;
378 regulator-ramp-delay = <7000>;
379 regulator-boot-on;
380 regulator-always-on;
381 };
382
383 /* VDD_ARM (1+R1/R2 = 1.635) */
384 reg_vdd_arm: sw3 {
385 regulator-name = "vddarm";
386 regulator-min-microvolt = <674400>;
387 regulator-max-microvolt = <1308000>;
388 lltc,fb-voltage-divider = <127000 200000>;
389 regulator-ramp-delay = <7000>;
390 regulator-boot-on;
391 regulator-always-on;
392 };
393
394 /* VDD_DDR (1+R1/R2 = 2.105) */
395 reg_vdd_ddr: sw4 {
396 regulator-name = "vddddr";
397 regulator-min-microvolt = <868310>;
398 regulator-max-microvolt = <1684000>;
399 lltc,fb-voltage-divider = <221000 200000>;
400 regulator-ramp-delay = <7000>;
401 regulator-boot-on;
402 regulator-always-on;
403 };
404
405 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
406 reg_2p5v: ldo2 {
407 regulator-name = "vdd2p5";
408 regulator-min-microvolt = <2490375>;
409 regulator-max-microvolt = <2490375>;
410 lltc,fb-voltage-divider = <487000 200000>;
411 regulator-boot-on;
412 regulator-always-on;
413 };
414
415 /* VDD_AUD_1P8: Audio codec */
416 reg_aud_1p8v: ldo3 {
417 regulator-name = "vdd1p8a";
418 regulator-min-microvolt = <1800000>;
419 regulator-max-microvolt = <1800000>;
420 regulator-boot-on;
421 };
422
423 /* VDD_HIGH (1+R1/R2 = 4.17) */
424 reg_3p0v: ldo4 {
425 regulator-name = "vdd3p0";
426 regulator-min-microvolt = <3023250>;
427 regulator-max-microvolt = <3023250>;
428 lltc,fb-voltage-divider = <634000 200000>;
429 regulator-boot-on;
430 regulator-always-on;
431 };
432 };
433 };
434};
435
436&i2c3 {
437 clock-frequency = <100000>;
438 pinctrl-names = "default";
439 pinctrl-0 = <&pinctrl_i2c3>;
440 status = "okay";
441
442 codec: sgtl5000@a {
443 compatible = "fsl,sgtl5000";
444 reg = <0x0a>;
445 clocks = <&clks IMX6QDL_CLK_CKO>;
446 VDDA-supply = <®_1p8v>;
447 VDDIO-supply = <®_3p3v>;
448 };
449
450 touchscreen: egalax_ts@4 {
451 compatible = "eeti,egalax_ts";
452 reg = <0x04>;
453 interrupt-parent = <&gpio1>;
454 interrupts = <11 2>;
455 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
456 };
457
458 accel@1e {
459 compatible = "nxp,fxos8700";
460 reg = <0x1e>;
461 };
462};
463
464&ldb {
465 status = "okay";
466
467 lvds-channel@0 {
468 fsl,data-mapping = "spwg";
469 fsl,data-width = <18>;
470 status = "okay";
471
472 display-timings {
473 native-mode = <&timing0>;
474 timing0: hsd100pxn1 {
475 clock-frequency = <65000000>;
476 hactive = <1024>;
477 vactive = <768>;
478 hback-porch = <220>;
479 hfront-porch = <40>;
480 vback-porch = <21>;
481 vfront-porch = <7>;
482 hsync-len = <60>;
483 vsync-len = <10>;
484 };
485 };
486 };
487};
488
489&pcie {
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_pcie>;
492 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
493 status = "okay";
494};
495
496&pwm2 {
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
499 status = "disabled";
500};
501
502&pwm3 {
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
505 status = "disabled";
506};
507
508&pwm4 {
509 #pwm-cells = <2>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&pinctrl_pwm4>;
512 status = "okay";
513};
514
515&ssi1 {
516 status = "okay";
517};
518
519&uart1 {
520 pinctrl-names = "default";
521 pinctrl-0 = <&pinctrl_uart1>;
522 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
523 status = "okay";
524};
525
526&uart2 {
527 pinctrl-names = "default";
528 pinctrl-0 = <&pinctrl_uart2>;
529 status = "okay";
530};
531
532&uart5 {
533 pinctrl-names = "default";
534 pinctrl-0 = <&pinctrl_uart5>;
535 status = "okay";
536};
537
538&usbotg {
539 vbus-supply = <®_usb_otg_vbus>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pinctrl_usbotg>;
542 disable-over-current;
543 status = "okay";
544};
545
546&usbh1 {
547 vbus-supply = <®_usb_h1_vbus>;
548 status = "okay";
549};
550
551&usdhc3 {
552 pinctrl-names = "default", "state_100mhz", "state_200mhz";
553 pinctrl-0 = <&pinctrl_usdhc3>;
554 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
555 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
556 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
557 vmmc-supply = <®_3p3v>;
558 no-1-8-v; /* firmware will remove if board revision supports */
559 status = "okay";
560};
561
562&wdog1 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_wdog>;
565 fsl,ext-reset-output;
566};
567
568&iomuxc {
569 pinctrl_audmux: audmuxgrp {
570 fsl,pins = <
571 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
572 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
573 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
574 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
575 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
576 >;
577 };
578
579 pinctrl_enet: enetgrp {
580 fsl,pins = <
581 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
582 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
583 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
584 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
585 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
586 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
587 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
588 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
589 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
590 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
591 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
592 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
593 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
594 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
595 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
596 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
597 >;
598 };
599
600 pinctrl_flexcan1: flexcan1grp {
601 fsl,pins = <
602 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
603 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
604 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
605 >;
606 };
607
608 pinctrl_gpio_leds: gpioledsgrp {
609 fsl,pins = <
610 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
611 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
612 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
613 >;
614 };
615
616 pinctrl_gpmi_nand: gpminandgrp {
617 fsl,pins = <
618 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
619 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
620 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
621 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
622 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
623 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
624 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
625 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
626 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
627 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
628 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
629 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
630 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
631 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
632 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
633 >;
634 };
635
636 pinctrl_i2c1: i2c1grp {
637 fsl,pins = <
638 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
639 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
640 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
641 >;
642 };
643
644 pinctrl_i2c2: i2c2grp {
645 fsl,pins = <
646 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
647 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
648 >;
649 };
650
651 pinctrl_i2c3: i2c3grp {
652 fsl,pins = <
653 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
654 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
655 >;
656 };
657
658 pinctrl_pcie: pciegrp {
659 fsl,pins = <
660 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
661 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
662 >;
663 };
664
665 pinctrl_pmic: pmicgrp {
666 fsl,pins = <
667 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
668 >;
669 };
670
671 pinctrl_pps: ppsgrp {
672 fsl,pins = <
673 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
674 >;
675 };
676
677 pinctrl_pwm2: pwm2grp {
678 fsl,pins = <
679 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
680 >;
681 };
682
683 pinctrl_pwm3: pwm3grp {
684 fsl,pins = <
685 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
686 >;
687 };
688
689 pinctrl_pwm4: pwm4grp {
690 fsl,pins = <
691 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
692 >;
693 };
694
695 pinctrl_uart1: uart1grp {
696 fsl,pins = <
697 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
698 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
699 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
700 >;
701 };
702
703 pinctrl_uart2: uart2grp {
704 fsl,pins = <
705 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
706 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
707 >;
708 };
709
710 pinctrl_uart5: uart5grp {
711 fsl,pins = <
712 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
713 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
714 >;
715 };
716
717 pinctrl_usbotg: usbotggrp {
718 fsl,pins = <
719 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
720 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
721 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
722 >;
723 };
724
725 pinctrl_usdhc3: usdhc3grp {
726 fsl,pins = <
727 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
728 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
729 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
730 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
731 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
732 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
733 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
734 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
735 >;
736 };
737
738 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
739 fsl,pins = <
740 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
741 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
742 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
743 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
744 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
745 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
746 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
747 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
748 >;
749 };
750
751 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
752 fsl,pins = <
753 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
754 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
755 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
756 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
757 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
758 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
759 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
760 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
761 >;
762 };
763
764 pinctrl_wdog: wdoggrp {
765 fsl,pins = <
766 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
767 >;
768 };
769};