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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 MOXA Inc. - https://www.moxa.com/
4 *
5 * Author: SZ Lin (林上智) <sz.lin@moxa.com>
6 */
7
8/dts-v1/;
9
10#include "am33xx.dtsi"
11
12/ {
13 model = "Moxa UC-8100-ME-T";
14 compatible = "moxa,uc-8100-me-t", "ti,am33xx";
15
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x20000000>; /* 512 MB */
25 };
26
27 vbat: vbat-regulator {
28 compatible = "regulator-fixed";
29 };
30
31 /* Power supply provides a fixed 3.3V @3A */
32 vmmcsd_fixed: vmmcsd-regulator {
33 compatible = "regulator-fixed";
34 regulator-name = "vmmcsd_fixed";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 regulator-boot-on;
38 };
39
40 leds {
41 compatible = "gpio-leds";
42 led1 {
43 label = "uc8100me:CEL1";
44 gpios = <&gpio_xten 8 0>;
45 default-state = "off";
46 };
47
48 led2 {
49 label = "uc8100me:CEL2";
50 gpios = <&gpio_xten 9 0>;
51 default-state = "off";
52 };
53
54 led3 {
55 label = "uc8100me:CEL3";
56 gpios = <&gpio_xten 10 0>;
57 default-state = "off";
58 };
59
60 led4 {
61 label = "uc8100me:DIA1";
62 gpios = <&gpio_xten 11 0>;
63 default-state = "off";
64 };
65 led5 {
66 label = "uc8100me:DIA2";
67 gpios = <&gpio_xten 12 0>;
68 default-state = "off";
69 };
70 led6 {
71 label = "uc8100me:DIA3";
72 gpios = <&gpio_xten 13 0>;
73 default-state = "off";
74 };
75 led7 {
76 label = "uc8100me:SD";
77 gpios = <&gpio_xten 14 0>;
78 default-state = "off";
79 };
80 led8 {
81 label = "uc8100me:USB";
82 gpios = <&gpio_xten 15 0>;
83 default-state = "off";
84 };
85 led9 {
86 label = "uc8100me:USER";
87 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
88 default-state = "off";
89 };
90 };
91
92 buttons: push_button {
93 compatible = "gpio-keys";
94 };
95
96};
97
98&am33xx_pinmux {
99 pinctrl-names = "default";
100 pinctrl-0 = <&minipcie_pins>;
101
102 minipcie_pins: pinmux_minipcie {
103 pinctrl-single,pins = <
104 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2_24 */
105 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2_25 */
106 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2_22 Power off PIN*/
107 >;
108 };
109
110 push_button_pins: pinmux_push_button {
111 pinctrl-single,pins = <
112 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahcklx.gpio3_21 */
113 >;
114 };
115
116 i2c0_pins: pinmux_i2c0_pins {
117 pinctrl-single,pins = <
118 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)
119 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)
120 >;
121 };
122
123
124 i2c1_pins: pinmux_i2c1_pins {
125 pinctrl-single,pins = <
126 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_ctsn.i2c1_sda */
127 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE3) /* uart0_rtsn.i2c1_scl */
128 >;
129 };
130
131 uart0_pins: pinmux_uart0_pins {
132 pinctrl-single,pins = <
133 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
134 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
135 >;
136 };
137
138 uart1_pins: pinmux_uart1_pins {
139 pinctrl-single,pins = <
140 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
141 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
142 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
143 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
144 >;
145 };
146
147 uart2_pins: pinmux_uart2_pins {
148 pinctrl-single,pins = <
149 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE6) /* lcd_data14.uart5_ctsn */
150 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT_PULLDOWN, MUX_MODE6) /* lcd_data15.uart5_rtsn */
151 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_INPUT_PULLUP, MUX_MODE4) /* lcd_data9.uart5_rxd */
152 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE4) /* lcd_data8.uart5_txd */
153 >;
154 };
155
156 cpsw_default: cpsw_default {
157 pinctrl-single,pins = <
158 /* Slave 1 */
159 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
160 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)
161 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
162 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
163 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)
164 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)
165 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)
166 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
167
168 /* Slave 2 */
169 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_crs_dv */
170 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rxer */
171 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_txen */
172 AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td1 */
173 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* rmii2_td0 */
174 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd1 */
175 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE3) /* rmii2_rd0 */
176 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE1) /* rmii2_refclk */
177
178 >;
179 };
180
181 davinci_mdio_default: davinci_mdio_default {
182 pinctrl-single,pins = <
183 /* MDIO */
184 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
185 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
186 >;
187 };
188
189 mmc0_pins_default: pinmux_mmc0_pins {
190 pinctrl-single,pins = <
191 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
192 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
193 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
194 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
195 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
196 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
197 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_14 */
198 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkx.gpio3_18 */
199 >;
200 };
201
202 mmc2_pins_default: pinmux_mmc2_pins {
203 pinctrl-single,pins = <
204 /* eMMC */
205 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad12.mmc2_dat0 */
206 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad13.mmc2_dat1 */
207 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad14.mmc2_dat2 */
208 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad15.mmc2_dat3 */
209 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad8.mmc2_dat4 */
210 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad9.mmc2_dat5 */
211 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad10.mmc2_dat6 */
212 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ad11.mmc2_dat7 */
213 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
214 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk */
215 >;
216 };
217
218 spi0_pins: pinmux_spi0 {
219 pinctrl-single,pins = <
220 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)
221 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
222 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)
223 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
224 >;
225 };
226
227};
228
229&uart0 {
230 /* Console */
231 status = "okay";
232 pinctrl-names = "default";
233 pinctrl-0 = <&uart0_pins>;
234};
235
236&uart1 {
237 /* UART 1 setting */
238 status = "okay";
239 pinctrl-names = "default";
240 pinctrl-0 = <&uart1_pins>;
241};
242
243&uart5 {
244 /* UART 2 setting */
245 status = "okay";
246 pinctrl-names = "default";
247 pinctrl-0 = <&uart2_pins>;
248};
249
250&i2c0 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&i2c0_pins>;
253
254 status = "okay";
255 clock-frequency = <400000>;
256
257 tpm: tpm@20 {
258 compatible = "infineon,slb9645tt";
259 reg = <0x20>;
260 };
261
262 tps: tps@2d {
263 compatible = "ti,tps65910";
264 reg = <0x2d>;
265 };
266
267 eeprom: eeprom@50 {
268 compatible = "atmel,24c16";
269 pagesize = <16>;
270 reg = <0x50>;
271 };
272
273 rtc_wdt: rtc_wdt@68 {
274 compatible = "dallas,ds1374";
275 reg = <0x68>;
276 };
277};
278
279&i2c1 {
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c1_pins>;
282
283 status = "okay";
284 clock-frequency = <400000>;
285 gpio_xten: gpio_xten@27 {
286 compatible = "nxp,pca9535";
287 gpio-controller;
288 #gpio-cells = <2>;
289 reg = <0x27>;
290 };
291};
292
293&usb0 {
294 dr_mode = "host";
295};
296
297&usb1 {
298 dr_mode = "host";
299};
300
301#include "tps65910.dtsi"
302
303&tps {
304 vcc1-supply = <&vbat>;
305 vcc2-supply = <&vbat>;
306 vcc3-supply = <&vbat>;
307 vcc4-supply = <&vbat>;
308 vcc5-supply = <&vbat>;
309 vcc6-supply = <&vbat>;
310 vcc7-supply = <&vbat>;
311 vccio-supply = <&vbat>;
312
313 regulators {
314 vrtc_reg: regulator@0 {
315 regulator-always-on;
316 };
317
318 vio_reg: regulator@1 {
319 regulator-always-on;
320 };
321
322 vdd1_reg: regulator@2 {
323 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
324 regulator-name = "vdd_mpu";
325 regulator-min-microvolt = <912500>;
326 regulator-max-microvolt = <1378000>;
327 regulator-boot-on;
328 regulator-always-on;
329 };
330
331 vdd2_reg: regulator@3 {
332 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
333 regulator-name = "vdd_core";
334 regulator-min-microvolt = <912500>;
335 regulator-max-microvolt = <1150000>;
336 regulator-boot-on;
337 regulator-always-on;
338 };
339
340 vdd3_reg: regulator@4 {
341 regulator-always-on;
342 };
343
344 vdig1_reg: regulator@5 {
345 regulator-always-on;
346 };
347
348 vdig2_reg: regulator@6 {
349 regulator-always-on;
350 };
351
352 vpll_reg: regulator@7 {
353 regulator-always-on;
354 };
355
356 vdac_reg: regulator@8 {
357 regulator-always-on;
358 };
359
360 vaux1_reg: regulator@9 {
361 regulator-always-on;
362 };
363
364 vaux2_reg: regulator@10 {
365 regulator-always-on;
366 };
367
368 vaux33_reg: regulator@11 {
369 regulator-always-on;
370 };
371
372 vmmc_reg: regulator@12 {
373 compatible = "regulator-fixed";
374 regulator-name = "vmmc_reg";
375 regulator-min-microvolt = <3300000>;
376 regulator-max-microvolt = <3300000>;
377 regulator-always-on;
378 };
379 };
380};
381
382/* Power */
383&vbat {
384 regulator-name = "vbat";
385 regulator-min-microvolt = <5000000>;
386 regulator-max-microvolt = <5000000>;
387};
388
389&mac {
390 pinctrl-names = "default";
391 pinctrl-0 = <&cpsw_default>;
392 dual_emac = <1>;
393 status = "okay";
394};
395
396&davinci_mdio {
397 pinctrl-names = "default";
398 pinctrl-0 = <&davinci_mdio_default>;
399 status = "okay";
400
401 ethphy0: ethernet-phy@4 {
402 reg = <4>;
403 };
404
405 ethphy1: ethernet-phy@5 {
406 reg = <5>;
407 };
408};
409
410&cpsw_emac0 {
411 status = "okay";
412 phy-handle = <ðphy0>;
413 phy-mode = "rmii";
414 dual_emac_res_vlan = <1>;
415};
416
417&cpsw_emac1 {
418 status = "okay";
419 phy-handle = <ðphy1>;
420 phy-mode = "rmii";
421 dual_emac_res_vlan = <2>;
422};
423
424&sham {
425 status = "okay";
426};
427
428&aes {
429 status = "okay";
430};
431
432&gpio0 {
433 ti,no-reset-on-init;
434};
435
436&mmc1 {
437 pinctrl-names = "default";
438 vmmc-supply = <&vmmcsd_fixed>;
439 bus-width = <4>;
440 pinctrl-0 = <&mmc0_pins_default>;
441 cd-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
442 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
443 status = "okay";
444};
445
446&mmc3 {
447 dmas = <&edma_xbar 12 0 1
448 &edma_xbar 13 0 2>;
449 dma-names = "tx", "rx";
450 pinctrl-names = "default";
451 vmmc-supply = <&vmmcsd_fixed>;
452 bus-width = <8>;
453 pinctrl-0 = <&mmc2_pins_default>;
454 non-removable;
455 status = "okay";
456};
457
458&buttons {
459 pinctrl-names = "default";
460 pinctrl-0 = <&push_button_pins>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463
464 button@0 {
465 label = "push_button";
466 linux,code = <0x100>;
467 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
468 };
469};
470
471/* SPI Busses */
472&spi0 {
473 status = "okay";
474 pinctrl-names = "default";
475 pinctrl-0 = <&spi0_pins>;
476
477 m25p80@0 {
478 compatible = "mx25l6405d";
479 spi-max-frequency = <40000000>;
480
481 reg = <0>;
482 spi-cpol;
483 spi-cpha;
484 #address-cells = <1>;
485 #size-cells = <1>;
486
487 /* reg : The partition's offset and size within the mtd bank. */
488 partitions@0 {
489 label = "MLO";
490 reg = <0x0 0x80000>;
491 };
492
493 partitions@1 {
494 label = "U-Boot";
495 reg = <0x80000 0x100000>;
496 };
497
498 partitions@2 {
499 label = "U-Boot Env";
500 reg = <0x180000 0x20000>;
501 };
502 };
503};