1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) Maxime Coquelin 2015
  4 * Copyright (C) STMicroelectronics 2017
  5 * Author:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
  6 */
  7
  8#include <linux/bitops.h>
  9#include <linux/delay.h>
 10#include <linux/hwspinlock.h>
 11#include <linux/interrupt.h>
 12#include <linux/io.h>
 13#include <linux/irq.h>
 14#include <linux/irqchip.h>
 15#include <linux/irqchip/chained_irq.h>
 16#include <linux/irqdomain.h>
 17#include <linux/module.h>
 18#include <linux/of_address.h>
 19#include <linux/of_irq.h>
 20#include <linux/of_platform.h>
 21#include <linux/syscore_ops.h>
 22
 23#include <dt-bindings/interrupt-controller/arm-gic.h>
 24
 25#define IRQS_PER_BANK 32
 26
 27#define HWSPNLCK_TIMEOUT	1000 /* usec */
 28
 29struct stm32_exti_bank {
 30	u32 imr_ofst;
 31	u32 emr_ofst;
 32	u32 rtsr_ofst;
 33	u32 ftsr_ofst;
 34	u32 swier_ofst;
 35	u32 rpr_ofst;
 36	u32 fpr_ofst;
 37};
 38
 39#define UNDEF_REG ~0
 40
 41struct stm32_desc_irq {
 42	u32 exti;
 43	u32 irq_parent;
 44	struct irq_chip *chip;
 45};
 46
 47struct stm32_exti_drv_data {
 48	const struct stm32_exti_bank **exti_banks;
 49	const struct stm32_desc_irq *desc_irqs;
 50	u32 bank_nr;
 51	u32 irq_nr;
 52};
 53
 54struct stm32_exti_chip_data {
 55	struct stm32_exti_host_data *host_data;
 56	const struct stm32_exti_bank *reg_bank;
 57	struct raw_spinlock rlock;
 58	u32 wake_active;
 59	u32 mask_cache;
 60	u32 rtsr_cache;
 61	u32 ftsr_cache;
 
 62};
 63
 64struct stm32_exti_host_data {
 65	void __iomem *base;
 
 66	struct stm32_exti_chip_data *chips_data;
 67	const struct stm32_exti_drv_data *drv_data;
 68	struct hwspinlock *hwlock;
 69};
 70
 71static struct stm32_exti_host_data *stm32_host_data;
 72
 73static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
 74	.imr_ofst	= 0x00,
 75	.emr_ofst	= 0x04,
 76	.rtsr_ofst	= 0x08,
 77	.ftsr_ofst	= 0x0C,
 78	.swier_ofst	= 0x10,
 79	.rpr_ofst	= 0x14,
 80	.fpr_ofst	= UNDEF_REG,
 81};
 82
 83static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
 84	&stm32f4xx_exti_b1,
 85};
 86
 87static const struct stm32_exti_drv_data stm32f4xx_drv_data = {
 88	.exti_banks = stm32f4xx_exti_banks,
 89	.bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks),
 90};
 91
 92static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
 93	.imr_ofst	= 0x80,
 94	.emr_ofst	= 0x84,
 95	.rtsr_ofst	= 0x00,
 96	.ftsr_ofst	= 0x04,
 97	.swier_ofst	= 0x08,
 98	.rpr_ofst	= 0x88,
 99	.fpr_ofst	= UNDEF_REG,
100};
101
102static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
103	.imr_ofst	= 0x90,
104	.emr_ofst	= 0x94,
105	.rtsr_ofst	= 0x20,
106	.ftsr_ofst	= 0x24,
107	.swier_ofst	= 0x28,
108	.rpr_ofst	= 0x98,
109	.fpr_ofst	= UNDEF_REG,
110};
111
112static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
113	.imr_ofst	= 0xA0,
114	.emr_ofst	= 0xA4,
115	.rtsr_ofst	= 0x40,
116	.ftsr_ofst	= 0x44,
117	.swier_ofst	= 0x48,
118	.rpr_ofst	= 0xA8,
119	.fpr_ofst	= UNDEF_REG,
120};
121
122static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
123	&stm32h7xx_exti_b1,
124	&stm32h7xx_exti_b2,
125	&stm32h7xx_exti_b3,
126};
127
128static const struct stm32_exti_drv_data stm32h7xx_drv_data = {
129	.exti_banks = stm32h7xx_exti_banks,
130	.bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks),
131};
132
133static const struct stm32_exti_bank stm32mp1_exti_b1 = {
134	.imr_ofst	= 0x80,
135	.emr_ofst	= 0x84,
136	.rtsr_ofst	= 0x00,
137	.ftsr_ofst	= 0x04,
138	.swier_ofst	= 0x08,
139	.rpr_ofst	= 0x0C,
140	.fpr_ofst	= 0x10,
141};
142
143static const struct stm32_exti_bank stm32mp1_exti_b2 = {
144	.imr_ofst	= 0x90,
145	.emr_ofst	= 0x94,
146	.rtsr_ofst	= 0x20,
147	.ftsr_ofst	= 0x24,
148	.swier_ofst	= 0x28,
149	.rpr_ofst	= 0x2C,
150	.fpr_ofst	= 0x30,
151};
152
153static const struct stm32_exti_bank stm32mp1_exti_b3 = {
154	.imr_ofst	= 0xA0,
155	.emr_ofst	= 0xA4,
156	.rtsr_ofst	= 0x40,
157	.ftsr_ofst	= 0x44,
158	.swier_ofst	= 0x48,
159	.rpr_ofst	= 0x4C,
160	.fpr_ofst	= 0x50,
161};
162
163static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
164	&stm32mp1_exti_b1,
165	&stm32mp1_exti_b2,
166	&stm32mp1_exti_b3,
167};
168
169static struct irq_chip stm32_exti_h_chip;
170static struct irq_chip stm32_exti_h_chip_direct;
171
172static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
173	{ .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
174	{ .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
175	{ .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
176	{ .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
177	{ .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
178	{ .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
179	{ .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
180	{ .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
181	{ .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
182	{ .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
183	{ .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
184	{ .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
185	{ .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
186	{ .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
187	{ .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
188	{ .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
189	{ .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
190	{ .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
191	{ .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
192	{ .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
193	{ .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
194	{ .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
195	{ .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
196	{ .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
197	{ .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
198	{ .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
199	{ .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
200	{ .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
201	{ .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
202	{ .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
203	{ .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
204};
205
206static const struct stm32_exti_drv_data stm32mp1_drv_data = {
207	.exti_banks = stm32mp1_exti_banks,
208	.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
209	.desc_irqs = stm32mp1_desc_irq,
210	.irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
211};
212
213static const struct
214stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
215				    irq_hw_number_t hwirq)
216{
217	const struct stm32_desc_irq *desc = NULL;
218	int i;
219
220	if (!drv_data->desc_irqs)
221		return NULL;
222
223	for (i = 0; i < drv_data->irq_nr; i++) {
224		desc = &drv_data->desc_irqs[i];
225		if (desc->exti == hwirq)
226			break;
227	}
228
229	return desc;
230}
231
232static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
233{
234	struct stm32_exti_chip_data *chip_data = gc->private;
235	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
236	unsigned long pending;
237
238	pending = irq_reg_readl(gc, stm32_bank->rpr_ofst);
239	if (stm32_bank->fpr_ofst != UNDEF_REG)
240		pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst);
241
242	return pending;
243}
244
245static void stm32_irq_handler(struct irq_desc *desc)
246{
247	struct irq_domain *domain = irq_desc_get_handler_data(desc);
248	struct irq_chip *chip = irq_desc_get_chip(desc);
249	unsigned int virq, nbanks = domain->gc->num_chips;
250	struct irq_chip_generic *gc;
251	unsigned long pending;
252	int n, i, irq_base = 0;
253
254	chained_irq_enter(chip, desc);
255
256	for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
257		gc = irq_get_domain_generic_chip(domain, irq_base);
258
259		while ((pending = stm32_exti_pending(gc))) {
260			for_each_set_bit(n, &pending, IRQS_PER_BANK) {
261				virq = irq_find_mapping(domain, irq_base + n);
262				generic_handle_irq(virq);
263			}
264		}
265	}
266
267	chained_irq_exit(chip, desc);
268}
269
270static int stm32_exti_set_type(struct irq_data *d,
271			       unsigned int type, u32 *rtsr, u32 *ftsr)
272{
273	u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
274
275	switch (type) {
276	case IRQ_TYPE_EDGE_RISING:
277		*rtsr |= mask;
278		*ftsr &= ~mask;
279		break;
280	case IRQ_TYPE_EDGE_FALLING:
281		*rtsr &= ~mask;
282		*ftsr |= mask;
283		break;
284	case IRQ_TYPE_EDGE_BOTH:
285		*rtsr |= mask;
286		*ftsr |= mask;
287		break;
288	default:
289		return -EINVAL;
290	}
291
292	return 0;
293}
294
295static int stm32_irq_set_type(struct irq_data *d, unsigned int type)
296{
297	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
298	struct stm32_exti_chip_data *chip_data = gc->private;
299	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
300	struct hwspinlock *hwlock = chip_data->host_data->hwlock;
301	u32 rtsr, ftsr;
302	int err;
303
304	irq_gc_lock(gc);
305
306	if (hwlock) {
307		err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
308		if (err) {
309			pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
310			goto unlock;
311		}
312	}
313
314	rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
315	ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
316
317	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
318	if (err)
319		goto unspinlock;
320
321	irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
322	irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
323
324unspinlock:
325	if (hwlock)
326		hwspin_unlock_in_atomic(hwlock);
327unlock:
328	irq_gc_unlock(gc);
329
330	return err;
331}
332
333static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data,
334			       u32 wake_active)
335{
336	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
337	void __iomem *base = chip_data->host_data->base;
338
339	/* save rtsr, ftsr registers */
340	chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst);
341	chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst);
342
343	writel_relaxed(wake_active, base + stm32_bank->imr_ofst);
344}
345
346static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data,
347			      u32 mask_cache)
348{
349	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
350	void __iomem *base = chip_data->host_data->base;
351
352	/* restore rtsr, ftsr, registers */
353	writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst);
354	writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst);
355
356	writel_relaxed(mask_cache, base + stm32_bank->imr_ofst);
357}
358
359static void stm32_irq_suspend(struct irq_chip_generic *gc)
360{
361	struct stm32_exti_chip_data *chip_data = gc->private;
362
363	irq_gc_lock(gc);
364	stm32_chip_suspend(chip_data, gc->wake_active);
365	irq_gc_unlock(gc);
366}
367
368static void stm32_irq_resume(struct irq_chip_generic *gc)
369{
370	struct stm32_exti_chip_data *chip_data = gc->private;
371
372	irq_gc_lock(gc);
373	stm32_chip_resume(chip_data, gc->mask_cache);
374	irq_gc_unlock(gc);
375}
376
377static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
378			    unsigned int nr_irqs, void *data)
379{
380	struct irq_fwspec *fwspec = data;
381	irq_hw_number_t hwirq;
382
383	hwirq = fwspec->param[0];
384
385	irq_map_generic_chip(d, virq, hwirq);
386
387	return 0;
388}
389
390static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
391			    unsigned int nr_irqs)
392{
393	struct irq_data *data = irq_domain_get_irq_data(d, virq);
394
395	irq_domain_reset_irq_data(data);
396}
397
398static const struct irq_domain_ops irq_exti_domain_ops = {
399	.map	= irq_map_generic_chip,
400	.alloc  = stm32_exti_alloc,
401	.free	= stm32_exti_free,
 
402};
403
404static void stm32_irq_ack(struct irq_data *d)
405{
406	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
407	struct stm32_exti_chip_data *chip_data = gc->private;
408	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
409
410	irq_gc_lock(gc);
411
412	irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst);
413	if (stm32_bank->fpr_ofst != UNDEF_REG)
414		irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst);
415
416	irq_gc_unlock(gc);
417}
418
419/* directly set the target bit without reading first. */
420static inline void stm32_exti_write_bit(struct irq_data *d, u32 reg)
421{
422	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
423	void __iomem *base = chip_data->host_data->base;
424	u32 val = BIT(d->hwirq % IRQS_PER_BANK);
425
426	writel_relaxed(val, base + reg);
427}
428
429static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg)
430{
431	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
432	void __iomem *base = chip_data->host_data->base;
433	u32 val;
434
435	val = readl_relaxed(base + reg);
436	val |= BIT(d->hwirq % IRQS_PER_BANK);
437	writel_relaxed(val, base + reg);
438
439	return val;
440}
441
442static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg)
443{
444	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
445	void __iomem *base = chip_data->host_data->base;
446	u32 val;
447
448	val = readl_relaxed(base + reg);
449	val &= ~BIT(d->hwirq % IRQS_PER_BANK);
450	writel_relaxed(val, base + reg);
451
452	return val;
453}
454
455static void stm32_exti_h_eoi(struct irq_data *d)
456{
457	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
458	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
459
460	raw_spin_lock(&chip_data->rlock);
461
462	stm32_exti_write_bit(d, stm32_bank->rpr_ofst);
463	if (stm32_bank->fpr_ofst != UNDEF_REG)
464		stm32_exti_write_bit(d, stm32_bank->fpr_ofst);
465
466	raw_spin_unlock(&chip_data->rlock);
467
468	if (d->parent_data->chip)
469		irq_chip_eoi_parent(d);
470}
471
472static void stm32_exti_h_mask(struct irq_data *d)
473{
474	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
475	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
476
477	raw_spin_lock(&chip_data->rlock);
478	chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst);
479	raw_spin_unlock(&chip_data->rlock);
480
481	if (d->parent_data->chip)
482		irq_chip_mask_parent(d);
483}
484
485static void stm32_exti_h_unmask(struct irq_data *d)
486{
487	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
488	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
489
490	raw_spin_lock(&chip_data->rlock);
491	chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst);
492	raw_spin_unlock(&chip_data->rlock);
493
494	if (d->parent_data->chip)
495		irq_chip_unmask_parent(d);
496}
497
498static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type)
499{
500	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
501	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
502	struct hwspinlock *hwlock = chip_data->host_data->hwlock;
503	void __iomem *base = chip_data->host_data->base;
504	u32 rtsr, ftsr;
505	int err;
506
507	raw_spin_lock(&chip_data->rlock);
508
509	if (hwlock) {
510		err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT);
511		if (err) {
512			pr_err("%s can't get hwspinlock (%d)\n", __func__, err);
513			goto unlock;
514		}
515	}
516
517	rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst);
518	ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst);
519
520	err = stm32_exti_set_type(d, type, &rtsr, &ftsr);
521	if (err)
522		goto unspinlock;
523
524	writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst);
525	writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst);
526
527unspinlock:
528	if (hwlock)
529		hwspin_unlock_in_atomic(hwlock);
530unlock:
531	raw_spin_unlock(&chip_data->rlock);
532
533	return err;
534}
535
536static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on)
537{
538	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
539	u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
540
541	raw_spin_lock(&chip_data->rlock);
542
543	if (on)
544		chip_data->wake_active |= mask;
545	else
546		chip_data->wake_active &= ~mask;
547
548	raw_spin_unlock(&chip_data->rlock);
549
550	return 0;
551}
552
553static int stm32_exti_h_set_affinity(struct irq_data *d,
554				     const struct cpumask *dest, bool force)
555{
556	if (d->parent_data->chip)
557		return irq_chip_set_affinity_parent(d, dest, force);
558
559	return -EINVAL;
560}
561
562static int __maybe_unused stm32_exti_h_suspend(void)
563{
564	struct stm32_exti_chip_data *chip_data;
565	int i;
566
567	for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
568		chip_data = &stm32_host_data->chips_data[i];
569		raw_spin_lock(&chip_data->rlock);
570		stm32_chip_suspend(chip_data, chip_data->wake_active);
571		raw_spin_unlock(&chip_data->rlock);
572	}
573
574	return 0;
575}
576
577static void __maybe_unused stm32_exti_h_resume(void)
578{
579	struct stm32_exti_chip_data *chip_data;
580	int i;
581
582	for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) {
583		chip_data = &stm32_host_data->chips_data[i];
584		raw_spin_lock(&chip_data->rlock);
585		stm32_chip_resume(chip_data, chip_data->mask_cache);
586		raw_spin_unlock(&chip_data->rlock);
587	}
588}
589
590static struct syscore_ops stm32_exti_h_syscore_ops = {
591#ifdef CONFIG_PM_SLEEP
592	.suspend	= stm32_exti_h_suspend,
593	.resume		= stm32_exti_h_resume,
594#endif
595};
596
597static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data)
598{
599	stm32_host_data = host_data;
600	register_syscore_ops(&stm32_exti_h_syscore_ops);
601}
602
603static void stm32_exti_h_syscore_deinit(void)
604{
605	unregister_syscore_ops(&stm32_exti_h_syscore_ops);
606}
607
608static int stm32_exti_h_retrigger(struct irq_data *d)
609{
610	struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d);
611	const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank;
612	void __iomem *base = chip_data->host_data->base;
613	u32 mask = BIT(d->hwirq % IRQS_PER_BANK);
614
615	writel_relaxed(mask, base + stm32_bank->swier_ofst);
616
617	return 0;
618}
619
620static struct irq_chip stm32_exti_h_chip = {
621	.name			= "stm32-exti-h",
622	.irq_eoi		= stm32_exti_h_eoi,
623	.irq_mask		= stm32_exti_h_mask,
624	.irq_unmask		= stm32_exti_h_unmask,
625	.irq_retrigger		= stm32_exti_h_retrigger,
626	.irq_set_type		= stm32_exti_h_set_type,
627	.irq_set_wake		= stm32_exti_h_set_wake,
628	.flags			= IRQCHIP_MASK_ON_SUSPEND,
629	.irq_set_affinity	= IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL,
630};
631
632static struct irq_chip stm32_exti_h_chip_direct = {
633	.name			= "stm32-exti-h-direct",
634	.irq_eoi		= irq_chip_eoi_parent,
635	.irq_ack		= irq_chip_ack_parent,
636	.irq_mask		= irq_chip_mask_parent,
637	.irq_unmask		= irq_chip_unmask_parent,
638	.irq_retrigger		= irq_chip_retrigger_hierarchy,
639	.irq_set_type		= irq_chip_set_type_parent,
640	.irq_set_wake		= stm32_exti_h_set_wake,
641	.flags			= IRQCHIP_MASK_ON_SUSPEND,
642	.irq_set_affinity	= IS_ENABLED(CONFIG_SMP) ? irq_chip_set_affinity_parent : NULL,
643};
644
645static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
646				     unsigned int virq,
647				     unsigned int nr_irqs, void *data)
648{
649	struct stm32_exti_host_data *host_data = dm->host_data;
650	struct stm32_exti_chip_data *chip_data;
651	const struct stm32_desc_irq *desc;
652	struct irq_fwspec *fwspec = data;
653	struct irq_fwspec p_fwspec;
654	irq_hw_number_t hwirq;
655	int bank;
656
657	hwirq = fwspec->param[0];
658	bank  = hwirq / IRQS_PER_BANK;
659	chip_data = &host_data->chips_data[bank];
660
661
662	desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
663	if (!desc)
664		return -EINVAL;
665
666	irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
667				      chip_data);
668	if (desc->irq_parent) {
669		p_fwspec.fwnode = dm->parent->fwnode;
670		p_fwspec.param_count = 3;
671		p_fwspec.param[0] = GIC_SPI;
672		p_fwspec.param[1] = desc->irq_parent;
673		p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;
674
675		return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
676	}
677
678	return 0;
679}
680
681static struct
682stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd,
683					   struct device_node *node)
684{
685	struct stm32_exti_host_data *host_data;
686
687	host_data = kzalloc(sizeof(*host_data), GFP_KERNEL);
688	if (!host_data)
689		return NULL;
690
691	host_data->drv_data = dd;
692	host_data->chips_data = kcalloc(dd->bank_nr,
693					sizeof(struct stm32_exti_chip_data),
694					GFP_KERNEL);
695	if (!host_data->chips_data)
696		goto free_host_data;
697
698	host_data->base = of_iomap(node, 0);
699	if (!host_data->base) {
700		pr_err("%pOF: Unable to map registers\n", node);
701		goto free_chips_data;
702	}
703
704	stm32_host_data = host_data;
705
706	return host_data;
707
708free_chips_data:
709	kfree(host_data->chips_data);
710free_host_data:
711	kfree(host_data);
712
713	return NULL;
714}
715
716static struct
717stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
718					   u32 bank_idx,
719					   struct device_node *node)
720{
721	const struct stm32_exti_bank *stm32_bank;
722	struct stm32_exti_chip_data *chip_data;
723	void __iomem *base = h_data->base;
724
725	stm32_bank = h_data->drv_data->exti_banks[bank_idx];
726	chip_data = &h_data->chips_data[bank_idx];
727	chip_data->host_data = h_data;
728	chip_data->reg_bank = stm32_bank;
729
730	raw_spin_lock_init(&chip_data->rlock);
731
732	/*
733	 * This IP has no reset, so after hot reboot we should
734	 * clear registers to avoid residue
735	 */
736	writel_relaxed(0, base + stm32_bank->imr_ofst);
737	writel_relaxed(0, base + stm32_bank->emr_ofst);
738
739	pr_info("%pOF: bank%d\n", node, bank_idx);
740
741	return chip_data;
742}
743
744static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data,
745				  struct device_node *node)
746{
747	struct stm32_exti_host_data *host_data;
748	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
749	int nr_irqs, ret, i;
750	struct irq_chip_generic *gc;
751	struct irq_domain *domain;
752
753	host_data = stm32_exti_host_init(drv_data, node);
754	if (!host_data)
755		return -ENOMEM;
756
757	domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK,
758				       &irq_exti_domain_ops, NULL);
759	if (!domain) {
760		pr_err("%pOFn: Could not register interrupt domain.\n",
761		       node);
762		ret = -ENOMEM;
763		goto out_unmap;
764	}
765
766	ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
767					     handle_edge_irq, clr, 0, 0);
768	if (ret) {
769		pr_err("%pOF: Could not allocate generic interrupt chip.\n",
770		       node);
771		goto out_free_domain;
772	}
773
774	for (i = 0; i < drv_data->bank_nr; i++) {
775		const struct stm32_exti_bank *stm32_bank;
776		struct stm32_exti_chip_data *chip_data;
777
778		stm32_bank = drv_data->exti_banks[i];
779		chip_data = stm32_exti_chip_init(host_data, i, node);
780
781		gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
782
783		gc->reg_base = host_data->base;
784		gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
785		gc->chip_types->chip.irq_ack = stm32_irq_ack;
786		gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
787		gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
788		gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
789		gc->chip_types->chip.irq_set_wake = irq_gc_set_wake;
790		gc->suspend = stm32_irq_suspend;
791		gc->resume = stm32_irq_resume;
792		gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK);
793
794		gc->chip_types->regs.mask = stm32_bank->imr_ofst;
795		gc->private = (void *)chip_data;
796	}
797
798	nr_irqs = of_irq_count(node);
799	for (i = 0; i < nr_irqs; i++) {
800		unsigned int irq = irq_of_parse_and_map(node, i);
801
802		irq_set_handler_data(irq, domain);
803		irq_set_chained_handler(irq, stm32_irq_handler);
804	}
805
806	return 0;
807
808out_free_domain:
809	irq_domain_remove(domain);
810out_unmap:
811	iounmap(host_data->base);
812	kfree(host_data->chips_data);
813	kfree(host_data);
814	return ret;
815}
816
817static const struct irq_domain_ops stm32_exti_h_domain_ops = {
818	.alloc	= stm32_exti_h_domain_alloc,
819	.free	= irq_domain_free_irqs_common,
820	.xlate = irq_domain_xlate_twocell,
821};
822
823static void stm32_exti_remove_irq(void *data)
824{
825	struct irq_domain *domain = data;
826
827	irq_domain_remove(domain);
828}
829
830static int stm32_exti_remove(struct platform_device *pdev)
831{
832	stm32_exti_h_syscore_deinit();
833	return 0;
834}
835
836static int stm32_exti_probe(struct platform_device *pdev)
837{
838	int ret, i;
839	struct device *dev = &pdev->dev;
840	struct device_node *np = dev->of_node;
841	struct irq_domain *parent_domain, *domain;
842	struct stm32_exti_host_data *host_data;
843	const struct stm32_exti_drv_data *drv_data;
844	struct resource *res;
845
846	host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL);
847	if (!host_data)
848		return -ENOMEM;
849
850	/* check for optional hwspinlock which may be not available yet */
851	ret = of_hwspin_lock_get_id(np, 0);
852	if (ret == -EPROBE_DEFER)
853		/* hwspinlock framework not yet ready */
854		return ret;
855
856	if (ret >= 0) {
857		host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
858		if (!host_data->hwlock) {
859			dev_err(dev, "Failed to request hwspinlock\n");
860			return -EINVAL;
861		}
862	} else if (ret != -ENOENT) {
863		/* note: ENOENT is a valid case (means 'no hwspinlock') */
864		dev_err(dev, "Failed to get hwspinlock\n");
865		return ret;
866	}
867
868	/* initialize host_data */
869	drv_data = of_device_get_match_data(dev);
870	if (!drv_data) {
871		dev_err(dev, "no of match data\n");
872		return -ENODEV;
873	}
874	host_data->drv_data = drv_data;
875
876	host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr,
877					     sizeof(*host_data->chips_data),
878					     GFP_KERNEL);
879	if (!host_data->chips_data)
880		return -ENOMEM;
881
882	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
883	host_data->base = devm_ioremap_resource(dev, res);
884	if (IS_ERR(host_data->base)) {
885		dev_err(dev, "Unable to map registers\n");
886		return PTR_ERR(host_data->base);
887	}
888
889	for (i = 0; i < drv_data->bank_nr; i++)
890		stm32_exti_chip_init(host_data, i, np);
891
892	parent_domain = irq_find_host(of_irq_find_parent(np));
893	if (!parent_domain) {
894		dev_err(dev, "GIC interrupt-parent not found\n");
895		return -EINVAL;
896	}
897
898	domain = irq_domain_add_hierarchy(parent_domain, 0,
899					  drv_data->bank_nr * IRQS_PER_BANK,
900					  np, &stm32_exti_h_domain_ops,
901					  host_data);
902
903	if (!domain) {
904		dev_err(dev, "Could not register exti domain\n");
905		return -ENOMEM;
906	}
907
908	ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain);
909	if (ret)
910		return ret;
911
912	stm32_exti_h_syscore_init(host_data);
913
914	return 0;
915}
916
917/* platform driver only for MP1 */
918static const struct of_device_id stm32_exti_ids[] = {
919	{ .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data},
920	{},
921};
922MODULE_DEVICE_TABLE(of, stm32_exti_ids);
923
924static struct platform_driver stm32_exti_driver = {
925	.probe		= stm32_exti_probe,
926	.remove		= stm32_exti_remove,
927	.driver		= {
928		.name	= "stm32_exti",
929		.of_match_table = stm32_exti_ids,
930	},
931};
932
933static int __init stm32_exti_arch_init(void)
934{
935	return platform_driver_register(&stm32_exti_driver);
936}
937
938static void __exit stm32_exti_arch_exit(void)
939{
940	return platform_driver_unregister(&stm32_exti_driver);
941}
942
943arch_initcall(stm32_exti_arch_init);
944module_exit(stm32_exti_arch_exit);
945
946/* no platform driver for F4 and H7 */
947static int __init stm32f4_exti_of_init(struct device_node *np,
948				       struct device_node *parent)
949{
950	return stm32_exti_init(&stm32f4xx_drv_data, np);
951}
952
953IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
954
955static int __init stm32h7_exti_of_init(struct device_node *np,
956				       struct device_node *parent)
957{
958	return stm32_exti_init(&stm32h7xx_drv_data, np);
959}
960
961IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);