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1/*
2 * Marvell Armada 370 and Armada XP SoC IRQ handling
3 *
4 * Copyright (C) 2012 Marvell
5 *
6 * Lior Amsalem <alior@marvell.com>
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 * Ben Dooks <ben.dooks@codethink.co.uk>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/cpu.h>
24#include <linux/io.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/irqdomain.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31#include <linux/msi.h>
32#include <asm/mach/arch.h>
33#include <asm/exception.h>
34#include <asm/smp_plat.h>
35#include <asm/mach/irq.h>
36
37/*
38 * Overall diagram of the Armada XP interrupt controller:
39 *
40 * To CPU 0 To CPU 1
41 *
42 * /\ /\
43 * || ||
44 * +---------------+ +---------------+
45 * | | | |
46 * | per-CPU | | per-CPU |
47 * | mask/unmask | | mask/unmask |
48 * | CPU0 | | CPU1 |
49 * | | | |
50 * +---------------+ +---------------+
51 * /\ /\
52 * || ||
53 * \\_______________________//
54 * ||
55 * +-------------------+
56 * | |
57 * | Global interrupt |
58 * | mask/unmask |
59 * | |
60 * +-------------------+
61 * /\
62 * ||
63 * interrupt from
64 * device
65 *
66 * The "global interrupt mask/unmask" is modified using the
67 * ARMADA_370_XP_INT_SET_ENABLE_OFFS and
68 * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
69 * to "main_int_base".
70 *
71 * The "per-CPU mask/unmask" is modified using the
72 * ARMADA_370_XP_INT_SET_MASK_OFFS and
73 * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
74 * "per_cpu_int_base". This base address points to a special address,
75 * which automatically accesses the registers of the current CPU.
76 *
77 * The per-CPU mask/unmask can also be adjusted using the global
78 * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
79 * to configure interrupt affinity.
80 *
81 * Due to this model, all interrupts need to be mask/unmasked at two
82 * different levels: at the global level and at the per-CPU level.
83 *
84 * This driver takes the following approach to deal with this:
85 *
86 * - For global interrupts:
87 *
88 * At ->map() time, a global interrupt is unmasked at the per-CPU
89 * mask/unmask level. It is therefore unmasked at this level for
90 * the current CPU, running the ->map() code. This allows to have
91 * the interrupt unmasked at this level in non-SMP
92 * configurations. In SMP configurations, the ->set_affinity()
93 * callback is called, which using the
94 * ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
95 * for the interrupt.
96 *
97 * The ->mask() and ->unmask() operations only mask/unmask the
98 * interrupt at the "global" level.
99 *
100 * So, a global interrupt is enabled at the per-CPU level as soon
101 * as it is mapped. At run time, the masking/unmasking takes place
102 * at the global level.
103 *
104 * - For per-CPU interrupts
105 *
106 * At ->map() time, a per-CPU interrupt is unmasked at the global
107 * mask/unmask level.
108 *
109 * The ->mask() and ->unmask() operations mask/unmask the interrupt
110 * at the per-CPU level.
111 *
112 * So, a per-CPU interrupt is enabled at the global level as soon
113 * as it is mapped. At run time, the masking/unmasking takes place
114 * at the per-CPU level.
115 */
116
117/* Registers relative to main_int_base */
118#define ARMADA_370_XP_INT_CONTROL (0x00)
119#define ARMADA_370_XP_SW_TRIG_INT_OFFS (0x04)
120#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
121#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
122#define ARMADA_370_XP_INT_SOURCE_CTL(irq) (0x100 + irq*4)
123#define ARMADA_370_XP_INT_SOURCE_CPU_MASK 0xF
124#define ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << cpuid)
125
126/* Registers relative to per_cpu_int_base */
127#define ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS (0x08)
128#define ARMADA_370_XP_IN_DRBEL_MSK_OFFS (0x0c)
129#define ARMADA_375_PPI_CAUSE (0x10)
130#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
131#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
132#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
133#define ARMADA_370_XP_INT_FABRIC_MASK_OFFS (0x54)
134#define ARMADA_370_XP_INT_CAUSE_PERF(cpu) (1 << cpu)
135
136#define ARMADA_370_XP_MAX_PER_CPU_IRQS (28)
137
138#define IPI_DOORBELL_START (0)
139#define IPI_DOORBELL_END (8)
140#define IPI_DOORBELL_MASK 0xFF
141#define PCI_MSI_DOORBELL_START (16)
142#define PCI_MSI_DOORBELL_NR (16)
143#define PCI_MSI_DOORBELL_END (32)
144#define PCI_MSI_DOORBELL_MASK 0xFFFF0000
145
146static void __iomem *per_cpu_int_base;
147static void __iomem *main_int_base;
148static struct irq_domain *armada_370_xp_mpic_domain;
149static u32 doorbell_mask_reg;
150static int parent_irq;
151#ifdef CONFIG_PCI_MSI
152static struct irq_domain *armada_370_xp_msi_domain;
153static struct irq_domain *armada_370_xp_msi_inner_domain;
154static DECLARE_BITMAP(msi_used, PCI_MSI_DOORBELL_NR);
155static DEFINE_MUTEX(msi_used_lock);
156static phys_addr_t msi_doorbell_addr;
157#endif
158
159static inline bool is_percpu_irq(irq_hw_number_t irq)
160{
161 if (irq <= ARMADA_370_XP_MAX_PER_CPU_IRQS)
162 return true;
163
164 return false;
165}
166
167/*
168 * In SMP mode:
169 * For shared global interrupts, mask/unmask global enable bit
170 * For CPU interrupts, mask/unmask the calling CPU's bit
171 */
172static void armada_370_xp_irq_mask(struct irq_data *d)
173{
174 irq_hw_number_t hwirq = irqd_to_hwirq(d);
175
176 if (!is_percpu_irq(hwirq))
177 writel(hwirq, main_int_base +
178 ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
179 else
180 writel(hwirq, per_cpu_int_base +
181 ARMADA_370_XP_INT_SET_MASK_OFFS);
182}
183
184static void armada_370_xp_irq_unmask(struct irq_data *d)
185{
186 irq_hw_number_t hwirq = irqd_to_hwirq(d);
187
188 if (!is_percpu_irq(hwirq))
189 writel(hwirq, main_int_base +
190 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
191 else
192 writel(hwirq, per_cpu_int_base +
193 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
194}
195
196#ifdef CONFIG_PCI_MSI
197
198static struct irq_chip armada_370_xp_msi_irq_chip = {
199 .name = "MPIC MSI",
200 .irq_mask = pci_msi_mask_irq,
201 .irq_unmask = pci_msi_unmask_irq,
202};
203
204static struct msi_domain_info armada_370_xp_msi_domain_info = {
205 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
206 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
207 .chip = &armada_370_xp_msi_irq_chip,
208};
209
210static void armada_370_xp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
211{
212 msg->address_lo = lower_32_bits(msi_doorbell_addr);
213 msg->address_hi = upper_32_bits(msi_doorbell_addr);
214 msg->data = 0xf00 | (data->hwirq + PCI_MSI_DOORBELL_START);
215}
216
217static int armada_370_xp_msi_set_affinity(struct irq_data *irq_data,
218 const struct cpumask *mask, bool force)
219{
220 return -EINVAL;
221}
222
223static struct irq_chip armada_370_xp_msi_bottom_irq_chip = {
224 .name = "MPIC MSI",
225 .irq_compose_msi_msg = armada_370_xp_compose_msi_msg,
226 .irq_set_affinity = armada_370_xp_msi_set_affinity,
227};
228
229static int armada_370_xp_msi_alloc(struct irq_domain *domain, unsigned int virq,
230 unsigned int nr_irqs, void *args)
231{
232 int hwirq, i;
233
234 mutex_lock(&msi_used_lock);
235
236 hwirq = bitmap_find_next_zero_area(msi_used, PCI_MSI_DOORBELL_NR,
237 0, nr_irqs, 0);
238 if (hwirq >= PCI_MSI_DOORBELL_NR) {
239 mutex_unlock(&msi_used_lock);
240 return -ENOSPC;
241 }
242
243 bitmap_set(msi_used, hwirq, nr_irqs);
244 mutex_unlock(&msi_used_lock);
245
246 for (i = 0; i < nr_irqs; i++) {
247 irq_domain_set_info(domain, virq + i, hwirq + i,
248 &armada_370_xp_msi_bottom_irq_chip,
249 domain->host_data, handle_simple_irq,
250 NULL, NULL);
251 }
252
253 return hwirq;
254}
255
256static void armada_370_xp_msi_free(struct irq_domain *domain,
257 unsigned int virq, unsigned int nr_irqs)
258{
259 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
260
261 mutex_lock(&msi_used_lock);
262 bitmap_clear(msi_used, d->hwirq, nr_irqs);
263 mutex_unlock(&msi_used_lock);
264}
265
266static const struct irq_domain_ops armada_370_xp_msi_domain_ops = {
267 .alloc = armada_370_xp_msi_alloc,
268 .free = armada_370_xp_msi_free,
269};
270
271static int armada_370_xp_msi_init(struct device_node *node,
272 phys_addr_t main_int_phys_base)
273{
274 u32 reg;
275
276 msi_doorbell_addr = main_int_phys_base +
277 ARMADA_370_XP_SW_TRIG_INT_OFFS;
278
279 armada_370_xp_msi_inner_domain =
280 irq_domain_add_linear(NULL, PCI_MSI_DOORBELL_NR,
281 &armada_370_xp_msi_domain_ops, NULL);
282 if (!armada_370_xp_msi_inner_domain)
283 return -ENOMEM;
284
285 armada_370_xp_msi_domain =
286 pci_msi_create_irq_domain(of_node_to_fwnode(node),
287 &armada_370_xp_msi_domain_info,
288 armada_370_xp_msi_inner_domain);
289 if (!armada_370_xp_msi_domain) {
290 irq_domain_remove(armada_370_xp_msi_inner_domain);
291 return -ENOMEM;
292 }
293
294 reg = readl(per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS)
295 | PCI_MSI_DOORBELL_MASK;
296
297 writel(reg, per_cpu_int_base +
298 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
299
300 /* Unmask IPI interrupt */
301 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
302
303 return 0;
304}
305#else
306static inline int armada_370_xp_msi_init(struct device_node *node,
307 phys_addr_t main_int_phys_base)
308{
309 return 0;
310}
311#endif
312
313#ifdef CONFIG_SMP
314static DEFINE_RAW_SPINLOCK(irq_controller_lock);
315
316static int armada_xp_set_affinity(struct irq_data *d,
317 const struct cpumask *mask_val, bool force)
318{
319 irq_hw_number_t hwirq = irqd_to_hwirq(d);
320 unsigned long reg, mask;
321 int cpu;
322
323 /* Select a single core from the affinity mask which is online */
324 cpu = cpumask_any_and(mask_val, cpu_online_mask);
325 mask = 1UL << cpu_logical_map(cpu);
326
327 raw_spin_lock(&irq_controller_lock);
328 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
329 reg = (reg & (~ARMADA_370_XP_INT_SOURCE_CPU_MASK)) | mask;
330 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));
331 raw_spin_unlock(&irq_controller_lock);
332
333 irq_data_update_effective_affinity(d, cpumask_of(cpu));
334
335 return IRQ_SET_MASK_OK;
336}
337#endif
338
339static struct irq_chip armada_370_xp_irq_chip = {
340 .name = "MPIC",
341 .irq_mask = armada_370_xp_irq_mask,
342 .irq_mask_ack = armada_370_xp_irq_mask,
343 .irq_unmask = armada_370_xp_irq_unmask,
344#ifdef CONFIG_SMP
345 .irq_set_affinity = armada_xp_set_affinity,
346#endif
347 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
348};
349
350static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
351 unsigned int virq, irq_hw_number_t hw)
352{
353 armada_370_xp_irq_mask(irq_get_irq_data(virq));
354 if (!is_percpu_irq(hw))
355 writel(hw, per_cpu_int_base +
356 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
357 else
358 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
359 irq_set_status_flags(virq, IRQ_LEVEL);
360
361 if (is_percpu_irq(hw)) {
362 irq_set_percpu_devid(virq);
363 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
364 handle_percpu_devid_irq);
365 } else {
366 irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
367 handle_level_irq);
368 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
369 }
370 irq_set_probe(virq);
371
372 return 0;
373}
374
375static void armada_xp_mpic_smp_cpu_init(void)
376{
377 u32 control;
378 int nr_irqs, i;
379
380 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
381 nr_irqs = (control >> 2) & 0x3ff;
382
383 for (i = 0; i < nr_irqs; i++)
384 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
385
386 /* Clear pending IPIs */
387 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
388
389 /* Enable first 8 IPIs */
390 writel(IPI_DOORBELL_MASK, per_cpu_int_base +
391 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
392
393 /* Unmask IPI interrupt */
394 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
395}
396
397static void armada_xp_mpic_perf_init(void)
398{
399 unsigned long cpuid = cpu_logical_map(smp_processor_id());
400
401 /* Enable Performance Counter Overflow interrupts */
402 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),
403 per_cpu_int_base + ARMADA_370_XP_INT_FABRIC_MASK_OFFS);
404}
405
406#ifdef CONFIG_SMP
407static void armada_mpic_send_doorbell(const struct cpumask *mask,
408 unsigned int irq)
409{
410 int cpu;
411 unsigned long map = 0;
412
413 /* Convert our logical CPU mask into a physical one. */
414 for_each_cpu(cpu, mask)
415 map |= 1 << cpu_logical_map(cpu);
416
417 /*
418 * Ensure that stores to Normal memory are visible to the
419 * other CPUs before issuing the IPI.
420 */
421 dsb();
422
423 /* submit softirq */
424 writel((map << 8) | irq, main_int_base +
425 ARMADA_370_XP_SW_TRIG_INT_OFFS);
426}
427
428static void armada_xp_mpic_reenable_percpu(void)
429{
430 unsigned int irq;
431
432 /* Re-enable per-CPU interrupts that were enabled before suspend */
433 for (irq = 0; irq < ARMADA_370_XP_MAX_PER_CPU_IRQS; irq++) {
434 struct irq_data *data;
435 int virq;
436
437 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
438 if (virq == 0)
439 continue;
440
441 data = irq_get_irq_data(virq);
442
443 if (!irq_percpu_is_enabled(virq))
444 continue;
445
446 armada_370_xp_irq_unmask(data);
447 }
448}
449
450static int armada_xp_mpic_starting_cpu(unsigned int cpu)
451{
452 armada_xp_mpic_perf_init();
453 armada_xp_mpic_smp_cpu_init();
454 armada_xp_mpic_reenable_percpu();
455 return 0;
456}
457
458static int mpic_cascaded_starting_cpu(unsigned int cpu)
459{
460 armada_xp_mpic_perf_init();
461 armada_xp_mpic_reenable_percpu();
462 enable_percpu_irq(parent_irq, IRQ_TYPE_NONE);
463 return 0;
464}
465#endif
466
467static const struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
468 .map = armada_370_xp_mpic_irq_map,
469 .xlate = irq_domain_xlate_onecell,
470};
471
472#ifdef CONFIG_PCI_MSI
473static void armada_370_xp_handle_msi_irq(struct pt_regs *regs, bool is_chained)
474{
475 u32 msimask, msinr;
476
477 msimask = readl_relaxed(per_cpu_int_base +
478 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
479 & PCI_MSI_DOORBELL_MASK;
480
481 writel(~msimask, per_cpu_int_base +
482 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
483
484 for (msinr = PCI_MSI_DOORBELL_START;
485 msinr < PCI_MSI_DOORBELL_END; msinr++) {
486 int irq;
487
488 if (!(msimask & BIT(msinr)))
489 continue;
490
491 if (is_chained) {
492 irq = irq_find_mapping(armada_370_xp_msi_inner_domain,
493 msinr - PCI_MSI_DOORBELL_START);
494 generic_handle_irq(irq);
495 } else {
496 irq = msinr - PCI_MSI_DOORBELL_START;
497 handle_domain_irq(armada_370_xp_msi_inner_domain,
498 irq, regs);
499 }
500 }
501}
502#else
503static void armada_370_xp_handle_msi_irq(struct pt_regs *r, bool b) {}
504#endif
505
506static void armada_370_xp_mpic_handle_cascade_irq(struct irq_desc *desc)
507{
508 struct irq_chip *chip = irq_desc_get_chip(desc);
509 unsigned long irqmap, irqn, irqsrc, cpuid;
510 unsigned int cascade_irq;
511
512 chained_irq_enter(chip, desc);
513
514 irqmap = readl_relaxed(per_cpu_int_base + ARMADA_375_PPI_CAUSE);
515 cpuid = cpu_logical_map(smp_processor_id());
516
517 for_each_set_bit(irqn, &irqmap, BITS_PER_LONG) {
518 irqsrc = readl_relaxed(main_int_base +
519 ARMADA_370_XP_INT_SOURCE_CTL(irqn));
520
521 /* Check if the interrupt is not masked on current CPU.
522 * Test IRQ (0-1) and FIQ (8-9) mask bits.
523 */
524 if (!(irqsrc & ARMADA_370_XP_INT_IRQ_FIQ_MASK(cpuid)))
525 continue;
526
527 if (irqn == 1) {
528 armada_370_xp_handle_msi_irq(NULL, true);
529 continue;
530 }
531
532 cascade_irq = irq_find_mapping(armada_370_xp_mpic_domain, irqn);
533 generic_handle_irq(cascade_irq);
534 }
535
536 chained_irq_exit(chip, desc);
537}
538
539static void __exception_irq_entry
540armada_370_xp_handle_irq(struct pt_regs *regs)
541{
542 u32 irqstat, irqnr;
543
544 do {
545 irqstat = readl_relaxed(per_cpu_int_base +
546 ARMADA_370_XP_CPU_INTACK_OFFS);
547 irqnr = irqstat & 0x3FF;
548
549 if (irqnr > 1022)
550 break;
551
552 if (irqnr > 1) {
553 handle_domain_irq(armada_370_xp_mpic_domain,
554 irqnr, regs);
555 continue;
556 }
557
558 /* MSI handling */
559 if (irqnr == 1)
560 armada_370_xp_handle_msi_irq(regs, false);
561
562#ifdef CONFIG_SMP
563 /* IPI Handling */
564 if (irqnr == 0) {
565 u32 ipimask, ipinr;
566
567 ipimask = readl_relaxed(per_cpu_int_base +
568 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS)
569 & IPI_DOORBELL_MASK;
570
571 writel(~ipimask, per_cpu_int_base +
572 ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);
573
574 /* Handle all pending doorbells */
575 for (ipinr = IPI_DOORBELL_START;
576 ipinr < IPI_DOORBELL_END; ipinr++) {
577 if (ipimask & (0x1 << ipinr))
578 handle_IPI(ipinr, regs);
579 }
580 continue;
581 }
582#endif
583
584 } while (1);
585}
586
587static int armada_370_xp_mpic_suspend(void)
588{
589 doorbell_mask_reg = readl(per_cpu_int_base +
590 ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
591 return 0;
592}
593
594static void armada_370_xp_mpic_resume(void)
595{
596 int nirqs;
597 irq_hw_number_t irq;
598
599 /* Re-enable interrupts */
600 nirqs = (readl(main_int_base + ARMADA_370_XP_INT_CONTROL) >> 2) & 0x3ff;
601 for (irq = 0; irq < nirqs; irq++) {
602 struct irq_data *data;
603 int virq;
604
605 virq = irq_linear_revmap(armada_370_xp_mpic_domain, irq);
606 if (virq == 0)
607 continue;
608
609 data = irq_get_irq_data(virq);
610
611 if (!is_percpu_irq(irq)) {
612 /* Non per-CPU interrupts */
613 writel(irq, per_cpu_int_base +
614 ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
615 if (!irqd_irq_disabled(data))
616 armada_370_xp_irq_unmask(data);
617 } else {
618 /* Per-CPU interrupts */
619 writel(irq, main_int_base +
620 ARMADA_370_XP_INT_SET_ENABLE_OFFS);
621
622 /*
623 * Re-enable on the current CPU,
624 * armada_xp_mpic_reenable_percpu() will take
625 * care of secondary CPUs when they come up.
626 */
627 if (irq_percpu_is_enabled(virq))
628 armada_370_xp_irq_unmask(data);
629 }
630 }
631
632 /* Reconfigure doorbells for IPIs and MSIs */
633 writel(doorbell_mask_reg,
634 per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_MSK_OFFS);
635 if (doorbell_mask_reg & IPI_DOORBELL_MASK)
636 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
637 if (doorbell_mask_reg & PCI_MSI_DOORBELL_MASK)
638 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
639}
640
641static struct syscore_ops armada_370_xp_mpic_syscore_ops = {
642 .suspend = armada_370_xp_mpic_suspend,
643 .resume = armada_370_xp_mpic_resume,
644};
645
646static int __init armada_370_xp_mpic_of_init(struct device_node *node,
647 struct device_node *parent)
648{
649 struct resource main_int_res, per_cpu_int_res;
650 int nr_irqs, i;
651 u32 control;
652
653 BUG_ON(of_address_to_resource(node, 0, &main_int_res));
654 BUG_ON(of_address_to_resource(node, 1, &per_cpu_int_res));
655
656 BUG_ON(!request_mem_region(main_int_res.start,
657 resource_size(&main_int_res),
658 node->full_name));
659 BUG_ON(!request_mem_region(per_cpu_int_res.start,
660 resource_size(&per_cpu_int_res),
661 node->full_name));
662
663 main_int_base = ioremap(main_int_res.start,
664 resource_size(&main_int_res));
665 BUG_ON(!main_int_base);
666
667 per_cpu_int_base = ioremap(per_cpu_int_res.start,
668 resource_size(&per_cpu_int_res));
669 BUG_ON(!per_cpu_int_base);
670
671 control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
672 nr_irqs = (control >> 2) & 0x3ff;
673
674 for (i = 0; i < nr_irqs; i++)
675 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);
676
677 armada_370_xp_mpic_domain =
678 irq_domain_add_linear(node, nr_irqs,
679 &armada_370_xp_mpic_irq_ops, NULL);
680 BUG_ON(!armada_370_xp_mpic_domain);
681 irq_domain_update_bus_token(armada_370_xp_mpic_domain, DOMAIN_BUS_WIRED);
682
683 /* Setup for the boot CPU */
684 armada_xp_mpic_perf_init();
685 armada_xp_mpic_smp_cpu_init();
686
687 armada_370_xp_msi_init(node, main_int_res.start);
688
689 parent_irq = irq_of_parse_and_map(node, 0);
690 if (parent_irq <= 0) {
691 irq_set_default_host(armada_370_xp_mpic_domain);
692 set_handle_irq(armada_370_xp_handle_irq);
693#ifdef CONFIG_SMP
694 set_smp_cross_call(armada_mpic_send_doorbell);
695 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
696 "irqchip/armada/ipi:starting",
697 armada_xp_mpic_starting_cpu, NULL);
698#endif
699 } else {
700#ifdef CONFIG_SMP
701 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
702 "irqchip/armada/cascade:starting",
703 mpic_cascaded_starting_cpu, NULL);
704#endif
705 irq_set_chained_handler(parent_irq,
706 armada_370_xp_mpic_handle_cascade_irq);
707 }
708
709 register_syscore_ops(&armada_370_xp_mpic_syscore_ops);
710
711 return 0;
712}
713
714IRQCHIP_DECLARE(armada_370_xp_mpic, "marvell,mpic", armada_370_xp_mpic_of_init);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Marvell Armada 370 and Armada XP SoC IRQ handling
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Lior Amsalem <alior@marvell.com>
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
10 * Ben Dooks <ben.dooks@codethink.co.uk>
11 */
12
13#include <linux/bitfield.h>
14#include <linux/bits.h>
15#include <linux/err.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/init.h>
19#include <linux/irq.h>
20#include <linux/interrupt.h>
21#include <linux/irqchip.h>
22#include <linux/irqchip/chained_irq.h>
23#include <linux/cpu.h>
24#include <linux/io.h>
25#include <linux/of_address.h>
26#include <linux/of_irq.h>
27#include <linux/of_pci.h>
28#include <linux/irqdomain.h>
29#include <linux/slab.h>
30#include <linux/syscore_ops.h>
31#include <linux/msi.h>
32#include <linux/types.h>
33#include <asm/mach/arch.h>
34#include <asm/exception.h>
35#include <asm/smp_plat.h>
36#include <asm/mach/irq.h>
37
38/*
39 * Overall diagram of the Armada XP interrupt controller:
40 *
41 * To CPU 0 To CPU 1
42 *
43 * /\ /\
44 * || ||
45 * +---------------+ +---------------+
46 * | | | |
47 * | per-CPU | | per-CPU |
48 * | mask/unmask | | mask/unmask |
49 * | CPU0 | | CPU1 |
50 * | | | |
51 * +---------------+ +---------------+
52 * /\ /\
53 * || ||
54 * \\_______________________//
55 * ||
56 * +-------------------+
57 * | |
58 * | Global interrupt |
59 * | mask/unmask |
60 * | |
61 * +-------------------+
62 * /\
63 * ||
64 * interrupt from
65 * device
66 *
67 * The "global interrupt mask/unmask" is modified using the
68 * MPIC_INT_SET_ENABLE and MPIC_INT_CLEAR_ENABLE
69 * registers, which are relative to "mpic->base".
70 *
71 * The "per-CPU mask/unmask" is modified using the MPIC_INT_SET_MASK
72 * and MPIC_INT_CLEAR_MASK registers, which are relative to
73 * "mpic->per_cpu". This base address points to a special address,
74 * which automatically accesses the registers of the current CPU.
75 *
76 * The per-CPU mask/unmask can also be adjusted using the global
77 * per-interrupt MPIC_INT_SOURCE_CTL register, which we use to
78 * configure interrupt affinity.
79 *
80 * Due to this model, all interrupts need to be mask/unmasked at two
81 * different levels: at the global level and at the per-CPU level.
82 *
83 * This driver takes the following approach to deal with this:
84 *
85 * - For global interrupts:
86 *
87 * At ->map() time, a global interrupt is unmasked at the per-CPU
88 * mask/unmask level. It is therefore unmasked at this level for
89 * the current CPU, running the ->map() code. This allows to have
90 * the interrupt unmasked at this level in non-SMP
91 * configurations. In SMP configurations, the ->set_affinity()
92 * callback is called, which using the MPIC_INT_SOURCE_CTL()
93 * readjusts the per-CPU mask/unmask for the interrupt.
94 *
95 * The ->mask() and ->unmask() operations only mask/unmask the
96 * interrupt at the "global" level.
97 *
98 * So, a global interrupt is enabled at the per-CPU level as soon
99 * as it is mapped. At run time, the masking/unmasking takes place
100 * at the global level.
101 *
102 * - For per-CPU interrupts
103 *
104 * At ->map() time, a per-CPU interrupt is unmasked at the global
105 * mask/unmask level.
106 *
107 * The ->mask() and ->unmask() operations mask/unmask the interrupt
108 * at the per-CPU level.
109 *
110 * So, a per-CPU interrupt is enabled at the global level as soon
111 * as it is mapped. At run time, the masking/unmasking takes place
112 * at the per-CPU level.
113 */
114
115/* Registers relative to mpic->base */
116#define MPIC_INT_CONTROL 0x00
117#define MPIC_INT_CONTROL_NUMINT_MASK GENMASK(12, 2)
118#define MPIC_SW_TRIG_INT 0x04
119#define MPIC_INT_SET_ENABLE 0x30
120#define MPIC_INT_CLEAR_ENABLE 0x34
121#define MPIC_INT_SOURCE_CTL(hwirq) (0x100 + (hwirq) * 4)
122#define MPIC_INT_SOURCE_CPU_MASK GENMASK(3, 0)
123#define MPIC_INT_IRQ_FIQ_MASK(cpuid) ((BIT(0) | BIT(8)) << (cpuid))
124
125/* Registers relative to mpic->per_cpu */
126#define MPIC_IN_DRBEL_CAUSE 0x08
127#define MPIC_IN_DRBEL_MASK 0x0c
128#define MPIC_PPI_CAUSE 0x10
129#define MPIC_CPU_INTACK 0x44
130#define MPIC_CPU_INTACK_IID_MASK GENMASK(9, 0)
131#define MPIC_INT_SET_MASK 0x48
132#define MPIC_INT_CLEAR_MASK 0x4C
133#define MPIC_INT_FABRIC_MASK 0x54
134#define MPIC_INT_CAUSE_PERF(cpu) BIT(cpu)
135
136#define MPIC_PER_CPU_IRQS_NR 29
137
138/* IPI and MSI interrupt definitions for IPI platforms */
139#define IPI_DOORBELL_NR 8
140#define IPI_DOORBELL_MASK GENMASK(7, 0)
141#define PCI_MSI_DOORBELL_START 16
142#define PCI_MSI_DOORBELL_NR 16
143#define PCI_MSI_DOORBELL_MASK GENMASK(31, 16)
144
145/* MSI interrupt definitions for non-IPI platforms */
146#define PCI_MSI_FULL_DOORBELL_START 0
147#define PCI_MSI_FULL_DOORBELL_NR 32
148#define PCI_MSI_FULL_DOORBELL_MASK GENMASK(31, 0)
149#define PCI_MSI_FULL_DOORBELL_SRC0_MASK GENMASK(15, 0)
150#define PCI_MSI_FULL_DOORBELL_SRC1_MASK GENMASK(31, 16)
151
152/**
153 * struct mpic - MPIC private data structure
154 * @base: MPIC registers base address
155 * @per_cpu: per-CPU registers base address
156 * @parent_irq: parent IRQ if MPIC is not top-level interrupt controller
157 * @domain: MPIC main interrupt domain
158 * @ipi_domain: IPI domain
159 * @msi_domain: MSI domain
160 * @msi_inner_domain: MSI inner domain
161 * @msi_used: bitmap of used MSI numbers
162 * @msi_lock: mutex serializing access to @msi_used
163 * @msi_doorbell_addr: physical address of MSI doorbell register
164 * @msi_doorbell_mask: mask of available doorbell bits for MSIs (either PCI_MSI_DOORBELL_MASK or
165 * PCI_MSI_FULL_DOORBELL_MASK)
166 * @msi_doorbell_start: first set bit in @msi_doorbell_mask
167 * @msi_doorbell_size: number of set bits in @msi_doorbell_mask
168 * @doorbell_mask: doorbell mask of MSIs and IPIs, stored on suspend, restored on resume
169 */
170struct mpic {
171 void __iomem *base;
172 void __iomem *per_cpu;
173 int parent_irq;
174 struct irq_domain *domain;
175#ifdef CONFIG_SMP
176 struct irq_domain *ipi_domain;
177#endif
178#ifdef CONFIG_PCI_MSI
179 struct irq_domain *msi_domain;
180 struct irq_domain *msi_inner_domain;
181 DECLARE_BITMAP(msi_used, PCI_MSI_FULL_DOORBELL_NR);
182 struct mutex msi_lock;
183 phys_addr_t msi_doorbell_addr;
184 u32 msi_doorbell_mask;
185 unsigned int msi_doorbell_start, msi_doorbell_size;
186#endif
187 u32 doorbell_mask;
188};
189
190static struct mpic *mpic_data __ro_after_init;
191
192static inline bool mpic_is_ipi_available(struct mpic *mpic)
193{
194 /*
195 * We distinguish IPI availability in the IC by the IC not having a
196 * parent irq defined. If a parent irq is defined, there is a parent
197 * interrupt controller (e.g. GIC) that takes care of inter-processor
198 * interrupts.
199 */
200 return mpic->parent_irq <= 0;
201}
202
203static inline bool mpic_is_percpu_irq(irq_hw_number_t hwirq)
204{
205 return hwirq < MPIC_PER_CPU_IRQS_NR;
206}
207
208/*
209 * In SMP mode:
210 * For shared global interrupts, mask/unmask global enable bit
211 * For CPU interrupts, mask/unmask the calling CPU's bit
212 */
213static void mpic_irq_mask(struct irq_data *d)
214{
215 struct mpic *mpic = irq_data_get_irq_chip_data(d);
216 irq_hw_number_t hwirq = irqd_to_hwirq(d);
217
218 if (!mpic_is_percpu_irq(hwirq))
219 writel(hwirq, mpic->base + MPIC_INT_CLEAR_ENABLE);
220 else
221 writel(hwirq, mpic->per_cpu + MPIC_INT_SET_MASK);
222}
223
224static void mpic_irq_unmask(struct irq_data *d)
225{
226 struct mpic *mpic = irq_data_get_irq_chip_data(d);
227 irq_hw_number_t hwirq = irqd_to_hwirq(d);
228
229 if (!mpic_is_percpu_irq(hwirq))
230 writel(hwirq, mpic->base + MPIC_INT_SET_ENABLE);
231 else
232 writel(hwirq, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
233}
234
235#ifdef CONFIG_PCI_MSI
236
237static struct irq_chip mpic_msi_irq_chip = {
238 .name = "MPIC MSI",
239 .irq_mask = pci_msi_mask_irq,
240 .irq_unmask = pci_msi_unmask_irq,
241};
242
243static struct msi_domain_info mpic_msi_domain_info = {
244 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
245 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
246 .chip = &mpic_msi_irq_chip,
247};
248
249static void mpic_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
250{
251 unsigned int cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
252 struct mpic *mpic = irq_data_get_irq_chip_data(d);
253
254 msg->address_lo = lower_32_bits(mpic->msi_doorbell_addr);
255 msg->address_hi = upper_32_bits(mpic->msi_doorbell_addr);
256 msg->data = BIT(cpu + 8) | (d->hwirq + mpic->msi_doorbell_start);
257}
258
259static int mpic_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
260{
261 unsigned int cpu;
262
263 if (!force)
264 cpu = cpumask_any_and(mask, cpu_online_mask);
265 else
266 cpu = cpumask_first(mask);
267
268 if (cpu >= nr_cpu_ids)
269 return -EINVAL;
270
271 irq_data_update_effective_affinity(d, cpumask_of(cpu));
272
273 return IRQ_SET_MASK_OK;
274}
275
276static struct irq_chip mpic_msi_bottom_irq_chip = {
277 .name = "MPIC MSI",
278 .irq_compose_msi_msg = mpic_compose_msi_msg,
279 .irq_set_affinity = mpic_msi_set_affinity,
280};
281
282static int mpic_msi_alloc(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs,
283 void *args)
284{
285 struct mpic *mpic = domain->host_data;
286 int hwirq;
287
288 mutex_lock(&mpic->msi_lock);
289 hwirq = bitmap_find_free_region(mpic->msi_used, mpic->msi_doorbell_size,
290 order_base_2(nr_irqs));
291 mutex_unlock(&mpic->msi_lock);
292
293 if (hwirq < 0)
294 return -ENOSPC;
295
296 for (unsigned int i = 0; i < nr_irqs; i++) {
297 irq_domain_set_info(domain, virq + i, hwirq + i,
298 &mpic_msi_bottom_irq_chip,
299 domain->host_data, handle_simple_irq,
300 NULL, NULL);
301 }
302
303 return 0;
304}
305
306static void mpic_msi_free(struct irq_domain *domain, unsigned int virq, unsigned int nr_irqs)
307{
308 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
309 struct mpic *mpic = domain->host_data;
310
311 mutex_lock(&mpic->msi_lock);
312 bitmap_release_region(mpic->msi_used, d->hwirq, order_base_2(nr_irqs));
313 mutex_unlock(&mpic->msi_lock);
314}
315
316static const struct irq_domain_ops mpic_msi_domain_ops = {
317 .alloc = mpic_msi_alloc,
318 .free = mpic_msi_free,
319};
320
321static void mpic_msi_reenable_percpu(struct mpic *mpic)
322{
323 u32 reg;
324
325 /* Enable MSI doorbell mask and combined cpu local interrupt */
326 reg = readl(mpic->per_cpu + MPIC_IN_DRBEL_MASK);
327 reg |= mpic->msi_doorbell_mask;
328 writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
329
330 /* Unmask local doorbell interrupt */
331 writel(1, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
332}
333
334static int __init mpic_msi_init(struct mpic *mpic, struct device_node *node,
335 phys_addr_t main_int_phys_base)
336{
337 mpic->msi_doorbell_addr = main_int_phys_base + MPIC_SW_TRIG_INT;
338
339 mutex_init(&mpic->msi_lock);
340
341 if (mpic_is_ipi_available(mpic)) {
342 mpic->msi_doorbell_start = PCI_MSI_DOORBELL_START;
343 mpic->msi_doorbell_size = PCI_MSI_DOORBELL_NR;
344 mpic->msi_doorbell_mask = PCI_MSI_DOORBELL_MASK;
345 } else {
346 mpic->msi_doorbell_start = PCI_MSI_FULL_DOORBELL_START;
347 mpic->msi_doorbell_size = PCI_MSI_FULL_DOORBELL_NR;
348 mpic->msi_doorbell_mask = PCI_MSI_FULL_DOORBELL_MASK;
349 }
350
351 mpic->msi_inner_domain = irq_domain_add_linear(NULL, mpic->msi_doorbell_size,
352 &mpic_msi_domain_ops, mpic);
353 if (!mpic->msi_inner_domain)
354 return -ENOMEM;
355
356 mpic->msi_domain = pci_msi_create_irq_domain(of_node_to_fwnode(node), &mpic_msi_domain_info,
357 mpic->msi_inner_domain);
358 if (!mpic->msi_domain) {
359 irq_domain_remove(mpic->msi_inner_domain);
360 return -ENOMEM;
361 }
362
363 mpic_msi_reenable_percpu(mpic);
364
365 /* Unmask low 16 MSI irqs on non-IPI platforms */
366 if (!mpic_is_ipi_available(mpic))
367 writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
368
369 return 0;
370}
371#else
372static __maybe_unused void mpic_msi_reenable_percpu(struct mpic *mpic) {}
373
374static inline int mpic_msi_init(struct mpic *mpic, struct device_node *node,
375 phys_addr_t main_int_phys_base)
376{
377 return 0;
378}
379#endif
380
381static void mpic_perf_init(struct mpic *mpic)
382{
383 u32 cpuid;
384
385 /*
386 * This Performance Counter Overflow interrupt is specific for
387 * Armada 370 and XP. It is not available on Armada 375, 38x and 39x.
388 */
389 if (!of_machine_is_compatible("marvell,armada-370-xp"))
390 return;
391
392 cpuid = cpu_logical_map(smp_processor_id());
393
394 /* Enable Performance Counter Overflow interrupts */
395 writel(MPIC_INT_CAUSE_PERF(cpuid), mpic->per_cpu + MPIC_INT_FABRIC_MASK);
396}
397
398#ifdef CONFIG_SMP
399static void mpic_ipi_mask(struct irq_data *d)
400{
401 struct mpic *mpic = irq_data_get_irq_chip_data(d);
402 u32 reg;
403
404 reg = readl(mpic->per_cpu + MPIC_IN_DRBEL_MASK);
405 reg &= ~BIT(d->hwirq);
406 writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
407}
408
409static void mpic_ipi_unmask(struct irq_data *d)
410{
411 struct mpic *mpic = irq_data_get_irq_chip_data(d);
412 u32 reg;
413
414 reg = readl(mpic->per_cpu + MPIC_IN_DRBEL_MASK);
415 reg |= BIT(d->hwirq);
416 writel(reg, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
417}
418
419static void mpic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask)
420{
421 struct mpic *mpic = irq_data_get_irq_chip_data(d);
422 unsigned int cpu;
423 u32 map = 0;
424
425 /* Convert our logical CPU mask into a physical one. */
426 for_each_cpu(cpu, mask)
427 map |= BIT(cpu_logical_map(cpu));
428
429 /*
430 * Ensure that stores to Normal memory are visible to the
431 * other CPUs before issuing the IPI.
432 */
433 dsb();
434
435 /* submit softirq */
436 writel((map << 8) | d->hwirq, mpic->base + MPIC_SW_TRIG_INT);
437}
438
439static void mpic_ipi_ack(struct irq_data *d)
440{
441 struct mpic *mpic = irq_data_get_irq_chip_data(d);
442
443 writel(~BIT(d->hwirq), mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
444}
445
446static struct irq_chip mpic_ipi_irqchip = {
447 .name = "IPI",
448 .irq_ack = mpic_ipi_ack,
449 .irq_mask = mpic_ipi_mask,
450 .irq_unmask = mpic_ipi_unmask,
451 .ipi_send_mask = mpic_ipi_send_mask,
452};
453
454static int mpic_ipi_alloc(struct irq_domain *d, unsigned int virq,
455 unsigned int nr_irqs, void *args)
456{
457 for (unsigned int i = 0; i < nr_irqs; i++) {
458 irq_set_percpu_devid(virq + i);
459 irq_domain_set_info(d, virq + i, i, &mpic_ipi_irqchip, d->host_data,
460 handle_percpu_devid_irq, NULL, NULL);
461 }
462
463 return 0;
464}
465
466static void mpic_ipi_free(struct irq_domain *d, unsigned int virq,
467 unsigned int nr_irqs)
468{
469 /* Not freeing IPIs */
470}
471
472static const struct irq_domain_ops mpic_ipi_domain_ops = {
473 .alloc = mpic_ipi_alloc,
474 .free = mpic_ipi_free,
475};
476
477static void mpic_ipi_resume(struct mpic *mpic)
478{
479 for (irq_hw_number_t i = 0; i < IPI_DOORBELL_NR; i++) {
480 unsigned int virq = irq_find_mapping(mpic->ipi_domain, i);
481 struct irq_data *d;
482
483 if (!virq || !irq_percpu_is_enabled(virq))
484 continue;
485
486 d = irq_domain_get_irq_data(mpic->ipi_domain, virq);
487 mpic_ipi_unmask(d);
488 }
489}
490
491static int __init mpic_ipi_init(struct mpic *mpic, struct device_node *node)
492{
493 int base_ipi;
494
495 mpic->ipi_domain = irq_domain_create_linear(of_node_to_fwnode(node), IPI_DOORBELL_NR,
496 &mpic_ipi_domain_ops, mpic);
497 if (WARN_ON(!mpic->ipi_domain))
498 return -ENOMEM;
499
500 irq_domain_update_bus_token(mpic->ipi_domain, DOMAIN_BUS_IPI);
501 base_ipi = irq_domain_alloc_irqs(mpic->ipi_domain, IPI_DOORBELL_NR, NUMA_NO_NODE, NULL);
502 if (WARN_ON(!base_ipi))
503 return -ENOMEM;
504
505 set_smp_ipi_range(base_ipi, IPI_DOORBELL_NR);
506
507 return 0;
508}
509
510static int mpic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, bool force)
511{
512 struct mpic *mpic = irq_data_get_irq_chip_data(d);
513 irq_hw_number_t hwirq = irqd_to_hwirq(d);
514 unsigned int cpu;
515
516 /* Select a single core from the affinity mask which is online */
517 cpu = cpumask_any_and(mask_val, cpu_online_mask);
518
519 atomic_io_modify(mpic->base + MPIC_INT_SOURCE_CTL(hwirq),
520 MPIC_INT_SOURCE_CPU_MASK, BIT(cpu_logical_map(cpu)));
521
522 irq_data_update_effective_affinity(d, cpumask_of(cpu));
523
524 return IRQ_SET_MASK_OK;
525}
526
527static void mpic_smp_cpu_init(struct mpic *mpic)
528{
529 for (irq_hw_number_t i = 0; i < mpic->domain->hwirq_max; i++)
530 writel(i, mpic->per_cpu + MPIC_INT_SET_MASK);
531
532 if (!mpic_is_ipi_available(mpic))
533 return;
534
535 /* Disable all IPIs */
536 writel(0, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
537
538 /* Clear pending IPIs */
539 writel(0, mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
540
541 /* Unmask IPI interrupt */
542 writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
543}
544
545static void mpic_reenable_percpu(struct mpic *mpic)
546{
547 /* Re-enable per-CPU interrupts that were enabled before suspend */
548 for (irq_hw_number_t i = 0; i < MPIC_PER_CPU_IRQS_NR; i++) {
549 unsigned int virq = irq_linear_revmap(mpic->domain, i);
550 struct irq_data *d;
551
552 if (!virq || !irq_percpu_is_enabled(virq))
553 continue;
554
555 d = irq_get_irq_data(virq);
556 mpic_irq_unmask(d);
557 }
558
559 if (mpic_is_ipi_available(mpic))
560 mpic_ipi_resume(mpic);
561
562 mpic_msi_reenable_percpu(mpic);
563}
564
565static int mpic_starting_cpu(unsigned int cpu)
566{
567 struct mpic *mpic = irq_get_default_host()->host_data;
568
569 mpic_perf_init(mpic);
570 mpic_smp_cpu_init(mpic);
571 mpic_reenable_percpu(mpic);
572
573 return 0;
574}
575
576static int mpic_cascaded_starting_cpu(unsigned int cpu)
577{
578 struct mpic *mpic = mpic_data;
579
580 mpic_perf_init(mpic);
581 mpic_reenable_percpu(mpic);
582 enable_percpu_irq(mpic->parent_irq, IRQ_TYPE_NONE);
583
584 return 0;
585}
586#else
587static void mpic_smp_cpu_init(struct mpic *mpic) {}
588static void mpic_ipi_resume(struct mpic *mpic) {}
589#endif
590
591static struct irq_chip mpic_irq_chip = {
592 .name = "MPIC",
593 .irq_mask = mpic_irq_mask,
594 .irq_mask_ack = mpic_irq_mask,
595 .irq_unmask = mpic_irq_unmask,
596#ifdef CONFIG_SMP
597 .irq_set_affinity = mpic_set_affinity,
598#endif
599 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND,
600};
601
602static int mpic_irq_map(struct irq_domain *domain, unsigned int virq, irq_hw_number_t hwirq)
603{
604 struct mpic *mpic = domain->host_data;
605
606 /* IRQs 0 and 1 cannot be mapped, they are handled internally */
607 if (hwirq <= 1)
608 return -EINVAL;
609
610 irq_set_chip_data(virq, mpic);
611
612 mpic_irq_mask(irq_get_irq_data(virq));
613 if (!mpic_is_percpu_irq(hwirq))
614 writel(hwirq, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
615 else
616 writel(hwirq, mpic->base + MPIC_INT_SET_ENABLE);
617 irq_set_status_flags(virq, IRQ_LEVEL);
618
619 if (mpic_is_percpu_irq(hwirq)) {
620 irq_set_percpu_devid(virq);
621 irq_set_chip_and_handler(virq, &mpic_irq_chip, handle_percpu_devid_irq);
622 } else {
623 irq_set_chip_and_handler(virq, &mpic_irq_chip, handle_level_irq);
624 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
625 }
626 irq_set_probe(virq);
627 return 0;
628}
629
630static const struct irq_domain_ops mpic_irq_ops = {
631 .map = mpic_irq_map,
632 .xlate = irq_domain_xlate_onecell,
633};
634
635#ifdef CONFIG_PCI_MSI
636static void mpic_handle_msi_irq(struct mpic *mpic)
637{
638 unsigned long cause;
639 unsigned int i;
640
641 cause = readl_relaxed(mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
642 cause &= mpic->msi_doorbell_mask;
643 writel(~cause, mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
644
645 for_each_set_bit(i, &cause, BITS_PER_LONG)
646 generic_handle_domain_irq(mpic->msi_inner_domain, i - mpic->msi_doorbell_start);
647}
648#else
649static void mpic_handle_msi_irq(struct mpic *mpic) {}
650#endif
651
652#ifdef CONFIG_SMP
653static void mpic_handle_ipi_irq(struct mpic *mpic)
654{
655 unsigned long cause;
656 irq_hw_number_t i;
657
658 cause = readl_relaxed(mpic->per_cpu + MPIC_IN_DRBEL_CAUSE);
659 cause &= IPI_DOORBELL_MASK;
660
661 for_each_set_bit(i, &cause, IPI_DOORBELL_NR)
662 generic_handle_domain_irq(mpic->ipi_domain, i);
663}
664#else
665static inline void mpic_handle_ipi_irq(struct mpic *mpic) {}
666#endif
667
668static void mpic_handle_cascade_irq(struct irq_desc *desc)
669{
670 struct mpic *mpic = irq_desc_get_handler_data(desc);
671 struct irq_chip *chip = irq_desc_get_chip(desc);
672 unsigned long cause;
673 u32 irqsrc, cpuid;
674 irq_hw_number_t i;
675
676 chained_irq_enter(chip, desc);
677
678 cause = readl_relaxed(mpic->per_cpu + MPIC_PPI_CAUSE);
679 cpuid = cpu_logical_map(smp_processor_id());
680
681 for_each_set_bit(i, &cause, MPIC_PER_CPU_IRQS_NR) {
682 irqsrc = readl_relaxed(mpic->base + MPIC_INT_SOURCE_CTL(i));
683
684 /* Check if the interrupt is not masked on current CPU.
685 * Test IRQ (0-1) and FIQ (8-9) mask bits.
686 */
687 if (!(irqsrc & MPIC_INT_IRQ_FIQ_MASK(cpuid)))
688 continue;
689
690 if (i == 0 || i == 1) {
691 mpic_handle_msi_irq(mpic);
692 continue;
693 }
694
695 generic_handle_domain_irq(mpic->domain, i);
696 }
697
698 chained_irq_exit(chip, desc);
699}
700
701static void __exception_irq_entry mpic_handle_irq(struct pt_regs *regs)
702{
703 struct mpic *mpic = irq_get_default_host()->host_data;
704 irq_hw_number_t i;
705 u32 irqstat;
706
707 do {
708 irqstat = readl_relaxed(mpic->per_cpu + MPIC_CPU_INTACK);
709 i = FIELD_GET(MPIC_CPU_INTACK_IID_MASK, irqstat);
710
711 if (i > 1022)
712 break;
713
714 if (i > 1)
715 generic_handle_domain_irq(mpic->domain, i);
716
717 /* MSI handling */
718 if (i == 1)
719 mpic_handle_msi_irq(mpic);
720
721 /* IPI Handling */
722 if (i == 0)
723 mpic_handle_ipi_irq(mpic);
724 } while (1);
725}
726
727static int mpic_suspend(void)
728{
729 struct mpic *mpic = mpic_data;
730
731 mpic->doorbell_mask = readl(mpic->per_cpu + MPIC_IN_DRBEL_MASK);
732
733 return 0;
734}
735
736static void mpic_resume(void)
737{
738 struct mpic *mpic = mpic_data;
739 bool src0, src1;
740
741 /* Re-enable interrupts */
742 for (irq_hw_number_t i = 0; i < mpic->domain->hwirq_max; i++) {
743 unsigned int virq = irq_linear_revmap(mpic->domain, i);
744 struct irq_data *d;
745
746 if (!virq)
747 continue;
748
749 d = irq_get_irq_data(virq);
750
751 if (!mpic_is_percpu_irq(i)) {
752 /* Non per-CPU interrupts */
753 writel(i, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
754 if (!irqd_irq_disabled(d))
755 mpic_irq_unmask(d);
756 } else {
757 /* Per-CPU interrupts */
758 writel(i, mpic->base + MPIC_INT_SET_ENABLE);
759
760 /*
761 * Re-enable on the current CPU, mpic_reenable_percpu()
762 * will take care of secondary CPUs when they come up.
763 */
764 if (irq_percpu_is_enabled(virq))
765 mpic_irq_unmask(d);
766 }
767 }
768
769 /* Reconfigure doorbells for IPIs and MSIs */
770 writel(mpic->doorbell_mask, mpic->per_cpu + MPIC_IN_DRBEL_MASK);
771
772 if (mpic_is_ipi_available(mpic)) {
773 src0 = mpic->doorbell_mask & IPI_DOORBELL_MASK;
774 src1 = mpic->doorbell_mask & PCI_MSI_DOORBELL_MASK;
775 } else {
776 src0 = mpic->doorbell_mask & PCI_MSI_FULL_DOORBELL_SRC0_MASK;
777 src1 = mpic->doorbell_mask & PCI_MSI_FULL_DOORBELL_SRC1_MASK;
778 }
779
780 if (src0)
781 writel(0, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
782 if (src1)
783 writel(1, mpic->per_cpu + MPIC_INT_CLEAR_MASK);
784
785 if (mpic_is_ipi_available(mpic))
786 mpic_ipi_resume(mpic);
787}
788
789static struct syscore_ops mpic_syscore_ops = {
790 .suspend = mpic_suspend,
791 .resume = mpic_resume,
792};
793
794static int __init mpic_map_region(struct device_node *np, int index,
795 void __iomem **base, phys_addr_t *phys_base)
796{
797 struct resource res;
798 int err;
799
800 err = of_address_to_resource(np, index, &res);
801 if (WARN_ON(err))
802 goto fail;
803
804 if (WARN_ON(!request_mem_region(res.start, resource_size(&res), np->full_name))) {
805 err = -EBUSY;
806 goto fail;
807 }
808
809 *base = ioremap(res.start, resource_size(&res));
810 if (WARN_ON(!*base)) {
811 err = -ENOMEM;
812 goto fail;
813 }
814
815 if (phys_base)
816 *phys_base = res.start;
817
818 return 0;
819
820fail:
821 pr_err("%pOF: Unable to map resource %d: %pE\n", np, index, ERR_PTR(err));
822 return err;
823}
824
825static int __init mpic_of_init(struct device_node *node, struct device_node *parent)
826{
827 phys_addr_t phys_base;
828 unsigned int nr_irqs;
829 struct mpic *mpic;
830 int err;
831
832 mpic = kzalloc(sizeof(*mpic), GFP_KERNEL);
833 if (WARN_ON(!mpic))
834 return -ENOMEM;
835
836 mpic_data = mpic;
837
838 err = mpic_map_region(node, 0, &mpic->base, &phys_base);
839 if (err)
840 return err;
841
842 err = mpic_map_region(node, 1, &mpic->per_cpu, NULL);
843 if (err)
844 return err;
845
846 nr_irqs = FIELD_GET(MPIC_INT_CONTROL_NUMINT_MASK, readl(mpic->base + MPIC_INT_CONTROL));
847
848 for (irq_hw_number_t i = 0; i < nr_irqs; i++)
849 writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE);
850
851 /*
852 * Initialize mpic->parent_irq before calling any other functions, since
853 * it is used to distinguish between IPI and non-IPI platforms.
854 */
855 mpic->parent_irq = irq_of_parse_and_map(node, 0);
856
857 /*
858 * On non-IPI platforms the driver currently supports only the per-CPU
859 * interrupts (the first 29 interrupts). See mpic_handle_cascade_irq().
860 */
861 if (!mpic_is_ipi_available(mpic))
862 nr_irqs = MPIC_PER_CPU_IRQS_NR;
863
864 mpic->domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, mpic);
865 if (!mpic->domain) {
866 pr_err("%pOF: Unable to add IRQ domain\n", node);
867 return -ENOMEM;
868 }
869
870 irq_domain_update_bus_token(mpic->domain, DOMAIN_BUS_WIRED);
871
872 /* Setup for the boot CPU */
873 mpic_perf_init(mpic);
874 mpic_smp_cpu_init(mpic);
875
876 err = mpic_msi_init(mpic, node, phys_base);
877 if (err) {
878 pr_err("%pOF: Unable to initialize MSI domain\n", node);
879 return err;
880 }
881
882 if (mpic_is_ipi_available(mpic)) {
883 irq_set_default_host(mpic->domain);
884 set_handle_irq(mpic_handle_irq);
885#ifdef CONFIG_SMP
886 err = mpic_ipi_init(mpic, node);
887 if (err) {
888 pr_err("%pOF: Unable to initialize IPI domain\n", node);
889 return err;
890 }
891
892 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
893 "irqchip/armada/ipi:starting",
894 mpic_starting_cpu, NULL);
895#endif
896 } else {
897#ifdef CONFIG_SMP
898 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_ARMADA_XP_STARTING,
899 "irqchip/armada/cascade:starting",
900 mpic_cascaded_starting_cpu, NULL);
901#endif
902 irq_set_chained_handler_and_data(mpic->parent_irq,
903 mpic_handle_cascade_irq, mpic);
904 }
905
906 register_syscore_ops(&mpic_syscore_ops);
907
908 return 0;
909}
910
911IRQCHIP_DECLARE(marvell_mpic, "marvell,mpic", mpic_of_init);