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1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2014-2018 Broadcom */
3
4/**
5 * DOC: Interrupt management for the V3D engine
6 *
7 * When we take a bin, render, TFU done, or CSD done interrupt, we
8 * need to signal the fence for that job so that the scheduler can
9 * queue up the next one and unblock any waiters.
10 *
11 * When we take the binner out of memory interrupt, we need to
12 * allocate some new memory and pass it to the binner so that the
13 * current job can make progress.
14 */
15
16#include <linux/platform_device.h>
17
18#include "v3d_drv.h"
19#include "v3d_regs.h"
20#include "v3d_trace.h"
21
22#define V3D_CORE_IRQS ((u32)(V3D_INT_OUTOMEM | \
23 V3D_INT_FLDONE | \
24 V3D_INT_FRDONE | \
25 V3D_INT_CSDDONE | \
26 V3D_INT_GMPV))
27
28#define V3D_HUB_IRQS ((u32)(V3D_HUB_INT_MMU_WRV | \
29 V3D_HUB_INT_MMU_PTI | \
30 V3D_HUB_INT_MMU_CAP | \
31 V3D_HUB_INT_TFUC))
32
33static irqreturn_t
34v3d_hub_irq(int irq, void *arg);
35
36static void
37v3d_overflow_mem_work(struct work_struct *work)
38{
39 struct v3d_dev *v3d =
40 container_of(work, struct v3d_dev, overflow_mem_work);
41 struct drm_device *dev = &v3d->drm;
42 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
43 struct drm_gem_object *obj;
44 unsigned long irqflags;
45
46 if (IS_ERR(bo)) {
47 DRM_ERROR("Couldn't allocate binner overflow mem\n");
48 return;
49 }
50 obj = &bo->base.base;
51
52 /* We lost a race, and our work task came in after the bin job
53 * completed and exited. This can happen because the HW
54 * signals OOM before it's fully OOM, so the binner might just
55 * barely complete.
56 *
57 * If we lose the race and our work task comes in after a new
58 * bin job got scheduled, that's fine. We'll just give them
59 * some binner pool anyway.
60 */
61 spin_lock_irqsave(&v3d->job_lock, irqflags);
62 if (!v3d->bin_job) {
63 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
64 goto out;
65 }
66
67 drm_gem_object_get(obj);
68 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
69 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
70
71 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << PAGE_SHIFT);
72 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
73
74out:
75 drm_gem_object_put(obj);
76}
77
78static irqreturn_t
79v3d_irq(int irq, void *arg)
80{
81 struct v3d_dev *v3d = arg;
82 u32 intsts;
83 irqreturn_t status = IRQ_NONE;
84
85 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
86
87 /* Acknowledge the interrupts we're handling here. */
88 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
89
90 if (intsts & V3D_INT_OUTOMEM) {
91 /* Note that the OOM status is edge signaled, so the
92 * interrupt won't happen again until the we actually
93 * add more memory. Also, as of V3D 4.1, FLDONE won't
94 * be reported until any OOM state has been cleared.
95 */
96 schedule_work(&v3d->overflow_mem_work);
97 status = IRQ_HANDLED;
98 }
99
100 if (intsts & V3D_INT_FLDONE) {
101 struct v3d_fence *fence =
102 to_v3d_fence(v3d->bin_job->base.irq_fence);
103
104 trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
105 dma_fence_signal(&fence->base);
106 status = IRQ_HANDLED;
107 }
108
109 if (intsts & V3D_INT_FRDONE) {
110 struct v3d_fence *fence =
111 to_v3d_fence(v3d->render_job->base.irq_fence);
112
113 trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
114 dma_fence_signal(&fence->base);
115 status = IRQ_HANDLED;
116 }
117
118 if (intsts & V3D_INT_CSDDONE) {
119 struct v3d_fence *fence =
120 to_v3d_fence(v3d->csd_job->base.irq_fence);
121
122 trace_v3d_csd_irq(&v3d->drm, fence->seqno);
123 dma_fence_signal(&fence->base);
124 status = IRQ_HANDLED;
125 }
126
127 /* We shouldn't be triggering these if we have GMP in
128 * always-allowed mode.
129 */
130 if (intsts & V3D_INT_GMPV)
131 dev_err(v3d->drm.dev, "GMP violation\n");
132
133 /* V3D 4.2 wires the hub and core IRQs together, so if we &
134 * didn't see the common one then check hub for MMU IRQs.
135 */
136 if (v3d->single_irq_line && status == IRQ_NONE)
137 return v3d_hub_irq(irq, arg);
138
139 return status;
140}
141
142static irqreturn_t
143v3d_hub_irq(int irq, void *arg)
144{
145 struct v3d_dev *v3d = arg;
146 u32 intsts;
147 irqreturn_t status = IRQ_NONE;
148
149 intsts = V3D_READ(V3D_HUB_INT_STS);
150
151 /* Acknowledge the interrupts we're handling here. */
152 V3D_WRITE(V3D_HUB_INT_CLR, intsts);
153
154 if (intsts & V3D_HUB_INT_TFUC) {
155 struct v3d_fence *fence =
156 to_v3d_fence(v3d->tfu_job->base.irq_fence);
157
158 trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
159 dma_fence_signal(&fence->base);
160 status = IRQ_HANDLED;
161 }
162
163 if (intsts & (V3D_HUB_INT_MMU_WRV |
164 V3D_HUB_INT_MMU_PTI |
165 V3D_HUB_INT_MMU_CAP)) {
166 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
167 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
168 (v3d->va_width - 32));
169 static const char *const v3d41_axi_ids[] = {
170 "L2T",
171 "PTB",
172 "PSE",
173 "TLB",
174 "CLE",
175 "TFU",
176 "MMU",
177 "GMP",
178 };
179 const char *client = "?";
180
181 V3D_WRITE(V3D_MMU_CTL,
182 V3D_READ(V3D_MMU_CTL) & (V3D_MMU_CTL_CAP_EXCEEDED |
183 V3D_MMU_CTL_PT_INVALID |
184 V3D_MMU_CTL_WRITE_VIOLATION));
185
186 if (v3d->ver >= 41) {
187 axi_id = axi_id >> 5;
188 if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
189 client = v3d41_axi_ids[axi_id];
190 }
191
192 dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
193 client, axi_id, (long long)vio_addr,
194 ((intsts & V3D_HUB_INT_MMU_WRV) ?
195 ", write violation" : ""),
196 ((intsts & V3D_HUB_INT_MMU_PTI) ?
197 ", pte invalid" : ""),
198 ((intsts & V3D_HUB_INT_MMU_CAP) ?
199 ", cap exceeded" : ""));
200 status = IRQ_HANDLED;
201 }
202
203 return status;
204}
205
206int
207v3d_irq_init(struct v3d_dev *v3d)
208{
209 int irq1, ret, core;
210
211 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
212
213 /* Clear any pending interrupts someone might have left around
214 * for us.
215 */
216 for (core = 0; core < v3d->cores; core++)
217 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
218 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
219
220 irq1 = platform_get_irq(v3d_to_pdev(v3d), 1);
221 if (irq1 == -EPROBE_DEFER)
222 return irq1;
223 if (irq1 > 0) {
224 ret = devm_request_irq(v3d->drm.dev, irq1,
225 v3d_irq, IRQF_SHARED,
226 "v3d_core0", v3d);
227 if (ret)
228 goto fail;
229 ret = devm_request_irq(v3d->drm.dev,
230 platform_get_irq(v3d_to_pdev(v3d), 0),
231 v3d_hub_irq, IRQF_SHARED,
232 "v3d_hub", v3d);
233 if (ret)
234 goto fail;
235 } else {
236 v3d->single_irq_line = true;
237
238 ret = devm_request_irq(v3d->drm.dev,
239 platform_get_irq(v3d_to_pdev(v3d), 0),
240 v3d_irq, IRQF_SHARED,
241 "v3d", v3d);
242 if (ret)
243 goto fail;
244 }
245
246 v3d_irq_enable(v3d);
247 return 0;
248
249fail:
250 if (ret != -EPROBE_DEFER)
251 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
252 return ret;
253}
254
255void
256v3d_irq_enable(struct v3d_dev *v3d)
257{
258 int core;
259
260 /* Enable our set of interrupts, masking out any others. */
261 for (core = 0; core < v3d->cores; core++) {
262 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS);
263 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS);
264 }
265
266 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS);
267 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS);
268}
269
270void
271v3d_irq_disable(struct v3d_dev *v3d)
272{
273 int core;
274
275 /* Disable all interrupts. */
276 for (core = 0; core < v3d->cores; core++)
277 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
278 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
279
280 /* Clear any pending interrupts we might have left. */
281 for (core = 0; core < v3d->cores; core++)
282 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS);
283 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS);
284
285 cancel_work_sync(&v3d->overflow_mem_work);
286}
287
288/** Reinitializes interrupt registers when a GPU reset is performed. */
289void v3d_irq_reset(struct v3d_dev *v3d)
290{
291 v3d_irq_enable(v3d);
292}
1// SPDX-License-Identifier: GPL-2.0+
2/* Copyright (C) 2014-2018 Broadcom */
3
4/**
5 * DOC: Interrupt management for the V3D engine
6 *
7 * When we take a bin, render, TFU done, or CSD done interrupt, we
8 * need to signal the fence for that job so that the scheduler can
9 * queue up the next one and unblock any waiters.
10 *
11 * When we take the binner out of memory interrupt, we need to
12 * allocate some new memory and pass it to the binner so that the
13 * current job can make progress.
14 */
15
16#include <linux/platform_device.h>
17#include <linux/sched/clock.h>
18
19#include "v3d_drv.h"
20#include "v3d_regs.h"
21#include "v3d_trace.h"
22
23#define V3D_CORE_IRQS(ver) ((u32)(V3D_INT_OUTOMEM | \
24 V3D_INT_FLDONE | \
25 V3D_INT_FRDONE | \
26 V3D_INT_CSDDONE(ver) | \
27 (ver < 71 ? V3D_INT_GMPV : 0)))
28
29#define V3D_HUB_IRQS(ver) ((u32)(V3D_HUB_INT_MMU_WRV | \
30 V3D_HUB_INT_MMU_PTI | \
31 V3D_HUB_INT_MMU_CAP | \
32 V3D_HUB_INT_TFUC | \
33 (ver >= 71 ? V3D_V7_HUB_INT_GMPV : 0)))
34
35static irqreturn_t
36v3d_hub_irq(int irq, void *arg);
37
38static void
39v3d_overflow_mem_work(struct work_struct *work)
40{
41 struct v3d_dev *v3d =
42 container_of(work, struct v3d_dev, overflow_mem_work);
43 struct drm_device *dev = &v3d->drm;
44 struct v3d_bo *bo = v3d_bo_create(dev, NULL /* XXX: GMP */, 256 * 1024);
45 struct drm_gem_object *obj;
46 unsigned long irqflags;
47
48 if (IS_ERR(bo)) {
49 DRM_ERROR("Couldn't allocate binner overflow mem\n");
50 return;
51 }
52 obj = &bo->base.base;
53
54 /* We lost a race, and our work task came in after the bin job
55 * completed and exited. This can happen because the HW
56 * signals OOM before it's fully OOM, so the binner might just
57 * barely complete.
58 *
59 * If we lose the race and our work task comes in after a new
60 * bin job got scheduled, that's fine. We'll just give them
61 * some binner pool anyway.
62 */
63 spin_lock_irqsave(&v3d->job_lock, irqflags);
64 if (!v3d->bin_job) {
65 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
66 goto out;
67 }
68
69 drm_gem_object_get(obj);
70 list_add_tail(&bo->unref_head, &v3d->bin_job->render->unref_list);
71 spin_unlock_irqrestore(&v3d->job_lock, irqflags);
72
73 v3d_mmu_flush_all(v3d);
74
75 V3D_CORE_WRITE(0, V3D_PTB_BPOA, bo->node.start << V3D_MMU_PAGE_SHIFT);
76 V3D_CORE_WRITE(0, V3D_PTB_BPOS, obj->size);
77
78out:
79 drm_gem_object_put(obj);
80}
81
82static irqreturn_t
83v3d_irq(int irq, void *arg)
84{
85 struct v3d_dev *v3d = arg;
86 u32 intsts;
87 irqreturn_t status = IRQ_NONE;
88
89 intsts = V3D_CORE_READ(0, V3D_CTL_INT_STS);
90
91 /* Acknowledge the interrupts we're handling here. */
92 V3D_CORE_WRITE(0, V3D_CTL_INT_CLR, intsts);
93
94 if (intsts & V3D_INT_OUTOMEM) {
95 /* Note that the OOM status is edge signaled, so the
96 * interrupt won't happen again until the we actually
97 * add more memory. Also, as of V3D 4.1, FLDONE won't
98 * be reported until any OOM state has been cleared.
99 */
100 schedule_work(&v3d->overflow_mem_work);
101 status = IRQ_HANDLED;
102 }
103
104 if (intsts & V3D_INT_FLDONE) {
105 struct v3d_fence *fence =
106 to_v3d_fence(v3d->bin_job->base.irq_fence);
107
108 v3d_job_update_stats(&v3d->bin_job->base, V3D_BIN);
109 trace_v3d_bcl_irq(&v3d->drm, fence->seqno);
110
111 v3d->bin_job = NULL;
112 dma_fence_signal(&fence->base);
113
114 status = IRQ_HANDLED;
115 }
116
117 if (intsts & V3D_INT_FRDONE) {
118 struct v3d_fence *fence =
119 to_v3d_fence(v3d->render_job->base.irq_fence);
120
121 v3d_job_update_stats(&v3d->render_job->base, V3D_RENDER);
122 trace_v3d_rcl_irq(&v3d->drm, fence->seqno);
123
124 v3d->render_job = NULL;
125 dma_fence_signal(&fence->base);
126
127 status = IRQ_HANDLED;
128 }
129
130 if (intsts & V3D_INT_CSDDONE(v3d->ver)) {
131 struct v3d_fence *fence =
132 to_v3d_fence(v3d->csd_job->base.irq_fence);
133
134 v3d_job_update_stats(&v3d->csd_job->base, V3D_CSD);
135 trace_v3d_csd_irq(&v3d->drm, fence->seqno);
136
137 v3d->csd_job = NULL;
138 dma_fence_signal(&fence->base);
139
140 status = IRQ_HANDLED;
141 }
142
143 /* We shouldn't be triggering these if we have GMP in
144 * always-allowed mode.
145 */
146 if (v3d->ver < 71 && (intsts & V3D_INT_GMPV))
147 dev_err(v3d->drm.dev, "GMP violation\n");
148
149 /* V3D 4.2 wires the hub and core IRQs together, so if we &
150 * didn't see the common one then check hub for MMU IRQs.
151 */
152 if (v3d->single_irq_line && status == IRQ_NONE)
153 return v3d_hub_irq(irq, arg);
154
155 return status;
156}
157
158static irqreturn_t
159v3d_hub_irq(int irq, void *arg)
160{
161 struct v3d_dev *v3d = arg;
162 u32 intsts;
163 irqreturn_t status = IRQ_NONE;
164
165 intsts = V3D_READ(V3D_HUB_INT_STS);
166
167 /* Acknowledge the interrupts we're handling here. */
168 V3D_WRITE(V3D_HUB_INT_CLR, intsts);
169
170 if (intsts & V3D_HUB_INT_TFUC) {
171 struct v3d_fence *fence =
172 to_v3d_fence(v3d->tfu_job->base.irq_fence);
173
174 v3d_job_update_stats(&v3d->tfu_job->base, V3D_TFU);
175 trace_v3d_tfu_irq(&v3d->drm, fence->seqno);
176
177 v3d->tfu_job = NULL;
178 dma_fence_signal(&fence->base);
179
180 status = IRQ_HANDLED;
181 }
182
183 if (intsts & (V3D_HUB_INT_MMU_WRV |
184 V3D_HUB_INT_MMU_PTI |
185 V3D_HUB_INT_MMU_CAP)) {
186 u32 axi_id = V3D_READ(V3D_MMU_VIO_ID);
187 u64 vio_addr = ((u64)V3D_READ(V3D_MMU_VIO_ADDR) <<
188 (v3d->va_width - 32));
189 static const char *const v3d41_axi_ids[] = {
190 "L2T",
191 "PTB",
192 "PSE",
193 "TLB",
194 "CLE",
195 "TFU",
196 "MMU",
197 "GMP",
198 };
199 const char *client = "?";
200
201 V3D_WRITE(V3D_MMU_CTL, V3D_READ(V3D_MMU_CTL));
202
203 if (v3d->ver >= 41) {
204 axi_id = axi_id >> 5;
205 if (axi_id < ARRAY_SIZE(v3d41_axi_ids))
206 client = v3d41_axi_ids[axi_id];
207 }
208
209 dev_err(v3d->drm.dev, "MMU error from client %s (%d) at 0x%llx%s%s%s\n",
210 client, axi_id, (long long)vio_addr,
211 ((intsts & V3D_HUB_INT_MMU_WRV) ?
212 ", write violation" : ""),
213 ((intsts & V3D_HUB_INT_MMU_PTI) ?
214 ", pte invalid" : ""),
215 ((intsts & V3D_HUB_INT_MMU_CAP) ?
216 ", cap exceeded" : ""));
217 status = IRQ_HANDLED;
218 }
219
220 if (v3d->ver >= 71 && (intsts & V3D_V7_HUB_INT_GMPV)) {
221 dev_err(v3d->drm.dev, "GMP Violation\n");
222 status = IRQ_HANDLED;
223 }
224
225 return status;
226}
227
228int
229v3d_irq_init(struct v3d_dev *v3d)
230{
231 int irq1, ret, core;
232
233 INIT_WORK(&v3d->overflow_mem_work, v3d_overflow_mem_work);
234
235 /* Clear any pending interrupts someone might have left around
236 * for us.
237 */
238 for (core = 0; core < v3d->cores; core++)
239 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
240 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
241
242 irq1 = platform_get_irq_optional(v3d_to_pdev(v3d), 1);
243 if (irq1 == -EPROBE_DEFER)
244 return irq1;
245 if (irq1 > 0) {
246 ret = devm_request_irq(v3d->drm.dev, irq1,
247 v3d_irq, IRQF_SHARED,
248 "v3d_core0", v3d);
249 if (ret)
250 goto fail;
251 ret = devm_request_irq(v3d->drm.dev,
252 platform_get_irq(v3d_to_pdev(v3d), 0),
253 v3d_hub_irq, IRQF_SHARED,
254 "v3d_hub", v3d);
255 if (ret)
256 goto fail;
257 } else {
258 v3d->single_irq_line = true;
259
260 ret = devm_request_irq(v3d->drm.dev,
261 platform_get_irq(v3d_to_pdev(v3d), 0),
262 v3d_irq, IRQF_SHARED,
263 "v3d", v3d);
264 if (ret)
265 goto fail;
266 }
267
268 v3d_irq_enable(v3d);
269 return 0;
270
271fail:
272 if (ret != -EPROBE_DEFER)
273 dev_err(v3d->drm.dev, "IRQ setup failed: %d\n", ret);
274 return ret;
275}
276
277void
278v3d_irq_enable(struct v3d_dev *v3d)
279{
280 int core;
281
282 /* Enable our set of interrupts, masking out any others. */
283 for (core = 0; core < v3d->cores; core++) {
284 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~V3D_CORE_IRQS(v3d->ver));
285 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_CLR, V3D_CORE_IRQS(v3d->ver));
286 }
287
288 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~V3D_HUB_IRQS(v3d->ver));
289 V3D_WRITE(V3D_HUB_INT_MSK_CLR, V3D_HUB_IRQS(v3d->ver));
290}
291
292void
293v3d_irq_disable(struct v3d_dev *v3d)
294{
295 int core;
296
297 /* Disable all interrupts. */
298 for (core = 0; core < v3d->cores; core++)
299 V3D_CORE_WRITE(core, V3D_CTL_INT_MSK_SET, ~0);
300 V3D_WRITE(V3D_HUB_INT_MSK_SET, ~0);
301
302 /* Clear any pending interrupts we might have left. */
303 for (core = 0; core < v3d->cores; core++)
304 V3D_CORE_WRITE(core, V3D_CTL_INT_CLR, V3D_CORE_IRQS(v3d->ver));
305 V3D_WRITE(V3D_HUB_INT_CLR, V3D_HUB_IRQS(v3d->ver));
306
307 cancel_work_sync(&v3d->overflow_mem_work);
308}
309
310/** Reinitializes interrupt registers when a GPU reset is performed. */
311void v3d_irq_reset(struct v3d_dev *v3d)
312{
313 v3d_irq_enable(v3d);
314}