1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include "smu_v13_0_10.h"
 25#include "amdgpu_reset.h"
 26#include "amdgpu_dpm.h"
 27#include "amdgpu_job.h"
 28#include "amdgpu_ring.h"
 29#include "amdgpu_ras.h"
 30#include "amdgpu_psp.h"
 31
 32static bool smu_v13_0_10_is_mode2_default(struct amdgpu_reset_control *reset_ctl)
 33{
 34	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
 35	if (adev->pm.fw_version >= 0x00502005 && !amdgpu_sriov_vf(adev))
 36		return true;
 37
 38	return false;
 39}
 40
 41static struct amdgpu_reset_handler *
 42smu_v13_0_10_get_reset_handler(struct amdgpu_reset_control *reset_ctl,
 43			    struct amdgpu_reset_context *reset_context)
 44{
 45	struct amdgpu_reset_handler *handler;
 46	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
 47	int i;
 48
 49	if (reset_context->method != AMD_RESET_METHOD_NONE) {
 50		for_each_handler(i, handler, reset_ctl) {
 51			if (handler->reset_method == reset_context->method)
 52				return handler;
 53		}
 54	}
 55
 56	if (smu_v13_0_10_is_mode2_default(reset_ctl) &&
 57		amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_MODE2) {
 58		for_each_handler(i, handler, reset_ctl)	{
 59			if (handler->reset_method == AMD_RESET_METHOD_MODE2)
 60				return handler;
 61		}
 62	}
 63
 64	return NULL;
 65}
 66
 67static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev)
 68{
 69	int r, i;
 70
 71	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_UNGATE);
 72	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_UNGATE);
 73
 74	for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
 75		if (!(adev->ip_blocks[i].version->type ==
 76			      AMD_IP_BLOCK_TYPE_GFX ||
 77		      adev->ip_blocks[i].version->type ==
 78			      AMD_IP_BLOCK_TYPE_SDMA ||
 79		      adev->ip_blocks[i].version->type ==
 80			      AMD_IP_BLOCK_TYPE_MES))
 81			continue;
 82
 83		r = amdgpu_ip_block_suspend(&adev->ip_blocks[i]);
 84		if (r)
 85			return r;
 86	}
 87
 88	return 0;
 89}
 90
 91static int
 92smu_v13_0_10_mode2_prepare_hwcontext(struct amdgpu_reset_control *reset_ctl,
 93				  struct amdgpu_reset_context *reset_context)
 94{
 95	int r = 0;
 96	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
 97
 98	if (!amdgpu_sriov_vf(adev))
 99		r = smu_v13_0_10_mode2_suspend_ip(adev);
100
101	return r;
102}
103
104static int smu_v13_0_10_mode2_reset(struct amdgpu_device *adev)
105{
106	return amdgpu_dpm_mode2_reset(adev);
107}
108
109static void smu_v13_0_10_async_reset(struct work_struct *work)
110{
111	struct amdgpu_reset_handler *handler;
112	struct amdgpu_reset_control *reset_ctl =
113		container_of(work, struct amdgpu_reset_control, reset_work);
114	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
115	int i;
116
117	for_each_handler(i, handler, reset_ctl)	{
118		if (handler->reset_method == reset_ctl->active_reset) {
119			dev_dbg(adev->dev, "Resetting device\n");
120			handler->do_reset(adev);
121			break;
122		}
123	}
124}
125static int
126smu_v13_0_10_mode2_perform_reset(struct amdgpu_reset_control *reset_ctl,
127			      struct amdgpu_reset_context *reset_context)
128{
129	struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle;
130	int r;
131
132	r = smu_v13_0_10_mode2_reset(adev);
133	if (r) {
134		dev_err(adev->dev,
135			"ASIC reset failed with error, %d ", r);
136	}
137	return r;
138}
139
140static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev)
141{
142	int i, r;
143	struct psp_context *psp = &adev->psp;
144	struct amdgpu_firmware_info *ucode;
145	struct amdgpu_firmware_info *ucode_list[2];
146	int ucode_count = 0;
147
148	for (i = 0; i < adev->firmware.max_ucodes; i++) {
149		ucode = &adev->firmware.ucode[i];
150
151		switch (ucode->ucode_id) {
152		case AMDGPU_UCODE_ID_IMU_I:
153		case AMDGPU_UCODE_ID_IMU_D:
154			ucode_list[ucode_count++] = ucode;
155			break;
156		default:
157			break;
158		}
159	}
160
161	r = psp_load_fw_list(psp, ucode_list, ucode_count);
162	if (r) {
163		dev_err(adev->dev, "IMU ucode load failed after mode2 reset\n");
164		return r;
165	}
166
167	r = psp_rlc_autoload_start(psp);
168	if (r) {
169		DRM_ERROR("Failed to start rlc autoload after mode2 reset\n");
170		return r;
171	}
172
173	amdgpu_dpm_enable_gfx_features(adev);
174
175	for (i = 0; i < adev->num_ip_blocks; i++) {
176		if (!(adev->ip_blocks[i].version->type ==
177			      AMD_IP_BLOCK_TYPE_GFX ||
178		      adev->ip_blocks[i].version->type ==
179			      AMD_IP_BLOCK_TYPE_MES ||
180		      adev->ip_blocks[i].version->type ==
181			      AMD_IP_BLOCK_TYPE_SDMA))
182			continue;
183		r = amdgpu_ip_block_resume(&adev->ip_blocks[i]);
184		if (r)
185			return r;
186	}
187
188	for (i = 0; i < adev->num_ip_blocks; i++) {
189		if (!(adev->ip_blocks[i].version->type ==
190			      AMD_IP_BLOCK_TYPE_GFX ||
191		      adev->ip_blocks[i].version->type ==
192			      AMD_IP_BLOCK_TYPE_MES ||
193		      adev->ip_blocks[i].version->type ==
194			      AMD_IP_BLOCK_TYPE_SDMA))
195			continue;
196
197		if (adev->ip_blocks[i].version->funcs->late_init) {
198			r = adev->ip_blocks[i].version->funcs->late_init(
199				&adev->ip_blocks[i]);
200			if (r) {
201				dev_err(adev->dev,
202					"late_init of IP block <%s> failed %d after reset\n",
203					adev->ip_blocks[i].version->funcs->name,
204					r);
205				return r;
206			}
207		}
208		adev->ip_blocks[i].status.late_initialized = true;
209	}
210
211	amdgpu_device_set_cg_state(adev, AMD_CG_STATE_GATE);
212	amdgpu_device_set_pg_state(adev, AMD_PG_STATE_GATE);
213
214	return r;
215}
216
217static int
218smu_v13_0_10_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl,
219				  struct amdgpu_reset_context *reset_context)
220{
221	int r;
222	struct amdgpu_device *tmp_adev = (struct amdgpu_device *)reset_ctl->handle;
223
224	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_RESET_RECOVERY);
225	dev_info(tmp_adev->dev,
226			"GPU reset succeeded, trying to resume\n");
227	r = smu_v13_0_10_mode2_restore_ip(tmp_adev);
228	if (r)
229		goto end;
230
231	amdgpu_register_gpu_instance(tmp_adev);
232
233	/* Resume RAS */
234	amdgpu_ras_resume(tmp_adev);
235
236	amdgpu_irq_gpu_reset_resume_helper(tmp_adev);
237
238	amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT);
239	r = amdgpu_ib_ring_tests(tmp_adev);
240	if (r) {
241		dev_err(tmp_adev->dev,
242			"ib ring test failed (%d).\n", r);
243		r = -EAGAIN;
244		goto end;
245	}
246
247end:
248	if (r)
249		return -EAGAIN;
250	else
251		return r;
252}
253
254static struct amdgpu_reset_handler smu_v13_0_10_mode2_handler = {
255	.reset_method		= AMD_RESET_METHOD_MODE2,
256	.prepare_env		= NULL,
257	.prepare_hwcontext	= smu_v13_0_10_mode2_prepare_hwcontext,
258	.perform_reset		= smu_v13_0_10_mode2_perform_reset,
259	.restore_hwcontext	= smu_v13_0_10_mode2_restore_hwcontext,
260	.restore_env		= NULL,
261	.do_reset		= smu_v13_0_10_mode2_reset,
262};
263
264static struct amdgpu_reset_handler
265	*smu_v13_0_10_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = {
266		&smu_v13_0_10_mode2_handler,
267	};
268
269int smu_v13_0_10_reset_init(struct amdgpu_device *adev)
270{
271	struct amdgpu_reset_control *reset_ctl;
272
273	reset_ctl = kzalloc(sizeof(*reset_ctl), GFP_KERNEL);
274	if (!reset_ctl)
275		return -ENOMEM;
276
277	reset_ctl->handle = adev;
278	reset_ctl->async_reset = smu_v13_0_10_async_reset;
279	reset_ctl->active_reset = AMD_RESET_METHOD_NONE;
280	reset_ctl->get_reset_handler = smu_v13_0_10_get_reset_handler;
281
282	INIT_WORK(&reset_ctl->reset_work, reset_ctl->async_reset);
283	/* Only mode2 is handled through reset control now */
284	reset_ctl->reset_handlers = &smu_v13_0_10_rst_handlers;
285
286	adev->reset_cntl = reset_ctl;
287
288	return 0;
289}
290
291int smu_v13_0_10_reset_fini(struct amdgpu_device *adev)
292{
293	kfree(adev->reset_cntl);
294	adev->reset_cntl = NULL;
295	return 0;
296}