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1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/platform_device.h>
19#include <linux/slab.h>
20#include <linux/syscore_ops.h>
21#include <linux/gpio/driver.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/bug.h>
25
26enum mxc_gpio_hwtype {
27 IMX1_GPIO, /* runs on i.mx1 */
28 IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
29 IMX31_GPIO, /* runs on i.mx31 */
30 IMX35_GPIO, /* runs on all other i.mx */
31};
32
33/* device type dependent stuff */
34struct mxc_gpio_hwdata {
35 unsigned dr_reg;
36 unsigned gdir_reg;
37 unsigned psr_reg;
38 unsigned icr1_reg;
39 unsigned icr2_reg;
40 unsigned imr_reg;
41 unsigned isr_reg;
42 int edge_sel_reg;
43 unsigned low_level;
44 unsigned high_level;
45 unsigned rise_edge;
46 unsigned fall_edge;
47};
48
49struct mxc_gpio_reg_saved {
50 u32 icr1;
51 u32 icr2;
52 u32 imr;
53 u32 gdir;
54 u32 edge_sel;
55 u32 dr;
56};
57
58struct mxc_gpio_port {
59 struct list_head node;
60 void __iomem *base;
61 struct clk *clk;
62 int irq;
63 int irq_high;
64 struct irq_domain *domain;
65 struct gpio_chip gc;
66 struct device *dev;
67 u32 both_edges;
68 struct mxc_gpio_reg_saved gpio_saved_reg;
69 bool power_off;
70};
71
72static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
73 .dr_reg = 0x1c,
74 .gdir_reg = 0x00,
75 .psr_reg = 0x24,
76 .icr1_reg = 0x28,
77 .icr2_reg = 0x2c,
78 .imr_reg = 0x30,
79 .isr_reg = 0x34,
80 .edge_sel_reg = -EINVAL,
81 .low_level = 0x03,
82 .high_level = 0x02,
83 .rise_edge = 0x00,
84 .fall_edge = 0x01,
85};
86
87static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
88 .dr_reg = 0x00,
89 .gdir_reg = 0x04,
90 .psr_reg = 0x08,
91 .icr1_reg = 0x0c,
92 .icr2_reg = 0x10,
93 .imr_reg = 0x14,
94 .isr_reg = 0x18,
95 .edge_sel_reg = -EINVAL,
96 .low_level = 0x00,
97 .high_level = 0x01,
98 .rise_edge = 0x02,
99 .fall_edge = 0x03,
100};
101
102static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
103 .dr_reg = 0x00,
104 .gdir_reg = 0x04,
105 .psr_reg = 0x08,
106 .icr1_reg = 0x0c,
107 .icr2_reg = 0x10,
108 .imr_reg = 0x14,
109 .isr_reg = 0x18,
110 .edge_sel_reg = 0x1c,
111 .low_level = 0x00,
112 .high_level = 0x01,
113 .rise_edge = 0x02,
114 .fall_edge = 0x03,
115};
116
117static enum mxc_gpio_hwtype mxc_gpio_hwtype;
118static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
119
120#define GPIO_DR (mxc_gpio_hwdata->dr_reg)
121#define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
122#define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
123#define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
124#define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
125#define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
126#define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
127#define GPIO_EDGE_SEL (mxc_gpio_hwdata->edge_sel_reg)
128
129#define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
130#define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
131#define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
132#define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
133#define GPIO_INT_BOTH_EDGES 0x4
134
135static const struct platform_device_id mxc_gpio_devtype[] = {
136 {
137 .name = "imx1-gpio",
138 .driver_data = IMX1_GPIO,
139 }, {
140 .name = "imx21-gpio",
141 .driver_data = IMX21_GPIO,
142 }, {
143 .name = "imx31-gpio",
144 .driver_data = IMX31_GPIO,
145 }, {
146 .name = "imx35-gpio",
147 .driver_data = IMX35_GPIO,
148 }, {
149 /* sentinel */
150 }
151};
152
153static const struct of_device_id mxc_gpio_dt_ids[] = {
154 { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
155 { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
156 { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
157 { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
158 { .compatible = "fsl,imx7d-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
159 { /* sentinel */ }
160};
161
162/*
163 * MX2 has one interrupt *for all* gpio ports. The list is used
164 * to save the references to all ports, so that mx2_gpio_irq_handler
165 * can walk through all interrupt status registers.
166 */
167static LIST_HEAD(mxc_gpio_ports);
168
169/* Note: This driver assumes 32 GPIOs are handled in one register */
170
171static int gpio_set_irq_type(struct irq_data *d, u32 type)
172{
173 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
174 struct mxc_gpio_port *port = gc->private;
175 u32 bit, val;
176 u32 gpio_idx = d->hwirq;
177 int edge;
178 void __iomem *reg = port->base;
179
180 port->both_edges &= ~(1 << gpio_idx);
181 switch (type) {
182 case IRQ_TYPE_EDGE_RISING:
183 edge = GPIO_INT_RISE_EDGE;
184 break;
185 case IRQ_TYPE_EDGE_FALLING:
186 edge = GPIO_INT_FALL_EDGE;
187 break;
188 case IRQ_TYPE_EDGE_BOTH:
189 if (GPIO_EDGE_SEL >= 0) {
190 edge = GPIO_INT_BOTH_EDGES;
191 } else {
192 val = port->gc.get(&port->gc, gpio_idx);
193 if (val) {
194 edge = GPIO_INT_LOW_LEV;
195 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
196 } else {
197 edge = GPIO_INT_HIGH_LEV;
198 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
199 }
200 port->both_edges |= 1 << gpio_idx;
201 }
202 break;
203 case IRQ_TYPE_LEVEL_LOW:
204 edge = GPIO_INT_LOW_LEV;
205 break;
206 case IRQ_TYPE_LEVEL_HIGH:
207 edge = GPIO_INT_HIGH_LEV;
208 break;
209 default:
210 return -EINVAL;
211 }
212
213 if (GPIO_EDGE_SEL >= 0) {
214 val = readl(port->base + GPIO_EDGE_SEL);
215 if (edge == GPIO_INT_BOTH_EDGES)
216 writel(val | (1 << gpio_idx),
217 port->base + GPIO_EDGE_SEL);
218 else
219 writel(val & ~(1 << gpio_idx),
220 port->base + GPIO_EDGE_SEL);
221 }
222
223 if (edge != GPIO_INT_BOTH_EDGES) {
224 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
225 bit = gpio_idx & 0xf;
226 val = readl(reg) & ~(0x3 << (bit << 1));
227 writel(val | (edge << (bit << 1)), reg);
228 }
229
230 writel(1 << gpio_idx, port->base + GPIO_ISR);
231
232 return 0;
233}
234
235static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
236{
237 void __iomem *reg = port->base;
238 u32 bit, val;
239 int edge;
240
241 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
242 bit = gpio & 0xf;
243 val = readl(reg);
244 edge = (val >> (bit << 1)) & 3;
245 val &= ~(0x3 << (bit << 1));
246 if (edge == GPIO_INT_HIGH_LEV) {
247 edge = GPIO_INT_LOW_LEV;
248 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
249 } else if (edge == GPIO_INT_LOW_LEV) {
250 edge = GPIO_INT_HIGH_LEV;
251 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
252 } else {
253 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
254 gpio, edge);
255 return;
256 }
257 writel(val | (edge << (bit << 1)), reg);
258}
259
260/* handle 32 interrupts in one status register */
261static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
262{
263 while (irq_stat != 0) {
264 int irqoffset = fls(irq_stat) - 1;
265
266 if (port->both_edges & (1 << irqoffset))
267 mxc_flip_edge(port, irqoffset);
268
269 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
270
271 irq_stat &= ~(1 << irqoffset);
272 }
273}
274
275/* MX1 and MX3 has one interrupt *per* gpio port */
276static void mx3_gpio_irq_handler(struct irq_desc *desc)
277{
278 u32 irq_stat;
279 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
280 struct irq_chip *chip = irq_desc_get_chip(desc);
281
282 chained_irq_enter(chip, desc);
283
284 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
285
286 mxc_gpio_irq_handler(port, irq_stat);
287
288 chained_irq_exit(chip, desc);
289}
290
291/* MX2 has one interrupt *for all* gpio ports */
292static void mx2_gpio_irq_handler(struct irq_desc *desc)
293{
294 u32 irq_msk, irq_stat;
295 struct mxc_gpio_port *port;
296 struct irq_chip *chip = irq_desc_get_chip(desc);
297
298 chained_irq_enter(chip, desc);
299
300 /* walk through all interrupt status registers */
301 list_for_each_entry(port, &mxc_gpio_ports, node) {
302 irq_msk = readl(port->base + GPIO_IMR);
303 if (!irq_msk)
304 continue;
305
306 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
307 if (irq_stat)
308 mxc_gpio_irq_handler(port, irq_stat);
309 }
310 chained_irq_exit(chip, desc);
311}
312
313/*
314 * Set interrupt number "irq" in the GPIO as a wake-up source.
315 * While system is running, all registered GPIO interrupts need to have
316 * wake-up enabled. When system is suspended, only selected GPIO interrupts
317 * need to have wake-up enabled.
318 * @param irq interrupt source number
319 * @param enable enable as wake-up if equal to non-zero
320 * @return This function returns 0 on success.
321 */
322static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
323{
324 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
325 struct mxc_gpio_port *port = gc->private;
326 u32 gpio_idx = d->hwirq;
327 int ret;
328
329 if (enable) {
330 if (port->irq_high && (gpio_idx >= 16))
331 ret = enable_irq_wake(port->irq_high);
332 else
333 ret = enable_irq_wake(port->irq);
334 } else {
335 if (port->irq_high && (gpio_idx >= 16))
336 ret = disable_irq_wake(port->irq_high);
337 else
338 ret = disable_irq_wake(port->irq);
339 }
340
341 return ret;
342}
343
344static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
345{
346 struct irq_chip_generic *gc;
347 struct irq_chip_type *ct;
348 int rv;
349
350 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
351 port->base, handle_level_irq);
352 if (!gc)
353 return -ENOMEM;
354 gc->private = port;
355
356 ct = gc->chip_types;
357 ct->chip.irq_ack = irq_gc_ack_set_bit;
358 ct->chip.irq_mask = irq_gc_mask_clr_bit;
359 ct->chip.irq_unmask = irq_gc_mask_set_bit;
360 ct->chip.irq_set_type = gpio_set_irq_type;
361 ct->chip.irq_set_wake = gpio_set_wake_irq;
362 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
363 ct->regs.ack = GPIO_ISR;
364 ct->regs.mask = GPIO_IMR;
365
366 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
367 IRQ_GC_INIT_NESTED_LOCK,
368 IRQ_NOREQUEST, 0);
369
370 return rv;
371}
372
373static void mxc_gpio_get_hw(struct platform_device *pdev)
374{
375 const struct of_device_id *of_id =
376 of_match_device(mxc_gpio_dt_ids, &pdev->dev);
377 enum mxc_gpio_hwtype hwtype;
378
379 if (of_id)
380 pdev->id_entry = of_id->data;
381 hwtype = pdev->id_entry->driver_data;
382
383 if (mxc_gpio_hwtype) {
384 /*
385 * The driver works with a reasonable presupposition,
386 * that is all gpio ports must be the same type when
387 * running on one soc.
388 */
389 BUG_ON(mxc_gpio_hwtype != hwtype);
390 return;
391 }
392
393 if (hwtype == IMX35_GPIO)
394 mxc_gpio_hwdata = &imx35_gpio_hwdata;
395 else if (hwtype == IMX31_GPIO)
396 mxc_gpio_hwdata = &imx31_gpio_hwdata;
397 else
398 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
399
400 mxc_gpio_hwtype = hwtype;
401}
402
403static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
404{
405 struct mxc_gpio_port *port = gpiochip_get_data(gc);
406
407 return irq_find_mapping(port->domain, offset);
408}
409
410static int mxc_gpio_probe(struct platform_device *pdev)
411{
412 struct device_node *np = pdev->dev.of_node;
413 struct mxc_gpio_port *port;
414 int irq_count;
415 int irq_base;
416 int err;
417
418 mxc_gpio_get_hw(pdev);
419
420 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
421 if (!port)
422 return -ENOMEM;
423
424 port->dev = &pdev->dev;
425
426 port->base = devm_platform_ioremap_resource(pdev, 0);
427 if (IS_ERR(port->base))
428 return PTR_ERR(port->base);
429
430 irq_count = platform_irq_count(pdev);
431 if (irq_count < 0)
432 return irq_count;
433
434 if (irq_count > 1) {
435 port->irq_high = platform_get_irq(pdev, 1);
436 if (port->irq_high < 0)
437 port->irq_high = 0;
438 }
439
440 port->irq = platform_get_irq(pdev, 0);
441 if (port->irq < 0)
442 return port->irq;
443
444 /* the controller clock is optional */
445 port->clk = devm_clk_get_optional(&pdev->dev, NULL);
446 if (IS_ERR(port->clk))
447 return PTR_ERR(port->clk);
448
449 err = clk_prepare_enable(port->clk);
450 if (err) {
451 dev_err(&pdev->dev, "Unable to enable clock.\n");
452 return err;
453 }
454
455 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
456 port->power_off = true;
457
458 /* disable the interrupt and clear the status */
459 writel(0, port->base + GPIO_IMR);
460 writel(~0, port->base + GPIO_ISR);
461
462 if (mxc_gpio_hwtype == IMX21_GPIO) {
463 /*
464 * Setup one handler for all GPIO interrupts. Actually setting
465 * the handler is needed only once, but doing it for every port
466 * is more robust and easier.
467 */
468 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
469 } else {
470 /* setup one handler for each entry */
471 irq_set_chained_handler_and_data(port->irq,
472 mx3_gpio_irq_handler, port);
473 if (port->irq_high > 0)
474 /* setup handler for GPIO 16 to 31 */
475 irq_set_chained_handler_and_data(port->irq_high,
476 mx3_gpio_irq_handler,
477 port);
478 }
479
480 err = bgpio_init(&port->gc, &pdev->dev, 4,
481 port->base + GPIO_PSR,
482 port->base + GPIO_DR, NULL,
483 port->base + GPIO_GDIR, NULL,
484 BGPIOF_READ_OUTPUT_REG_SET);
485 if (err)
486 goto out_bgio;
487
488 port->gc.request = gpiochip_generic_request;
489 port->gc.free = gpiochip_generic_free;
490 port->gc.to_irq = mxc_gpio_to_irq;
491 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
492 pdev->id * 32;
493
494 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
495 if (err)
496 goto out_bgio;
497
498 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
499 if (irq_base < 0) {
500 err = irq_base;
501 goto out_bgio;
502 }
503
504 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
505 &irq_domain_simple_ops, NULL);
506 if (!port->domain) {
507 err = -ENODEV;
508 goto out_bgio;
509 }
510
511 /* gpio-mxc can be a generic irq chip */
512 err = mxc_gpio_init_gc(port, irq_base);
513 if (err < 0)
514 goto out_irqdomain_remove;
515
516 list_add_tail(&port->node, &mxc_gpio_ports);
517
518 platform_set_drvdata(pdev, port);
519
520 return 0;
521
522out_irqdomain_remove:
523 irq_domain_remove(port->domain);
524out_bgio:
525 clk_disable_unprepare(port->clk);
526 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
527 return err;
528}
529
530static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
531{
532 if (!port->power_off)
533 return;
534
535 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
536 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
537 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
538 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
539 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
540 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
541}
542
543static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
544{
545 if (!port->power_off)
546 return;
547
548 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
549 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
550 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
551 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
552 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
553 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
554}
555
556static int mxc_gpio_syscore_suspend(void)
557{
558 struct mxc_gpio_port *port;
559
560 /* walk through all ports */
561 list_for_each_entry(port, &mxc_gpio_ports, node) {
562 mxc_gpio_save_regs(port);
563 clk_disable_unprepare(port->clk);
564 }
565
566 return 0;
567}
568
569static void mxc_gpio_syscore_resume(void)
570{
571 struct mxc_gpio_port *port;
572 int ret;
573
574 /* walk through all ports */
575 list_for_each_entry(port, &mxc_gpio_ports, node) {
576 ret = clk_prepare_enable(port->clk);
577 if (ret) {
578 pr_err("mxc: failed to enable gpio clock %d\n", ret);
579 return;
580 }
581 mxc_gpio_restore_regs(port);
582 }
583}
584
585static struct syscore_ops mxc_gpio_syscore_ops = {
586 .suspend = mxc_gpio_syscore_suspend,
587 .resume = mxc_gpio_syscore_resume,
588};
589
590static struct platform_driver mxc_gpio_driver = {
591 .driver = {
592 .name = "gpio-mxc",
593 .of_match_table = mxc_gpio_dt_ids,
594 .suppress_bind_attrs = true,
595 },
596 .probe = mxc_gpio_probe,
597 .id_table = mxc_gpio_devtype,
598};
599
600static int __init gpio_mxc_init(void)
601{
602 register_syscore_ops(&mxc_gpio_syscore_ops);
603
604 return platform_driver_register(&mxc_gpio_driver);
605}
606subsys_initcall(gpio_mxc_init);
1// SPDX-License-Identifier: GPL-2.0+
2//
3// MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
4// Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5//
6// Based on code from Freescale Semiconductor,
7// Authors: Daniel Mack, Juergen Beisert.
8// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
9
10#include <linux/clk.h>
11#include <linux/err.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/irqchip/chained_irq.h>
18#include <linux/module.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio/driver.h>
25#include <linux/of.h>
26#include <linux/bug.h>
27
28#define IMX_SCU_WAKEUP_OFF 0
29#define IMX_SCU_WAKEUP_LOW_LVL 4
30#define IMX_SCU_WAKEUP_FALL_EDGE 5
31#define IMX_SCU_WAKEUP_RISE_EDGE 6
32#define IMX_SCU_WAKEUP_HIGH_LVL 7
33
34/* device type dependent stuff */
35struct mxc_gpio_hwdata {
36 unsigned dr_reg;
37 unsigned gdir_reg;
38 unsigned psr_reg;
39 unsigned icr1_reg;
40 unsigned icr2_reg;
41 unsigned imr_reg;
42 unsigned isr_reg;
43 int edge_sel_reg;
44 unsigned low_level;
45 unsigned high_level;
46 unsigned rise_edge;
47 unsigned fall_edge;
48};
49
50struct mxc_gpio_reg_saved {
51 u32 icr1;
52 u32 icr2;
53 u32 imr;
54 u32 gdir;
55 u32 edge_sel;
56 u32 dr;
57};
58
59struct mxc_gpio_port {
60 struct list_head node;
61 void __iomem *base;
62 struct clk *clk;
63 int irq;
64 int irq_high;
65 void (*mx_irq_handler)(struct irq_desc *desc);
66 struct irq_domain *domain;
67 struct gpio_chip gc;
68 struct device *dev;
69 u32 both_edges;
70 struct mxc_gpio_reg_saved gpio_saved_reg;
71 bool power_off;
72 u32 wakeup_pads;
73 bool is_pad_wakeup;
74 u32 pad_type[32];
75 const struct mxc_gpio_hwdata *hwdata;
76};
77
78static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
79 .dr_reg = 0x1c,
80 .gdir_reg = 0x00,
81 .psr_reg = 0x24,
82 .icr1_reg = 0x28,
83 .icr2_reg = 0x2c,
84 .imr_reg = 0x30,
85 .isr_reg = 0x34,
86 .edge_sel_reg = -EINVAL,
87 .low_level = 0x03,
88 .high_level = 0x02,
89 .rise_edge = 0x00,
90 .fall_edge = 0x01,
91};
92
93static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
94 .dr_reg = 0x00,
95 .gdir_reg = 0x04,
96 .psr_reg = 0x08,
97 .icr1_reg = 0x0c,
98 .icr2_reg = 0x10,
99 .imr_reg = 0x14,
100 .isr_reg = 0x18,
101 .edge_sel_reg = -EINVAL,
102 .low_level = 0x00,
103 .high_level = 0x01,
104 .rise_edge = 0x02,
105 .fall_edge = 0x03,
106};
107
108static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
109 .dr_reg = 0x00,
110 .gdir_reg = 0x04,
111 .psr_reg = 0x08,
112 .icr1_reg = 0x0c,
113 .icr2_reg = 0x10,
114 .imr_reg = 0x14,
115 .isr_reg = 0x18,
116 .edge_sel_reg = 0x1c,
117 .low_level = 0x00,
118 .high_level = 0x01,
119 .rise_edge = 0x02,
120 .fall_edge = 0x03,
121};
122
123#define GPIO_DR (port->hwdata->dr_reg)
124#define GPIO_GDIR (port->hwdata->gdir_reg)
125#define GPIO_PSR (port->hwdata->psr_reg)
126#define GPIO_ICR1 (port->hwdata->icr1_reg)
127#define GPIO_ICR2 (port->hwdata->icr2_reg)
128#define GPIO_IMR (port->hwdata->imr_reg)
129#define GPIO_ISR (port->hwdata->isr_reg)
130#define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg)
131
132#define GPIO_INT_LOW_LEV (port->hwdata->low_level)
133#define GPIO_INT_HIGH_LEV (port->hwdata->high_level)
134#define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge)
135#define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge)
136#define GPIO_INT_BOTH_EDGES 0x4
137
138static const struct of_device_id mxc_gpio_dt_ids[] = {
139 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata },
140 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata },
141 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata },
142 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata },
143 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata },
144 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata },
145 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata },
146 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata },
147 { /* sentinel */ }
148};
149MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids);
150
151/*
152 * MX2 has one interrupt *for all* gpio ports. The list is used
153 * to save the references to all ports, so that mx2_gpio_irq_handler
154 * can walk through all interrupt status registers.
155 */
156static LIST_HEAD(mxc_gpio_ports);
157
158/* Note: This driver assumes 32 GPIOs are handled in one register */
159
160static int gpio_set_irq_type(struct irq_data *d, u32 type)
161{
162 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
163 struct mxc_gpio_port *port = gc->private;
164 unsigned long flags;
165 u32 bit, val;
166 u32 gpio_idx = d->hwirq;
167 int edge;
168 void __iomem *reg = port->base;
169
170 port->both_edges &= ~(1 << gpio_idx);
171 switch (type) {
172 case IRQ_TYPE_EDGE_RISING:
173 edge = GPIO_INT_RISE_EDGE;
174 break;
175 case IRQ_TYPE_EDGE_FALLING:
176 edge = GPIO_INT_FALL_EDGE;
177 break;
178 case IRQ_TYPE_EDGE_BOTH:
179 if (GPIO_EDGE_SEL >= 0) {
180 edge = GPIO_INT_BOTH_EDGES;
181 } else {
182 val = port->gc.get(&port->gc, gpio_idx);
183 if (val) {
184 edge = GPIO_INT_LOW_LEV;
185 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx);
186 } else {
187 edge = GPIO_INT_HIGH_LEV;
188 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx);
189 }
190 port->both_edges |= 1 << gpio_idx;
191 }
192 break;
193 case IRQ_TYPE_LEVEL_LOW:
194 edge = GPIO_INT_LOW_LEV;
195 break;
196 case IRQ_TYPE_LEVEL_HIGH:
197 edge = GPIO_INT_HIGH_LEV;
198 break;
199 default:
200 return -EINVAL;
201 }
202
203 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
204
205 if (GPIO_EDGE_SEL >= 0) {
206 val = readl(port->base + GPIO_EDGE_SEL);
207 if (edge == GPIO_INT_BOTH_EDGES)
208 writel(val | (1 << gpio_idx),
209 port->base + GPIO_EDGE_SEL);
210 else
211 writel(val & ~(1 << gpio_idx),
212 port->base + GPIO_EDGE_SEL);
213 }
214
215 if (edge != GPIO_INT_BOTH_EDGES) {
216 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
217 bit = gpio_idx & 0xf;
218 val = readl(reg) & ~(0x3 << (bit << 1));
219 writel(val | (edge << (bit << 1)), reg);
220 }
221
222 writel(1 << gpio_idx, port->base + GPIO_ISR);
223 port->pad_type[gpio_idx] = type;
224
225 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
226
227 return port->gc.direction_input(&port->gc, gpio_idx);
228}
229
230static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
231{
232 void __iomem *reg = port->base;
233 unsigned long flags;
234 u32 bit, val;
235 int edge;
236
237 raw_spin_lock_irqsave(&port->gc.bgpio_lock, flags);
238
239 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
240 bit = gpio & 0xf;
241 val = readl(reg);
242 edge = (val >> (bit << 1)) & 3;
243 val &= ~(0x3 << (bit << 1));
244 if (edge == GPIO_INT_HIGH_LEV) {
245 edge = GPIO_INT_LOW_LEV;
246 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
247 } else if (edge == GPIO_INT_LOW_LEV) {
248 edge = GPIO_INT_HIGH_LEV;
249 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
250 } else {
251 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
252 gpio, edge);
253 goto unlock;
254 }
255 writel(val | (edge << (bit << 1)), reg);
256
257unlock:
258 raw_spin_unlock_irqrestore(&port->gc.bgpio_lock, flags);
259}
260
261/* handle 32 interrupts in one status register */
262static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
263{
264 while (irq_stat != 0) {
265 int irqoffset = fls(irq_stat) - 1;
266
267 if (port->both_edges & (1 << irqoffset))
268 mxc_flip_edge(port, irqoffset);
269
270 generic_handle_domain_irq(port->domain, irqoffset);
271
272 irq_stat &= ~(1 << irqoffset);
273 }
274}
275
276/* MX1 and MX3 has one interrupt *per* gpio port */
277static void mx3_gpio_irq_handler(struct irq_desc *desc)
278{
279 u32 irq_stat;
280 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
281 struct irq_chip *chip = irq_desc_get_chip(desc);
282
283 if (port->is_pad_wakeup)
284 return;
285
286 chained_irq_enter(chip, desc);
287
288 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
289
290 mxc_gpio_irq_handler(port, irq_stat);
291
292 chained_irq_exit(chip, desc);
293}
294
295/* MX2 has one interrupt *for all* gpio ports */
296static void mx2_gpio_irq_handler(struct irq_desc *desc)
297{
298 u32 irq_msk, irq_stat;
299 struct mxc_gpio_port *port;
300 struct irq_chip *chip = irq_desc_get_chip(desc);
301
302 chained_irq_enter(chip, desc);
303
304 /* walk through all interrupt status registers */
305 list_for_each_entry(port, &mxc_gpio_ports, node) {
306 irq_msk = readl(port->base + GPIO_IMR);
307 if (!irq_msk)
308 continue;
309
310 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
311 if (irq_stat)
312 mxc_gpio_irq_handler(port, irq_stat);
313 }
314 chained_irq_exit(chip, desc);
315}
316
317/*
318 * Set interrupt number "irq" in the GPIO as a wake-up source.
319 * While system is running, all registered GPIO interrupts need to have
320 * wake-up enabled. When system is suspended, only selected GPIO interrupts
321 * need to have wake-up enabled.
322 * @param irq interrupt source number
323 * @param enable enable as wake-up if equal to non-zero
324 * @return This function returns 0 on success.
325 */
326static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
327{
328 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
329 struct mxc_gpio_port *port = gc->private;
330 u32 gpio_idx = d->hwirq;
331 int ret;
332
333 if (enable) {
334 if (port->irq_high && (gpio_idx >= 16))
335 ret = enable_irq_wake(port->irq_high);
336 else
337 ret = enable_irq_wake(port->irq);
338 port->wakeup_pads |= (1 << gpio_idx);
339 } else {
340 if (port->irq_high && (gpio_idx >= 16))
341 ret = disable_irq_wake(port->irq_high);
342 else
343 ret = disable_irq_wake(port->irq);
344 port->wakeup_pads &= ~(1 << gpio_idx);
345 }
346
347 return ret;
348}
349
350static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
351{
352 struct irq_chip_generic *gc;
353 struct irq_chip_type *ct;
354 int rv;
355
356 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
357 port->base, handle_level_irq);
358 if (!gc)
359 return -ENOMEM;
360 gc->private = port;
361
362 ct = gc->chip_types;
363 ct->chip.irq_ack = irq_gc_ack_set_bit;
364 ct->chip.irq_mask = irq_gc_mask_clr_bit;
365 ct->chip.irq_unmask = irq_gc_mask_set_bit;
366 ct->chip.irq_set_type = gpio_set_irq_type;
367 ct->chip.irq_set_wake = gpio_set_wake_irq;
368 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
369 ct->regs.ack = GPIO_ISR;
370 ct->regs.mask = GPIO_IMR;
371
372 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
373 IRQ_GC_INIT_NESTED_LOCK,
374 IRQ_NOREQUEST, 0);
375
376 return rv;
377}
378
379static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
380{
381 struct mxc_gpio_port *port = gpiochip_get_data(gc);
382
383 return irq_find_mapping(port->domain, offset);
384}
385
386static int mxc_gpio_request(struct gpio_chip *chip, unsigned int offset)
387{
388 int ret;
389
390 ret = gpiochip_generic_request(chip, offset);
391 if (ret)
392 return ret;
393
394 return pm_runtime_resume_and_get(chip->parent);
395}
396
397static void mxc_gpio_free(struct gpio_chip *chip, unsigned int offset)
398{
399 gpiochip_generic_free(chip, offset);
400 pm_runtime_put(chip->parent);
401}
402
403static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable)
404{
405 if (enable)
406 irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port);
407 else
408 irq_set_chained_handler_and_data(port->irq, NULL, NULL);
409
410 /* setup handler for GPIO 16 to 31 */
411 if (port->irq_high > 0) {
412 if (enable)
413 irq_set_chained_handler_and_data(port->irq_high,
414 port->mx_irq_handler,
415 port);
416 else
417 irq_set_chained_handler_and_data(port->irq_high, NULL, NULL);
418 }
419}
420
421static int mxc_gpio_probe(struct platform_device *pdev)
422{
423 struct device_node *np = pdev->dev.of_node;
424 struct mxc_gpio_port *port;
425 int irq_count;
426 int irq_base;
427 int err;
428
429 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
430 if (!port)
431 return -ENOMEM;
432
433 port->dev = &pdev->dev;
434 port->hwdata = device_get_match_data(&pdev->dev);
435
436 port->base = devm_platform_ioremap_resource(pdev, 0);
437 if (IS_ERR(port->base))
438 return PTR_ERR(port->base);
439
440 irq_count = platform_irq_count(pdev);
441 if (irq_count < 0)
442 return irq_count;
443
444 if (irq_count > 1) {
445 port->irq_high = platform_get_irq(pdev, 1);
446 if (port->irq_high < 0)
447 port->irq_high = 0;
448 }
449
450 port->irq = platform_get_irq(pdev, 0);
451 if (port->irq < 0)
452 return port->irq;
453
454 /* the controller clock is optional */
455 port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
456 if (IS_ERR(port->clk))
457 return PTR_ERR(port->clk);
458
459 if (of_device_is_compatible(np, "fsl,imx7d-gpio"))
460 port->power_off = true;
461
462 pm_runtime_get_noresume(&pdev->dev);
463 pm_runtime_set_active(&pdev->dev);
464 pm_runtime_enable(&pdev->dev);
465
466 /* disable the interrupt and clear the status */
467 writel(0, port->base + GPIO_IMR);
468 writel(~0, port->base + GPIO_ISR);
469
470 if (of_device_is_compatible(np, "fsl,imx21-gpio")) {
471 /*
472 * Setup one handler for all GPIO interrupts. Actually setting
473 * the handler is needed only once, but doing it for every port
474 * is more robust and easier.
475 */
476 port->irq_high = -1;
477 port->mx_irq_handler = mx2_gpio_irq_handler;
478 } else
479 port->mx_irq_handler = mx3_gpio_irq_handler;
480
481 mxc_update_irq_chained_handler(port, true);
482 err = bgpio_init(&port->gc, &pdev->dev, 4,
483 port->base + GPIO_PSR,
484 port->base + GPIO_DR, NULL,
485 port->base + GPIO_GDIR, NULL,
486 BGPIOF_READ_OUTPUT_REG_SET);
487 if (err)
488 goto out_bgio;
489
490 port->gc.request = mxc_gpio_request;
491 port->gc.free = mxc_gpio_free;
492 port->gc.to_irq = mxc_gpio_to_irq;
493 port->gc.base = of_alias_get_id(np, "gpio") * 32;
494
495 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
496 if (err)
497 goto out_bgio;
498
499 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
500 if (irq_base < 0) {
501 err = irq_base;
502 goto out_bgio;
503 }
504
505 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
506 &irq_domain_simple_ops, NULL);
507 if (!port->domain) {
508 err = -ENODEV;
509 goto out_bgio;
510 }
511
512 irq_domain_set_pm_device(port->domain, &pdev->dev);
513
514 /* gpio-mxc can be a generic irq chip */
515 err = mxc_gpio_init_gc(port, irq_base);
516 if (err < 0)
517 goto out_irqdomain_remove;
518
519 list_add_tail(&port->node, &mxc_gpio_ports);
520
521 platform_set_drvdata(pdev, port);
522 pm_runtime_put_autosuspend(&pdev->dev);
523
524 return 0;
525
526out_irqdomain_remove:
527 irq_domain_remove(port->domain);
528out_bgio:
529 pm_runtime_disable(&pdev->dev);
530 pm_runtime_put_noidle(&pdev->dev);
531 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
532 return err;
533}
534
535static void mxc_gpio_save_regs(struct mxc_gpio_port *port)
536{
537 if (!port->power_off)
538 return;
539
540 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1);
541 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2);
542 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR);
543 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR);
544 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL);
545 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR);
546}
547
548static void mxc_gpio_restore_regs(struct mxc_gpio_port *port)
549{
550 if (!port->power_off)
551 return;
552
553 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1);
554 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2);
555 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR);
556 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR);
557 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL);
558 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR);
559}
560
561static bool mxc_gpio_generic_config(struct mxc_gpio_port *port,
562 unsigned int offset, unsigned long conf)
563{
564 struct device_node *np = port->dev->of_node;
565
566 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") ||
567 of_device_is_compatible(np, "fsl,imx8qxp-gpio") ||
568 of_device_is_compatible(np, "fsl,imx8qm-gpio"))
569 return (gpiochip_generic_config(&port->gc, offset, conf) == 0);
570
571 return false;
572}
573
574static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable)
575{
576 unsigned long config;
577 bool ret = false;
578 int i, type;
579
580 static const u32 pad_type_map[] = {
581 IMX_SCU_WAKEUP_OFF, /* 0 */
582 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */
583 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */
584 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */
585 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */
586 IMX_SCU_WAKEUP_OFF, /* 5 */
587 IMX_SCU_WAKEUP_OFF, /* 6 */
588 IMX_SCU_WAKEUP_OFF, /* 7 */
589 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */
590 };
591
592 for (i = 0; i < 32; i++) {
593 if ((port->wakeup_pads & (1 << i))) {
594 type = port->pad_type[i];
595 if (enable)
596 config = pad_type_map[type];
597 else
598 config = IMX_SCU_WAKEUP_OFF;
599 ret |= mxc_gpio_generic_config(port, i, config);
600 }
601 }
602
603 return ret;
604}
605
606static int mxc_gpio_runtime_suspend(struct device *dev)
607{
608 struct mxc_gpio_port *port = dev_get_drvdata(dev);
609
610 mxc_gpio_save_regs(port);
611 clk_disable_unprepare(port->clk);
612 mxc_update_irq_chained_handler(port, false);
613
614 return 0;
615}
616
617static int mxc_gpio_runtime_resume(struct device *dev)
618{
619 struct mxc_gpio_port *port = dev_get_drvdata(dev);
620 int ret;
621
622 mxc_update_irq_chained_handler(port, true);
623 ret = clk_prepare_enable(port->clk);
624 if (ret) {
625 mxc_update_irq_chained_handler(port, false);
626 return ret;
627 }
628
629 mxc_gpio_restore_regs(port);
630
631 return 0;
632}
633
634static int mxc_gpio_noirq_suspend(struct device *dev)
635{
636 struct platform_device *pdev = to_platform_device(dev);
637 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
638
639 if (port->wakeup_pads > 0)
640 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true);
641
642 return 0;
643}
644
645static int mxc_gpio_noirq_resume(struct device *dev)
646{
647 struct platform_device *pdev = to_platform_device(dev);
648 struct mxc_gpio_port *port = platform_get_drvdata(pdev);
649
650 if (port->wakeup_pads > 0)
651 mxc_gpio_set_pad_wakeup(port, false);
652 port->is_pad_wakeup = false;
653
654 return 0;
655}
656
657static const struct dev_pm_ops mxc_gpio_dev_pm_ops = {
658 NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume)
659 RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL)
660};
661
662static int mxc_gpio_syscore_suspend(void)
663{
664 struct mxc_gpio_port *port;
665 int ret;
666
667 /* walk through all ports */
668 list_for_each_entry(port, &mxc_gpio_ports, node) {
669 ret = clk_prepare_enable(port->clk);
670 if (ret)
671 return ret;
672 mxc_gpio_save_regs(port);
673 clk_disable_unprepare(port->clk);
674 }
675
676 return 0;
677}
678
679static void mxc_gpio_syscore_resume(void)
680{
681 struct mxc_gpio_port *port;
682 int ret;
683
684 /* walk through all ports */
685 list_for_each_entry(port, &mxc_gpio_ports, node) {
686 ret = clk_prepare_enable(port->clk);
687 if (ret) {
688 pr_err("mxc: failed to enable gpio clock %d\n", ret);
689 return;
690 }
691 mxc_gpio_restore_regs(port);
692 clk_disable_unprepare(port->clk);
693 }
694}
695
696static struct syscore_ops mxc_gpio_syscore_ops = {
697 .suspend = mxc_gpio_syscore_suspend,
698 .resume = mxc_gpio_syscore_resume,
699};
700
701static struct platform_driver mxc_gpio_driver = {
702 .driver = {
703 .name = "gpio-mxc",
704 .of_match_table = mxc_gpio_dt_ids,
705 .suppress_bind_attrs = true,
706 .pm = pm_ptr(&mxc_gpio_dev_pm_ops),
707 },
708 .probe = mxc_gpio_probe,
709};
710
711static int __init gpio_mxc_init(void)
712{
713 register_syscore_ops(&mxc_gpio_syscore_ops);
714
715 return platform_driver_register(&mxc_gpio_driver);
716}
717subsys_initcall(gpio_mxc_init);
718
719MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>");
720MODULE_DESCRIPTION("i.MX GPIO Driver");
721MODULE_LICENSE("GPL");