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1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "armv7-m.dtsi"
49#include <dt-bindings/clock/stm32fx-clock.h>
50#include <dt-bindings/mfd/stm32f4-rcc.h>
51
52/ {
53 #address-cells = <1>;
54 #size-cells = <1>;
55
56 clocks {
57 clk_hse: clk-hse {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <0>;
61 };
62
63 clk_lse: clk-lse {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 clk_lsi: clk-lsi {
70 #clock-cells = <0>;
71 compatible = "fixed-clock";
72 clock-frequency = <32000>;
73 };
74
75 clk_i2s_ckin: i2s-ckin {
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-frequency = <0>;
79 };
80 };
81
82 soc {
83 romem: efuse@1fff7800 {
84 compatible = "st,stm32f4-otp";
85 reg = <0x1fff7800 0x400>;
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ts_cal1: calib@22c {
89 reg = <0x22c 0x2>;
90 };
91 ts_cal2: calib@22e {
92 reg = <0x22e 0x2>;
93 };
94 };
95
96 timer2: timer@40000000 {
97 compatible = "st,stm32-timer";
98 reg = <0x40000000 0x400>;
99 interrupts = <28>;
100 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
101 status = "disabled";
102 };
103
104 timers2: timers@40000000 {
105 #address-cells = <1>;
106 #size-cells = <0>;
107 compatible = "st,stm32-timers";
108 reg = <0x40000000 0x400>;
109 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clock-names = "int";
111 status = "disabled";
112
113 pwm {
114 compatible = "st,stm32-pwm";
115 #pwm-cells = <3>;
116 status = "disabled";
117 };
118
119 timer@1 {
120 compatible = "st,stm32-timer-trigger";
121 reg = <1>;
122 status = "disabled";
123 };
124 };
125
126 timer3: timer@40000400 {
127 compatible = "st,stm32-timer";
128 reg = <0x40000400 0x400>;
129 interrupts = <29>;
130 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
131 status = "disabled";
132 };
133
134 timers3: timers@40000400 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "st,stm32-timers";
138 reg = <0x40000400 0x400>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
140 clock-names = "int";
141 status = "disabled";
142
143 pwm {
144 compatible = "st,stm32-pwm";
145 #pwm-cells = <3>;
146 status = "disabled";
147 };
148
149 timer@2 {
150 compatible = "st,stm32-timer-trigger";
151 reg = <2>;
152 status = "disabled";
153 };
154 };
155
156 timer4: timer@40000800 {
157 compatible = "st,stm32-timer";
158 reg = <0x40000800 0x400>;
159 interrupts = <30>;
160 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
161 status = "disabled";
162 };
163
164 timers4: timers@40000800 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 compatible = "st,stm32-timers";
168 reg = <0x40000800 0x400>;
169 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
170 clock-names = "int";
171 status = "disabled";
172
173 pwm {
174 compatible = "st,stm32-pwm";
175 #pwm-cells = <3>;
176 status = "disabled";
177 };
178
179 timer@3 {
180 compatible = "st,stm32-timer-trigger";
181 reg = <3>;
182 status = "disabled";
183 };
184 };
185
186 timer5: timer@40000c00 {
187 compatible = "st,stm32-timer";
188 reg = <0x40000c00 0x400>;
189 interrupts = <50>;
190 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
191 };
192
193 timers5: timers@40000c00 {
194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "st,stm32-timers";
197 reg = <0x40000C00 0x400>;
198 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
199 clock-names = "int";
200 status = "disabled";
201
202 pwm {
203 compatible = "st,stm32-pwm";
204 #pwm-cells = <3>;
205 status = "disabled";
206 };
207
208 timer@4 {
209 compatible = "st,stm32-timer-trigger";
210 reg = <4>;
211 status = "disabled";
212 };
213 };
214
215 timer6: timer@40001000 {
216 compatible = "st,stm32-timer";
217 reg = <0x40001000 0x400>;
218 interrupts = <54>;
219 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
220 status = "disabled";
221 };
222
223 timers6: timers@40001000 {
224 #address-cells = <1>;
225 #size-cells = <0>;
226 compatible = "st,stm32-timers";
227 reg = <0x40001000 0x400>;
228 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
229 clock-names = "int";
230 status = "disabled";
231
232 timer@5 {
233 compatible = "st,stm32-timer-trigger";
234 reg = <5>;
235 status = "disabled";
236 };
237 };
238
239 timer7: timer@40001400 {
240 compatible = "st,stm32-timer";
241 reg = <0x40001400 0x400>;
242 interrupts = <55>;
243 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
244 status = "disabled";
245 };
246
247 timers7: timers@40001400 {
248 #address-cells = <1>;
249 #size-cells = <0>;
250 compatible = "st,stm32-timers";
251 reg = <0x40001400 0x400>;
252 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
253 clock-names = "int";
254 status = "disabled";
255
256 timer@6 {
257 compatible = "st,stm32-timer-trigger";
258 reg = <6>;
259 status = "disabled";
260 };
261 };
262
263 timers12: timers@40001800 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "st,stm32-timers";
267 reg = <0x40001800 0x400>;
268 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
269 clock-names = "int";
270 status = "disabled";
271
272 pwm {
273 compatible = "st,stm32-pwm";
274 #pwm-cells = <3>;
275 status = "disabled";
276 };
277
278 timer@11 {
279 compatible = "st,stm32-timer-trigger";
280 reg = <11>;
281 status = "disabled";
282 };
283 };
284
285 timers13: timers@40001c00 {
286 #address-cells = <1>;
287 #size-cells = <0>;
288 compatible = "st,stm32-timers";
289 reg = <0x40001C00 0x400>;
290 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
291 clock-names = "int";
292 status = "disabled";
293
294 pwm {
295 compatible = "st,stm32-pwm";
296 #pwm-cells = <3>;
297 status = "disabled";
298 };
299 };
300
301 timers14: timers@40002000 {
302 #address-cells = <1>;
303 #size-cells = <0>;
304 compatible = "st,stm32-timers";
305 reg = <0x40002000 0x400>;
306 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
307 clock-names = "int";
308 status = "disabled";
309
310 pwm {
311 compatible = "st,stm32-pwm";
312 #pwm-cells = <3>;
313 status = "disabled";
314 };
315 };
316
317 rtc: rtc@40002800 {
318 compatible = "st,stm32-rtc";
319 reg = <0x40002800 0x400>;
320 clocks = <&rcc 1 CLK_RTC>;
321 assigned-clocks = <&rcc 1 CLK_RTC>;
322 assigned-clock-parents = <&rcc 1 CLK_LSE>;
323 interrupt-parent = <&exti>;
324 interrupts = <17 1>;
325 st,syscfg = <&pwrcfg 0x00 0x100>;
326 status = "disabled";
327 };
328
329 iwdg: watchdog@40003000 {
330 compatible = "st,stm32-iwdg";
331 reg = <0x40003000 0x400>;
332 clocks = <&clk_lsi>;
333 clock-names = "lsi";
334 status = "disabled";
335 };
336
337 spi2: spi@40003800 {
338 #address-cells = <1>;
339 #size-cells = <0>;
340 compatible = "st,stm32f4-spi";
341 reg = <0x40003800 0x400>;
342 interrupts = <36>;
343 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>;
344 status = "disabled";
345 };
346
347 spi3: spi@40003c00 {
348 #address-cells = <1>;
349 #size-cells = <0>;
350 compatible = "st,stm32f4-spi";
351 reg = <0x40003c00 0x400>;
352 interrupts = <51>;
353 clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>;
354 status = "disabled";
355 };
356
357 usart2: serial@40004400 {
358 compatible = "st,stm32-uart";
359 reg = <0x40004400 0x400>;
360 interrupts = <38>;
361 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
362 status = "disabled";
363 };
364
365 usart3: serial@40004800 {
366 compatible = "st,stm32-uart";
367 reg = <0x40004800 0x400>;
368 interrupts = <39>;
369 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
370 status = "disabled";
371 dmas = <&dma1 1 4 0x400 0x0>,
372 <&dma1 3 4 0x400 0x0>;
373 dma-names = "rx", "tx";
374 };
375
376 usart4: serial@40004c00 {
377 compatible = "st,stm32-uart";
378 reg = <0x40004c00 0x400>;
379 interrupts = <52>;
380 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
381 status = "disabled";
382 };
383
384 usart5: serial@40005000 {
385 compatible = "st,stm32-uart";
386 reg = <0x40005000 0x400>;
387 interrupts = <53>;
388 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
389 status = "disabled";
390 };
391
392 i2c1: i2c@40005400 {
393 compatible = "st,stm32f4-i2c";
394 reg = <0x40005400 0x400>;
395 interrupts = <31>,
396 <32>;
397 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
398 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
399 #address-cells = <1>;
400 #size-cells = <0>;
401 status = "disabled";
402 };
403
404 i2c3: i2c@40005c00 {
405 compatible = "st,stm32f4-i2c";
406 reg = <0x40005c00 0x400>;
407 interrupts = <72>,
408 <73>;
409 resets = <&rcc STM32F4_APB1_RESET(I2C3)>;
410 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C3)>;
411 #address-cells = <1>;
412 #size-cells = <0>;
413 status = "disabled";
414 };
415
416 dac: dac@40007400 {
417 compatible = "st,stm32f4-dac-core";
418 reg = <0x40007400 0x400>;
419 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
420 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
421 clock-names = "pclk";
422 #address-cells = <1>;
423 #size-cells = <0>;
424 status = "disabled";
425
426 dac1: dac@1 {
427 compatible = "st,stm32-dac";
428 #io-channel-cells = <1>;
429 reg = <1>;
430 status = "disabled";
431 };
432
433 dac2: dac@2 {
434 compatible = "st,stm32-dac";
435 #io-channel-cells = <1>;
436 reg = <2>;
437 status = "disabled";
438 };
439 };
440
441 usart7: serial@40007800 {
442 compatible = "st,stm32-uart";
443 reg = <0x40007800 0x400>;
444 interrupts = <82>;
445 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
446 status = "disabled";
447 };
448
449 usart8: serial@40007c00 {
450 compatible = "st,stm32-uart";
451 reg = <0x40007c00 0x400>;
452 interrupts = <83>;
453 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
454 status = "disabled";
455 };
456
457 timers1: timers@40010000 {
458 #address-cells = <1>;
459 #size-cells = <0>;
460 compatible = "st,stm32-timers";
461 reg = <0x40010000 0x400>;
462 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
463 clock-names = "int";
464 status = "disabled";
465
466 pwm {
467 compatible = "st,stm32-pwm";
468 #pwm-cells = <3>;
469 status = "disabled";
470 };
471
472 timer@0 {
473 compatible = "st,stm32-timer-trigger";
474 reg = <0>;
475 status = "disabled";
476 };
477 };
478
479 timers8: timers@40010400 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "st,stm32-timers";
483 reg = <0x40010400 0x400>;
484 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
485 clock-names = "int";
486 status = "disabled";
487
488 pwm {
489 compatible = "st,stm32-pwm";
490 #pwm-cells = <3>;
491 status = "disabled";
492 };
493
494 timer@7 {
495 compatible = "st,stm32-timer-trigger";
496 reg = <7>;
497 status = "disabled";
498 };
499 };
500
501 usart1: serial@40011000 {
502 compatible = "st,stm32-uart";
503 reg = <0x40011000 0x400>;
504 interrupts = <37>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
506 status = "disabled";
507 dmas = <&dma2 2 4 0x400 0x0>,
508 <&dma2 7 4 0x400 0x0>;
509 dma-names = "rx", "tx";
510 };
511
512 usart6: serial@40011400 {
513 compatible = "st,stm32-uart";
514 reg = <0x40011400 0x400>;
515 interrupts = <71>;
516 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
517 status = "disabled";
518 };
519
520 adc: adc@40012000 {
521 compatible = "st,stm32f4-adc-core";
522 reg = <0x40012000 0x400>;
523 interrupts = <18>;
524 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
525 clock-names = "adc";
526 interrupt-controller;
527 #interrupt-cells = <1>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 status = "disabled";
531
532 adc1: adc@0 {
533 compatible = "st,stm32f4-adc";
534 #io-channel-cells = <1>;
535 reg = <0x0>;
536 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
537 interrupt-parent = <&adc>;
538 interrupts = <0>;
539 dmas = <&dma2 0 0 0x400 0x0>;
540 dma-names = "rx";
541 status = "disabled";
542 };
543
544 adc2: adc@100 {
545 compatible = "st,stm32f4-adc";
546 #io-channel-cells = <1>;
547 reg = <0x100>;
548 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
549 interrupt-parent = <&adc>;
550 interrupts = <1>;
551 dmas = <&dma2 3 1 0x400 0x0>;
552 dma-names = "rx";
553 status = "disabled";
554 };
555
556 adc3: adc@200 {
557 compatible = "st,stm32f4-adc";
558 #io-channel-cells = <1>;
559 reg = <0x200>;
560 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
561 interrupt-parent = <&adc>;
562 interrupts = <2>;
563 dmas = <&dma2 1 2 0x400 0x0>;
564 dma-names = "rx";
565 status = "disabled";
566 };
567 };
568
569 sdio: sdio@40012c00 {
570 compatible = "arm,pl180", "arm,primecell";
571 arm,primecell-periphid = <0x00880180>;
572 reg = <0x40012c00 0x400>;
573 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
574 clock-names = "apb_pclk";
575 interrupts = <49>;
576 max-frequency = <48000000>;
577 status = "disabled";
578 };
579
580 spi1: spi@40013000 {
581 #address-cells = <1>;
582 #size-cells = <0>;
583 compatible = "st,stm32f4-spi";
584 reg = <0x40013000 0x400>;
585 interrupts = <35>;
586 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>;
587 status = "disabled";
588 };
589
590 spi4: spi@40013400 {
591 #address-cells = <1>;
592 #size-cells = <0>;
593 compatible = "st,stm32f4-spi";
594 reg = <0x40013400 0x400>;
595 interrupts = <84>;
596 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>;
597 status = "disabled";
598 };
599
600 syscfg: syscon@40013800 {
601 compatible = "st,stm32-syscfg", "syscon";
602 reg = <0x40013800 0x400>;
603 };
604
605 exti: interrupt-controller@40013c00 {
606 compatible = "st,stm32-exti";
607 interrupt-controller;
608 #interrupt-cells = <2>;
609 reg = <0x40013C00 0x400>;
610 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
611 };
612
613 timers9: timers@40014000 {
614 #address-cells = <1>;
615 #size-cells = <0>;
616 compatible = "st,stm32-timers";
617 reg = <0x40014000 0x400>;
618 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
619 clock-names = "int";
620 status = "disabled";
621
622 pwm {
623 compatible = "st,stm32-pwm";
624 #pwm-cells = <3>;
625 status = "disabled";
626 };
627
628 timer@8 {
629 compatible = "st,stm32-timer-trigger";
630 reg = <8>;
631 status = "disabled";
632 };
633 };
634
635 timers10: timers@40014400 {
636 #address-cells = <1>;
637 #size-cells = <0>;
638 compatible = "st,stm32-timers";
639 reg = <0x40014400 0x400>;
640 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
641 clock-names = "int";
642 status = "disabled";
643
644 pwm {
645 compatible = "st,stm32-pwm";
646 #pwm-cells = <3>;
647 status = "disabled";
648 };
649 };
650
651 timers11: timers@40014800 {
652 #address-cells = <1>;
653 #size-cells = <0>;
654 compatible = "st,stm32-timers";
655 reg = <0x40014800 0x400>;
656 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
657 clock-names = "int";
658 status = "disabled";
659
660 pwm {
661 compatible = "st,stm32-pwm";
662 #pwm-cells = <3>;
663 status = "disabled";
664 };
665 };
666
667 spi5: spi@40015000 {
668 #address-cells = <1>;
669 #size-cells = <0>;
670 compatible = "st,stm32f4-spi";
671 reg = <0x40015000 0x400>;
672 interrupts = <85>;
673 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>;
674 dmas = <&dma2 3 2 0x400 0x0>,
675 <&dma2 4 2 0x400 0x0>;
676 dma-names = "rx", "tx";
677 status = "disabled";
678 };
679
680 spi6: spi@40015400 {
681 #address-cells = <1>;
682 #size-cells = <0>;
683 compatible = "st,stm32f4-spi";
684 reg = <0x40015400 0x400>;
685 interrupts = <86>;
686 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>;
687 status = "disabled";
688 };
689
690 pwrcfg: power-config@40007000 {
691 compatible = "st,stm32-power-config", "syscon";
692 reg = <0x40007000 0x400>;
693 };
694
695 ltdc: display-controller@40016800 {
696 compatible = "st,stm32-ltdc";
697 reg = <0x40016800 0x200>;
698 interrupts = <88>, <89>;
699 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
700 clocks = <&rcc 1 CLK_LCD>;
701 clock-names = "lcd";
702 status = "disabled";
703 };
704
705 crc: crc@40023000 {
706 compatible = "st,stm32f4-crc";
707 reg = <0x40023000 0x400>;
708 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
709 status = "disabled";
710 };
711
712 rcc: rcc@40023810 {
713 #reset-cells = <1>;
714 #clock-cells = <2>;
715 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
716 reg = <0x40023800 0x400>;
717 clocks = <&clk_hse>, <&clk_i2s_ckin>;
718 st,syscfg = <&pwrcfg>;
719 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
720 assigned-clock-rates = <1000000>;
721 };
722
723 dma1: dma-controller@40026000 {
724 compatible = "st,stm32-dma";
725 reg = <0x40026000 0x400>;
726 interrupts = <11>,
727 <12>,
728 <13>,
729 <14>,
730 <15>,
731 <16>,
732 <17>,
733 <47>;
734 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
735 #dma-cells = <4>;
736 };
737
738 dma2: dma-controller@40026400 {
739 compatible = "st,stm32-dma";
740 reg = <0x40026400 0x400>;
741 interrupts = <56>,
742 <57>,
743 <58>,
744 <59>,
745 <60>,
746 <68>,
747 <69>,
748 <70>;
749 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
750 #dma-cells = <4>;
751 st,mem2mem;
752 };
753
754 mac: ethernet@40028000 {
755 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
756 reg = <0x40028000 0x8000>;
757 reg-names = "stmmaceth";
758 interrupts = <61>;
759 interrupt-names = "macirq";
760 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
761 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
762 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
763 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
764 st,syscon = <&syscfg 0x4>;
765 snps,pbl = <8>;
766 snps,mixed-burst;
767 status = "disabled";
768 };
769
770 usbotg_hs: usb@40040000 {
771 compatible = "snps,dwc2";
772 reg = <0x40040000 0x40000>;
773 interrupts = <77>;
774 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
775 clock-names = "otg";
776 status = "disabled";
777 };
778
779 usbotg_fs: usb@50000000 {
780 compatible = "st,stm32f4x9-fsotg";
781 reg = <0x50000000 0x40000>;
782 interrupts = <67>;
783 clocks = <&rcc 0 39>;
784 clock-names = "otg";
785 status = "disabled";
786 };
787
788 dcmi: dcmi@50050000 {
789 compatible = "st,stm32-dcmi";
790 reg = <0x50050000 0x400>;
791 interrupts = <78>;
792 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
793 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
794 clock-names = "mclk";
795 pinctrl-names = "default";
796 pinctrl-0 = <&dcmi_pins>;
797 dmas = <&dma2 1 1 0x414 0x3>;
798 dma-names = "tx";
799 status = "disabled";
800 };
801
802 rng: rng@50060800 {
803 compatible = "st,stm32-rng";
804 reg = <0x50060800 0x400>;
805 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
806
807 };
808 };
809};
810
811&systick {
812 clocks = <&rcc 1 SYSTICK>;
813 status = "okay";
814};