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v5.9
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * An RTC driver for Allwinner A10/A20
  4 *
  5 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  6 */
  7
  8#include <linux/delay.h>
  9#include <linux/err.h>
 10#include <linux/fs.h>
 11#include <linux/init.h>
 12#include <linux/interrupt.h>
 13#include <linux/io.h>
 14#include <linux/kernel.h>
 15#include <linux/module.h>
 16#include <linux/of.h>
 17#include <linux/of_address.h>
 18#include <linux/of_device.h>
 19#include <linux/platform_device.h>
 20#include <linux/rtc.h>
 21#include <linux/types.h>
 22
 23#define SUNXI_LOSC_CTRL				0x0000
 24#define SUNXI_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
 25#define SUNXI_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
 26
 27#define SUNXI_RTC_YMD				0x0004
 28
 29#define SUNXI_RTC_HMS				0x0008
 30
 31#define SUNXI_ALRM_DHMS				0x000c
 32
 33#define SUNXI_ALRM_EN				0x0014
 34#define SUNXI_ALRM_EN_CNT_EN			BIT(8)
 35
 36#define SUNXI_ALRM_IRQ_EN			0x0018
 37#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)
 38
 39#define SUNXI_ALRM_IRQ_STA			0x001c
 40#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0)
 41
 42#define SUNXI_MASK_DH				0x0000001f
 43#define SUNXI_MASK_SM				0x0000003f
 44#define SUNXI_MASK_M				0x0000000f
 45#define SUNXI_MASK_LY				0x00000001
 46#define SUNXI_MASK_D				0x00000ffe
 47#define SUNXI_MASK_M				0x0000000f
 48
 49#define SUNXI_GET(x, mask, shift)		(((x) & ((mask) << (shift))) \
 50							>> (shift))
 51
 52#define SUNXI_SET(x, mask, shift)		(((x) & (mask)) << (shift))
 53
 54/*
 55 * Get date values
 56 */
 57#define SUNXI_DATE_GET_DAY_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 0)
 58#define SUNXI_DATE_GET_MON_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_M, 8)
 59#define SUNXI_DATE_GET_YEAR_VALUE(x, mask)	SUNXI_GET(x, mask, 16)
 60
 61/*
 62 * Get time values
 63 */
 64#define SUNXI_TIME_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
 65#define SUNXI_TIME_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
 66#define SUNXI_TIME_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
 67
 68/*
 69 * Get alarm values
 70 */
 71#define SUNXI_ALRM_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
 72#define SUNXI_ALRM_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
 73#define SUNXI_ALRM_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
 74
 75/*
 76 * Set date values
 77 */
 78#define SUNXI_DATE_SET_DAY_VALUE(x)		SUNXI_DATE_GET_DAY_VALUE(x)
 79#define SUNXI_DATE_SET_MON_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_M, 8)
 80#define SUNXI_DATE_SET_YEAR_VALUE(x, mask)	SUNXI_SET(x, mask, 16)
 81#define SUNXI_LEAP_SET_VALUE(x, shift)		SUNXI_SET(x, SUNXI_MASK_LY, shift)
 82
 83/*
 84 * Set time values
 85 */
 86#define SUNXI_TIME_SET_SEC_VALUE(x)		SUNXI_TIME_GET_SEC_VALUE(x)
 87#define SUNXI_TIME_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
 88#define SUNXI_TIME_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
 89
 90/*
 91 * Set alarm values
 92 */
 93#define SUNXI_ALRM_SET_SEC_VALUE(x)		SUNXI_ALRM_GET_SEC_VALUE(x)
 94#define SUNXI_ALRM_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
 95#define SUNXI_ALRM_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
 96#define SUNXI_ALRM_SET_DAY_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_D, 21)
 97
 98/*
 99 * Time unit conversions
100 */
101#define SEC_IN_MIN				60
102#define SEC_IN_HOUR				(60 * SEC_IN_MIN)
103#define SEC_IN_DAY				(24 * SEC_IN_HOUR)
104
105/*
106 * The year parameter passed to the driver is usually an offset relative to
107 * the year 1900. This macro is used to convert this offset to another one
108 * relative to the minimum year allowed by the hardware.
109 */
110#define SUNXI_YEAR_OFF(x)			((x)->min - 1900)
111
112/*
113 * min and max year are arbitrary set considering the limited range of the
114 * hardware register field
115 */
116struct sunxi_rtc_data_year {
117	unsigned int min;		/* min year allowed */
118	unsigned int max;		/* max year allowed */
119	unsigned int mask;		/* mask for the year field */
120	unsigned char leap_shift;	/* bit shift to get the leap year */
121};
122
123static const struct sunxi_rtc_data_year data_year_param[] = {
124	[0] = {
125		.min		= 2010,
126		.max		= 2073,
127		.mask		= 0x3f,
128		.leap_shift	= 22,
129	},
130	[1] = {
131		.min		= 1970,
132		.max		= 2225,
133		.mask		= 0xff,
134		.leap_shift	= 24,
135	},
136};
137
138struct sunxi_rtc_dev {
139	struct rtc_device *rtc;
140	struct device *dev;
141	const struct sunxi_rtc_data_year *data_year;
142	void __iomem *base;
143	int irq;
144};
145
146static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
147{
148	struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
149	u32 val;
150
151	val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
152
153	if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
154		val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
155		writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
156
157		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
158
159		return IRQ_HANDLED;
160	}
161
162	return IRQ_NONE;
163}
164
165static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
166{
167	u32 alrm_val = 0;
168	u32 alrm_irq_val = 0;
169
170	if (to) {
171		alrm_val = readl(chip->base + SUNXI_ALRM_EN);
172		alrm_val |= SUNXI_ALRM_EN_CNT_EN;
173
174		alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
175		alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
176	} else {
177		writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
178				chip->base + SUNXI_ALRM_IRQ_STA);
179	}
180
181	writel(alrm_val, chip->base + SUNXI_ALRM_EN);
182	writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
183}
184
185static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
186{
187	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
188	struct rtc_time *alrm_tm = &wkalrm->time;
189	u32 alrm;
190	u32 alrm_en;
191	u32 date;
192
193	alrm = readl(chip->base + SUNXI_ALRM_DHMS);
194	date = readl(chip->base + SUNXI_RTC_YMD);
195
196	alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
197	alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
198	alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
199
200	alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
201	alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
202	alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
203			chip->data_year->mask);
204
205	alrm_tm->tm_mon -= 1;
206
207	/*
208	 * switch from (data_year->min)-relative offset to
209	 * a (1900)-relative one
210	 */
211	alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
212
213	alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
214	if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
215		wkalrm->enabled = 1;
216
217	return 0;
218}
219
220static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
221{
222	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
223	u32 date, time;
224
225	/*
226	 * read again in case it changes
227	 */
228	do {
229		date = readl(chip->base + SUNXI_RTC_YMD);
230		time = readl(chip->base + SUNXI_RTC_HMS);
231	} while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
232		 (time != readl(chip->base + SUNXI_RTC_HMS)));
233
234	rtc_tm->tm_sec  = SUNXI_TIME_GET_SEC_VALUE(time);
235	rtc_tm->tm_min  = SUNXI_TIME_GET_MIN_VALUE(time);
236	rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
237
238	rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
239	rtc_tm->tm_mon  = SUNXI_DATE_GET_MON_VALUE(date);
240	rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
241					chip->data_year->mask);
242
243	rtc_tm->tm_mon  -= 1;
244
245	/*
246	 * switch from (data_year->min)-relative offset to
247	 * a (1900)-relative one
248	 */
249	rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
250
251	return 0;
252}
253
254static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
255{
256	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
257	struct rtc_time *alrm_tm = &wkalrm->time;
258	struct rtc_time tm_now;
259	u32 alrm;
260	time64_t diff;
261	unsigned long time_gap;
262	unsigned long time_gap_day;
263	unsigned long time_gap_hour;
264	unsigned long time_gap_min;
265	int ret;
266
267	ret = sunxi_rtc_gettime(dev, &tm_now);
268	if (ret < 0) {
269		dev_err(dev, "Error in getting time\n");
270		return -EINVAL;
271	}
272
273	diff = rtc_tm_sub(alrm_tm, &tm_now);
274	if (diff <= 0) {
275		dev_err(dev, "Date to set in the past\n");
276		return -EINVAL;
277	}
278
279	if (diff > 255 * SEC_IN_DAY) {
280		dev_err(dev, "Day must be in the range 0 - 255\n");
281		return -EINVAL;
282	}
283
284	time_gap = diff;
285	time_gap_day = time_gap / SEC_IN_DAY;
286	time_gap -= time_gap_day * SEC_IN_DAY;
287	time_gap_hour = time_gap / SEC_IN_HOUR;
288	time_gap -= time_gap_hour * SEC_IN_HOUR;
289	time_gap_min = time_gap / SEC_IN_MIN;
290	time_gap -= time_gap_min * SEC_IN_MIN;
291
292	sunxi_rtc_setaie(0, chip);
293	writel(0, chip->base + SUNXI_ALRM_DHMS);
294	usleep_range(100, 300);
295
296	alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
297		SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
298		SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
299		SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
300	writel(alrm, chip->base + SUNXI_ALRM_DHMS);
301
302	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
303	writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
304
305	sunxi_rtc_setaie(wkalrm->enabled, chip);
306
307	return 0;
308}
309
310static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
311			  unsigned int mask, unsigned int ms_timeout)
312{
313	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
314	u32 reg;
315
316	do {
317		reg = readl(chip->base + offset);
318		reg &= mask;
319
320		if (reg == mask)
321			return 0;
322
323	} while (time_before(jiffies, timeout));
324
325	return -ETIMEDOUT;
326}
327
328static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
329{
330	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
331	u32 date = 0;
332	u32 time = 0;
333	unsigned int year;
334
335	/*
336	 * the input rtc_tm->tm_year is the offset relative to 1900. We use
337	 * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
338	 * allowed by the hardware
339	 */
340
341	year = rtc_tm->tm_year + 1900;
342	if (year < chip->data_year->min || year > chip->data_year->max) {
343		dev_err(dev, "rtc only supports year in range %u - %u\n",
344			chip->data_year->min, chip->data_year->max);
345		return -EINVAL;
346	}
347
348	rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
349	rtc_tm->tm_mon += 1;
350
351	date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
352		SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
353		SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
354				chip->data_year->mask);
355
356	if (is_leap_year(year))
357		date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
358
359	time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
360		SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
361		SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
362
363	writel(0, chip->base + SUNXI_RTC_HMS);
364	writel(0, chip->base + SUNXI_RTC_YMD);
365
366	writel(time, chip->base + SUNXI_RTC_HMS);
367
368	/*
369	 * After writing the RTC HH-MM-SS register, the
370	 * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
371	 * be cleared until the real writing operation is finished
372	 */
373
374	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
375				SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
376		dev_err(dev, "Failed to set rtc time.\n");
377		return -1;
378	}
379
380	writel(date, chip->base + SUNXI_RTC_YMD);
381
382	/*
383	 * After writing the RTC YY-MM-DD register, the
384	 * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
385	 * be cleared until the real writing operation is finished
386	 */
387
388	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
389				SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
390		dev_err(dev, "Failed to set rtc time.\n");
391		return -1;
392	}
393
394	return 0;
395}
396
397static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
398{
399	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
400
401	if (!enabled)
402		sunxi_rtc_setaie(enabled, chip);
403
404	return 0;
405}
406
407static const struct rtc_class_ops sunxi_rtc_ops = {
408	.read_time		= sunxi_rtc_gettime,
409	.set_time		= sunxi_rtc_settime,
410	.read_alarm		= sunxi_rtc_getalarm,
411	.set_alarm		= sunxi_rtc_setalarm,
412	.alarm_irq_enable	= sunxi_rtc_alarm_irq_enable
413};
414
415static const struct of_device_id sunxi_rtc_dt_ids[] = {
416	{ .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
417	{ .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
418	{ /* sentinel */ },
419};
420MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
421
422static int sunxi_rtc_probe(struct platform_device *pdev)
423{
424	struct sunxi_rtc_dev *chip;
 
425	int ret;
426
427	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
428	if (!chip)
429		return -ENOMEM;
430
431	platform_set_drvdata(pdev, chip);
432	chip->dev = &pdev->dev;
433
434	chip->rtc = devm_rtc_allocate_device(&pdev->dev);
435	if (IS_ERR(chip->rtc))
436		return PTR_ERR(chip->rtc);
437
438	chip->base = devm_platform_ioremap_resource(pdev, 0);
 
439	if (IS_ERR(chip->base))
440		return PTR_ERR(chip->base);
441
442	chip->irq = platform_get_irq(pdev, 0);
443	if (chip->irq < 0)
444		return chip->irq;
445	ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
446			0, dev_name(&pdev->dev), chip);
447	if (ret) {
448		dev_err(&pdev->dev, "Could not request IRQ\n");
449		return ret;
450	}
451
452	chip->data_year = of_device_get_match_data(&pdev->dev);
453	if (!chip->data_year) {
454		dev_err(&pdev->dev, "Unable to setup RTC data\n");
455		return -ENODEV;
456	}
457
458	/* clear the alarm count value */
459	writel(0, chip->base + SUNXI_ALRM_DHMS);
460
461	/* disable alarm, not generate irq pending */
462	writel(0, chip->base + SUNXI_ALRM_EN);
463
464	/* disable alarm week/cnt irq, unset to cpu */
465	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
466
467	/* clear alarm week/cnt irq pending */
468	writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
469			SUNXI_ALRM_IRQ_STA);
470
471	chip->rtc->ops = &sunxi_rtc_ops;
472
473	return rtc_register_device(chip->rtc);
474}
475
476static struct platform_driver sunxi_rtc_driver = {
477	.probe		= sunxi_rtc_probe,
478	.driver		= {
479		.name		= "sunxi-rtc",
480		.of_match_table = sunxi_rtc_dt_ids,
481	},
482};
483
484module_platform_driver(sunxi_rtc_driver);
485
486MODULE_DESCRIPTION("sunxi RTC driver");
487MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
488MODULE_LICENSE("GPL");
v5.4
  1// SPDX-License-Identifier: GPL-2.0-or-later
  2/*
  3 * An RTC driver for Allwinner A10/A20
  4 *
  5 * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  6 */
  7
  8#include <linux/delay.h>
  9#include <linux/err.h>
 10#include <linux/fs.h>
 11#include <linux/init.h>
 12#include <linux/interrupt.h>
 13#include <linux/io.h>
 14#include <linux/kernel.h>
 15#include <linux/module.h>
 16#include <linux/of.h>
 17#include <linux/of_address.h>
 18#include <linux/of_device.h>
 19#include <linux/platform_device.h>
 20#include <linux/rtc.h>
 21#include <linux/types.h>
 22
 23#define SUNXI_LOSC_CTRL				0x0000
 24#define SUNXI_LOSC_CTRL_RTC_HMS_ACC		BIT(8)
 25#define SUNXI_LOSC_CTRL_RTC_YMD_ACC		BIT(7)
 26
 27#define SUNXI_RTC_YMD				0x0004
 28
 29#define SUNXI_RTC_HMS				0x0008
 30
 31#define SUNXI_ALRM_DHMS				0x000c
 32
 33#define SUNXI_ALRM_EN				0x0014
 34#define SUNXI_ALRM_EN_CNT_EN			BIT(8)
 35
 36#define SUNXI_ALRM_IRQ_EN			0x0018
 37#define SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN		BIT(0)
 38
 39#define SUNXI_ALRM_IRQ_STA			0x001c
 40#define SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND		BIT(0)
 41
 42#define SUNXI_MASK_DH				0x0000001f
 43#define SUNXI_MASK_SM				0x0000003f
 44#define SUNXI_MASK_M				0x0000000f
 45#define SUNXI_MASK_LY				0x00000001
 46#define SUNXI_MASK_D				0x00000ffe
 47#define SUNXI_MASK_M				0x0000000f
 48
 49#define SUNXI_GET(x, mask, shift)		(((x) & ((mask) << (shift))) \
 50							>> (shift))
 51
 52#define SUNXI_SET(x, mask, shift)		(((x) & (mask)) << (shift))
 53
 54/*
 55 * Get date values
 56 */
 57#define SUNXI_DATE_GET_DAY_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 0)
 58#define SUNXI_DATE_GET_MON_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_M, 8)
 59#define SUNXI_DATE_GET_YEAR_VALUE(x, mask)	SUNXI_GET(x, mask, 16)
 60
 61/*
 62 * Get time values
 63 */
 64#define SUNXI_TIME_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
 65#define SUNXI_TIME_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
 66#define SUNXI_TIME_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
 67
 68/*
 69 * Get alarm values
 70 */
 71#define SUNXI_ALRM_GET_SEC_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 0)
 72#define SUNXI_ALRM_GET_MIN_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_SM, 8)
 73#define SUNXI_ALRM_GET_HOUR_VALUE(x)		SUNXI_GET(x, SUNXI_MASK_DH, 16)
 74
 75/*
 76 * Set date values
 77 */
 78#define SUNXI_DATE_SET_DAY_VALUE(x)		SUNXI_DATE_GET_DAY_VALUE(x)
 79#define SUNXI_DATE_SET_MON_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_M, 8)
 80#define SUNXI_DATE_SET_YEAR_VALUE(x, mask)	SUNXI_SET(x, mask, 16)
 81#define SUNXI_LEAP_SET_VALUE(x, shift)		SUNXI_SET(x, SUNXI_MASK_LY, shift)
 82
 83/*
 84 * Set time values
 85 */
 86#define SUNXI_TIME_SET_SEC_VALUE(x)		SUNXI_TIME_GET_SEC_VALUE(x)
 87#define SUNXI_TIME_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
 88#define SUNXI_TIME_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
 89
 90/*
 91 * Set alarm values
 92 */
 93#define SUNXI_ALRM_SET_SEC_VALUE(x)		SUNXI_ALRM_GET_SEC_VALUE(x)
 94#define SUNXI_ALRM_SET_MIN_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_SM, 8)
 95#define SUNXI_ALRM_SET_HOUR_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_DH, 16)
 96#define SUNXI_ALRM_SET_DAY_VALUE(x)		SUNXI_SET(x, SUNXI_MASK_D, 21)
 97
 98/*
 99 * Time unit conversions
100 */
101#define SEC_IN_MIN				60
102#define SEC_IN_HOUR				(60 * SEC_IN_MIN)
103#define SEC_IN_DAY				(24 * SEC_IN_HOUR)
104
105/*
106 * The year parameter passed to the driver is usually an offset relative to
107 * the year 1900. This macro is used to convert this offset to another one
108 * relative to the minimum year allowed by the hardware.
109 */
110#define SUNXI_YEAR_OFF(x)			((x)->min - 1900)
111
112/*
113 * min and max year are arbitrary set considering the limited range of the
114 * hardware register field
115 */
116struct sunxi_rtc_data_year {
117	unsigned int min;		/* min year allowed */
118	unsigned int max;		/* max year allowed */
119	unsigned int mask;		/* mask for the year field */
120	unsigned char leap_shift;	/* bit shift to get the leap year */
121};
122
123static const struct sunxi_rtc_data_year data_year_param[] = {
124	[0] = {
125		.min		= 2010,
126		.max		= 2073,
127		.mask		= 0x3f,
128		.leap_shift	= 22,
129	},
130	[1] = {
131		.min		= 1970,
132		.max		= 2225,
133		.mask		= 0xff,
134		.leap_shift	= 24,
135	},
136};
137
138struct sunxi_rtc_dev {
139	struct rtc_device *rtc;
140	struct device *dev;
141	const struct sunxi_rtc_data_year *data_year;
142	void __iomem *base;
143	int irq;
144};
145
146static irqreturn_t sunxi_rtc_alarmirq(int irq, void *id)
147{
148	struct sunxi_rtc_dev *chip = (struct sunxi_rtc_dev *) id;
149	u32 val;
150
151	val = readl(chip->base + SUNXI_ALRM_IRQ_STA);
152
153	if (val & SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND) {
154		val |= SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND;
155		writel(val, chip->base + SUNXI_ALRM_IRQ_STA);
156
157		rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
158
159		return IRQ_HANDLED;
160	}
161
162	return IRQ_NONE;
163}
164
165static void sunxi_rtc_setaie(unsigned int to, struct sunxi_rtc_dev *chip)
166{
167	u32 alrm_val = 0;
168	u32 alrm_irq_val = 0;
169
170	if (to) {
171		alrm_val = readl(chip->base + SUNXI_ALRM_EN);
172		alrm_val |= SUNXI_ALRM_EN_CNT_EN;
173
174		alrm_irq_val = readl(chip->base + SUNXI_ALRM_IRQ_EN);
175		alrm_irq_val |= SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN;
176	} else {
177		writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND,
178				chip->base + SUNXI_ALRM_IRQ_STA);
179	}
180
181	writel(alrm_val, chip->base + SUNXI_ALRM_EN);
182	writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN);
183}
184
185static int sunxi_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
186{
187	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
188	struct rtc_time *alrm_tm = &wkalrm->time;
189	u32 alrm;
190	u32 alrm_en;
191	u32 date;
192
193	alrm = readl(chip->base + SUNXI_ALRM_DHMS);
194	date = readl(chip->base + SUNXI_RTC_YMD);
195
196	alrm_tm->tm_sec = SUNXI_ALRM_GET_SEC_VALUE(alrm);
197	alrm_tm->tm_min = SUNXI_ALRM_GET_MIN_VALUE(alrm);
198	alrm_tm->tm_hour = SUNXI_ALRM_GET_HOUR_VALUE(alrm);
199
200	alrm_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
201	alrm_tm->tm_mon = SUNXI_DATE_GET_MON_VALUE(date);
202	alrm_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
203			chip->data_year->mask);
204
205	alrm_tm->tm_mon -= 1;
206
207	/*
208	 * switch from (data_year->min)-relative offset to
209	 * a (1900)-relative one
210	 */
211	alrm_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
212
213	alrm_en = readl(chip->base + SUNXI_ALRM_IRQ_EN);
214	if (alrm_en & SUNXI_ALRM_EN_CNT_EN)
215		wkalrm->enabled = 1;
216
217	return 0;
218}
219
220static int sunxi_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
221{
222	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
223	u32 date, time;
224
225	/*
226	 * read again in case it changes
227	 */
228	do {
229		date = readl(chip->base + SUNXI_RTC_YMD);
230		time = readl(chip->base + SUNXI_RTC_HMS);
231	} while ((date != readl(chip->base + SUNXI_RTC_YMD)) ||
232		 (time != readl(chip->base + SUNXI_RTC_HMS)));
233
234	rtc_tm->tm_sec  = SUNXI_TIME_GET_SEC_VALUE(time);
235	rtc_tm->tm_min  = SUNXI_TIME_GET_MIN_VALUE(time);
236	rtc_tm->tm_hour = SUNXI_TIME_GET_HOUR_VALUE(time);
237
238	rtc_tm->tm_mday = SUNXI_DATE_GET_DAY_VALUE(date);
239	rtc_tm->tm_mon  = SUNXI_DATE_GET_MON_VALUE(date);
240	rtc_tm->tm_year = SUNXI_DATE_GET_YEAR_VALUE(date,
241					chip->data_year->mask);
242
243	rtc_tm->tm_mon  -= 1;
244
245	/*
246	 * switch from (data_year->min)-relative offset to
247	 * a (1900)-relative one
248	 */
249	rtc_tm->tm_year += SUNXI_YEAR_OFF(chip->data_year);
250
251	return 0;
252}
253
254static int sunxi_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
255{
256	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
257	struct rtc_time *alrm_tm = &wkalrm->time;
258	struct rtc_time tm_now;
259	u32 alrm;
260	time64_t diff;
261	unsigned long time_gap;
262	unsigned long time_gap_day;
263	unsigned long time_gap_hour;
264	unsigned long time_gap_min;
265	int ret;
266
267	ret = sunxi_rtc_gettime(dev, &tm_now);
268	if (ret < 0) {
269		dev_err(dev, "Error in getting time\n");
270		return -EINVAL;
271	}
272
273	diff = rtc_tm_sub(alrm_tm, &tm_now);
274	if (diff <= 0) {
275		dev_err(dev, "Date to set in the past\n");
276		return -EINVAL;
277	}
278
279	if (diff > 255 * SEC_IN_DAY) {
280		dev_err(dev, "Day must be in the range 0 - 255\n");
281		return -EINVAL;
282	}
283
284	time_gap = diff;
285	time_gap_day = time_gap / SEC_IN_DAY;
286	time_gap -= time_gap_day * SEC_IN_DAY;
287	time_gap_hour = time_gap / SEC_IN_HOUR;
288	time_gap -= time_gap_hour * SEC_IN_HOUR;
289	time_gap_min = time_gap / SEC_IN_MIN;
290	time_gap -= time_gap_min * SEC_IN_MIN;
291
292	sunxi_rtc_setaie(0, chip);
293	writel(0, chip->base + SUNXI_ALRM_DHMS);
294	usleep_range(100, 300);
295
296	alrm = SUNXI_ALRM_SET_SEC_VALUE(time_gap) |
297		SUNXI_ALRM_SET_MIN_VALUE(time_gap_min) |
298		SUNXI_ALRM_SET_HOUR_VALUE(time_gap_hour) |
299		SUNXI_ALRM_SET_DAY_VALUE(time_gap_day);
300	writel(alrm, chip->base + SUNXI_ALRM_DHMS);
301
302	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
303	writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN);
304
305	sunxi_rtc_setaie(wkalrm->enabled, chip);
306
307	return 0;
308}
309
310static int sunxi_rtc_wait(struct sunxi_rtc_dev *chip, int offset,
311			  unsigned int mask, unsigned int ms_timeout)
312{
313	const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
314	u32 reg;
315
316	do {
317		reg = readl(chip->base + offset);
318		reg &= mask;
319
320		if (reg == mask)
321			return 0;
322
323	} while (time_before(jiffies, timeout));
324
325	return -ETIMEDOUT;
326}
327
328static int sunxi_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
329{
330	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
331	u32 date = 0;
332	u32 time = 0;
333	unsigned int year;
334
335	/*
336	 * the input rtc_tm->tm_year is the offset relative to 1900. We use
337	 * the SUNXI_YEAR_OFF macro to rebase it with respect to the min year
338	 * allowed by the hardware
339	 */
340
341	year = rtc_tm->tm_year + 1900;
342	if (year < chip->data_year->min || year > chip->data_year->max) {
343		dev_err(dev, "rtc only supports year in range %u - %u\n",
344			chip->data_year->min, chip->data_year->max);
345		return -EINVAL;
346	}
347
348	rtc_tm->tm_year -= SUNXI_YEAR_OFF(chip->data_year);
349	rtc_tm->tm_mon += 1;
350
351	date = SUNXI_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
352		SUNXI_DATE_SET_MON_VALUE(rtc_tm->tm_mon)  |
353		SUNXI_DATE_SET_YEAR_VALUE(rtc_tm->tm_year,
354				chip->data_year->mask);
355
356	if (is_leap_year(year))
357		date |= SUNXI_LEAP_SET_VALUE(1, chip->data_year->leap_shift);
358
359	time = SUNXI_TIME_SET_SEC_VALUE(rtc_tm->tm_sec)  |
360		SUNXI_TIME_SET_MIN_VALUE(rtc_tm->tm_min)  |
361		SUNXI_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
362
363	writel(0, chip->base + SUNXI_RTC_HMS);
364	writel(0, chip->base + SUNXI_RTC_YMD);
365
366	writel(time, chip->base + SUNXI_RTC_HMS);
367
368	/*
369	 * After writing the RTC HH-MM-SS register, the
370	 * SUNXI_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
371	 * be cleared until the real writing operation is finished
372	 */
373
374	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
375				SUNXI_LOSC_CTRL_RTC_HMS_ACC, 50)) {
376		dev_err(dev, "Failed to set rtc time.\n");
377		return -1;
378	}
379
380	writel(date, chip->base + SUNXI_RTC_YMD);
381
382	/*
383	 * After writing the RTC YY-MM-DD register, the
384	 * SUNXI_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
385	 * be cleared until the real writing operation is finished
386	 */
387
388	if (sunxi_rtc_wait(chip, SUNXI_LOSC_CTRL,
389				SUNXI_LOSC_CTRL_RTC_YMD_ACC, 50)) {
390		dev_err(dev, "Failed to set rtc time.\n");
391		return -1;
392	}
393
394	return 0;
395}
396
397static int sunxi_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
398{
399	struct sunxi_rtc_dev *chip = dev_get_drvdata(dev);
400
401	if (!enabled)
402		sunxi_rtc_setaie(enabled, chip);
403
404	return 0;
405}
406
407static const struct rtc_class_ops sunxi_rtc_ops = {
408	.read_time		= sunxi_rtc_gettime,
409	.set_time		= sunxi_rtc_settime,
410	.read_alarm		= sunxi_rtc_getalarm,
411	.set_alarm		= sunxi_rtc_setalarm,
412	.alarm_irq_enable	= sunxi_rtc_alarm_irq_enable
413};
414
415static const struct of_device_id sunxi_rtc_dt_ids[] = {
416	{ .compatible = "allwinner,sun4i-a10-rtc", .data = &data_year_param[0] },
417	{ .compatible = "allwinner,sun7i-a20-rtc", .data = &data_year_param[1] },
418	{ /* sentinel */ },
419};
420MODULE_DEVICE_TABLE(of, sunxi_rtc_dt_ids);
421
422static int sunxi_rtc_probe(struct platform_device *pdev)
423{
424	struct sunxi_rtc_dev *chip;
425	struct resource *res;
426	int ret;
427
428	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
429	if (!chip)
430		return -ENOMEM;
431
432	platform_set_drvdata(pdev, chip);
433	chip->dev = &pdev->dev;
434
435	chip->rtc = devm_rtc_allocate_device(&pdev->dev);
436	if (IS_ERR(chip->rtc))
437		return PTR_ERR(chip->rtc);
438
439	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
440	chip->base = devm_ioremap_resource(&pdev->dev, res);
441	if (IS_ERR(chip->base))
442		return PTR_ERR(chip->base);
443
444	chip->irq = platform_get_irq(pdev, 0);
445	if (chip->irq < 0)
446		return chip->irq;
447	ret = devm_request_irq(&pdev->dev, chip->irq, sunxi_rtc_alarmirq,
448			0, dev_name(&pdev->dev), chip);
449	if (ret) {
450		dev_err(&pdev->dev, "Could not request IRQ\n");
451		return ret;
452	}
453
454	chip->data_year = of_device_get_match_data(&pdev->dev);
455	if (!chip->data_year) {
456		dev_err(&pdev->dev, "Unable to setup RTC data\n");
457		return -ENODEV;
458	}
459
460	/* clear the alarm count value */
461	writel(0, chip->base + SUNXI_ALRM_DHMS);
462
463	/* disable alarm, not generate irq pending */
464	writel(0, chip->base + SUNXI_ALRM_EN);
465
466	/* disable alarm week/cnt irq, unset to cpu */
467	writel(0, chip->base + SUNXI_ALRM_IRQ_EN);
468
469	/* clear alarm week/cnt irq pending */
470	writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, chip->base +
471			SUNXI_ALRM_IRQ_STA);
472
473	chip->rtc->ops = &sunxi_rtc_ops;
474
475	return rtc_register_device(chip->rtc);
476}
477
478static struct platform_driver sunxi_rtc_driver = {
479	.probe		= sunxi_rtc_probe,
480	.driver		= {
481		.name		= "sunxi-rtc",
482		.of_match_table = sunxi_rtc_dt_ids,
483	},
484};
485
486module_platform_driver(sunxi_rtc_driver);
487
488MODULE_DESCRIPTION("sunxi RTC driver");
489MODULE_AUTHOR("Carlo Caione <carlo.caione@gmail.com>");
490MODULE_LICENSE("GPL");