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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Xilinx, Inc.
4 *
5 */
6
7#include <linux/err.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/reset-controller.h>
11#include <linux/firmware/xlnx-zynqmp.h>
12
13#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
14#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
15
16struct zynqmp_reset_data {
17 struct reset_controller_dev rcdev;
18};
19
20static inline struct zynqmp_reset_data *
21to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
22{
23 return container_of(rcdev, struct zynqmp_reset_data, rcdev);
24}
25
26static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
27 unsigned long id)
28{
29 return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
30 PM_RESET_ACTION_ASSERT);
31}
32
33static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
34 unsigned long id)
35{
36 return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
37 PM_RESET_ACTION_RELEASE);
38}
39
40static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
41 unsigned long id)
42{
43 int val, err;
44
45 err = zynqmp_pm_reset_get_status(ZYNQMP_RESET_ID + id, &val);
46 if (err)
47 return err;
48
49 return val;
50}
51
52static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
53 unsigned long id)
54{
55 return zynqmp_pm_reset_assert(ZYNQMP_RESET_ID + id,
56 PM_RESET_ACTION_PULSE);
57}
58
59static const struct reset_control_ops zynqmp_reset_ops = {
60 .reset = zynqmp_reset_reset,
61 .assert = zynqmp_reset_assert,
62 .deassert = zynqmp_reset_deassert,
63 .status = zynqmp_reset_status,
64};
65
66static int zynqmp_reset_probe(struct platform_device *pdev)
67{
68 struct zynqmp_reset_data *priv;
69
70 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
71 if (!priv)
72 return -ENOMEM;
73
74 platform_set_drvdata(pdev, priv);
75
76 priv->rcdev.ops = &zynqmp_reset_ops;
77 priv->rcdev.owner = THIS_MODULE;
78 priv->rcdev.of_node = pdev->dev.of_node;
79 priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
80
81 return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
82}
83
84static const struct of_device_id zynqmp_reset_dt_ids[] = {
85 { .compatible = "xlnx,zynqmp-reset", },
86 { /* sentinel */ },
87};
88
89static struct platform_driver zynqmp_reset_driver = {
90 .probe = zynqmp_reset_probe,
91 .driver = {
92 .name = KBUILD_MODNAME,
93 .of_match_table = zynqmp_reset_dt_ids,
94 },
95};
96
97static int __init zynqmp_reset_init(void)
98{
99 return platform_driver_register(&zynqmp_reset_driver);
100}
101
102arch_initcall(zynqmp_reset_init);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Xilinx, Inc.
4 *
5 */
6
7#include <linux/err.h>
8#include <linux/of.h>
9#include <linux/platform_device.h>
10#include <linux/reset-controller.h>
11#include <linux/firmware/xlnx-zynqmp.h>
12
13#define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START)
14#define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START
15
16struct zynqmp_reset_data {
17 struct reset_controller_dev rcdev;
18 const struct zynqmp_eemi_ops *eemi_ops;
19};
20
21static inline struct zynqmp_reset_data *
22to_zynqmp_reset_data(struct reset_controller_dev *rcdev)
23{
24 return container_of(rcdev, struct zynqmp_reset_data, rcdev);
25}
26
27static int zynqmp_reset_assert(struct reset_controller_dev *rcdev,
28 unsigned long id)
29{
30 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
31
32 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
33 PM_RESET_ACTION_ASSERT);
34}
35
36static int zynqmp_reset_deassert(struct reset_controller_dev *rcdev,
37 unsigned long id)
38{
39 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
40
41 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
42 PM_RESET_ACTION_RELEASE);
43}
44
45static int zynqmp_reset_status(struct reset_controller_dev *rcdev,
46 unsigned long id)
47{
48 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
49 int val, err;
50
51 err = priv->eemi_ops->reset_get_status(ZYNQMP_RESET_ID + id, &val);
52 if (err)
53 return err;
54
55 return val;
56}
57
58static int zynqmp_reset_reset(struct reset_controller_dev *rcdev,
59 unsigned long id)
60{
61 struct zynqmp_reset_data *priv = to_zynqmp_reset_data(rcdev);
62
63 return priv->eemi_ops->reset_assert(ZYNQMP_RESET_ID + id,
64 PM_RESET_ACTION_PULSE);
65}
66
67static struct reset_control_ops zynqmp_reset_ops = {
68 .reset = zynqmp_reset_reset,
69 .assert = zynqmp_reset_assert,
70 .deassert = zynqmp_reset_deassert,
71 .status = zynqmp_reset_status,
72};
73
74static int zynqmp_reset_probe(struct platform_device *pdev)
75{
76 struct zynqmp_reset_data *priv;
77
78 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
79 if (!priv)
80 return -ENOMEM;
81
82 priv->eemi_ops = zynqmp_pm_get_eemi_ops();
83 if (IS_ERR(priv->eemi_ops))
84 return PTR_ERR(priv->eemi_ops);
85
86 platform_set_drvdata(pdev, priv);
87
88 priv->rcdev.ops = &zynqmp_reset_ops;
89 priv->rcdev.owner = THIS_MODULE;
90 priv->rcdev.of_node = pdev->dev.of_node;
91 priv->rcdev.nr_resets = ZYNQMP_NR_RESETS;
92
93 return devm_reset_controller_register(&pdev->dev, &priv->rcdev);
94}
95
96static const struct of_device_id zynqmp_reset_dt_ids[] = {
97 { .compatible = "xlnx,zynqmp-reset", },
98 { /* sentinel */ },
99};
100
101static struct platform_driver zynqmp_reset_driver = {
102 .probe = zynqmp_reset_probe,
103 .driver = {
104 .name = KBUILD_MODNAME,
105 .of_match_table = zynqmp_reset_dt_ids,
106 },
107};
108
109static int __init zynqmp_reset_init(void)
110{
111 return platform_driver_register(&zynqmp_reset_driver);
112}
113
114arch_initcall(zynqmp_reset_init);