1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
   4 * Copyright (C) 2015 Google, Inc.
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/clk/tegra.h>
   9#include <linux/delay.h>
  10#include <linux/io.h>
  11#include <linux/mailbox_client.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/phy/phy.h>
  15#include <linux/platform_device.h>
  16#include <linux/regulator/consumer.h>
  17#include <linux/reset.h>
  18#include <linux/slab.h>
  19
  20#include <soc/tegra/fuse.h>
  21
  22#include "xusb.h"
  23
  24#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(x) \
  25					((x) ? (11 + ((x) - 1) * 6) : 0)
  26#define FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK 0x3f
  27#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT 7
  28#define FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK 0xf
  29
  30#define FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT 0
  31#define FUSE_USB_CALIB_EXT_RPD_CTRL_MASK 0x1f
  32
  33#define XUSB_PADCTL_USB2_PAD_MUX 0x004
  34#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT 16
  35#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK 0x3
  36#define XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB 0x1
  37#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT 18
  38#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK 0x3
  39#define XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB 0x1
  40
  41#define XUSB_PADCTL_USB2_PORT_CAP 0x008
  42#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(x) (0x0 << ((x) * 4))
  43#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(x) (0x1 << ((x) * 4))
  44#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(x) (0x2 << ((x) * 4))
  45#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(x) (0x3 << ((x) * 4))
  46#define XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(x) (0x3 << ((x) * 4))
  47
  48#define XUSB_PADCTL_SS_PORT_MAP 0x014
  49#define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
  50#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_SHIFT(x) ((x) * 5)
  51#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(x) (0x7 << ((x) * 5))
  52#define XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(x, v) (((v) & 0x7) << ((x) * 5))
  53#define XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED 0x7
  54
  55#define XUSB_PADCTL_ELPG_PROGRAM1 0x024
  56#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
  57#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
  58#define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
  59#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
  60#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(x) \
  61							(1 << (1 + (x) * 3))
  62#define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(x) (1 << ((x) * 3))
  63
  64#define XUSB_PADCTL_USB3_PAD_MUX 0x028
  65#define XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(x) (1 << (1 + (x)))
  66#define XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(x) (1 << (8 + (x)))
  67
  68#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(x) (0x080 + (x) * 0x40)
  69#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP (1 << 18)
  70#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN (1 << 22)
  71
  72#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(x) (0x084 + (x) * 0x40)
  73#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT 7
  74#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK 0x3
  75#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL 0x1
  76#define XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18 (1 << 6)
  77
  78#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x088 + (x) * 0x40)
  79#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI (1 << 29)
  80#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 (1 << 27)
  81#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD (1 << 26)
  82#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT 0
  83#define XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK 0x3f
  84
  85#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x08c + (x) * 0x40)
  86#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT 26
  87#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK 0x1f
  88#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT 3
  89#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK 0xf
  90#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR (1 << 2)
  91#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD (1 << 1)
  92#define XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD (1 << 0)
  93
  94#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
  95#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD (1 << 11)
  96#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT 3
  97#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK 0x7
  98#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL 0x7
  99#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT 0
 100#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK 0x7
 101#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL 0x2
 102
 103#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
 104#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK (1 << 26)
 105#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT 19
 106#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK 0x7f
 107#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL 0x0a
 108#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT 12
 109#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK 0x7f
 110#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL 0x1e
 111
 112#define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
 113#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE (1 << 18)
 114#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 (1 << 17)
 115#define XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 (1 << 16)
 116#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE (1 << 15)
 117#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 (1 << 14)
 118#define XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 (1 << 13)
 119#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE (1 << 9)
 120#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 (1 << 8)
 121#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 (1 << 7)
 122#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE (1 << 6)
 123#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 (1 << 5)
 124#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 (1 << 4)
 125#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE (1 << 3)
 126#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 (1 << 2)
 127#define XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 (1 << 1)
 128
 129#define XUSB_PADCTL_HSIC_PADX_CTL1(x) (0x304 + (x) * 0x20)
 130#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT 0
 131#define XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK 0xf
 132
 133#define XUSB_PADCTL_HSIC_PADX_CTL2(x) (0x308 + (x) * 0x20)
 134#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT 8
 135#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK 0xf
 136#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT 0
 137#define XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK 0xff
 138
 139#define XUSB_PADCTL_HSIC_PAD_TRK_CTL 0x340
 140#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK (1 << 19)
 141#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT 12
 142#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK 0x7f
 143#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL 0x0a
 144#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT 5
 145#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK 0x7f
 146#define XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL 0x1e
 147
 148#define XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL 0x344
 149
 150#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
 151#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT 20
 152#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK 0xff
 153#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL 0x19
 154#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL 0x1e
 155#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT 16
 156#define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3
 157#define XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS (1 << 15)
 158#define XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD (1 << 4)
 159#define XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE (1 << 3)
 160#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT 1
 161#define XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK 0x3
 162#define XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ (1 << 0)
 163
 164#define XUSB_PADCTL_UPHY_PLL_P0_CTL2 0x364
 165#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT 4
 166#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK 0xffffff
 167#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL 0x136
 168#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD (1 << 2)
 169#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE (1 << 1)
 170#define XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN (1 << 0)
 171
 172#define XUSB_PADCTL_UPHY_PLL_P0_CTL4 0x36c
 173#define XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN (1 << 19)
 174#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN (1 << 15)
 175#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT 12
 176#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK 0x3
 177#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL 0x2
 178#define XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL 0x0
 179#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN (1 << 8)
 180#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT 4
 181#define XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK 0xf
 182
 183#define XUSB_PADCTL_UPHY_PLL_P0_CTL5 0x370
 184#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT 16
 185#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK 0xff
 186#define XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL 0x2a
 187
 188#define XUSB_PADCTL_UPHY_PLL_P0_CTL8 0x37c
 189#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE (1 << 31)
 190#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD (1 << 15)
 191#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN (1 << 13)
 192#define XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN (1 << 12)
 193
 194#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(x) (0x460 + (x) * 0x40)
 195#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT 20
 196#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK 0x3
 197#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL 0x1
 198#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN BIT(18)
 199#define XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD BIT(13)
 200
 201#define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
 202
 203#define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
 204
 205#define XUSB_PADCTL_UPHY_PLL_S0_CTL4 0x86c
 206
 207#define XUSB_PADCTL_UPHY_PLL_S0_CTL5 0x870
 208
 209#define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
 210
 211#define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
 212
 213#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(x) (0xa60 + (x) * 0x40)
 214#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT 16
 215#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK 0x3
 216#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL 0x2
 217
 218#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(x) (0xa64 + (x) * 0x40)
 219#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT 0
 220#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK 0xffff
 221#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL 0x00fc
 222
 223#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(x) (0xa68 + (x) * 0x40)
 224#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL 0xc0077f1f
 225
 226#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(x) (0xa6c + (x) * 0x40)
 227#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT 16
 228#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK 0xffff
 229#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL 0x01c7
 230
 231#define XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(x) (0xa74 + (x) * 0x40)
 232#define XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL 0xfcf01368
 233
 234#define XUSB_PADCTL_USB2_VBUS_ID 0xc60
 235#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON (1 << 14)
 236#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT 18
 237#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK 0xf
 238#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING 8
 239#define XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED 0
 240
 241struct tegra210_xusb_fuse_calibration {
 242	u32 hs_curr_level[4];
 243	u32 hs_term_range_adj;
 244	u32 rpd_ctrl;
 245};
 246
 247struct tegra210_xusb_padctl {
 248	struct tegra_xusb_padctl base;
 249
 250	struct tegra210_xusb_fuse_calibration fuse;
 251};
 252
 253static inline struct tegra210_xusb_padctl *
 254to_tegra210_xusb_padctl(struct tegra_xusb_padctl *padctl)
 255{
 256	return container_of(padctl, struct tegra210_xusb_padctl, base);
 257}
 258
 259/* must be called under padctl->lock */
 260static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 261{
 262	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
 263	unsigned long timeout;
 264	u32 value;
 265	int err;
 266
 267	if (pcie->enable > 0) {
 268		pcie->enable++;
 269		return 0;
 270	}
 271
 272	err = clk_prepare_enable(pcie->pll);
 273	if (err < 0)
 274		return err;
 275
 276	err = reset_control_deassert(pcie->rst);
 277	if (err < 0)
 278		goto disable;
 279
 280	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 281	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
 282		   XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
 283	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
 284		 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
 285	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 286
 287	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 288	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
 289		   XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
 290	value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
 291		 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
 292	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5);
 293
 294	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 295	value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 296	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 297
 298	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 299	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 300	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 301
 302	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 303	value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 304	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 305
 306	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 307	value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
 308		    XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 309		   (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
 310		    XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
 311	value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
 312		  XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 313		 XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
 314	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 315
 316	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 317	value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
 318		    XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
 319		   (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
 320		    XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
 321	value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
 322		 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 323	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 324
 325	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 326	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
 327	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 328
 329	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 330	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
 331		   XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
 332	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 333
 334	usleep_range(10, 20);
 335
 336	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 337	value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
 338	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL4);
 339
 340	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 341	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 342	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 343
 344	timeout = jiffies + msecs_to_jiffies(100);
 345
 346	while (time_before(jiffies, timeout)) {
 347		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 348		if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
 349			break;
 350
 351		usleep_range(10, 20);
 352	}
 353
 354	if (time_after_eq(jiffies, timeout)) {
 355		err = -ETIMEDOUT;
 356		goto reset;
 357	}
 358
 359	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 360	value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 361	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 362
 363	timeout = jiffies + msecs_to_jiffies(100);
 364
 365	while (time_before(jiffies, timeout)) {
 366		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 367		if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
 368			break;
 369
 370		usleep_range(10, 20);
 371	}
 372
 373	if (time_after_eq(jiffies, timeout)) {
 374		err = -ETIMEDOUT;
 375		goto reset;
 376	}
 377
 378	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 379	value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
 380	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 381
 382	timeout = jiffies + msecs_to_jiffies(100);
 383
 384	while (time_before(jiffies, timeout)) {
 385		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 386		if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
 387			break;
 388
 389		usleep_range(10, 20);
 390	}
 391
 392	if (time_after_eq(jiffies, timeout)) {
 393		err = -ETIMEDOUT;
 394		goto reset;
 395	}
 396
 397	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 398	value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
 399		 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 400	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 401
 402	timeout = jiffies + msecs_to_jiffies(100);
 403
 404	while (time_before(jiffies, timeout)) {
 405		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 406		if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
 407			break;
 408
 409		usleep_range(10, 20);
 410	}
 411
 412	if (time_after_eq(jiffies, timeout)) {
 413		err = -ETIMEDOUT;
 414		goto reset;
 415	}
 416
 417	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 418	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
 419	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 420
 421	timeout = jiffies + msecs_to_jiffies(100);
 422
 423	while (time_before(jiffies, timeout)) {
 424		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 425		if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
 426			break;
 427
 428		usleep_range(10, 20);
 429	}
 430
 431	if (time_after_eq(jiffies, timeout)) {
 432		err = -ETIMEDOUT;
 433		goto reset;
 434	}
 435
 436	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 437	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 438	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 439
 440	tegra210_xusb_pll_hw_control_enable();
 441
 442	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 443	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 444	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 445
 446	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 447	value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 448	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 449
 450	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 451	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 452	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 453
 454	usleep_range(10, 20);
 455
 456	tegra210_xusb_pll_hw_sequence_start();
 457
 458	pcie->enable++;
 459
 460	return 0;
 461
 462reset:
 463	reset_control_assert(pcie->rst);
 464disable:
 465	clk_disable_unprepare(pcie->pll);
 466	return err;
 467}
 468
 469static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
 470{
 471	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(padctl->pcie);
 472
 473	mutex_lock(&padctl->lock);
 474
 475	if (WARN_ON(pcie->enable == 0))
 476		goto unlock;
 477
 478	if (--pcie->enable > 0)
 479		goto unlock;
 480
 481	reset_control_assert(pcie->rst);
 482	clk_disable_unprepare(pcie->pll);
 483
 484unlock:
 485	mutex_unlock(&padctl->lock);
 486}
 487
 488/* must be called under padctl->lock */
 489static int tegra210_sata_uphy_enable(struct tegra_xusb_padctl *padctl, bool usb)
 490{
 491	struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
 492	unsigned long timeout;
 493	u32 value;
 494	int err;
 495
 496	if (sata->enable > 0) {
 497		sata->enable++;
 498		return 0;
 499	}
 500
 501	err = clk_prepare_enable(sata->pll);
 502	if (err < 0)
 503		return err;
 504
 505	err = reset_control_deassert(sata->rst);
 506	if (err < 0)
 507		goto disable;
 508
 509	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 510	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
 511		   XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
 512	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL <<
 513		 XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT;
 514	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 515
 516	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
 517	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK <<
 518		   XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT);
 519	value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL <<
 520		 XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_SHIFT;
 521	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL5);
 522
 523	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 524	value |= XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 525	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 526
 527	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 528	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 529	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 530
 531	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 532	value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 533	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 534
 535	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 536	value &= ~((XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_MASK <<
 537		    XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT) |
 538		   (XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_MASK <<
 539		    XUSB_PADCTL_UPHY_PLL_CTL4_REFCLK_SEL_SHIFT));
 540	value |= XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_EN;
 541
 542	if (usb)
 543		value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_USB_VAL <<
 544			  XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
 545	else
 546		value |= (XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SATA_VAL <<
 547			  XUSB_PADCTL_UPHY_PLL_CTL4_TXCLKREF_SEL_SHIFT);
 548
 549	value &= ~XUSB_PADCTL_UPHY_PLL_CTL4_XDIGCLK_EN;
 550	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 551
 552	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 553	value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK <<
 554		    XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_SHIFT) |
 555		   (XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_MASK <<
 556		    XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT));
 557
 558	if (usb)
 559		value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_USB_VAL <<
 560			 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 561	else
 562		value |= XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SATA_VAL <<
 563			 XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_NDIV_SHIFT;
 564
 565	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 566
 567	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 568	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_IDDQ;
 569	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 570
 571	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 572	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_MASK <<
 573		   XUSB_PADCTL_UPHY_PLL_CTL1_SLEEP_SHIFT);
 574	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 575
 576	usleep_range(10, 20);
 577
 578	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 579	value |= XUSB_PADCTL_UPHY_PLL_CTL4_REFCLKBUF_EN;
 580	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL4);
 581
 582	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 583	value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 584	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 585
 586	timeout = jiffies + msecs_to_jiffies(100);
 587
 588	while (time_before(jiffies, timeout)) {
 589		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 590		if (value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE)
 591			break;
 592
 593		usleep_range(10, 20);
 594	}
 595
 596	if (time_after_eq(jiffies, timeout)) {
 597		err = -ETIMEDOUT;
 598		goto reset;
 599	}
 600
 601	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 602	value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_EN;
 603	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 604
 605	timeout = jiffies + msecs_to_jiffies(100);
 606
 607	while (time_before(jiffies, timeout)) {
 608		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 609		if (!(value & XUSB_PADCTL_UPHY_PLL_CTL2_CAL_DONE))
 610			break;
 611
 612		usleep_range(10, 20);
 613	}
 614
 615	if (time_after_eq(jiffies, timeout)) {
 616		err = -ETIMEDOUT;
 617		goto reset;
 618	}
 619
 620	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 621	value |= XUSB_PADCTL_UPHY_PLL_CTL1_ENABLE;
 622	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 623
 624	timeout = jiffies + msecs_to_jiffies(100);
 625
 626	while (time_before(jiffies, timeout)) {
 627		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 628		if (value & XUSB_PADCTL_UPHY_PLL_CTL1_LOCKDET_STATUS)
 629			break;
 630
 631		usleep_range(10, 20);
 632	}
 633
 634	if (time_after_eq(jiffies, timeout)) {
 635		err = -ETIMEDOUT;
 636		goto reset;
 637	}
 638
 639	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 640	value |= XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN |
 641		 XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 642	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 643
 644	timeout = jiffies + msecs_to_jiffies(100);
 645
 646	while (time_before(jiffies, timeout)) {
 647		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 648		if (value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE)
 649			break;
 650
 651		usleep_range(10, 20);
 652	}
 653
 654	if (time_after_eq(jiffies, timeout)) {
 655		err = -ETIMEDOUT;
 656		goto reset;
 657	}
 658
 659	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 660	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_EN;
 661	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 662
 663	timeout = jiffies + msecs_to_jiffies(100);
 664
 665	while (time_before(jiffies, timeout)) {
 666		value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 667		if (!(value & XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_DONE))
 668			break;
 669
 670		usleep_range(10, 20);
 671	}
 672
 673	if (time_after_eq(jiffies, timeout)) {
 674		err = -ETIMEDOUT;
 675		goto reset;
 676	}
 677
 678	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 679	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 680	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 681
 682	tegra210_sata_pll_hw_control_enable();
 683
 684	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 685	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
 686	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL1);
 687
 688	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 689	value &= ~XUSB_PADCTL_UPHY_PLL_CTL2_CAL_OVRD;
 690	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL2);
 691
 692	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 693	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_OVRD;
 694	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_S0_CTL8);
 695
 696	usleep_range(10, 20);
 697
 698	tegra210_sata_pll_hw_sequence_start();
 699
 700	sata->enable++;
 701
 702	return 0;
 703
 704reset:
 705	reset_control_assert(sata->rst);
 706disable:
 707	clk_disable_unprepare(sata->pll);
 708	return err;
 709}
 710
 711static void tegra210_sata_uphy_disable(struct tegra_xusb_padctl *padctl)
 712{
 713	struct tegra_xusb_sata_pad *sata = to_sata_pad(padctl->sata);
 714
 715	mutex_lock(&padctl->lock);
 716
 717	if (WARN_ON(sata->enable == 0))
 718		goto unlock;
 719
 720	if (--sata->enable > 0)
 721		goto unlock;
 722
 723	reset_control_assert(sata->rst);
 724	clk_disable_unprepare(sata->pll);
 725
 726unlock:
 727	mutex_unlock(&padctl->lock);
 728}
 729
 730static int tegra210_xusb_padctl_enable(struct tegra_xusb_padctl *padctl)
 731{
 732	u32 value;
 733
 734	mutex_lock(&padctl->lock);
 735
 736	if (padctl->enable++ > 0)
 737		goto out;
 738
 739	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 740	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
 741	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 742
 743	usleep_range(100, 200);
 744
 745	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 746	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
 747	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 748
 749	usleep_range(100, 200);
 750
 751	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 752	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
 753	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 754
 755out:
 756	mutex_unlock(&padctl->lock);
 757	return 0;
 758}
 759
 760static int tegra210_xusb_padctl_disable(struct tegra_xusb_padctl *padctl)
 761{
 762	u32 value;
 763
 764	mutex_lock(&padctl->lock);
 765
 766	if (WARN_ON(padctl->enable == 0))
 767		goto out;
 768
 769	if (--padctl->enable > 0)
 770		goto out;
 771
 772	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 773	value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN;
 774	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 775
 776	usleep_range(100, 200);
 777
 778	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 779	value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY;
 780	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 781
 782	usleep_range(100, 200);
 783
 784	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
 785	value |= XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN;
 786	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
 787
 788out:
 789	mutex_unlock(&padctl->lock);
 790	return 0;
 791}
 792
 793static int tegra210_hsic_set_idle(struct tegra_xusb_padctl *padctl,
 794				  unsigned int index, bool idle)
 795{
 796	u32 value;
 797
 798	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
 799
 800	value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
 801		   XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
 802		   XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE);
 803
 804	if (idle)
 805		value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
 806			 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
 807			 XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE;
 808	else
 809		value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
 810			   XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
 811			   XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE);
 812
 813	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
 814
 815	return 0;
 816}
 817
 818static int tegra210_usb3_set_lfps_detect(struct tegra_xusb_padctl *padctl,
 819					 unsigned int index, bool enable)
 820{
 821	struct tegra_xusb_port *port;
 822	struct tegra_xusb_lane *lane;
 823	u32 value, offset;
 824
 825	port = tegra_xusb_find_port(padctl, "usb3", index);
 826	if (!port)
 827		return -ENODEV;
 828
 829	lane = port->lane;
 830
 831	if (lane->pad == padctl->pcie)
 832		offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);
 833	else
 834		offset = XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1;
 835
 836	value = padctl_readl(padctl, offset);
 837
 838	value &= ~((XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_MASK <<
 839		    XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
 840		   XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
 841		   XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD);
 842
 843	if (!enable) {
 844		value |= (XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_VAL <<
 845			  XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_IDLE_MODE_SHIFT) |
 846			 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_TERM_EN |
 847			 XUSB_PADCTL_UPHY_MISC_PAD_CTL1_AUX_RX_MODE_OVRD;
 848	}
 849
 850	padctl_writel(padctl, value, offset);
 851
 852	return 0;
 853}
 854
 855#define TEGRA210_LANE(_name, _offset, _shift, _mask, _type)		\
 856	{								\
 857		.name = _name,						\
 858		.offset = _offset,					\
 859		.shift = _shift,					\
 860		.mask = _mask,						\
 861		.num_funcs = ARRAY_SIZE(tegra210_##_type##_functions),	\
 862		.funcs = tegra210_##_type##_functions,			\
 863	}
 864
 865static const char *tegra210_usb2_functions[] = {
 866	"snps",
 867	"xusb",
 868	"uart"
 869};
 870
 871static const struct tegra_xusb_lane_soc tegra210_usb2_lanes[] = {
 872	TEGRA210_LANE("usb2-0", 0x004,  0, 0x3, usb2),
 873	TEGRA210_LANE("usb2-1", 0x004,  2, 0x3, usb2),
 874	TEGRA210_LANE("usb2-2", 0x004,  4, 0x3, usb2),
 875	TEGRA210_LANE("usb2-3", 0x004,  6, 0x3, usb2),
 876};
 877
 878static struct tegra_xusb_lane *
 879tegra210_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
 880			 unsigned int index)
 881{
 882	struct tegra_xusb_usb2_lane *usb2;
 883	int err;
 884
 885	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
 886	if (!usb2)
 887		return ERR_PTR(-ENOMEM);
 888
 889	INIT_LIST_HEAD(&usb2->base.list);
 890	usb2->base.soc = &pad->soc->lanes[index];
 891	usb2->base.index = index;
 892	usb2->base.pad = pad;
 893	usb2->base.np = np;
 894
 895	err = tegra_xusb_lane_parse_dt(&usb2->base, np);
 896	if (err < 0) {
 897		kfree(usb2);
 898		return ERR_PTR(err);
 899	}
 900
 901	return &usb2->base;
 902}
 903
 904static void tegra210_usb2_lane_remove(struct tegra_xusb_lane *lane)
 905{
 906	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
 907
 908	kfree(usb2);
 909}
 910
 911static const struct tegra_xusb_lane_ops tegra210_usb2_lane_ops = {
 912	.probe = tegra210_usb2_lane_probe,
 913	.remove = tegra210_usb2_lane_remove,
 914};
 915
 916static int tegra210_usb2_phy_init(struct phy *phy)
 917{
 918	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 919	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 920	u32 value;
 921
 922	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
 923	value &= ~(XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_MASK <<
 924		   XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT);
 925	value |= XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_XUSB <<
 926		 XUSB_PADCTL_USB2_PAD_MUX_USB2_BIAS_PAD_SHIFT;
 927	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
 928
 929	return tegra210_xusb_padctl_enable(padctl);
 930}
 931
 932static int tegra210_usb2_phy_exit(struct phy *phy)
 933{
 934	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 935
 936	return tegra210_xusb_padctl_disable(lane->pad->padctl);
 937}
 938
 939static int tegra210_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
 940					      bool status)
 941{
 942	u32 value;
 943
 944	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
 945
 946	value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
 947
 948	if (status) {
 949		value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
 950		value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
 951			   XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
 952		value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
 953			 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
 954	} else {
 955		value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
 956	}
 957
 958	padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
 959
 960	return 0;
 961}
 962
 963static int tegra210_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
 964					    bool status)
 965{
 966	u32 value;
 967
 968	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
 969
 970	value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
 971
 972	if (status) {
 973		if (value & XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON) {
 974			value &= ~XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_VBUS_ON;
 975			padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
 976			usleep_range(1000, 2000);
 977
 978			value = padctl_readl(padctl, XUSB_PADCTL_USB2_VBUS_ID);
 979		}
 980
 981		value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
 982			   XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
 983		value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_GROUNDED <<
 984			 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
 985	} else {
 986		value &= ~(XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_MASK <<
 987			   XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT);
 988		value |= XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_FLOATING <<
 989			 XUSB_PADCTL_USB2_VBUS_ID_OVERRIDE_SHIFT;
 990	}
 991
 992	padctl_writel(padctl, value, XUSB_PADCTL_USB2_VBUS_ID);
 993
 994	return 0;
 995}
 996
 997static int tegra210_usb2_phy_set_mode(struct phy *phy, enum phy_mode mode,
 998				      int submode)
 999{
1000	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1001	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1002	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
1003								lane->index);
1004	int err = 0;
1005
1006	mutex_lock(&padctl->lock);
1007
1008	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
1009
1010	if (mode == PHY_MODE_USB_OTG) {
1011		if (submode == USB_ROLE_HOST) {
1012			tegra210_xusb_padctl_id_override(padctl, true);
1013
1014			err = regulator_enable(port->supply);
1015		} else if (submode == USB_ROLE_DEVICE) {
1016			tegra210_xusb_padctl_vbus_override(padctl, true);
1017		} else if (submode == USB_ROLE_NONE) {
1018			/*
1019			 * When port is peripheral only or role transitions to
1020			 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
1021			 * be enabled.
1022			 */
1023			if (regulator_is_enabled(port->supply))
1024				regulator_disable(port->supply);
1025
1026			tegra210_xusb_padctl_id_override(padctl, false);
1027			tegra210_xusb_padctl_vbus_override(padctl, false);
1028		}
1029	}
1030
1031	mutex_unlock(&padctl->lock);
1032
1033	return err;
1034}
1035
1036static int tegra210_usb2_phy_power_on(struct phy *phy)
1037{
1038	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1039	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
1040	struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
1041	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1042	struct tegra210_xusb_padctl *priv;
1043	struct tegra_xusb_usb2_port *port;
1044	unsigned int index = lane->index;
1045	u32 value;
1046	int err;
1047
1048	port = tegra_xusb_find_usb2_port(padctl, index);
1049	if (!port) {
1050		dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
1051		return -ENODEV;
1052	}
1053
1054	priv = to_tegra210_xusb_padctl(padctl);
1055
1056	if (port->usb3_port_fake != -1) {
1057		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1058		value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(
1059					port->usb3_port_fake);
1060		value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(
1061					port->usb3_port_fake, index);
1062		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1063
1064		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1065		value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1066					port->usb3_port_fake);
1067		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1068
1069		usleep_range(100, 200);
1070
1071		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1072		value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1073					port->usb3_port_fake);
1074		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1075
1076		usleep_range(100, 200);
1077
1078		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1079		value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1080					port->usb3_port_fake);
1081		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1082	}
1083
1084	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1085	value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_MASK <<
1086		    XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT) |
1087		   (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_MASK <<
1088		    XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT));
1089	value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_VAL <<
1090		  XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_DISCON_LEVEL_SHIFT);
1091
1092	if (tegra_sku_info.revision < TEGRA_REVISION_A02)
1093		value |=
1094			(XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_VAL <<
1095			XUSB_PADCTL_USB2_BIAS_PAD_CTL0_HS_SQUELCH_LEVEL_SHIFT);
1096
1097	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1098
1099	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1100	value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
1101	if (port->mode == USB_DR_MODE_UNKNOWN)
1102		value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
1103	else if (port->mode == USB_DR_MODE_PERIPHERAL)
1104		value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
1105	else if (port->mode == USB_DR_MODE_HOST)
1106		value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
1107	else if (port->mode == USB_DR_MODE_OTG)
1108		value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
1109	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
1110
1111	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1112	value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_MASK <<
1113		    XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT) |
1114		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD |
1115		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD2 |
1116		   XUSB_PADCTL_USB2_OTG_PAD_CTL0_PD_ZI);
1117	value |= (priv->fuse.hs_curr_level[index] +
1118		  usb2->hs_curr_level_offset) <<
1119		 XUSB_PADCTL_USB2_OTG_PAD_CTL0_HS_CURR_LEVEL_SHIFT;
1120	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1121
1122	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1123	value &= ~((XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_MASK <<
1124		    XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
1125		   (XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_MASK <<
1126		    XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT) |
1127		   XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DR |
1128		   XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_CHRP_OVRD |
1129		   XUSB_PADCTL_USB2_OTG_PAD_CTL1_PD_DISC_OVRD);
1130	value |= (priv->fuse.hs_term_range_adj <<
1131		  XUSB_PADCTL_USB2_OTG_PAD_CTL1_TERM_RANGE_ADJ_SHIFT) |
1132		 (priv->fuse.rpd_ctrl <<
1133		  XUSB_PADCTL_USB2_OTG_PAD_CTL1_RPD_CTRL_SHIFT);
1134	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1135
1136	value = padctl_readl(padctl,
1137			     XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1138	value &= ~(XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_MASK <<
1139		   XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT);
1140	if (port->mode == USB_DR_MODE_HOST)
1141		value |= XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_FIX18;
1142	else
1143		value |=
1144		      XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_VAL <<
1145		      XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL1_VREG_LEV_SHIFT;
1146	padctl_writel(padctl, value,
1147		      XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1148
1149	if (port->supply && port->mode == USB_DR_MODE_HOST) {
1150		err = regulator_enable(port->supply);
1151		if (err)
1152			return err;
1153	}
1154
1155	mutex_lock(&padctl->lock);
1156
1157	if (pad->enable > 0) {
1158		pad->enable++;
1159		mutex_unlock(&padctl->lock);
1160		return 0;
1161	}
1162
1163	err = clk_prepare_enable(pad->clk);
1164	if (err)
1165		goto disable_regulator;
1166
1167	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1168	value &= ~((XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_MASK <<
1169		    XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1170		   (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_MASK <<
1171		    XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT));
1172	value |= (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_VAL <<
1173		  XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_START_TIMER_SHIFT) |
1174		 (XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_VAL <<
1175		  XUSB_PADCTL_USB2_BIAS_PAD_CTL1_TRK_DONE_RESET_TIMER_SHIFT);
1176	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1177
1178	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1179	value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1180	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1181
1182	udelay(1);
1183
1184	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1185	value &= ~XUSB_PADCTL_USB2_BIAS_PAD_CTL1_PD_TRK;
1186	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
1187
1188	udelay(50);
1189
1190	clk_disable_unprepare(pad->clk);
1191
1192	pad->enable++;
1193	mutex_unlock(&padctl->lock);
1194
1195	return 0;
1196
1197disable_regulator:
1198	regulator_disable(port->supply);
1199	mutex_unlock(&padctl->lock);
1200	return err;
1201}
1202
1203static int tegra210_usb2_phy_power_off(struct phy *phy)
1204{
1205	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1206	struct tegra_xusb_usb2_pad *pad = to_usb2_pad(lane->pad);
1207	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1208	struct tegra_xusb_usb2_port *port;
1209	u32 value;
1210
1211	port = tegra_xusb_find_usb2_port(padctl, lane->index);
1212	if (!port) {
1213		dev_err(&phy->dev, "no port found for USB2 lane %u\n",
1214			lane->index);
1215		return -ENODEV;
1216	}
1217
1218	mutex_lock(&padctl->lock);
1219
1220	if (port->usb3_port_fake != -1) {
1221		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1222		value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(
1223					port->usb3_port_fake);
1224		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1225
1226		usleep_range(100, 200);
1227
1228		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1229		value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(
1230					port->usb3_port_fake);
1231		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1232
1233		usleep_range(250, 350);
1234
1235		value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
1236		value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(
1237					port->usb3_port_fake);
1238		padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
1239
1240		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1241		value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(port->usb3_port_fake,
1242					XUSB_PADCTL_SS_PORT_MAP_PORT_DISABLED);
1243		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
1244	}
1245
1246	if (WARN_ON(pad->enable == 0))
1247		goto out;
1248
1249	if (--pad->enable > 0)
1250		goto out;
1251
1252	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1253	value |= XUSB_PADCTL_USB2_BIAS_PAD_CTL0_PD;
1254	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
1255
1256out:
1257	regulator_disable(port->supply);
1258	mutex_unlock(&padctl->lock);
1259	return 0;
1260}
1261
1262static const struct phy_ops tegra210_usb2_phy_ops = {
1263	.init = tegra210_usb2_phy_init,
1264	.exit = tegra210_usb2_phy_exit,
1265	.power_on = tegra210_usb2_phy_power_on,
1266	.power_off = tegra210_usb2_phy_power_off,
1267	.set_mode = tegra210_usb2_phy_set_mode,
1268	.owner = THIS_MODULE,
1269};
1270
1271static struct tegra_xusb_pad *
1272tegra210_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1273			const struct tegra_xusb_pad_soc *soc,
1274			struct device_node *np)
1275{
1276	struct tegra_xusb_usb2_pad *usb2;
1277	struct tegra_xusb_pad *pad;
1278	int err;
1279
1280	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1281	if (!usb2)
1282		return ERR_PTR(-ENOMEM);
1283
1284	pad = &usb2->base;
1285	pad->ops = &tegra210_usb2_lane_ops;
1286	pad->soc = soc;
1287
1288	err = tegra_xusb_pad_init(pad, padctl, np);
1289	if (err < 0) {
1290		kfree(usb2);
1291		goto out;
1292	}
1293
1294	usb2->clk = devm_clk_get(&pad->dev, "trk");
1295	if (IS_ERR(usb2->clk)) {
1296		err = PTR_ERR(usb2->clk);
1297		dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1298		goto unregister;
1299	}
1300
1301	err = tegra_xusb_pad_register(pad, &tegra210_usb2_phy_ops);
1302	if (err < 0)
1303		goto unregister;
1304
1305	dev_set_drvdata(&pad->dev, pad);
1306
1307	return pad;
1308
1309unregister:
1310	device_unregister(&pad->dev);
1311out:
1312	return ERR_PTR(err);
1313}
1314
1315static void tegra210_usb2_pad_remove(struct tegra_xusb_pad *pad)
1316{
1317	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1318
1319	kfree(usb2);
1320}
1321
1322static const struct tegra_xusb_pad_ops tegra210_usb2_ops = {
1323	.probe = tegra210_usb2_pad_probe,
1324	.remove = tegra210_usb2_pad_remove,
1325};
1326
1327static const struct tegra_xusb_pad_soc tegra210_usb2_pad = {
1328	.name = "usb2",
1329	.num_lanes = ARRAY_SIZE(tegra210_usb2_lanes),
1330	.lanes = tegra210_usb2_lanes,
1331	.ops = &tegra210_usb2_ops,
1332};
1333
1334static const char *tegra210_hsic_functions[] = {
1335	"snps",
1336	"xusb",
1337};
1338
1339static const struct tegra_xusb_lane_soc tegra210_hsic_lanes[] = {
1340	TEGRA210_LANE("hsic-0", 0x004, 14, 0x1, hsic),
1341};
1342
1343static struct tegra_xusb_lane *
1344tegra210_hsic_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1345			 unsigned int index)
1346{
1347	struct tegra_xusb_hsic_lane *hsic;
1348	int err;
1349
1350	hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1351	if (!hsic)
1352		return ERR_PTR(-ENOMEM);
1353
1354	INIT_LIST_HEAD(&hsic->base.list);
1355	hsic->base.soc = &pad->soc->lanes[index];
1356	hsic->base.index = index;
1357	hsic->base.pad = pad;
1358	hsic->base.np = np;
1359
1360	err = tegra_xusb_lane_parse_dt(&hsic->base, np);
1361	if (err < 0) {
1362		kfree(hsic);
1363		return ERR_PTR(err);
1364	}
1365
1366	return &hsic->base;
1367}
1368
1369static void tegra210_hsic_lane_remove(struct tegra_xusb_lane *lane)
1370{
1371	struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1372
1373	kfree(hsic);
1374}
1375
1376static const struct tegra_xusb_lane_ops tegra210_hsic_lane_ops = {
1377	.probe = tegra210_hsic_lane_probe,
1378	.remove = tegra210_hsic_lane_remove,
1379};
1380
1381static int tegra210_hsic_phy_init(struct phy *phy)
1382{
1383	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1384	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1385	u32 value;
1386
1387	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1388	value &= ~(XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_MASK <<
1389		   XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT);
1390	value |= XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_XUSB <<
1391		 XUSB_PADCTL_USB2_PAD_MUX_HSIC_PAD_TRK_SHIFT;
1392	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
1393
1394	return tegra210_xusb_padctl_enable(padctl);
1395}
1396
1397static int tegra210_hsic_phy_exit(struct phy *phy)
1398{
1399	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1400
1401	return tegra210_xusb_padctl_disable(lane->pad->padctl);
1402}
1403
1404static int tegra210_hsic_phy_power_on(struct phy *phy)
1405{
1406	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1407	struct tegra_xusb_hsic_lane *hsic = to_hsic_lane(lane);
1408	struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1409	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 
1410	unsigned int index = lane->index;
1411	u32 value;
1412	int err;
1413
 
 
1414	err = regulator_enable(pad->supply);
1415	if (err)
1416		return err;
1417
1418	padctl_writel(padctl, hsic->strobe_trim,
1419		      XUSB_PADCTL_HSIC_STRB_TRIM_CONTROL);
1420
1421	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1422	value &= ~(XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_MASK <<
1423		   XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1424	value |= (hsic->tx_rtune_p <<
1425		  XUSB_PADCTL_HSIC_PAD_CTL1_TX_RTUNEP_SHIFT);
1426	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1427
1428	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1429	value &= ~((XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_MASK <<
1430		    XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1431		   (XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_MASK <<
1432		    XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT));
1433	value |= (hsic->rx_strobe_trim <<
1434		  XUSB_PADCTL_HSIC_PAD_CTL2_RX_STROBE_TRIM_SHIFT) |
1435		 (hsic->rx_data_trim <<
1436		  XUSB_PADCTL_HSIC_PAD_CTL2_RX_DATA_TRIM_SHIFT);
1437	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1438
1439	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1440	value &= ~(XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA0 |
1441		   XUSB_PADCTL_HSIC_PAD_CTL0_RPU_DATA1 |
1442		   XUSB_PADCTL_HSIC_PAD_CTL0_RPU_STROBE |
1443		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1444		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1445		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1446		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1447		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1448		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1449		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1450		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1451		   XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE);
1452	value |= XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA0 |
1453		 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_DATA1 |
1454		 XUSB_PADCTL_HSIC_PAD_CTL0_RPD_STROBE;
1455	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1456
1457	err = clk_prepare_enable(pad->clk);
1458	if (err)
1459		goto disable;
1460
1461	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1462	value &= ~((XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_MASK <<
1463		    XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1464		   (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_MASK <<
1465		    XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT));
1466	value |= (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_VAL <<
1467		  XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_START_TIMER_SHIFT) |
1468		 (XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_VAL <<
1469		  XUSB_PADCTL_HSIC_PAD_TRK_CTL_TRK_DONE_RESET_TIMER_SHIFT);
1470	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1471
1472	udelay(1);
1473
1474	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1475	value &= ~XUSB_PADCTL_HSIC_PAD_TRK_CTL_PD_TRK;
1476	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PAD_TRK_CTL);
1477
1478	udelay(50);
1479
1480	clk_disable_unprepare(pad->clk);
1481
1482	return 0;
1483
1484disable:
1485	regulator_disable(pad->supply);
1486	return err;
1487}
1488
1489static int tegra210_hsic_phy_power_off(struct phy *phy)
1490{
1491	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1492	struct tegra_xusb_hsic_pad *pad = to_hsic_pad(lane->pad);
1493	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1494	unsigned int index = lane->index;
1495	u32 value;
1496
1497	value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1498	value |= XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA0 |
1499		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_DATA1 |
1500		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_RX_STROBE |
1501		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA0 |
1502		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_DATA1 |
1503		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_ZI_STROBE |
1504		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA0 |
1505		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_DATA1 |
1506		 XUSB_PADCTL_HSIC_PAD_CTL0_PD_TX_STROBE;
1507	padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1508
1509	regulator_disable(pad->supply);
1510
1511	return 0;
1512}
1513
1514static const struct phy_ops tegra210_hsic_phy_ops = {
1515	.init = tegra210_hsic_phy_init,
1516	.exit = tegra210_hsic_phy_exit,
1517	.power_on = tegra210_hsic_phy_power_on,
1518	.power_off = tegra210_hsic_phy_power_off,
1519	.owner = THIS_MODULE,
1520};
1521
1522static struct tegra_xusb_pad *
1523tegra210_hsic_pad_probe(struct tegra_xusb_padctl *padctl,
1524			const struct tegra_xusb_pad_soc *soc,
1525			struct device_node *np)
1526{
1527	struct tegra_xusb_hsic_pad *hsic;
1528	struct tegra_xusb_pad *pad;
1529	int err;
1530
1531	hsic = kzalloc(sizeof(*hsic), GFP_KERNEL);
1532	if (!hsic)
1533		return ERR_PTR(-ENOMEM);
1534
1535	pad = &hsic->base;
1536	pad->ops = &tegra210_hsic_lane_ops;
1537	pad->soc = soc;
1538
1539	err = tegra_xusb_pad_init(pad, padctl, np);
1540	if (err < 0) {
1541		kfree(hsic);
1542		goto out;
1543	}
1544
1545	hsic->clk = devm_clk_get(&pad->dev, "trk");
1546	if (IS_ERR(hsic->clk)) {
1547		err = PTR_ERR(hsic->clk);
1548		dev_err(&pad->dev, "failed to get trk clock: %d\n", err);
1549		goto unregister;
1550	}
1551
1552	err = tegra_xusb_pad_register(pad, &tegra210_hsic_phy_ops);
1553	if (err < 0)
1554		goto unregister;
1555
1556	dev_set_drvdata(&pad->dev, pad);
1557
1558	return pad;
1559
1560unregister:
1561	device_unregister(&pad->dev);
1562out:
1563	return ERR_PTR(err);
1564}
1565
1566static void tegra210_hsic_pad_remove(struct tegra_xusb_pad *pad)
1567{
1568	struct tegra_xusb_hsic_pad *hsic = to_hsic_pad(pad);
1569
1570	kfree(hsic);
1571}
1572
1573static const struct tegra_xusb_pad_ops tegra210_hsic_ops = {
1574	.probe = tegra210_hsic_pad_probe,
1575	.remove = tegra210_hsic_pad_remove,
1576};
1577
1578static const struct tegra_xusb_pad_soc tegra210_hsic_pad = {
1579	.name = "hsic",
1580	.num_lanes = ARRAY_SIZE(tegra210_hsic_lanes),
1581	.lanes = tegra210_hsic_lanes,
1582	.ops = &tegra210_hsic_ops,
1583};
1584
1585static const char *tegra210_pcie_functions[] = {
1586	"pcie-x1",
1587	"usb3-ss",
1588	"sata",
1589	"pcie-x4",
1590};
1591
1592static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
1593	TEGRA210_LANE("pcie-0", 0x028, 12, 0x3, pcie),
1594	TEGRA210_LANE("pcie-1", 0x028, 14, 0x3, pcie),
1595	TEGRA210_LANE("pcie-2", 0x028, 16, 0x3, pcie),
1596	TEGRA210_LANE("pcie-3", 0x028, 18, 0x3, pcie),
1597	TEGRA210_LANE("pcie-4", 0x028, 20, 0x3, pcie),
1598	TEGRA210_LANE("pcie-5", 0x028, 22, 0x3, pcie),
1599	TEGRA210_LANE("pcie-6", 0x028, 24, 0x3, pcie),
1600};
1601
1602static struct tegra_xusb_lane *
1603tegra210_pcie_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1604			 unsigned int index)
1605{
1606	struct tegra_xusb_pcie_lane *pcie;
1607	int err;
1608
1609	pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1610	if (!pcie)
1611		return ERR_PTR(-ENOMEM);
1612
1613	INIT_LIST_HEAD(&pcie->base.list);
1614	pcie->base.soc = &pad->soc->lanes[index];
1615	pcie->base.index = index;
1616	pcie->base.pad = pad;
1617	pcie->base.np = np;
1618
1619	err = tegra_xusb_lane_parse_dt(&pcie->base, np);
1620	if (err < 0) {
1621		kfree(pcie);
1622		return ERR_PTR(err);
1623	}
1624
1625	return &pcie->base;
1626}
1627
1628static void tegra210_pcie_lane_remove(struct tegra_xusb_lane *lane)
1629{
1630	struct tegra_xusb_pcie_lane *pcie = to_pcie_lane(lane);
1631
1632	kfree(pcie);
1633}
1634
1635static const struct tegra_xusb_lane_ops tegra210_pcie_lane_ops = {
1636	.probe = tegra210_pcie_lane_probe,
1637	.remove = tegra210_pcie_lane_remove,
1638};
1639
1640static int tegra210_pcie_phy_init(struct phy *phy)
1641{
1642	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1643
1644	return tegra210_xusb_padctl_enable(lane->pad->padctl);
1645}
1646
1647static int tegra210_pcie_phy_exit(struct phy *phy)
1648{
1649	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1650
1651	return tegra210_xusb_padctl_disable(lane->pad->padctl);
1652}
1653
1654static int tegra210_pcie_phy_power_on(struct phy *phy)
1655{
1656	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1657	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1658	u32 value;
1659	int err;
1660
1661	mutex_lock(&padctl->lock);
1662
1663	err = tegra210_pex_uphy_enable(padctl);
1664	if (err < 0)
1665		goto unlock;
1666
1667	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1668	value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1669	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1670
1671unlock:
1672	mutex_unlock(&padctl->lock);
1673	return err;
1674}
1675
1676static int tegra210_pcie_phy_power_off(struct phy *phy)
1677{
1678	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1679	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1680	u32 value;
1681
1682	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1683	value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1684	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1685
1686	tegra210_pex_uphy_disable(padctl);
1687
1688	return 0;
1689}
1690
1691static const struct phy_ops tegra210_pcie_phy_ops = {
1692	.init = tegra210_pcie_phy_init,
1693	.exit = tegra210_pcie_phy_exit,
1694	.power_on = tegra210_pcie_phy_power_on,
1695	.power_off = tegra210_pcie_phy_power_off,
1696	.owner = THIS_MODULE,
1697};
1698
1699static struct tegra_xusb_pad *
1700tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
1701			const struct tegra_xusb_pad_soc *soc,
1702			struct device_node *np)
1703{
1704	struct tegra_xusb_pcie_pad *pcie;
1705	struct tegra_xusb_pad *pad;
1706	int err;
1707
1708	pcie = kzalloc(sizeof(*pcie), GFP_KERNEL);
1709	if (!pcie)
1710		return ERR_PTR(-ENOMEM);
1711
1712	pad = &pcie->base;
1713	pad->ops = &tegra210_pcie_lane_ops;
1714	pad->soc = soc;
1715
1716	err = tegra_xusb_pad_init(pad, padctl, np);
1717	if (err < 0) {
1718		kfree(pcie);
1719		goto out;
1720	}
1721
1722	pcie->pll = devm_clk_get(&pad->dev, "pll");
1723	if (IS_ERR(pcie->pll)) {
1724		err = PTR_ERR(pcie->pll);
1725		dev_err(&pad->dev, "failed to get PLL: %d\n", err);
1726		goto unregister;
1727	}
1728
1729	pcie->rst = devm_reset_control_get(&pad->dev, "phy");
1730	if (IS_ERR(pcie->rst)) {
1731		err = PTR_ERR(pcie->rst);
1732		dev_err(&pad->dev, "failed to get PCIe pad reset: %d\n", err);
1733		goto unregister;
1734	}
1735
1736	err = tegra_xusb_pad_register(pad, &tegra210_pcie_phy_ops);
1737	if (err < 0)
1738		goto unregister;
1739
1740	dev_set_drvdata(&pad->dev, pad);
1741
1742	return pad;
1743
1744unregister:
1745	device_unregister(&pad->dev);
1746out:
1747	return ERR_PTR(err);
1748}
1749
1750static void tegra210_pcie_pad_remove(struct tegra_xusb_pad *pad)
1751{
1752	struct tegra_xusb_pcie_pad *pcie = to_pcie_pad(pad);
1753
1754	kfree(pcie);
1755}
1756
1757static const struct tegra_xusb_pad_ops tegra210_pcie_ops = {
1758	.probe = tegra210_pcie_pad_probe,
1759	.remove = tegra210_pcie_pad_remove,
1760};
1761
1762static const struct tegra_xusb_pad_soc tegra210_pcie_pad = {
1763	.name = "pcie",
1764	.num_lanes = ARRAY_SIZE(tegra210_pcie_lanes),
1765	.lanes = tegra210_pcie_lanes,
1766	.ops = &tegra210_pcie_ops,
1767};
1768
1769static const struct tegra_xusb_lane_soc tegra210_sata_lanes[] = {
1770	TEGRA210_LANE("sata-0", 0x028, 30, 0x3, pcie),
1771};
1772
1773static struct tegra_xusb_lane *
1774tegra210_sata_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1775			 unsigned int index)
1776{
1777	struct tegra_xusb_sata_lane *sata;
1778	int err;
1779
1780	sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1781	if (!sata)
1782		return ERR_PTR(-ENOMEM);
1783
1784	INIT_LIST_HEAD(&sata->base.list);
1785	sata->base.soc = &pad->soc->lanes[index];
1786	sata->base.index = index;
1787	sata->base.pad = pad;
1788	sata->base.np = np;
1789
1790	err = tegra_xusb_lane_parse_dt(&sata->base, np);
1791	if (err < 0) {
1792		kfree(sata);
1793		return ERR_PTR(err);
1794	}
1795
1796	return &sata->base;
1797}
1798
1799static void tegra210_sata_lane_remove(struct tegra_xusb_lane *lane)
1800{
1801	struct tegra_xusb_sata_lane *sata = to_sata_lane(lane);
1802
1803	kfree(sata);
1804}
1805
1806static const struct tegra_xusb_lane_ops tegra210_sata_lane_ops = {
1807	.probe = tegra210_sata_lane_probe,
1808	.remove = tegra210_sata_lane_remove,
1809};
1810
1811static int tegra210_sata_phy_init(struct phy *phy)
1812{
1813	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1814
1815	return tegra210_xusb_padctl_enable(lane->pad->padctl);
1816}
1817
1818static int tegra210_sata_phy_exit(struct phy *phy)
1819{
1820	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1821
1822	return tegra210_xusb_padctl_disable(lane->pad->padctl);
1823}
1824
1825static int tegra210_sata_phy_power_on(struct phy *phy)
1826{
1827	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1828	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1829	u32 value;
1830	int err;
1831
1832	mutex_lock(&padctl->lock);
1833
1834	err = tegra210_sata_uphy_enable(padctl, false);
1835	if (err < 0)
1836		goto unlock;
1837
1838	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1839	value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1840	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1841
1842unlock:
1843	mutex_unlock(&padctl->lock);
1844	return err;
1845}
1846
1847static int tegra210_sata_phy_power_off(struct phy *phy)
1848{
1849	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1850	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1851	u32 value;
1852
1853	value = padctl_readl(padctl, XUSB_PADCTL_USB3_PAD_MUX);
1854	value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1855	padctl_writel(padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
1856
1857	tegra210_sata_uphy_disable(lane->pad->padctl);
1858
1859	return 0;
1860}
1861
1862static const struct phy_ops tegra210_sata_phy_ops = {
1863	.init = tegra210_sata_phy_init,
1864	.exit = tegra210_sata_phy_exit,
1865	.power_on = tegra210_sata_phy_power_on,
1866	.power_off = tegra210_sata_phy_power_off,
1867	.owner = THIS_MODULE,
1868};
1869
1870static struct tegra_xusb_pad *
1871tegra210_sata_pad_probe(struct tegra_xusb_padctl *padctl,
1872			const struct tegra_xusb_pad_soc *soc,
1873			struct device_node *np)
1874{
1875	struct tegra_xusb_sata_pad *sata;
1876	struct tegra_xusb_pad *pad;
1877	int err;
1878
1879	sata = kzalloc(sizeof(*sata), GFP_KERNEL);
1880	if (!sata)
1881		return ERR_PTR(-ENOMEM);
1882
1883	pad = &sata->base;
1884	pad->ops = &tegra210_sata_lane_ops;
1885	pad->soc = soc;
1886
1887	err = tegra_xusb_pad_init(pad, padctl, np);
1888	if (err < 0) {
1889		kfree(sata);
1890		goto out;
1891	}
1892
1893	sata->rst = devm_reset_control_get(&pad->dev, "phy");
1894	if (IS_ERR(sata->rst)) {
1895		err = PTR_ERR(sata->rst);
1896		dev_err(&pad->dev, "failed to get SATA pad reset: %d\n", err);
1897		goto unregister;
1898	}
1899
1900	err = tegra_xusb_pad_register(pad, &tegra210_sata_phy_ops);
1901	if (err < 0)
1902		goto unregister;
1903
1904	dev_set_drvdata(&pad->dev, pad);
1905
1906	return pad;
1907
1908unregister:
1909	device_unregister(&pad->dev);
1910out:
1911	return ERR_PTR(err);
1912}
1913
1914static void tegra210_sata_pad_remove(struct tegra_xusb_pad *pad)
1915{
1916	struct tegra_xusb_sata_pad *sata = to_sata_pad(pad);
1917
1918	kfree(sata);
1919}
1920
1921static const struct tegra_xusb_pad_ops tegra210_sata_ops = {
1922	.probe = tegra210_sata_pad_probe,
1923	.remove = tegra210_sata_pad_remove,
1924};
1925
1926static const struct tegra_xusb_pad_soc tegra210_sata_pad = {
1927	.name = "sata",
1928	.num_lanes = ARRAY_SIZE(tegra210_sata_lanes),
1929	.lanes = tegra210_sata_lanes,
1930	.ops = &tegra210_sata_ops,
1931};
1932
1933static const struct tegra_xusb_pad_soc * const tegra210_pads[] = {
1934	&tegra210_usb2_pad,
1935	&tegra210_hsic_pad,
1936	&tegra210_pcie_pad,
1937	&tegra210_sata_pad,
1938};
1939
1940static int tegra210_usb2_port_enable(struct tegra_xusb_port *port)
1941{
1942	return 0;
1943}
1944
1945static void tegra210_usb2_port_disable(struct tegra_xusb_port *port)
1946{
1947}
1948
1949static struct tegra_xusb_lane *
1950tegra210_usb2_port_map(struct tegra_xusb_port *port)
1951{
1952	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1953}
1954
1955static const struct tegra_xusb_port_ops tegra210_usb2_port_ops = {
1956	.release = tegra_xusb_usb2_port_release,
1957	.remove = tegra_xusb_usb2_port_remove,
1958	.enable = tegra210_usb2_port_enable,
1959	.disable = tegra210_usb2_port_disable,
1960	.map = tegra210_usb2_port_map,
1961};
1962
1963static int tegra210_hsic_port_enable(struct tegra_xusb_port *port)
1964{
1965	return 0;
1966}
1967
1968static void tegra210_hsic_port_disable(struct tegra_xusb_port *port)
1969{
1970}
1971
1972static struct tegra_xusb_lane *
1973tegra210_hsic_port_map(struct tegra_xusb_port *port)
1974{
1975	return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
1976}
1977
1978static const struct tegra_xusb_port_ops tegra210_hsic_port_ops = {
1979	.release = tegra_xusb_hsic_port_release,
1980	.enable = tegra210_hsic_port_enable,
1981	.disable = tegra210_hsic_port_disable,
1982	.map = tegra210_hsic_port_map,
1983};
1984
1985static int tegra210_usb3_port_enable(struct tegra_xusb_port *port)
1986{
1987	struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
1988	struct tegra_xusb_padctl *padctl = port->padctl;
1989	struct tegra_xusb_lane *lane = usb3->base.lane;
1990	unsigned int index = port->index;
1991	u32 value;
1992	int err;
1993
1994	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
1995
1996	if (!usb3->internal)
1997		value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1998	else
1999		value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2000
2001	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2002	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
2003	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2004
2005	/*
2006	 * TODO: move this code into the PCIe/SATA PHY ->power_on() callbacks
2007	 * and conditionalize based on mux function? This seems to work, but
2008	 * might not be the exact proper sequence.
2009	 */
2010	err = regulator_enable(usb3->supply);
2011	if (err < 0)
2012		return err;
2013
2014	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2015	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_MASK <<
2016		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT);
2017	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_VAL <<
2018		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL1_TX_TERM_CTRL_SHIFT;
2019	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2020
2021	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2022	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_MASK <<
2023		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT);
2024	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_VAL <<
2025		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL2_RX_CTLE_SHIFT;
2026	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2027
2028	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL3_RX_DFE_VAL,
2029		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
2030
2031	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2032	value &= ~(XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_MASK <<
2033		   XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT);
2034	value |= XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_VAL <<
2035		 XUSB_PADCTL_UPHY_USB3_PAD_ECTL4_RX_CDR_CTRL_SHIFT;
2036	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2037
2038	padctl_writel(padctl, XUSB_PADCTL_UPHY_USB3_PAD_ECTL6_RX_EQ_CTRL_H_VAL,
2039		      XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
2040
2041	if (lane->pad == padctl->sata)
2042		err = tegra210_sata_uphy_enable(padctl, true);
2043	else
2044		err = tegra210_pex_uphy_enable(padctl);
2045
2046	if (err) {
2047		dev_err(&port->dev, "%s: failed to enable UPHY: %d\n",
2048			__func__, err);
2049		return err;
2050	}
2051
2052	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2053	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2054	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2055
2056	usleep_range(100, 200);
2057
2058	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2059	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2060	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2061
2062	usleep_range(100, 200);
2063
2064	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2065	value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2066	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2067
2068	return 0;
2069}
2070
2071static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
2072{
2073	struct tegra_xusb_usb3_port *usb3 = to_usb3_port(port);
2074	struct tegra_xusb_padctl *padctl = port->padctl;
2075	struct tegra_xusb_lane *lane = port->lane;
2076	unsigned int index = port->index;
2077	u32 value;
2078
2079	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2080	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2081	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2082
2083	usleep_range(100, 200);
2084
2085	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2086	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2087	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2088
2089	usleep_range(250, 350);
2090
2091	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM1);
2092	value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2093	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM1);
2094
2095	if (lane->pad == padctl->sata)
2096		tegra210_sata_uphy_disable(padctl);
2097	else
2098		tegra210_pex_uphy_disable(padctl);
2099
2100	regulator_disable(usb3->supply);
2101
2102	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_MAP);
2103	value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2104	value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);
2105	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_MAP);
2106}
2107
2108static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
2109	{ 0, "pcie", 6 },
2110	{ 1, "pcie", 5 },
2111	{ 2, "pcie", 0 },
2112	{ 2, "pcie", 3 },
2113	{ 3, "pcie", 4 },
2114	{ 3, "pcie", 4 },
2115	{ 0, NULL,   0 }
2116};
2117
2118static struct tegra_xusb_lane *
2119tegra210_usb3_port_map(struct tegra_xusb_port *port)
2120{
2121	return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");
2122}
2123
2124static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {
2125	.release = tegra_xusb_usb3_port_release,
2126	.remove = tegra_xusb_usb3_port_remove,
2127	.enable = tegra210_usb3_port_enable,
2128	.disable = tegra210_usb3_port_disable,
2129	.map = tegra210_usb3_port_map,
2130};
2131
2132static int tegra210_utmi_port_reset(struct phy *phy)
2133{
2134	struct tegra_xusb_padctl *padctl;
2135	struct tegra_xusb_lane *lane;
2136	u32 value;
2137
2138	lane = phy_get_drvdata(phy);
2139	padctl = lane->pad->padctl;
2140
2141	value = padctl_readl(padctl,
2142		     XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));
2143
2144	if ((value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIP) ||
2145	    (value & XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPAD_CTL0_ZIN)) {
2146		tegra210_xusb_padctl_vbus_override(padctl, false);
2147		tegra210_xusb_padctl_vbus_override(padctl, true);
2148		return 1;
2149	}
2150
2151	return 0;
2152}
2153
2154static int
2155tegra210_xusb_read_fuse_calibration(struct tegra210_xusb_fuse_calibration *fuse)
2156{
2157	unsigned int i;
2158	u32 value;
2159	int err;
2160
2161	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
2162	if (err < 0)
2163		return err;
2164
2165	for (i = 0; i < ARRAY_SIZE(fuse->hs_curr_level); i++) {
2166		fuse->hs_curr_level[i] =
2167			(value >> FUSE_SKU_CALIB_HS_CURR_LEVEL_PADX_SHIFT(i)) &
2168			FUSE_SKU_CALIB_HS_CURR_LEVEL_PAD_MASK;
2169	}
2170
2171	fuse->hs_term_range_adj =
2172		(value >> FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_SHIFT) &
2173		FUSE_SKU_CALIB_HS_TERM_RANGE_ADJ_MASK;
2174
2175	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
2176	if (err < 0)
2177		return err;
2178
2179	fuse->rpd_ctrl =
2180		(value >> FUSE_USB_CALIB_EXT_RPD_CTRL_SHIFT) &
2181		FUSE_USB_CALIB_EXT_RPD_CTRL_MASK;
2182
2183	return 0;
2184}
2185
2186static struct tegra_xusb_padctl *
2187tegra210_xusb_padctl_probe(struct device *dev,
2188			   const struct tegra_xusb_padctl_soc *soc)
2189{
2190	struct tegra210_xusb_padctl *padctl;
2191	int err;
2192
2193	padctl = devm_kzalloc(dev, sizeof(*padctl), GFP_KERNEL);
2194	if (!padctl)
2195		return ERR_PTR(-ENOMEM);
2196
2197	padctl->base.dev = dev;
2198	padctl->base.soc = soc;
2199
2200	err = tegra210_xusb_read_fuse_calibration(&padctl->fuse);
2201	if (err < 0)
2202		return ERR_PTR(err);
2203
2204	return &padctl->base;
2205}
2206
2207static void tegra210_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
2208{
2209}
2210
2211static const struct tegra_xusb_padctl_ops tegra210_xusb_padctl_ops = {
2212	.probe = tegra210_xusb_padctl_probe,
2213	.remove = tegra210_xusb_padctl_remove,
2214	.usb3_set_lfps_detect = tegra210_usb3_set_lfps_detect,
2215	.hsic_set_idle = tegra210_hsic_set_idle,
2216	.vbus_override = tegra210_xusb_padctl_vbus_override,
2217	.utmi_port_reset = tegra210_utmi_port_reset,
2218};
2219
2220static const char * const tegra210_xusb_padctl_supply_names[] = {
2221	"avdd-pll-utmip",
2222	"avdd-pll-uerefe",
2223	"dvdd-pex-pll",
2224	"hvdd-pex-pll-e",
2225};
2226
2227const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
2228	.num_pads = ARRAY_SIZE(tegra210_pads),
2229	.pads = tegra210_pads,
2230	.ports = {
2231		.usb2 = {
2232			.ops = &tegra210_usb2_port_ops,
2233			.count = 4,
2234		},
2235		.hsic = {
2236			.ops = &tegra210_hsic_port_ops,
2237			.count = 1,
2238		},
2239		.usb3 = {
2240			.ops = &tegra210_usb3_port_ops,
2241			.count = 4,
2242		},
2243	},
2244	.ops = &tegra210_xusb_padctl_ops,
2245	.supply_names = tegra210_xusb_padctl_supply_names,
2246	.num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
2247	.need_fake_usb3_port = true,
2248};
2249EXPORT_SYMBOL_GPL(tegra210_xusb_padctl_soc);
2250
2251MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
2252MODULE_DESCRIPTION("NVIDIA Tegra 210 XUSB Pad Controller driver");
2253MODULE_LICENSE("GPL v2");