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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8#define pr_fmt(fmt) "AMD-Vi: " fmt
9#define dev_fmt(fmt) pr_fmt(fmt)
10
11#include <linux/ratelimit.h>
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/amba/bus.h>
15#include <linux/platform_device.h>
16#include <linux/pci-ats.h>
17#include <linux/bitmap.h>
18#include <linux/slab.h>
19#include <linux/debugfs.h>
20#include <linux/scatterlist.h>
21#include <linux/dma-mapping.h>
22#include <linux/dma-direct.h>
23#include <linux/iommu-helper.h>
24#include <linux/iommu.h>
25#include <linux/delay.h>
26#include <linux/amd-iommu.h>
27#include <linux/notifier.h>
28#include <linux/export.h>
29#include <linux/irq.h>
30#include <linux/msi.h>
31#include <linux/dma-contiguous.h>
32#include <linux/irqdomain.h>
33#include <linux/percpu.h>
34#include <linux/iova.h>
35#include <asm/irq_remapping.h>
36#include <asm/io_apic.h>
37#include <asm/apic.h>
38#include <asm/hw_irq.h>
39#include <asm/msidef.h>
40#include <asm/proto.h>
41#include <asm/iommu.h>
42#include <asm/gart.h>
43#include <asm/dma.h>
44
45#include "amd_iommu_proto.h"
46#include "amd_iommu_types.h"
47#include "irq_remapping.h"
48
49#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
50
51#define LOOP_TIMEOUT 100000
52
53/* IO virtual address start page frame number */
54#define IOVA_START_PFN (1)
55#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
56
57/* Reserved IOVA ranges */
58#define MSI_RANGE_START (0xfee00000)
59#define MSI_RANGE_END (0xfeefffff)
60#define HT_RANGE_START (0xfd00000000ULL)
61#define HT_RANGE_END (0xffffffffffULL)
62
63/*
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
67 * that we support.
68 *
69 * 512GB Pages are not supported due to a hardware bug
70 */
71#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
72
73static DEFINE_SPINLOCK(pd_bitmap_lock);
74
75/* List of all available dev_data structures */
76static LLIST_HEAD(dev_data_list);
77
78LIST_HEAD(ioapic_map);
79LIST_HEAD(hpet_map);
80LIST_HEAD(acpihid_map);
81
82/*
83 * Domain for untranslated devices - only allocated
84 * if iommu=pt passed on kernel cmd line.
85 */
86const struct iommu_ops amd_iommu_ops;
87
88static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
89int amd_iommu_max_glx_val = -1;
90
91static const struct dma_map_ops amd_iommu_dma_ops;
92
93/*
94 * general struct to manage commands send to an IOMMU
95 */
96struct iommu_cmd {
97 u32 data[4];
98};
99
100struct kmem_cache *amd_iommu_irq_cache;
101
102static void update_domain(struct protection_domain *domain);
103static int protection_domain_init(struct protection_domain *domain);
104static void detach_device(struct device *dev);
105static void iova_domain_flush_tlb(struct iova_domain *iovad);
106
107/*
108 * Data container for a dma_ops specific protection domain
109 */
110struct dma_ops_domain {
111 /* generic protection domain information */
112 struct protection_domain domain;
113
114 /* IOVA RB-Tree */
115 struct iova_domain iovad;
116};
117
118static struct iova_domain reserved_iova_ranges;
119static struct lock_class_key reserved_rbtree_key;
120
121/****************************************************************************
122 *
123 * Helper functions
124 *
125 ****************************************************************************/
126
127static inline int match_hid_uid(struct device *dev,
128 struct acpihid_map_entry *entry)
129{
130 struct acpi_device *adev = ACPI_COMPANION(dev);
131 const char *hid, *uid;
132
133 if (!adev)
134 return -ENODEV;
135
136 hid = acpi_device_hid(adev);
137 uid = acpi_device_uid(adev);
138
139 if (!hid || !(*hid))
140 return -ENODEV;
141
142 if (!uid || !(*uid))
143 return strcmp(hid, entry->hid);
144
145 if (!(*entry->uid))
146 return strcmp(hid, entry->hid);
147
148 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
149}
150
151static inline u16 get_pci_device_id(struct device *dev)
152{
153 struct pci_dev *pdev = to_pci_dev(dev);
154
155 return pci_dev_id(pdev);
156}
157
158static inline int get_acpihid_device_id(struct device *dev,
159 struct acpihid_map_entry **entry)
160{
161 struct acpihid_map_entry *p;
162
163 list_for_each_entry(p, &acpihid_map, list) {
164 if (!match_hid_uid(dev, p)) {
165 if (entry)
166 *entry = p;
167 return p->devid;
168 }
169 }
170 return -EINVAL;
171}
172
173static inline int get_device_id(struct device *dev)
174{
175 int devid;
176
177 if (dev_is_pci(dev))
178 devid = get_pci_device_id(dev);
179 else
180 devid = get_acpihid_device_id(dev, NULL);
181
182 return devid;
183}
184
185static struct protection_domain *to_pdomain(struct iommu_domain *dom)
186{
187 return container_of(dom, struct protection_domain, domain);
188}
189
190static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
191{
192 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
193 return container_of(domain, struct dma_ops_domain, domain);
194}
195
196static struct iommu_dev_data *alloc_dev_data(u16 devid)
197{
198 struct iommu_dev_data *dev_data;
199
200 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
201 if (!dev_data)
202 return NULL;
203
204 spin_lock_init(&dev_data->lock);
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
207
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
209 return dev_data;
210}
211
212static struct iommu_dev_data *search_dev_data(u16 devid)
213{
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
216
217 if (llist_empty(&dev_data_list))
218 return NULL;
219
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
223 return dev_data;
224 }
225
226 return NULL;
227}
228
229static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
230{
231 *(u16 *)data = alias;
232 return 0;
233}
234
235static u16 get_alias(struct device *dev)
236{
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
239
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
242
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
245 return devid;
246
247 ivrs_alias = amd_iommu_alias_table[devid];
248
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
250
251 if (ivrs_alias == pci_alias)
252 return ivrs_alias;
253
254 /*
255 * DMA alias showdown
256 *
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
262 */
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
270 }
271
272 return pci_alias;
273 }
274
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
281
282 /*
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
285 */
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
291 }
292
293 return ivrs_alias;
294}
295
296static struct iommu_dev_data *find_dev_data(u16 devid)
297{
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
300
301 dev_data = search_dev_data(devid);
302
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
305 if (!dev_data)
306 return NULL;
307
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
310 }
311
312 return dev_data;
313}
314
315struct iommu_dev_data *get_dev_data(struct device *dev)
316{
317 return dev->archdata.iommu;
318}
319EXPORT_SYMBOL(get_dev_data);
320
321/*
322* Find or create an IOMMU group for a acpihid device.
323*/
324static struct iommu_group *acpihid_device_group(struct device *dev)
325{
326 struct acpihid_map_entry *p, *entry = NULL;
327 int devid;
328
329 devid = get_acpihid_device_id(dev, &entry);
330 if (devid < 0)
331 return ERR_PTR(devid);
332
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
336 }
337
338 if (!entry->group)
339 entry->group = generic_device_group(dev);
340 else
341 iommu_group_ref_get(entry->group);
342
343 return entry->group;
344}
345
346static bool pci_iommuv2_capable(struct pci_dev *pdev)
347{
348 static const int caps[] = {
349 PCI_EXT_CAP_ID_ATS,
350 PCI_EXT_CAP_ID_PRI,
351 PCI_EXT_CAP_ID_PASID,
352 };
353 int i, pos;
354
355 if (pci_ats_disabled())
356 return false;
357
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
360 if (pos == 0)
361 return false;
362 }
363
364 return true;
365}
366
367static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
368{
369 struct iommu_dev_data *dev_data;
370
371 dev_data = get_dev_data(&pdev->dev);
372
373 return dev_data->errata & (1 << erratum) ? true : false;
374}
375
376/*
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
379 */
380static bool check_device(struct device *dev)
381{
382 int devid;
383
384 if (!dev || !dev->dma_mask)
385 return false;
386
387 devid = get_device_id(dev);
388 if (devid < 0)
389 return false;
390
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
393 return false;
394
395 if (amd_iommu_rlookup_table[devid] == NULL)
396 return false;
397
398 return true;
399}
400
401static void init_iommu_group(struct device *dev)
402{
403 struct iommu_group *group;
404
405 group = iommu_group_get_for_dev(dev);
406 if (IS_ERR(group))
407 return;
408
409 iommu_group_put(group);
410}
411
412static int iommu_init_device(struct device *dev)
413{
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
416 int devid;
417
418 if (dev->archdata.iommu)
419 return 0;
420
421 devid = get_device_id(dev);
422 if (devid < 0)
423 return devid;
424
425 iommu = amd_iommu_rlookup_table[devid];
426
427 dev_data = find_dev_data(devid);
428 if (!dev_data)
429 return -ENOMEM;
430
431 dev_data->alias = get_alias(dev);
432
433 /*
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
438 */
439 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
442
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
445 }
446
447 dev->archdata.iommu = dev_data;
448
449 iommu_device_link(&iommu->iommu, dev);
450
451 return 0;
452}
453
454static void iommu_ignore_device(struct device *dev)
455{
456 u16 alias;
457 int devid;
458
459 devid = get_device_id(dev);
460 if (devid < 0)
461 return;
462
463 alias = get_alias(dev);
464
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
467
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
470}
471
472static void iommu_uninit_device(struct device *dev)
473{
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
476 int devid;
477
478 devid = get_device_id(dev);
479 if (devid < 0)
480 return;
481
482 iommu = amd_iommu_rlookup_table[devid];
483
484 dev_data = search_dev_data(devid);
485 if (!dev_data)
486 return;
487
488 if (dev_data->domain)
489 detach_device(dev);
490
491 iommu_device_unlink(&iommu->iommu, dev);
492
493 iommu_group_remove_device(dev);
494
495 /* Remove dma-ops */
496 dev->dma_ops = NULL;
497
498 /*
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
501 */
502}
503
504/*
505 * Helper function to get the first pte of a large mapping
506 */
507static u64 *first_pte_l7(u64 *pte, unsigned long *page_size,
508 unsigned long *count)
509{
510 unsigned long pte_mask, pg_size, cnt;
511 u64 *fpte;
512
513 pg_size = PTE_PAGE_SIZE(*pte);
514 cnt = PAGE_SIZE_PTE_COUNT(pg_size);
515 pte_mask = ~((cnt << 3) - 1);
516 fpte = (u64 *)(((unsigned long)pte) & pte_mask);
517
518 if (page_size)
519 *page_size = pg_size;
520
521 if (count)
522 *count = cnt;
523
524 return fpte;
525}
526
527/****************************************************************************
528 *
529 * Interrupt handling functions
530 *
531 ****************************************************************************/
532
533static void dump_dte_entry(u16 devid)
534{
535 int i;
536
537 for (i = 0; i < 4; ++i)
538 pr_err("DTE[%d]: %016llx\n", i,
539 amd_iommu_dev_table[devid].data[i]);
540}
541
542static void dump_command(unsigned long phys_addr)
543{
544 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
545 int i;
546
547 for (i = 0; i < 4; ++i)
548 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
549}
550
551static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
552 u64 address, int flags)
553{
554 struct iommu_dev_data *dev_data = NULL;
555 struct pci_dev *pdev;
556
557 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
558 devid & 0xff);
559 if (pdev)
560 dev_data = get_dev_data(&pdev->dev);
561
562 if (dev_data && __ratelimit(&dev_data->rs)) {
563 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
564 domain_id, address, flags);
565 } else if (printk_ratelimit()) {
566 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
567 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
568 domain_id, address, flags);
569 }
570
571 if (pdev)
572 pci_dev_put(pdev);
573}
574
575static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
576{
577 struct device *dev = iommu->iommu.dev;
578 int type, devid, pasid, flags, tag;
579 volatile u32 *event = __evt;
580 int count = 0;
581 u64 address;
582
583retry:
584 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
585 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
586 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
587 (event[1] & EVENT_DOMID_MASK_LO);
588 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
589 address = (u64)(((u64)event[3]) << 32) | event[2];
590
591 if (type == 0) {
592 /* Did we hit the erratum? */
593 if (++count == LOOP_TIMEOUT) {
594 pr_err("No event written to event log\n");
595 return;
596 }
597 udelay(1);
598 goto retry;
599 }
600
601 if (type == EVENT_TYPE_IO_FAULT) {
602 amd_iommu_report_page_fault(devid, pasid, address, flags);
603 return;
604 }
605
606 switch (type) {
607 case EVENT_TYPE_ILL_DEV:
608 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
609 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
610 pasid, address, flags);
611 dump_dte_entry(devid);
612 break;
613 case EVENT_TYPE_DEV_TAB_ERR:
614 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
615 "address=0x%llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 address, flags);
618 break;
619 case EVENT_TYPE_PAGE_TAB_ERR:
620 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
621 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622 pasid, address, flags);
623 break;
624 case EVENT_TYPE_ILL_CMD:
625 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
626 dump_command(address);
627 break;
628 case EVENT_TYPE_CMD_HARD_ERR:
629 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
630 address, flags);
631 break;
632 case EVENT_TYPE_IOTLB_INV_TO:
633 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
634 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
635 address);
636 break;
637 case EVENT_TYPE_INV_DEV_REQ:
638 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
639 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
640 pasid, address, flags);
641 break;
642 case EVENT_TYPE_INV_PPR_REQ:
643 pasid = ((event[0] >> 16) & 0xFFFF)
644 | ((event[1] << 6) & 0xF0000);
645 tag = event[1] & 0x03FF;
646 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 pasid, address, flags, tag);
649 break;
650 default:
651 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
652 event[0], event[1], event[2], event[3]);
653 }
654
655 memset(__evt, 0, 4 * sizeof(u32));
656}
657
658static void iommu_poll_events(struct amd_iommu *iommu)
659{
660 u32 head, tail;
661
662 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
663 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
664
665 while (head != tail) {
666 iommu_print_event(iommu, iommu->evt_buf + head);
667 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
668 }
669
670 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
671}
672
673static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
674{
675 struct amd_iommu_fault fault;
676
677 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
678 pr_err_ratelimited("Unknown PPR request received\n");
679 return;
680 }
681
682 fault.address = raw[1];
683 fault.pasid = PPR_PASID(raw[0]);
684 fault.device_id = PPR_DEVID(raw[0]);
685 fault.tag = PPR_TAG(raw[0]);
686 fault.flags = PPR_FLAGS(raw[0]);
687
688 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
689}
690
691static void iommu_poll_ppr_log(struct amd_iommu *iommu)
692{
693 u32 head, tail;
694
695 if (iommu->ppr_log == NULL)
696 return;
697
698 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
699 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
700
701 while (head != tail) {
702 volatile u64 *raw;
703 u64 entry[2];
704 int i;
705
706 raw = (u64 *)(iommu->ppr_log + head);
707
708 /*
709 * Hardware bug: Interrupt may arrive before the entry is
710 * written to memory. If this happens we need to wait for the
711 * entry to arrive.
712 */
713 for (i = 0; i < LOOP_TIMEOUT; ++i) {
714 if (PPR_REQ_TYPE(raw[0]) != 0)
715 break;
716 udelay(1);
717 }
718
719 /* Avoid memcpy function-call overhead */
720 entry[0] = raw[0];
721 entry[1] = raw[1];
722
723 /*
724 * To detect the hardware bug we need to clear the entry
725 * back to zero.
726 */
727 raw[0] = raw[1] = 0UL;
728
729 /* Update head pointer of hardware ring-buffer */
730 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
731 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
732
733 /* Handle PPR entry */
734 iommu_handle_ppr_entry(iommu, entry);
735
736 /* Refresh ring-buffer information */
737 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
738 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
739 }
740}
741
742#ifdef CONFIG_IRQ_REMAP
743static int (*iommu_ga_log_notifier)(u32);
744
745int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
746{
747 iommu_ga_log_notifier = notifier;
748
749 return 0;
750}
751EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
752
753static void iommu_poll_ga_log(struct amd_iommu *iommu)
754{
755 u32 head, tail, cnt = 0;
756
757 if (iommu->ga_log == NULL)
758 return;
759
760 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
761 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
762
763 while (head != tail) {
764 volatile u64 *raw;
765 u64 log_entry;
766
767 raw = (u64 *)(iommu->ga_log + head);
768 cnt++;
769
770 /* Avoid memcpy function-call overhead */
771 log_entry = *raw;
772
773 /* Update head pointer of hardware ring-buffer */
774 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
775 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
776
777 /* Handle GA entry */
778 switch (GA_REQ_TYPE(log_entry)) {
779 case GA_GUEST_NR:
780 if (!iommu_ga_log_notifier)
781 break;
782
783 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
784 __func__, GA_DEVID(log_entry),
785 GA_TAG(log_entry));
786
787 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
788 pr_err("GA log notifier failed.\n");
789 break;
790 default:
791 break;
792 }
793 }
794}
795#endif /* CONFIG_IRQ_REMAP */
796
797#define AMD_IOMMU_INT_MASK \
798 (MMIO_STATUS_EVT_INT_MASK | \
799 MMIO_STATUS_PPR_INT_MASK | \
800 MMIO_STATUS_GALOG_INT_MASK)
801
802irqreturn_t amd_iommu_int_thread(int irq, void *data)
803{
804 struct amd_iommu *iommu = (struct amd_iommu *) data;
805 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
806
807 while (status & AMD_IOMMU_INT_MASK) {
808 /* Enable EVT and PPR and GA interrupts again */
809 writel(AMD_IOMMU_INT_MASK,
810 iommu->mmio_base + MMIO_STATUS_OFFSET);
811
812 if (status & MMIO_STATUS_EVT_INT_MASK) {
813 pr_devel("Processing IOMMU Event Log\n");
814 iommu_poll_events(iommu);
815 }
816
817 if (status & MMIO_STATUS_PPR_INT_MASK) {
818 pr_devel("Processing IOMMU PPR Log\n");
819 iommu_poll_ppr_log(iommu);
820 }
821
822#ifdef CONFIG_IRQ_REMAP
823 if (status & MMIO_STATUS_GALOG_INT_MASK) {
824 pr_devel("Processing IOMMU GA Log\n");
825 iommu_poll_ga_log(iommu);
826 }
827#endif
828
829 /*
830 * Hardware bug: ERBT1312
831 * When re-enabling interrupt (by writing 1
832 * to clear the bit), the hardware might also try to set
833 * the interrupt bit in the event status register.
834 * In this scenario, the bit will be set, and disable
835 * subsequent interrupts.
836 *
837 * Workaround: The IOMMU driver should read back the
838 * status register and check if the interrupt bits are cleared.
839 * If not, driver will need to go through the interrupt handler
840 * again and re-clear the bits
841 */
842 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
843 }
844 return IRQ_HANDLED;
845}
846
847irqreturn_t amd_iommu_int_handler(int irq, void *data)
848{
849 return IRQ_WAKE_THREAD;
850}
851
852/****************************************************************************
853 *
854 * IOMMU command queuing functions
855 *
856 ****************************************************************************/
857
858static int wait_on_sem(volatile u64 *sem)
859{
860 int i = 0;
861
862 while (*sem == 0 && i < LOOP_TIMEOUT) {
863 udelay(1);
864 i += 1;
865 }
866
867 if (i == LOOP_TIMEOUT) {
868 pr_alert("Completion-Wait loop timed out\n");
869 return -EIO;
870 }
871
872 return 0;
873}
874
875static void copy_cmd_to_buffer(struct amd_iommu *iommu,
876 struct iommu_cmd *cmd)
877{
878 u8 *target;
879
880 target = iommu->cmd_buf + iommu->cmd_buf_tail;
881
882 iommu->cmd_buf_tail += sizeof(*cmd);
883 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
884
885 /* Copy command to buffer */
886 memcpy(target, cmd, sizeof(*cmd));
887
888 /* Tell the IOMMU about it */
889 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
890}
891
892static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
893{
894 u64 paddr = iommu_virt_to_phys((void *)address);
895
896 WARN_ON(address & 0x7ULL);
897
898 memset(cmd, 0, sizeof(*cmd));
899 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
900 cmd->data[1] = upper_32_bits(paddr);
901 cmd->data[2] = 1;
902 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
903}
904
905static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
906{
907 memset(cmd, 0, sizeof(*cmd));
908 cmd->data[0] = devid;
909 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
910}
911
912static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
913 size_t size, u16 domid, int pde)
914{
915 u64 pages;
916 bool s;
917
918 pages = iommu_num_pages(address, size, PAGE_SIZE);
919 s = false;
920
921 if (pages > 1) {
922 /*
923 * If we have to flush more than one page, flush all
924 * TLB entries for this domain
925 */
926 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
927 s = true;
928 }
929
930 address &= PAGE_MASK;
931
932 memset(cmd, 0, sizeof(*cmd));
933 cmd->data[1] |= domid;
934 cmd->data[2] = lower_32_bits(address);
935 cmd->data[3] = upper_32_bits(address);
936 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
937 if (s) /* size bit - we flush more than one 4kb page */
938 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
939 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
940 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
941}
942
943static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
944 u64 address, size_t size)
945{
946 u64 pages;
947 bool s;
948
949 pages = iommu_num_pages(address, size, PAGE_SIZE);
950 s = false;
951
952 if (pages > 1) {
953 /*
954 * If we have to flush more than one page, flush all
955 * TLB entries for this domain
956 */
957 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
958 s = true;
959 }
960
961 address &= PAGE_MASK;
962
963 memset(cmd, 0, sizeof(*cmd));
964 cmd->data[0] = devid;
965 cmd->data[0] |= (qdep & 0xff) << 24;
966 cmd->data[1] = devid;
967 cmd->data[2] = lower_32_bits(address);
968 cmd->data[3] = upper_32_bits(address);
969 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
970 if (s)
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
972}
973
974static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
975 u64 address, bool size)
976{
977 memset(cmd, 0, sizeof(*cmd));
978
979 address &= ~(0xfffULL);
980
981 cmd->data[0] = pasid;
982 cmd->data[1] = domid;
983 cmd->data[2] = lower_32_bits(address);
984 cmd->data[3] = upper_32_bits(address);
985 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
986 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
987 if (size)
988 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
989 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
990}
991
992static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
993 int qdep, u64 address, bool size)
994{
995 memset(cmd, 0, sizeof(*cmd));
996
997 address &= ~(0xfffULL);
998
999 cmd->data[0] = devid;
1000 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1001 cmd->data[0] |= (qdep & 0xff) << 24;
1002 cmd->data[1] = devid;
1003 cmd->data[1] |= (pasid & 0xff) << 16;
1004 cmd->data[2] = lower_32_bits(address);
1005 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1006 cmd->data[3] = upper_32_bits(address);
1007 if (size)
1008 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1009 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1010}
1011
1012static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1013 int status, int tag, bool gn)
1014{
1015 memset(cmd, 0, sizeof(*cmd));
1016
1017 cmd->data[0] = devid;
1018 if (gn) {
1019 cmd->data[1] = pasid;
1020 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1021 }
1022 cmd->data[3] = tag & 0x1ff;
1023 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1024
1025 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1026}
1027
1028static void build_inv_all(struct iommu_cmd *cmd)
1029{
1030 memset(cmd, 0, sizeof(*cmd));
1031 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1032}
1033
1034static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1035{
1036 memset(cmd, 0, sizeof(*cmd));
1037 cmd->data[0] = devid;
1038 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1039}
1040
1041/*
1042 * Writes the command to the IOMMUs command buffer and informs the
1043 * hardware about the new command.
1044 */
1045static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1046 struct iommu_cmd *cmd,
1047 bool sync)
1048{
1049 unsigned int count = 0;
1050 u32 left, next_tail;
1051
1052 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1053again:
1054 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1055
1056 if (left <= 0x20) {
1057 /* Skip udelay() the first time around */
1058 if (count++) {
1059 if (count == LOOP_TIMEOUT) {
1060 pr_err("Command buffer timeout\n");
1061 return -EIO;
1062 }
1063
1064 udelay(1);
1065 }
1066
1067 /* Update head and recheck remaining space */
1068 iommu->cmd_buf_head = readl(iommu->mmio_base +
1069 MMIO_CMD_HEAD_OFFSET);
1070
1071 goto again;
1072 }
1073
1074 copy_cmd_to_buffer(iommu, cmd);
1075
1076 /* Do we need to make sure all commands are processed? */
1077 iommu->need_sync = sync;
1078
1079 return 0;
1080}
1081
1082static int iommu_queue_command_sync(struct amd_iommu *iommu,
1083 struct iommu_cmd *cmd,
1084 bool sync)
1085{
1086 unsigned long flags;
1087 int ret;
1088
1089 raw_spin_lock_irqsave(&iommu->lock, flags);
1090 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1091 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1092
1093 return ret;
1094}
1095
1096static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1097{
1098 return iommu_queue_command_sync(iommu, cmd, true);
1099}
1100
1101/*
1102 * This function queues a completion wait command into the command
1103 * buffer of an IOMMU
1104 */
1105static int iommu_completion_wait(struct amd_iommu *iommu)
1106{
1107 struct iommu_cmd cmd;
1108 unsigned long flags;
1109 int ret;
1110
1111 if (!iommu->need_sync)
1112 return 0;
1113
1114
1115 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1116
1117 raw_spin_lock_irqsave(&iommu->lock, flags);
1118
1119 iommu->cmd_sem = 0;
1120
1121 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1122 if (ret)
1123 goto out_unlock;
1124
1125 ret = wait_on_sem(&iommu->cmd_sem);
1126
1127out_unlock:
1128 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1129
1130 return ret;
1131}
1132
1133static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1134{
1135 struct iommu_cmd cmd;
1136
1137 build_inv_dte(&cmd, devid);
1138
1139 return iommu_queue_command(iommu, &cmd);
1140}
1141
1142static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1143{
1144 u32 devid;
1145
1146 for (devid = 0; devid <= 0xffff; ++devid)
1147 iommu_flush_dte(iommu, devid);
1148
1149 iommu_completion_wait(iommu);
1150}
1151
1152/*
1153 * This function uses heavy locking and may disable irqs for some time. But
1154 * this is no issue because it is only called during resume.
1155 */
1156static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1157{
1158 u32 dom_id;
1159
1160 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1161 struct iommu_cmd cmd;
1162 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1163 dom_id, 1);
1164 iommu_queue_command(iommu, &cmd);
1165 }
1166
1167 iommu_completion_wait(iommu);
1168}
1169
1170static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1171{
1172 struct iommu_cmd cmd;
1173
1174 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1175 dom_id, 1);
1176 iommu_queue_command(iommu, &cmd);
1177
1178 iommu_completion_wait(iommu);
1179}
1180
1181static void amd_iommu_flush_all(struct amd_iommu *iommu)
1182{
1183 struct iommu_cmd cmd;
1184
1185 build_inv_all(&cmd);
1186
1187 iommu_queue_command(iommu, &cmd);
1188 iommu_completion_wait(iommu);
1189}
1190
1191static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1192{
1193 struct iommu_cmd cmd;
1194
1195 build_inv_irt(&cmd, devid);
1196
1197 iommu_queue_command(iommu, &cmd);
1198}
1199
1200static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1201{
1202 u32 devid;
1203
1204 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1205 iommu_flush_irt(iommu, devid);
1206
1207 iommu_completion_wait(iommu);
1208}
1209
1210void iommu_flush_all_caches(struct amd_iommu *iommu)
1211{
1212 if (iommu_feature(iommu, FEATURE_IA)) {
1213 amd_iommu_flush_all(iommu);
1214 } else {
1215 amd_iommu_flush_dte_all(iommu);
1216 amd_iommu_flush_irt_all(iommu);
1217 amd_iommu_flush_tlb_all(iommu);
1218 }
1219}
1220
1221/*
1222 * Command send function for flushing on-device TLB
1223 */
1224static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1225 u64 address, size_t size)
1226{
1227 struct amd_iommu *iommu;
1228 struct iommu_cmd cmd;
1229 int qdep;
1230
1231 qdep = dev_data->ats.qdep;
1232 iommu = amd_iommu_rlookup_table[dev_data->devid];
1233
1234 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1235
1236 return iommu_queue_command(iommu, &cmd);
1237}
1238
1239/*
1240 * Command send function for invalidating a device table entry
1241 */
1242static int device_flush_dte(struct iommu_dev_data *dev_data)
1243{
1244 struct amd_iommu *iommu;
1245 u16 alias;
1246 int ret;
1247
1248 iommu = amd_iommu_rlookup_table[dev_data->devid];
1249 alias = dev_data->alias;
1250
1251 ret = iommu_flush_dte(iommu, dev_data->devid);
1252 if (!ret && alias != dev_data->devid)
1253 ret = iommu_flush_dte(iommu, alias);
1254 if (ret)
1255 return ret;
1256
1257 if (dev_data->ats.enabled)
1258 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1259
1260 return ret;
1261}
1262
1263/*
1264 * TLB invalidation function which is called from the mapping functions.
1265 * It invalidates a single PTE if the range to flush is within a single
1266 * page. Otherwise it flushes the whole TLB of the IOMMU.
1267 */
1268static void __domain_flush_pages(struct protection_domain *domain,
1269 u64 address, size_t size, int pde)
1270{
1271 struct iommu_dev_data *dev_data;
1272 struct iommu_cmd cmd;
1273 int ret = 0, i;
1274
1275 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1276
1277 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1278 if (!domain->dev_iommu[i])
1279 continue;
1280
1281 /*
1282 * Devices of this domain are behind this IOMMU
1283 * We need a TLB flush
1284 */
1285 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1286 }
1287
1288 list_for_each_entry(dev_data, &domain->dev_list, list) {
1289
1290 if (!dev_data->ats.enabled)
1291 continue;
1292
1293 ret |= device_flush_iotlb(dev_data, address, size);
1294 }
1295
1296 WARN_ON(ret);
1297}
1298
1299static void domain_flush_pages(struct protection_domain *domain,
1300 u64 address, size_t size)
1301{
1302 __domain_flush_pages(domain, address, size, 0);
1303}
1304
1305/* Flush the whole IO/TLB for a given protection domain */
1306static void domain_flush_tlb(struct protection_domain *domain)
1307{
1308 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1309}
1310
1311/* Flush the whole IO/TLB for a given protection domain - including PDE */
1312static void domain_flush_tlb_pde(struct protection_domain *domain)
1313{
1314 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1315}
1316
1317static void domain_flush_complete(struct protection_domain *domain)
1318{
1319 int i;
1320
1321 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1322 if (domain && !domain->dev_iommu[i])
1323 continue;
1324
1325 /*
1326 * Devices of this domain are behind this IOMMU
1327 * We need to wait for completion of all commands.
1328 */
1329 iommu_completion_wait(amd_iommus[i]);
1330 }
1331}
1332
1333/* Flush the not present cache if it exists */
1334static void domain_flush_np_cache(struct protection_domain *domain,
1335 dma_addr_t iova, size_t size)
1336{
1337 if (unlikely(amd_iommu_np_cache)) {
1338 unsigned long flags;
1339
1340 spin_lock_irqsave(&domain->lock, flags);
1341 domain_flush_pages(domain, iova, size);
1342 domain_flush_complete(domain);
1343 spin_unlock_irqrestore(&domain->lock, flags);
1344 }
1345}
1346
1347
1348/*
1349 * This function flushes the DTEs for all devices in domain
1350 */
1351static void domain_flush_devices(struct protection_domain *domain)
1352{
1353 struct iommu_dev_data *dev_data;
1354
1355 list_for_each_entry(dev_data, &domain->dev_list, list)
1356 device_flush_dte(dev_data);
1357}
1358
1359/****************************************************************************
1360 *
1361 * The functions below are used the create the page table mappings for
1362 * unity mapped regions.
1363 *
1364 ****************************************************************************/
1365
1366static void free_page_list(struct page *freelist)
1367{
1368 while (freelist != NULL) {
1369 unsigned long p = (unsigned long)page_address(freelist);
1370 freelist = freelist->freelist;
1371 free_page(p);
1372 }
1373}
1374
1375static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1376{
1377 struct page *p = virt_to_page((void *)pt);
1378
1379 p->freelist = freelist;
1380
1381 return p;
1382}
1383
1384#define DEFINE_FREE_PT_FN(LVL, FN) \
1385static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1386{ \
1387 unsigned long p; \
1388 u64 *pt; \
1389 int i; \
1390 \
1391 pt = (u64 *)__pt; \
1392 \
1393 for (i = 0; i < 512; ++i) { \
1394 /* PTE present? */ \
1395 if (!IOMMU_PTE_PRESENT(pt[i])) \
1396 continue; \
1397 \
1398 /* Large PTE? */ \
1399 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1400 PM_PTE_LEVEL(pt[i]) == 7) \
1401 continue; \
1402 \
1403 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1404 freelist = FN(p, freelist); \
1405 } \
1406 \
1407 return free_pt_page((unsigned long)pt, freelist); \
1408}
1409
1410DEFINE_FREE_PT_FN(l2, free_pt_page)
1411DEFINE_FREE_PT_FN(l3, free_pt_l2)
1412DEFINE_FREE_PT_FN(l4, free_pt_l3)
1413DEFINE_FREE_PT_FN(l5, free_pt_l4)
1414DEFINE_FREE_PT_FN(l6, free_pt_l5)
1415
1416static struct page *free_sub_pt(unsigned long root, int mode,
1417 struct page *freelist)
1418{
1419 switch (mode) {
1420 case PAGE_MODE_NONE:
1421 case PAGE_MODE_7_LEVEL:
1422 break;
1423 case PAGE_MODE_1_LEVEL:
1424 freelist = free_pt_page(root, freelist);
1425 break;
1426 case PAGE_MODE_2_LEVEL:
1427 freelist = free_pt_l2(root, freelist);
1428 break;
1429 case PAGE_MODE_3_LEVEL:
1430 freelist = free_pt_l3(root, freelist);
1431 break;
1432 case PAGE_MODE_4_LEVEL:
1433 freelist = free_pt_l4(root, freelist);
1434 break;
1435 case PAGE_MODE_5_LEVEL:
1436 freelist = free_pt_l5(root, freelist);
1437 break;
1438 case PAGE_MODE_6_LEVEL:
1439 freelist = free_pt_l6(root, freelist);
1440 break;
1441 default:
1442 BUG();
1443 }
1444
1445 return freelist;
1446}
1447
1448static void free_pagetable(struct protection_domain *domain)
1449{
1450 unsigned long root = (unsigned long)domain->pt_root;
1451 struct page *freelist = NULL;
1452
1453 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1454 domain->mode > PAGE_MODE_6_LEVEL);
1455
1456 freelist = free_sub_pt(root, domain->mode, freelist);
1457
1458 free_page_list(freelist);
1459}
1460
1461/*
1462 * This function is used to add another level to an IO page table. Adding
1463 * another level increases the size of the address space by 9 bits to a size up
1464 * to 64 bits.
1465 */
1466static bool increase_address_space(struct protection_domain *domain,
1467 unsigned long address,
1468 gfp_t gfp)
1469{
1470 unsigned long flags;
1471 bool ret = false;
1472 u64 *pte;
1473
1474 spin_lock_irqsave(&domain->lock, flags);
1475
1476 if (address <= PM_LEVEL_SIZE(domain->mode) ||
1477 WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1478 goto out;
1479
1480 pte = (void *)get_zeroed_page(gfp);
1481 if (!pte)
1482 goto out;
1483
1484 *pte = PM_LEVEL_PDE(domain->mode,
1485 iommu_virt_to_phys(domain->pt_root));
1486 domain->pt_root = pte;
1487 domain->mode += 1;
1488
1489 ret = true;
1490
1491out:
1492 spin_unlock_irqrestore(&domain->lock, flags);
1493
1494 return ret;
1495}
1496
1497static u64 *alloc_pte(struct protection_domain *domain,
1498 unsigned long address,
1499 unsigned long page_size,
1500 u64 **pte_page,
1501 gfp_t gfp,
1502 bool *updated)
1503{
1504 int level, end_lvl;
1505 u64 *pte, *page;
1506
1507 BUG_ON(!is_power_of_2(page_size));
1508
1509 while (address > PM_LEVEL_SIZE(domain->mode))
1510 *updated = increase_address_space(domain, address, gfp) || *updated;
1511
1512 level = domain->mode - 1;
1513 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1514 address = PAGE_SIZE_ALIGN(address, page_size);
1515 end_lvl = PAGE_SIZE_LEVEL(page_size);
1516
1517 while (level > end_lvl) {
1518 u64 __pte, __npte;
1519 int pte_level;
1520
1521 __pte = *pte;
1522 pte_level = PM_PTE_LEVEL(__pte);
1523
1524 /*
1525 * If we replace a series of large PTEs, we need
1526 * to tear down all of them.
1527 */
1528 if (IOMMU_PTE_PRESENT(__pte) &&
1529 pte_level == PAGE_MODE_7_LEVEL) {
1530 unsigned long count, i;
1531 u64 *lpte;
1532
1533 lpte = first_pte_l7(pte, NULL, &count);
1534
1535 /*
1536 * Unmap the replicated PTEs that still match the
1537 * original large mapping
1538 */
1539 for (i = 0; i < count; ++i)
1540 cmpxchg64(&lpte[i], __pte, 0ULL);
1541
1542 *updated = true;
1543 continue;
1544 }
1545
1546 if (!IOMMU_PTE_PRESENT(__pte) ||
1547 pte_level == PAGE_MODE_NONE) {
1548 page = (u64 *)get_zeroed_page(gfp);
1549
1550 if (!page)
1551 return NULL;
1552
1553 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1554
1555 /* pte could have been changed somewhere. */
1556 if (cmpxchg64(pte, __pte, __npte) != __pte)
1557 free_page((unsigned long)page);
1558 else if (IOMMU_PTE_PRESENT(__pte))
1559 *updated = true;
1560
1561 continue;
1562 }
1563
1564 /* No level skipping support yet */
1565 if (pte_level != level)
1566 return NULL;
1567
1568 level -= 1;
1569
1570 pte = IOMMU_PTE_PAGE(__pte);
1571
1572 if (pte_page && level == end_lvl)
1573 *pte_page = pte;
1574
1575 pte = &pte[PM_LEVEL_INDEX(level, address)];
1576 }
1577
1578 return pte;
1579}
1580
1581/*
1582 * This function checks if there is a PTE for a given dma address. If
1583 * there is one, it returns the pointer to it.
1584 */
1585static u64 *fetch_pte(struct protection_domain *domain,
1586 unsigned long address,
1587 unsigned long *page_size)
1588{
1589 int level;
1590 u64 *pte;
1591
1592 *page_size = 0;
1593
1594 if (address > PM_LEVEL_SIZE(domain->mode))
1595 return NULL;
1596
1597 level = domain->mode - 1;
1598 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1599 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1600
1601 while (level > 0) {
1602
1603 /* Not Present */
1604 if (!IOMMU_PTE_PRESENT(*pte))
1605 return NULL;
1606
1607 /* Large PTE */
1608 if (PM_PTE_LEVEL(*pte) == 7 ||
1609 PM_PTE_LEVEL(*pte) == 0)
1610 break;
1611
1612 /* No level skipping support yet */
1613 if (PM_PTE_LEVEL(*pte) != level)
1614 return NULL;
1615
1616 level -= 1;
1617
1618 /* Walk to the next level */
1619 pte = IOMMU_PTE_PAGE(*pte);
1620 pte = &pte[PM_LEVEL_INDEX(level, address)];
1621 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1622 }
1623
1624 /*
1625 * If we have a series of large PTEs, make
1626 * sure to return a pointer to the first one.
1627 */
1628 if (PM_PTE_LEVEL(*pte) == PAGE_MODE_7_LEVEL)
1629 pte = first_pte_l7(pte, page_size, NULL);
1630
1631 return pte;
1632}
1633
1634static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1635{
1636 unsigned long pt;
1637 int mode;
1638
1639 while (cmpxchg64(pte, pteval, 0) != pteval) {
1640 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1641 pteval = *pte;
1642 }
1643
1644 if (!IOMMU_PTE_PRESENT(pteval))
1645 return freelist;
1646
1647 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1648 mode = IOMMU_PTE_MODE(pteval);
1649
1650 return free_sub_pt(pt, mode, freelist);
1651}
1652
1653/*
1654 * Generic mapping functions. It maps a physical address into a DMA
1655 * address space. It allocates the page table pages if necessary.
1656 * In the future it can be extended to a generic mapping function
1657 * supporting all features of AMD IOMMU page tables like level skipping
1658 * and full 64 bit address spaces.
1659 */
1660static int iommu_map_page(struct protection_domain *dom,
1661 unsigned long bus_addr,
1662 unsigned long phys_addr,
1663 unsigned long page_size,
1664 int prot,
1665 gfp_t gfp)
1666{
1667 struct page *freelist = NULL;
1668 bool updated = false;
1669 u64 __pte, *pte;
1670 int ret, i, count;
1671
1672 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1673 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1674
1675 ret = -EINVAL;
1676 if (!(prot & IOMMU_PROT_MASK))
1677 goto out;
1678
1679 count = PAGE_SIZE_PTE_COUNT(page_size);
1680 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp, &updated);
1681
1682 ret = -ENOMEM;
1683 if (!pte)
1684 goto out;
1685
1686 for (i = 0; i < count; ++i)
1687 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1688
1689 if (freelist != NULL)
1690 updated = true;
1691
1692 if (count > 1) {
1693 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1694 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1695 } else
1696 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1697
1698 if (prot & IOMMU_PROT_IR)
1699 __pte |= IOMMU_PTE_IR;
1700 if (prot & IOMMU_PROT_IW)
1701 __pte |= IOMMU_PTE_IW;
1702
1703 for (i = 0; i < count; ++i)
1704 pte[i] = __pte;
1705
1706 ret = 0;
1707
1708out:
1709 if (updated) {
1710 unsigned long flags;
1711
1712 spin_lock_irqsave(&dom->lock, flags);
1713 update_domain(dom);
1714 spin_unlock_irqrestore(&dom->lock, flags);
1715 }
1716
1717 /* Everything flushed out, free pages now */
1718 free_page_list(freelist);
1719
1720 return ret;
1721}
1722
1723static unsigned long iommu_unmap_page(struct protection_domain *dom,
1724 unsigned long bus_addr,
1725 unsigned long page_size)
1726{
1727 unsigned long long unmapped;
1728 unsigned long unmap_size;
1729 u64 *pte;
1730
1731 BUG_ON(!is_power_of_2(page_size));
1732
1733 unmapped = 0;
1734
1735 while (unmapped < page_size) {
1736
1737 pte = fetch_pte(dom, bus_addr, &unmap_size);
1738
1739 if (pte) {
1740 int i, count;
1741
1742 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1743 for (i = 0; i < count; i++)
1744 pte[i] = 0ULL;
1745 }
1746
1747 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1748 unmapped += unmap_size;
1749 }
1750
1751 BUG_ON(unmapped && !is_power_of_2(unmapped));
1752
1753 return unmapped;
1754}
1755
1756/****************************************************************************
1757 *
1758 * The next functions belong to the address allocator for the dma_ops
1759 * interface functions.
1760 *
1761 ****************************************************************************/
1762
1763
1764static unsigned long dma_ops_alloc_iova(struct device *dev,
1765 struct dma_ops_domain *dma_dom,
1766 unsigned int pages, u64 dma_mask)
1767{
1768 unsigned long pfn = 0;
1769
1770 pages = __roundup_pow_of_two(pages);
1771
1772 if (dma_mask > DMA_BIT_MASK(32))
1773 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1774 IOVA_PFN(DMA_BIT_MASK(32)), false);
1775
1776 if (!pfn)
1777 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1778 IOVA_PFN(dma_mask), true);
1779
1780 return (pfn << PAGE_SHIFT);
1781}
1782
1783static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1784 unsigned long address,
1785 unsigned int pages)
1786{
1787 pages = __roundup_pow_of_two(pages);
1788 address >>= PAGE_SHIFT;
1789
1790 free_iova_fast(&dma_dom->iovad, address, pages);
1791}
1792
1793/****************************************************************************
1794 *
1795 * The next functions belong to the domain allocation. A domain is
1796 * allocated for every IOMMU as the default domain. If device isolation
1797 * is enabled, every device get its own domain. The most important thing
1798 * about domains is the page table mapping the DMA address space they
1799 * contain.
1800 *
1801 ****************************************************************************/
1802
1803static u16 domain_id_alloc(void)
1804{
1805 int id;
1806
1807 spin_lock(&pd_bitmap_lock);
1808 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1809 BUG_ON(id == 0);
1810 if (id > 0 && id < MAX_DOMAIN_ID)
1811 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1812 else
1813 id = 0;
1814 spin_unlock(&pd_bitmap_lock);
1815
1816 return id;
1817}
1818
1819static void domain_id_free(int id)
1820{
1821 spin_lock(&pd_bitmap_lock);
1822 if (id > 0 && id < MAX_DOMAIN_ID)
1823 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1824 spin_unlock(&pd_bitmap_lock);
1825}
1826
1827static void free_gcr3_tbl_level1(u64 *tbl)
1828{
1829 u64 *ptr;
1830 int i;
1831
1832 for (i = 0; i < 512; ++i) {
1833 if (!(tbl[i] & GCR3_VALID))
1834 continue;
1835
1836 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1837
1838 free_page((unsigned long)ptr);
1839 }
1840}
1841
1842static void free_gcr3_tbl_level2(u64 *tbl)
1843{
1844 u64 *ptr;
1845 int i;
1846
1847 for (i = 0; i < 512; ++i) {
1848 if (!(tbl[i] & GCR3_VALID))
1849 continue;
1850
1851 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1852
1853 free_gcr3_tbl_level1(ptr);
1854 }
1855}
1856
1857static void free_gcr3_table(struct protection_domain *domain)
1858{
1859 if (domain->glx == 2)
1860 free_gcr3_tbl_level2(domain->gcr3_tbl);
1861 else if (domain->glx == 1)
1862 free_gcr3_tbl_level1(domain->gcr3_tbl);
1863 else
1864 BUG_ON(domain->glx != 0);
1865
1866 free_page((unsigned long)domain->gcr3_tbl);
1867}
1868
1869static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1870{
1871 unsigned long flags;
1872
1873 spin_lock_irqsave(&dom->domain.lock, flags);
1874 domain_flush_tlb(&dom->domain);
1875 domain_flush_complete(&dom->domain);
1876 spin_unlock_irqrestore(&dom->domain.lock, flags);
1877}
1878
1879static void iova_domain_flush_tlb(struct iova_domain *iovad)
1880{
1881 struct dma_ops_domain *dom;
1882
1883 dom = container_of(iovad, struct dma_ops_domain, iovad);
1884
1885 dma_ops_domain_flush_tlb(dom);
1886}
1887
1888/*
1889 * Free a domain, only used if something went wrong in the
1890 * allocation path and we need to free an already allocated page table
1891 */
1892static void dma_ops_domain_free(struct dma_ops_domain *dom)
1893{
1894 if (!dom)
1895 return;
1896
1897 put_iova_domain(&dom->iovad);
1898
1899 free_pagetable(&dom->domain);
1900
1901 if (dom->domain.id)
1902 domain_id_free(dom->domain.id);
1903
1904 kfree(dom);
1905}
1906
1907/*
1908 * Allocates a new protection domain usable for the dma_ops functions.
1909 * It also initializes the page table and the address allocator data
1910 * structures required for the dma_ops interface
1911 */
1912static struct dma_ops_domain *dma_ops_domain_alloc(void)
1913{
1914 struct dma_ops_domain *dma_dom;
1915
1916 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1917 if (!dma_dom)
1918 return NULL;
1919
1920 if (protection_domain_init(&dma_dom->domain))
1921 goto free_dma_dom;
1922
1923 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1924 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1925 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1926 if (!dma_dom->domain.pt_root)
1927 goto free_dma_dom;
1928
1929 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1930
1931 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1932 goto free_dma_dom;
1933
1934 /* Initialize reserved ranges */
1935 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1936
1937 return dma_dom;
1938
1939free_dma_dom:
1940 dma_ops_domain_free(dma_dom);
1941
1942 return NULL;
1943}
1944
1945/*
1946 * little helper function to check whether a given protection domain is a
1947 * dma_ops domain
1948 */
1949static bool dma_ops_domain(struct protection_domain *domain)
1950{
1951 return domain->flags & PD_DMA_OPS_MASK;
1952}
1953
1954static void set_dte_entry(u16 devid, struct protection_domain *domain,
1955 bool ats, bool ppr)
1956{
1957 u64 pte_root = 0;
1958 u64 flags = 0;
1959 u32 old_domid;
1960
1961 if (domain->mode != PAGE_MODE_NONE)
1962 pte_root = iommu_virt_to_phys(domain->pt_root);
1963
1964 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1965 << DEV_ENTRY_MODE_SHIFT;
1966 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1967
1968 flags = amd_iommu_dev_table[devid].data[1];
1969
1970 if (ats)
1971 flags |= DTE_FLAG_IOTLB;
1972
1973 if (ppr) {
1974 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1975
1976 if (iommu_feature(iommu, FEATURE_EPHSUP))
1977 pte_root |= 1ULL << DEV_ENTRY_PPR;
1978 }
1979
1980 if (domain->flags & PD_IOMMUV2_MASK) {
1981 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1982 u64 glx = domain->glx;
1983 u64 tmp;
1984
1985 pte_root |= DTE_FLAG_GV;
1986 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1987
1988 /* First mask out possible old values for GCR3 table */
1989 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1990 flags &= ~tmp;
1991
1992 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1993 flags &= ~tmp;
1994
1995 /* Encode GCR3 table into DTE */
1996 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1997 pte_root |= tmp;
1998
1999 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2000 flags |= tmp;
2001
2002 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2003 flags |= tmp;
2004 }
2005
2006 flags &= ~DEV_DOMID_MASK;
2007 flags |= domain->id;
2008
2009 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
2010 amd_iommu_dev_table[devid].data[1] = flags;
2011 amd_iommu_dev_table[devid].data[0] = pte_root;
2012
2013 /*
2014 * A kdump kernel might be replacing a domain ID that was copied from
2015 * the previous kernel--if so, it needs to flush the translation cache
2016 * entries for the old domain ID that is being overwritten
2017 */
2018 if (old_domid) {
2019 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2020
2021 amd_iommu_flush_tlb_domid(iommu, old_domid);
2022 }
2023}
2024
2025static void clear_dte_entry(u16 devid)
2026{
2027 /* remove entry from the device table seen by the hardware */
2028 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
2029 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
2030
2031 amd_iommu_apply_erratum_63(devid);
2032}
2033
2034static void do_attach(struct iommu_dev_data *dev_data,
2035 struct protection_domain *domain)
2036{
2037 struct amd_iommu *iommu;
2038 u16 alias;
2039 bool ats;
2040
2041 iommu = amd_iommu_rlookup_table[dev_data->devid];
2042 alias = dev_data->alias;
2043 ats = dev_data->ats.enabled;
2044
2045 /* Update data structures */
2046 dev_data->domain = domain;
2047 list_add(&dev_data->list, &domain->dev_list);
2048
2049 /* Do reference counting */
2050 domain->dev_iommu[iommu->index] += 1;
2051 domain->dev_cnt += 1;
2052
2053 /* Update device table */
2054 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
2055 if (alias != dev_data->devid)
2056 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
2057
2058 device_flush_dte(dev_data);
2059}
2060
2061static void do_detach(struct iommu_dev_data *dev_data)
2062{
2063 struct protection_domain *domain = dev_data->domain;
2064 struct amd_iommu *iommu;
2065 u16 alias;
2066
2067 iommu = amd_iommu_rlookup_table[dev_data->devid];
2068 alias = dev_data->alias;
2069
2070 /* Update data structures */
2071 dev_data->domain = NULL;
2072 list_del(&dev_data->list);
2073 clear_dte_entry(dev_data->devid);
2074 if (alias != dev_data->devid)
2075 clear_dte_entry(alias);
2076
2077 /* Flush the DTE entry */
2078 device_flush_dte(dev_data);
2079
2080 /* Flush IOTLB */
2081 domain_flush_tlb_pde(domain);
2082
2083 /* Wait for the flushes to finish */
2084 domain_flush_complete(domain);
2085
2086 /* decrease reference counters - needs to happen after the flushes */
2087 domain->dev_iommu[iommu->index] -= 1;
2088 domain->dev_cnt -= 1;
2089}
2090
2091static void pdev_iommuv2_disable(struct pci_dev *pdev)
2092{
2093 pci_disable_ats(pdev);
2094 pci_disable_pri(pdev);
2095 pci_disable_pasid(pdev);
2096}
2097
2098/* FIXME: Change generic reset-function to do the same */
2099static int pri_reset_while_enabled(struct pci_dev *pdev)
2100{
2101 u16 control;
2102 int pos;
2103
2104 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2105 if (!pos)
2106 return -EINVAL;
2107
2108 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2109 control |= PCI_PRI_CTRL_RESET;
2110 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2111
2112 return 0;
2113}
2114
2115static int pdev_iommuv2_enable(struct pci_dev *pdev)
2116{
2117 bool reset_enable;
2118 int reqs, ret;
2119
2120 /* FIXME: Hardcode number of outstanding requests for now */
2121 reqs = 32;
2122 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2123 reqs = 1;
2124 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2125
2126 /* Only allow access to user-accessible pages */
2127 ret = pci_enable_pasid(pdev, 0);
2128 if (ret)
2129 goto out_err;
2130
2131 /* First reset the PRI state of the device */
2132 ret = pci_reset_pri(pdev);
2133 if (ret)
2134 goto out_err;
2135
2136 /* Enable PRI */
2137 ret = pci_enable_pri(pdev, reqs);
2138 if (ret)
2139 goto out_err;
2140
2141 if (reset_enable) {
2142 ret = pri_reset_while_enabled(pdev);
2143 if (ret)
2144 goto out_err;
2145 }
2146
2147 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2148 if (ret)
2149 goto out_err;
2150
2151 return 0;
2152
2153out_err:
2154 pci_disable_pri(pdev);
2155 pci_disable_pasid(pdev);
2156
2157 return ret;
2158}
2159
2160/*
2161 * If a device is not yet associated with a domain, this function makes the
2162 * device visible in the domain
2163 */
2164static int attach_device(struct device *dev,
2165 struct protection_domain *domain)
2166{
2167 struct pci_dev *pdev;
2168 struct iommu_dev_data *dev_data;
2169 unsigned long flags;
2170 int ret;
2171
2172 spin_lock_irqsave(&domain->lock, flags);
2173
2174 dev_data = get_dev_data(dev);
2175
2176 spin_lock(&dev_data->lock);
2177
2178 ret = -EBUSY;
2179 if (dev_data->domain != NULL)
2180 goto out;
2181
2182 if (!dev_is_pci(dev))
2183 goto skip_ats_check;
2184
2185 pdev = to_pci_dev(dev);
2186 if (domain->flags & PD_IOMMUV2_MASK) {
2187 ret = -EINVAL;
2188 if (!dev_data->passthrough)
2189 goto out;
2190
2191 if (dev_data->iommu_v2) {
2192 if (pdev_iommuv2_enable(pdev) != 0)
2193 goto out;
2194
2195 dev_data->ats.enabled = true;
2196 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2197 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2198 }
2199 } else if (amd_iommu_iotlb_sup &&
2200 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2201 dev_data->ats.enabled = true;
2202 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2203 }
2204
2205skip_ats_check:
2206 ret = 0;
2207
2208 do_attach(dev_data, domain);
2209
2210 /*
2211 * We might boot into a crash-kernel here. The crashed kernel
2212 * left the caches in the IOMMU dirty. So we have to flush
2213 * here to evict all dirty stuff.
2214 */
2215 domain_flush_tlb_pde(domain);
2216
2217 domain_flush_complete(domain);
2218
2219out:
2220 spin_unlock(&dev_data->lock);
2221
2222 spin_unlock_irqrestore(&domain->lock, flags);
2223
2224 return ret;
2225}
2226
2227/*
2228 * Removes a device from a protection domain (with devtable_lock held)
2229 */
2230static void detach_device(struct device *dev)
2231{
2232 struct protection_domain *domain;
2233 struct iommu_dev_data *dev_data;
2234 unsigned long flags;
2235
2236 dev_data = get_dev_data(dev);
2237 domain = dev_data->domain;
2238
2239 spin_lock_irqsave(&domain->lock, flags);
2240
2241 spin_lock(&dev_data->lock);
2242
2243 /*
2244 * First check if the device is still attached. It might already
2245 * be detached from its domain because the generic
2246 * iommu_detach_group code detached it and we try again here in
2247 * our alias handling.
2248 */
2249 if (WARN_ON(!dev_data->domain))
2250 goto out;
2251
2252 do_detach(dev_data);
2253
2254 if (!dev_is_pci(dev))
2255 goto out;
2256
2257 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2258 pdev_iommuv2_disable(to_pci_dev(dev));
2259 else if (dev_data->ats.enabled)
2260 pci_disable_ats(to_pci_dev(dev));
2261
2262 dev_data->ats.enabled = false;
2263
2264out:
2265 spin_unlock(&dev_data->lock);
2266
2267 spin_unlock_irqrestore(&domain->lock, flags);
2268}
2269
2270static int amd_iommu_add_device(struct device *dev)
2271{
2272 struct iommu_dev_data *dev_data;
2273 struct iommu_domain *domain;
2274 struct amd_iommu *iommu;
2275 int ret, devid;
2276
2277 if (!check_device(dev) || get_dev_data(dev))
2278 return 0;
2279
2280 devid = get_device_id(dev);
2281 if (devid < 0)
2282 return devid;
2283
2284 iommu = amd_iommu_rlookup_table[devid];
2285
2286 ret = iommu_init_device(dev);
2287 if (ret) {
2288 if (ret != -ENOTSUPP)
2289 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2290
2291 iommu_ignore_device(dev);
2292 dev->dma_ops = NULL;
2293 goto out;
2294 }
2295 init_iommu_group(dev);
2296
2297 dev_data = get_dev_data(dev);
2298
2299 BUG_ON(!dev_data);
2300
2301 if (dev_data->iommu_v2)
2302 iommu_request_dm_for_dev(dev);
2303
2304 /* Domains are initialized for this device - have a look what we ended up with */
2305 domain = iommu_get_domain_for_dev(dev);
2306 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2307 dev_data->passthrough = true;
2308 else
2309 dev->dma_ops = &amd_iommu_dma_ops;
2310
2311out:
2312 iommu_completion_wait(iommu);
2313
2314 return 0;
2315}
2316
2317static void amd_iommu_remove_device(struct device *dev)
2318{
2319 struct amd_iommu *iommu;
2320 int devid;
2321
2322 if (!check_device(dev))
2323 return;
2324
2325 devid = get_device_id(dev);
2326 if (devid < 0)
2327 return;
2328
2329 iommu = amd_iommu_rlookup_table[devid];
2330
2331 iommu_uninit_device(dev);
2332 iommu_completion_wait(iommu);
2333}
2334
2335static struct iommu_group *amd_iommu_device_group(struct device *dev)
2336{
2337 if (dev_is_pci(dev))
2338 return pci_device_group(dev);
2339
2340 return acpihid_device_group(dev);
2341}
2342
2343/*****************************************************************************
2344 *
2345 * The next functions belong to the dma_ops mapping/unmapping code.
2346 *
2347 *****************************************************************************/
2348
2349/*
2350 * In the dma_ops path we only have the struct device. This function
2351 * finds the corresponding IOMMU, the protection domain and the
2352 * requestor id for a given device.
2353 * If the device is not yet associated with a domain this is also done
2354 * in this function.
2355 */
2356static struct protection_domain *get_domain(struct device *dev)
2357{
2358 struct protection_domain *domain;
2359 struct iommu_domain *io_domain;
2360
2361 if (!check_device(dev))
2362 return ERR_PTR(-EINVAL);
2363
2364 domain = get_dev_data(dev)->domain;
2365 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2366 get_dev_data(dev)->defer_attach = false;
2367 io_domain = iommu_get_domain_for_dev(dev);
2368 domain = to_pdomain(io_domain);
2369 attach_device(dev, domain);
2370 }
2371 if (domain == NULL)
2372 return ERR_PTR(-EBUSY);
2373
2374 if (!dma_ops_domain(domain))
2375 return ERR_PTR(-EBUSY);
2376
2377 return domain;
2378}
2379
2380static void update_device_table(struct protection_domain *domain)
2381{
2382 struct iommu_dev_data *dev_data;
2383
2384 list_for_each_entry(dev_data, &domain->dev_list, list) {
2385 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2386 dev_data->iommu_v2);
2387
2388 if (dev_data->devid == dev_data->alias)
2389 continue;
2390
2391 /* There is an alias, update device table entry for it */
2392 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2393 dev_data->iommu_v2);
2394 }
2395}
2396
2397static void update_domain(struct protection_domain *domain)
2398{
2399 update_device_table(domain);
2400
2401 domain_flush_devices(domain);
2402 domain_flush_tlb_pde(domain);
2403}
2404
2405static int dir2prot(enum dma_data_direction direction)
2406{
2407 if (direction == DMA_TO_DEVICE)
2408 return IOMMU_PROT_IR;
2409 else if (direction == DMA_FROM_DEVICE)
2410 return IOMMU_PROT_IW;
2411 else if (direction == DMA_BIDIRECTIONAL)
2412 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2413 else
2414 return 0;
2415}
2416
2417/*
2418 * This function contains common code for mapping of a physically
2419 * contiguous memory region into DMA address space. It is used by all
2420 * mapping functions provided with this IOMMU driver.
2421 * Must be called with the domain lock held.
2422 */
2423static dma_addr_t __map_single(struct device *dev,
2424 struct dma_ops_domain *dma_dom,
2425 phys_addr_t paddr,
2426 size_t size,
2427 enum dma_data_direction direction,
2428 u64 dma_mask)
2429{
2430 dma_addr_t offset = paddr & ~PAGE_MASK;
2431 dma_addr_t address, start, ret;
2432 unsigned long flags;
2433 unsigned int pages;
2434 int prot = 0;
2435 int i;
2436
2437 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2438 paddr &= PAGE_MASK;
2439
2440 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2441 if (!address)
2442 goto out;
2443
2444 prot = dir2prot(direction);
2445
2446 start = address;
2447 for (i = 0; i < pages; ++i) {
2448 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2449 PAGE_SIZE, prot, GFP_ATOMIC);
2450 if (ret)
2451 goto out_unmap;
2452
2453 paddr += PAGE_SIZE;
2454 start += PAGE_SIZE;
2455 }
2456 address += offset;
2457
2458 domain_flush_np_cache(&dma_dom->domain, address, size);
2459
2460out:
2461 return address;
2462
2463out_unmap:
2464
2465 for (--i; i >= 0; --i) {
2466 start -= PAGE_SIZE;
2467 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2468 }
2469
2470 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2471 domain_flush_tlb(&dma_dom->domain);
2472 domain_flush_complete(&dma_dom->domain);
2473 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2474
2475 dma_ops_free_iova(dma_dom, address, pages);
2476
2477 return DMA_MAPPING_ERROR;
2478}
2479
2480/*
2481 * Does the reverse of the __map_single function. Must be called with
2482 * the domain lock held too
2483 */
2484static void __unmap_single(struct dma_ops_domain *dma_dom,
2485 dma_addr_t dma_addr,
2486 size_t size,
2487 int dir)
2488{
2489 dma_addr_t i, start;
2490 unsigned int pages;
2491
2492 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2493 dma_addr &= PAGE_MASK;
2494 start = dma_addr;
2495
2496 for (i = 0; i < pages; ++i) {
2497 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2498 start += PAGE_SIZE;
2499 }
2500
2501 if (amd_iommu_unmap_flush) {
2502 unsigned long flags;
2503
2504 spin_lock_irqsave(&dma_dom->domain.lock, flags);
2505 domain_flush_tlb(&dma_dom->domain);
2506 domain_flush_complete(&dma_dom->domain);
2507 spin_unlock_irqrestore(&dma_dom->domain.lock, flags);
2508 dma_ops_free_iova(dma_dom, dma_addr, pages);
2509 } else {
2510 pages = __roundup_pow_of_two(pages);
2511 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2512 }
2513}
2514
2515/*
2516 * The exported map_single function for dma_ops.
2517 */
2518static dma_addr_t map_page(struct device *dev, struct page *page,
2519 unsigned long offset, size_t size,
2520 enum dma_data_direction dir,
2521 unsigned long attrs)
2522{
2523 phys_addr_t paddr = page_to_phys(page) + offset;
2524 struct protection_domain *domain;
2525 struct dma_ops_domain *dma_dom;
2526 u64 dma_mask;
2527
2528 domain = get_domain(dev);
2529 if (PTR_ERR(domain) == -EINVAL)
2530 return (dma_addr_t)paddr;
2531 else if (IS_ERR(domain))
2532 return DMA_MAPPING_ERROR;
2533
2534 dma_mask = *dev->dma_mask;
2535 dma_dom = to_dma_ops_domain(domain);
2536
2537 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2538}
2539
2540/*
2541 * The exported unmap_single function for dma_ops.
2542 */
2543static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2544 enum dma_data_direction dir, unsigned long attrs)
2545{
2546 struct protection_domain *domain;
2547 struct dma_ops_domain *dma_dom;
2548
2549 domain = get_domain(dev);
2550 if (IS_ERR(domain))
2551 return;
2552
2553 dma_dom = to_dma_ops_domain(domain);
2554
2555 __unmap_single(dma_dom, dma_addr, size, dir);
2556}
2557
2558static int sg_num_pages(struct device *dev,
2559 struct scatterlist *sglist,
2560 int nelems)
2561{
2562 unsigned long mask, boundary_size;
2563 struct scatterlist *s;
2564 int i, npages = 0;
2565
2566 mask = dma_get_seg_boundary(dev);
2567 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2568 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2569
2570 for_each_sg(sglist, s, nelems, i) {
2571 int p, n;
2572
2573 s->dma_address = npages << PAGE_SHIFT;
2574 p = npages % boundary_size;
2575 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2576 if (p + n > boundary_size)
2577 npages += boundary_size - p;
2578 npages += n;
2579 }
2580
2581 return npages;
2582}
2583
2584/*
2585 * The exported map_sg function for dma_ops (handles scatter-gather
2586 * lists).
2587 */
2588static int map_sg(struct device *dev, struct scatterlist *sglist,
2589 int nelems, enum dma_data_direction direction,
2590 unsigned long attrs)
2591{
2592 int mapped_pages = 0, npages = 0, prot = 0, i;
2593 struct protection_domain *domain;
2594 struct dma_ops_domain *dma_dom;
2595 struct scatterlist *s;
2596 unsigned long address;
2597 u64 dma_mask;
2598 int ret;
2599
2600 domain = get_domain(dev);
2601 if (IS_ERR(domain))
2602 return 0;
2603
2604 dma_dom = to_dma_ops_domain(domain);
2605 dma_mask = *dev->dma_mask;
2606
2607 npages = sg_num_pages(dev, sglist, nelems);
2608
2609 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2610 if (!address)
2611 goto out_err;
2612
2613 prot = dir2prot(direction);
2614
2615 /* Map all sg entries */
2616 for_each_sg(sglist, s, nelems, i) {
2617 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2618
2619 for (j = 0; j < pages; ++j) {
2620 unsigned long bus_addr, phys_addr;
2621
2622 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2623 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2624 ret = iommu_map_page(domain, bus_addr, phys_addr,
2625 PAGE_SIZE, prot,
2626 GFP_ATOMIC | __GFP_NOWARN);
2627 if (ret)
2628 goto out_unmap;
2629
2630 mapped_pages += 1;
2631 }
2632 }
2633
2634 /* Everything is mapped - write the right values into s->dma_address */
2635 for_each_sg(sglist, s, nelems, i) {
2636 /*
2637 * Add in the remaining piece of the scatter-gather offset that
2638 * was masked out when we were determining the physical address
2639 * via (sg_phys(s) & PAGE_MASK) earlier.
2640 */
2641 s->dma_address += address + (s->offset & ~PAGE_MASK);
2642 s->dma_length = s->length;
2643 }
2644
2645 if (s)
2646 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2647
2648 return nelems;
2649
2650out_unmap:
2651 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2652 npages, ret);
2653
2654 for_each_sg(sglist, s, nelems, i) {
2655 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2656
2657 for (j = 0; j < pages; ++j) {
2658 unsigned long bus_addr;
2659
2660 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2661 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2662
2663 if (--mapped_pages == 0)
2664 goto out_free_iova;
2665 }
2666 }
2667
2668out_free_iova:
2669 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2670
2671out_err:
2672 return 0;
2673}
2674
2675/*
2676 * The exported map_sg function for dma_ops (handles scatter-gather
2677 * lists).
2678 */
2679static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2680 int nelems, enum dma_data_direction dir,
2681 unsigned long attrs)
2682{
2683 struct protection_domain *domain;
2684 struct dma_ops_domain *dma_dom;
2685 unsigned long startaddr;
2686 int npages;
2687
2688 domain = get_domain(dev);
2689 if (IS_ERR(domain))
2690 return;
2691
2692 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2693 dma_dom = to_dma_ops_domain(domain);
2694 npages = sg_num_pages(dev, sglist, nelems);
2695
2696 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2697}
2698
2699/*
2700 * The exported alloc_coherent function for dma_ops.
2701 */
2702static void *alloc_coherent(struct device *dev, size_t size,
2703 dma_addr_t *dma_addr, gfp_t flag,
2704 unsigned long attrs)
2705{
2706 u64 dma_mask = dev->coherent_dma_mask;
2707 struct protection_domain *domain;
2708 struct dma_ops_domain *dma_dom;
2709 struct page *page;
2710
2711 domain = get_domain(dev);
2712 if (PTR_ERR(domain) == -EINVAL) {
2713 page = alloc_pages(flag, get_order(size));
2714 *dma_addr = page_to_phys(page);
2715 return page_address(page);
2716 } else if (IS_ERR(domain))
2717 return NULL;
2718
2719 dma_dom = to_dma_ops_domain(domain);
2720 size = PAGE_ALIGN(size);
2721 dma_mask = dev->coherent_dma_mask;
2722 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2723 flag |= __GFP_ZERO;
2724
2725 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2726 if (!page) {
2727 if (!gfpflags_allow_blocking(flag))
2728 return NULL;
2729
2730 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2731 get_order(size), flag & __GFP_NOWARN);
2732 if (!page)
2733 return NULL;
2734 }
2735
2736 if (!dma_mask)
2737 dma_mask = *dev->dma_mask;
2738
2739 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2740 size, DMA_BIDIRECTIONAL, dma_mask);
2741
2742 if (*dma_addr == DMA_MAPPING_ERROR)
2743 goto out_free;
2744
2745 return page_address(page);
2746
2747out_free:
2748
2749 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2750 __free_pages(page, get_order(size));
2751
2752 return NULL;
2753}
2754
2755/*
2756 * The exported free_coherent function for dma_ops.
2757 */
2758static void free_coherent(struct device *dev, size_t size,
2759 void *virt_addr, dma_addr_t dma_addr,
2760 unsigned long attrs)
2761{
2762 struct protection_domain *domain;
2763 struct dma_ops_domain *dma_dom;
2764 struct page *page;
2765
2766 page = virt_to_page(virt_addr);
2767 size = PAGE_ALIGN(size);
2768
2769 domain = get_domain(dev);
2770 if (IS_ERR(domain))
2771 goto free_mem;
2772
2773 dma_dom = to_dma_ops_domain(domain);
2774
2775 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2776
2777free_mem:
2778 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2779 __free_pages(page, get_order(size));
2780}
2781
2782/*
2783 * This function is called by the DMA layer to find out if we can handle a
2784 * particular device. It is part of the dma_ops.
2785 */
2786static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2787{
2788 if (!dma_direct_supported(dev, mask))
2789 return 0;
2790 return check_device(dev);
2791}
2792
2793static const struct dma_map_ops amd_iommu_dma_ops = {
2794 .alloc = alloc_coherent,
2795 .free = free_coherent,
2796 .map_page = map_page,
2797 .unmap_page = unmap_page,
2798 .map_sg = map_sg,
2799 .unmap_sg = unmap_sg,
2800 .dma_supported = amd_iommu_dma_supported,
2801 .mmap = dma_common_mmap,
2802 .get_sgtable = dma_common_get_sgtable,
2803};
2804
2805static int init_reserved_iova_ranges(void)
2806{
2807 struct pci_dev *pdev = NULL;
2808 struct iova *val;
2809
2810 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2811
2812 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2813 &reserved_rbtree_key);
2814
2815 /* MSI memory range */
2816 val = reserve_iova(&reserved_iova_ranges,
2817 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2818 if (!val) {
2819 pr_err("Reserving MSI range failed\n");
2820 return -ENOMEM;
2821 }
2822
2823 /* HT memory range */
2824 val = reserve_iova(&reserved_iova_ranges,
2825 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2826 if (!val) {
2827 pr_err("Reserving HT range failed\n");
2828 return -ENOMEM;
2829 }
2830
2831 /*
2832 * Memory used for PCI resources
2833 * FIXME: Check whether we can reserve the PCI-hole completly
2834 */
2835 for_each_pci_dev(pdev) {
2836 int i;
2837
2838 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2839 struct resource *r = &pdev->resource[i];
2840
2841 if (!(r->flags & IORESOURCE_MEM))
2842 continue;
2843
2844 val = reserve_iova(&reserved_iova_ranges,
2845 IOVA_PFN(r->start),
2846 IOVA_PFN(r->end));
2847 if (!val) {
2848 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2849 return -ENOMEM;
2850 }
2851 }
2852 }
2853
2854 return 0;
2855}
2856
2857int __init amd_iommu_init_api(void)
2858{
2859 int ret, err = 0;
2860
2861 ret = iova_cache_get();
2862 if (ret)
2863 return ret;
2864
2865 ret = init_reserved_iova_ranges();
2866 if (ret)
2867 return ret;
2868
2869 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2870 if (err)
2871 return err;
2872#ifdef CONFIG_ARM_AMBA
2873 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2874 if (err)
2875 return err;
2876#endif
2877 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2878 if (err)
2879 return err;
2880
2881 return 0;
2882}
2883
2884int __init amd_iommu_init_dma_ops(void)
2885{
2886 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
2887 iommu_detected = 1;
2888
2889 if (amd_iommu_unmap_flush)
2890 pr_info("IO/TLB flush on unmap enabled\n");
2891 else
2892 pr_info("Lazy IO/TLB flushing enabled\n");
2893
2894 return 0;
2895
2896}
2897
2898/*****************************************************************************
2899 *
2900 * The following functions belong to the exported interface of AMD IOMMU
2901 *
2902 * This interface allows access to lower level functions of the IOMMU
2903 * like protection domain handling and assignement of devices to domains
2904 * which is not possible with the dma_ops interface.
2905 *
2906 *****************************************************************************/
2907
2908static void cleanup_domain(struct protection_domain *domain)
2909{
2910 struct iommu_dev_data *entry;
2911 unsigned long flags;
2912
2913 spin_lock_irqsave(&domain->lock, flags);
2914
2915 while (!list_empty(&domain->dev_list)) {
2916 entry = list_first_entry(&domain->dev_list,
2917 struct iommu_dev_data, list);
2918 BUG_ON(!entry->domain);
2919 do_detach(entry);
2920 }
2921
2922 spin_unlock_irqrestore(&domain->lock, flags);
2923}
2924
2925static void protection_domain_free(struct protection_domain *domain)
2926{
2927 if (!domain)
2928 return;
2929
2930 if (domain->id)
2931 domain_id_free(domain->id);
2932
2933 kfree(domain);
2934}
2935
2936static int protection_domain_init(struct protection_domain *domain)
2937{
2938 spin_lock_init(&domain->lock);
2939 mutex_init(&domain->api_lock);
2940 domain->id = domain_id_alloc();
2941 if (!domain->id)
2942 return -ENOMEM;
2943 INIT_LIST_HEAD(&domain->dev_list);
2944
2945 return 0;
2946}
2947
2948static struct protection_domain *protection_domain_alloc(void)
2949{
2950 struct protection_domain *domain;
2951
2952 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2953 if (!domain)
2954 return NULL;
2955
2956 if (protection_domain_init(domain))
2957 goto out_err;
2958
2959 return domain;
2960
2961out_err:
2962 kfree(domain);
2963
2964 return NULL;
2965}
2966
2967static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2968{
2969 struct protection_domain *pdomain;
2970 struct dma_ops_domain *dma_domain;
2971
2972 switch (type) {
2973 case IOMMU_DOMAIN_UNMANAGED:
2974 pdomain = protection_domain_alloc();
2975 if (!pdomain)
2976 return NULL;
2977
2978 pdomain->mode = PAGE_MODE_3_LEVEL;
2979 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2980 if (!pdomain->pt_root) {
2981 protection_domain_free(pdomain);
2982 return NULL;
2983 }
2984
2985 pdomain->domain.geometry.aperture_start = 0;
2986 pdomain->domain.geometry.aperture_end = ~0ULL;
2987 pdomain->domain.geometry.force_aperture = true;
2988
2989 break;
2990 case IOMMU_DOMAIN_DMA:
2991 dma_domain = dma_ops_domain_alloc();
2992 if (!dma_domain) {
2993 pr_err("Failed to allocate\n");
2994 return NULL;
2995 }
2996 pdomain = &dma_domain->domain;
2997 break;
2998 case IOMMU_DOMAIN_IDENTITY:
2999 pdomain = protection_domain_alloc();
3000 if (!pdomain)
3001 return NULL;
3002
3003 pdomain->mode = PAGE_MODE_NONE;
3004 break;
3005 default:
3006 return NULL;
3007 }
3008
3009 return &pdomain->domain;
3010}
3011
3012static void amd_iommu_domain_free(struct iommu_domain *dom)
3013{
3014 struct protection_domain *domain;
3015 struct dma_ops_domain *dma_dom;
3016
3017 domain = to_pdomain(dom);
3018
3019 if (domain->dev_cnt > 0)
3020 cleanup_domain(domain);
3021
3022 BUG_ON(domain->dev_cnt != 0);
3023
3024 if (!dom)
3025 return;
3026
3027 switch (dom->type) {
3028 case IOMMU_DOMAIN_DMA:
3029 /* Now release the domain */
3030 dma_dom = to_dma_ops_domain(domain);
3031 dma_ops_domain_free(dma_dom);
3032 break;
3033 default:
3034 if (domain->mode != PAGE_MODE_NONE)
3035 free_pagetable(domain);
3036
3037 if (domain->flags & PD_IOMMUV2_MASK)
3038 free_gcr3_table(domain);
3039
3040 protection_domain_free(domain);
3041 break;
3042 }
3043}
3044
3045static void amd_iommu_detach_device(struct iommu_domain *dom,
3046 struct device *dev)
3047{
3048 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3049 struct amd_iommu *iommu;
3050 int devid;
3051
3052 if (!check_device(dev))
3053 return;
3054
3055 devid = get_device_id(dev);
3056 if (devid < 0)
3057 return;
3058
3059 if (dev_data->domain != NULL)
3060 detach_device(dev);
3061
3062 iommu = amd_iommu_rlookup_table[devid];
3063 if (!iommu)
3064 return;
3065
3066#ifdef CONFIG_IRQ_REMAP
3067 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3068 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3069 dev_data->use_vapic = 0;
3070#endif
3071
3072 iommu_completion_wait(iommu);
3073}
3074
3075static int amd_iommu_attach_device(struct iommu_domain *dom,
3076 struct device *dev)
3077{
3078 struct protection_domain *domain = to_pdomain(dom);
3079 struct iommu_dev_data *dev_data;
3080 struct amd_iommu *iommu;
3081 int ret;
3082
3083 if (!check_device(dev))
3084 return -EINVAL;
3085
3086 dev_data = dev->archdata.iommu;
3087
3088 iommu = amd_iommu_rlookup_table[dev_data->devid];
3089 if (!iommu)
3090 return -EINVAL;
3091
3092 if (dev_data->domain)
3093 detach_device(dev);
3094
3095 ret = attach_device(dev, domain);
3096
3097#ifdef CONFIG_IRQ_REMAP
3098 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3099 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3100 dev_data->use_vapic = 1;
3101 else
3102 dev_data->use_vapic = 0;
3103 }
3104#endif
3105
3106 iommu_completion_wait(iommu);
3107
3108 return ret;
3109}
3110
3111static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3112 phys_addr_t paddr, size_t page_size, int iommu_prot)
3113{
3114 struct protection_domain *domain = to_pdomain(dom);
3115 int prot = 0;
3116 int ret;
3117
3118 if (domain->mode == PAGE_MODE_NONE)
3119 return -EINVAL;
3120
3121 if (iommu_prot & IOMMU_READ)
3122 prot |= IOMMU_PROT_IR;
3123 if (iommu_prot & IOMMU_WRITE)
3124 prot |= IOMMU_PROT_IW;
3125
3126 mutex_lock(&domain->api_lock);
3127 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3128 mutex_unlock(&domain->api_lock);
3129
3130 domain_flush_np_cache(domain, iova, page_size);
3131
3132 return ret;
3133}
3134
3135static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3136 size_t page_size,
3137 struct iommu_iotlb_gather *gather)
3138{
3139 struct protection_domain *domain = to_pdomain(dom);
3140 size_t unmap_size;
3141
3142 if (domain->mode == PAGE_MODE_NONE)
3143 return 0;
3144
3145 mutex_lock(&domain->api_lock);
3146 unmap_size = iommu_unmap_page(domain, iova, page_size);
3147 mutex_unlock(&domain->api_lock);
3148
3149 return unmap_size;
3150}
3151
3152static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3153 dma_addr_t iova)
3154{
3155 struct protection_domain *domain = to_pdomain(dom);
3156 unsigned long offset_mask, pte_pgsize;
3157 u64 *pte, __pte;
3158
3159 if (domain->mode == PAGE_MODE_NONE)
3160 return iova;
3161
3162 pte = fetch_pte(domain, iova, &pte_pgsize);
3163
3164 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3165 return 0;
3166
3167 offset_mask = pte_pgsize - 1;
3168 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3169
3170 return (__pte & ~offset_mask) | (iova & offset_mask);
3171}
3172
3173static bool amd_iommu_capable(enum iommu_cap cap)
3174{
3175 switch (cap) {
3176 case IOMMU_CAP_CACHE_COHERENCY:
3177 return true;
3178 case IOMMU_CAP_INTR_REMAP:
3179 return (irq_remapping_enabled == 1);
3180 case IOMMU_CAP_NOEXEC:
3181 return false;
3182 default:
3183 break;
3184 }
3185
3186 return false;
3187}
3188
3189static void amd_iommu_get_resv_regions(struct device *dev,
3190 struct list_head *head)
3191{
3192 struct iommu_resv_region *region;
3193 struct unity_map_entry *entry;
3194 int devid;
3195
3196 devid = get_device_id(dev);
3197 if (devid < 0)
3198 return;
3199
3200 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3201 int type, prot = 0;
3202 size_t length;
3203
3204 if (devid < entry->devid_start || devid > entry->devid_end)
3205 continue;
3206
3207 type = IOMMU_RESV_DIRECT;
3208 length = entry->address_end - entry->address_start;
3209 if (entry->prot & IOMMU_PROT_IR)
3210 prot |= IOMMU_READ;
3211 if (entry->prot & IOMMU_PROT_IW)
3212 prot |= IOMMU_WRITE;
3213 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3214 /* Exclusion range */
3215 type = IOMMU_RESV_RESERVED;
3216
3217 region = iommu_alloc_resv_region(entry->address_start,
3218 length, prot, type);
3219 if (!region) {
3220 dev_err(dev, "Out of memory allocating dm-regions\n");
3221 return;
3222 }
3223 list_add_tail(®ion->list, head);
3224 }
3225
3226 region = iommu_alloc_resv_region(MSI_RANGE_START,
3227 MSI_RANGE_END - MSI_RANGE_START + 1,
3228 0, IOMMU_RESV_MSI);
3229 if (!region)
3230 return;
3231 list_add_tail(®ion->list, head);
3232
3233 region = iommu_alloc_resv_region(HT_RANGE_START,
3234 HT_RANGE_END - HT_RANGE_START + 1,
3235 0, IOMMU_RESV_RESERVED);
3236 if (!region)
3237 return;
3238 list_add_tail(®ion->list, head);
3239}
3240
3241static void amd_iommu_put_resv_regions(struct device *dev,
3242 struct list_head *head)
3243{
3244 struct iommu_resv_region *entry, *next;
3245
3246 list_for_each_entry_safe(entry, next, head, list)
3247 kfree(entry);
3248}
3249
3250static void amd_iommu_apply_resv_region(struct device *dev,
3251 struct iommu_domain *domain,
3252 struct iommu_resv_region *region)
3253{
3254 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3255 unsigned long start, end;
3256
3257 start = IOVA_PFN(region->start);
3258 end = IOVA_PFN(region->start + region->length - 1);
3259
3260 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3261}
3262
3263static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3264 struct device *dev)
3265{
3266 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3267 return dev_data->defer_attach;
3268}
3269
3270static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3271{
3272 struct protection_domain *dom = to_pdomain(domain);
3273 unsigned long flags;
3274
3275 spin_lock_irqsave(&dom->lock, flags);
3276 domain_flush_tlb_pde(dom);
3277 domain_flush_complete(dom);
3278 spin_unlock_irqrestore(&dom->lock, flags);
3279}
3280
3281static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
3282 struct iommu_iotlb_gather *gather)
3283{
3284 amd_iommu_flush_iotlb_all(domain);
3285}
3286
3287const struct iommu_ops amd_iommu_ops = {
3288 .capable = amd_iommu_capable,
3289 .domain_alloc = amd_iommu_domain_alloc,
3290 .domain_free = amd_iommu_domain_free,
3291 .attach_dev = amd_iommu_attach_device,
3292 .detach_dev = amd_iommu_detach_device,
3293 .map = amd_iommu_map,
3294 .unmap = amd_iommu_unmap,
3295 .iova_to_phys = amd_iommu_iova_to_phys,
3296 .add_device = amd_iommu_add_device,
3297 .remove_device = amd_iommu_remove_device,
3298 .device_group = amd_iommu_device_group,
3299 .get_resv_regions = amd_iommu_get_resv_regions,
3300 .put_resv_regions = amd_iommu_put_resv_regions,
3301 .apply_resv_region = amd_iommu_apply_resv_region,
3302 .is_attach_deferred = amd_iommu_is_attach_deferred,
3303 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3304 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3305 .iotlb_sync = amd_iommu_iotlb_sync,
3306};
3307
3308/*****************************************************************************
3309 *
3310 * The next functions do a basic initialization of IOMMU for pass through
3311 * mode
3312 *
3313 * In passthrough mode the IOMMU is initialized and enabled but not used for
3314 * DMA-API translation.
3315 *
3316 *****************************************************************************/
3317
3318/* IOMMUv2 specific functions */
3319int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3320{
3321 return atomic_notifier_chain_register(&ppr_notifier, nb);
3322}
3323EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3324
3325int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3326{
3327 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3328}
3329EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3330
3331void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3332{
3333 struct protection_domain *domain = to_pdomain(dom);
3334 unsigned long flags;
3335
3336 spin_lock_irqsave(&domain->lock, flags);
3337
3338 /* Update data structure */
3339 domain->mode = PAGE_MODE_NONE;
3340
3341 /* Make changes visible to IOMMUs */
3342 update_domain(domain);
3343
3344 /* Page-table is not visible to IOMMU anymore, so free it */
3345 free_pagetable(domain);
3346
3347 spin_unlock_irqrestore(&domain->lock, flags);
3348}
3349EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3350
3351int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3352{
3353 struct protection_domain *domain = to_pdomain(dom);
3354 unsigned long flags;
3355 int levels, ret;
3356
3357 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3358 return -EINVAL;
3359
3360 /* Number of GCR3 table levels required */
3361 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3362 levels += 1;
3363
3364 if (levels > amd_iommu_max_glx_val)
3365 return -EINVAL;
3366
3367 spin_lock_irqsave(&domain->lock, flags);
3368
3369 /*
3370 * Save us all sanity checks whether devices already in the
3371 * domain support IOMMUv2. Just force that the domain has no
3372 * devices attached when it is switched into IOMMUv2 mode.
3373 */
3374 ret = -EBUSY;
3375 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3376 goto out;
3377
3378 ret = -ENOMEM;
3379 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3380 if (domain->gcr3_tbl == NULL)
3381 goto out;
3382
3383 domain->glx = levels;
3384 domain->flags |= PD_IOMMUV2_MASK;
3385
3386 update_domain(domain);
3387
3388 ret = 0;
3389
3390out:
3391 spin_unlock_irqrestore(&domain->lock, flags);
3392
3393 return ret;
3394}
3395EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3396
3397static int __flush_pasid(struct protection_domain *domain, int pasid,
3398 u64 address, bool size)
3399{
3400 struct iommu_dev_data *dev_data;
3401 struct iommu_cmd cmd;
3402 int i, ret;
3403
3404 if (!(domain->flags & PD_IOMMUV2_MASK))
3405 return -EINVAL;
3406
3407 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3408
3409 /*
3410 * IOMMU TLB needs to be flushed before Device TLB to
3411 * prevent device TLB refill from IOMMU TLB
3412 */
3413 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3414 if (domain->dev_iommu[i] == 0)
3415 continue;
3416
3417 ret = iommu_queue_command(amd_iommus[i], &cmd);
3418 if (ret != 0)
3419 goto out;
3420 }
3421
3422 /* Wait until IOMMU TLB flushes are complete */
3423 domain_flush_complete(domain);
3424
3425 /* Now flush device TLBs */
3426 list_for_each_entry(dev_data, &domain->dev_list, list) {
3427 struct amd_iommu *iommu;
3428 int qdep;
3429
3430 /*
3431 There might be non-IOMMUv2 capable devices in an IOMMUv2
3432 * domain.
3433 */
3434 if (!dev_data->ats.enabled)
3435 continue;
3436
3437 qdep = dev_data->ats.qdep;
3438 iommu = amd_iommu_rlookup_table[dev_data->devid];
3439
3440 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3441 qdep, address, size);
3442
3443 ret = iommu_queue_command(iommu, &cmd);
3444 if (ret != 0)
3445 goto out;
3446 }
3447
3448 /* Wait until all device TLBs are flushed */
3449 domain_flush_complete(domain);
3450
3451 ret = 0;
3452
3453out:
3454
3455 return ret;
3456}
3457
3458static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3459 u64 address)
3460{
3461 return __flush_pasid(domain, pasid, address, false);
3462}
3463
3464int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3465 u64 address)
3466{
3467 struct protection_domain *domain = to_pdomain(dom);
3468 unsigned long flags;
3469 int ret;
3470
3471 spin_lock_irqsave(&domain->lock, flags);
3472 ret = __amd_iommu_flush_page(domain, pasid, address);
3473 spin_unlock_irqrestore(&domain->lock, flags);
3474
3475 return ret;
3476}
3477EXPORT_SYMBOL(amd_iommu_flush_page);
3478
3479static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3480{
3481 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3482 true);
3483}
3484
3485int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3486{
3487 struct protection_domain *domain = to_pdomain(dom);
3488 unsigned long flags;
3489 int ret;
3490
3491 spin_lock_irqsave(&domain->lock, flags);
3492 ret = __amd_iommu_flush_tlb(domain, pasid);
3493 spin_unlock_irqrestore(&domain->lock, flags);
3494
3495 return ret;
3496}
3497EXPORT_SYMBOL(amd_iommu_flush_tlb);
3498
3499static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3500{
3501 int index;
3502 u64 *pte;
3503
3504 while (true) {
3505
3506 index = (pasid >> (9 * level)) & 0x1ff;
3507 pte = &root[index];
3508
3509 if (level == 0)
3510 break;
3511
3512 if (!(*pte & GCR3_VALID)) {
3513 if (!alloc)
3514 return NULL;
3515
3516 root = (void *)get_zeroed_page(GFP_ATOMIC);
3517 if (root == NULL)
3518 return NULL;
3519
3520 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3521 }
3522
3523 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3524
3525 level -= 1;
3526 }
3527
3528 return pte;
3529}
3530
3531static int __set_gcr3(struct protection_domain *domain, int pasid,
3532 unsigned long cr3)
3533{
3534 u64 *pte;
3535
3536 if (domain->mode != PAGE_MODE_NONE)
3537 return -EINVAL;
3538
3539 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3540 if (pte == NULL)
3541 return -ENOMEM;
3542
3543 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3544
3545 return __amd_iommu_flush_tlb(domain, pasid);
3546}
3547
3548static int __clear_gcr3(struct protection_domain *domain, int pasid)
3549{
3550 u64 *pte;
3551
3552 if (domain->mode != PAGE_MODE_NONE)
3553 return -EINVAL;
3554
3555 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3556 if (pte == NULL)
3557 return 0;
3558
3559 *pte = 0;
3560
3561 return __amd_iommu_flush_tlb(domain, pasid);
3562}
3563
3564int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3565 unsigned long cr3)
3566{
3567 struct protection_domain *domain = to_pdomain(dom);
3568 unsigned long flags;
3569 int ret;
3570
3571 spin_lock_irqsave(&domain->lock, flags);
3572 ret = __set_gcr3(domain, pasid, cr3);
3573 spin_unlock_irqrestore(&domain->lock, flags);
3574
3575 return ret;
3576}
3577EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3578
3579int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3580{
3581 struct protection_domain *domain = to_pdomain(dom);
3582 unsigned long flags;
3583 int ret;
3584
3585 spin_lock_irqsave(&domain->lock, flags);
3586 ret = __clear_gcr3(domain, pasid);
3587 spin_unlock_irqrestore(&domain->lock, flags);
3588
3589 return ret;
3590}
3591EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3592
3593int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3594 int status, int tag)
3595{
3596 struct iommu_dev_data *dev_data;
3597 struct amd_iommu *iommu;
3598 struct iommu_cmd cmd;
3599
3600 dev_data = get_dev_data(&pdev->dev);
3601 iommu = amd_iommu_rlookup_table[dev_data->devid];
3602
3603 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3604 tag, dev_data->pri_tlp);
3605
3606 return iommu_queue_command(iommu, &cmd);
3607}
3608EXPORT_SYMBOL(amd_iommu_complete_ppr);
3609
3610struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3611{
3612 struct protection_domain *pdomain;
3613
3614 pdomain = get_domain(&pdev->dev);
3615 if (IS_ERR(pdomain))
3616 return NULL;
3617
3618 /* Only return IOMMUv2 domains */
3619 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3620 return NULL;
3621
3622 return &pdomain->domain;
3623}
3624EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3625
3626void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3627{
3628 struct iommu_dev_data *dev_data;
3629
3630 if (!amd_iommu_v2_supported())
3631 return;
3632
3633 dev_data = get_dev_data(&pdev->dev);
3634 dev_data->errata |= (1 << erratum);
3635}
3636EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3637
3638int amd_iommu_device_info(struct pci_dev *pdev,
3639 struct amd_iommu_device_info *info)
3640{
3641 int max_pasids;
3642 int pos;
3643
3644 if (pdev == NULL || info == NULL)
3645 return -EINVAL;
3646
3647 if (!amd_iommu_v2_supported())
3648 return -EINVAL;
3649
3650 memset(info, 0, sizeof(*info));
3651
3652 if (!pci_ats_disabled()) {
3653 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3654 if (pos)
3655 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3656 }
3657
3658 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3659 if (pos)
3660 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3661
3662 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3663 if (pos) {
3664 int features;
3665
3666 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3667 max_pasids = min(max_pasids, (1 << 20));
3668
3669 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3670 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3671
3672 features = pci_pasid_features(pdev);
3673 if (features & PCI_PASID_CAP_EXEC)
3674 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3675 if (features & PCI_PASID_CAP_PRIV)
3676 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3677 }
3678
3679 return 0;
3680}
3681EXPORT_SYMBOL(amd_iommu_device_info);
3682
3683#ifdef CONFIG_IRQ_REMAP
3684
3685/*****************************************************************************
3686 *
3687 * Interrupt Remapping Implementation
3688 *
3689 *****************************************************************************/
3690
3691static struct irq_chip amd_ir_chip;
3692static DEFINE_SPINLOCK(iommu_table_lock);
3693
3694static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3695{
3696 u64 dte;
3697
3698 dte = amd_iommu_dev_table[devid].data[2];
3699 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3700 dte |= iommu_virt_to_phys(table->table);
3701 dte |= DTE_IRQ_REMAP_INTCTL;
3702 dte |= DTE_IRQ_TABLE_LEN;
3703 dte |= DTE_IRQ_REMAP_ENABLE;
3704
3705 amd_iommu_dev_table[devid].data[2] = dte;
3706}
3707
3708static struct irq_remap_table *get_irq_table(u16 devid)
3709{
3710 struct irq_remap_table *table;
3711
3712 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3713 "%s: no iommu for devid %x\n", __func__, devid))
3714 return NULL;
3715
3716 table = irq_lookup_table[devid];
3717 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3718 return NULL;
3719
3720 return table;
3721}
3722
3723static struct irq_remap_table *__alloc_irq_table(void)
3724{
3725 struct irq_remap_table *table;
3726
3727 table = kzalloc(sizeof(*table), GFP_KERNEL);
3728 if (!table)
3729 return NULL;
3730
3731 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3732 if (!table->table) {
3733 kfree(table);
3734 return NULL;
3735 }
3736 raw_spin_lock_init(&table->lock);
3737
3738 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3739 memset(table->table, 0,
3740 MAX_IRQS_PER_TABLE * sizeof(u32));
3741 else
3742 memset(table->table, 0,
3743 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3744 return table;
3745}
3746
3747static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3748 struct irq_remap_table *table)
3749{
3750 irq_lookup_table[devid] = table;
3751 set_dte_irq_entry(devid, table);
3752 iommu_flush_dte(iommu, devid);
3753}
3754
3755static struct irq_remap_table *alloc_irq_table(u16 devid)
3756{
3757 struct irq_remap_table *table = NULL;
3758 struct irq_remap_table *new_table = NULL;
3759 struct amd_iommu *iommu;
3760 unsigned long flags;
3761 u16 alias;
3762
3763 spin_lock_irqsave(&iommu_table_lock, flags);
3764
3765 iommu = amd_iommu_rlookup_table[devid];
3766 if (!iommu)
3767 goto out_unlock;
3768
3769 table = irq_lookup_table[devid];
3770 if (table)
3771 goto out_unlock;
3772
3773 alias = amd_iommu_alias_table[devid];
3774 table = irq_lookup_table[alias];
3775 if (table) {
3776 set_remap_table_entry(iommu, devid, table);
3777 goto out_wait;
3778 }
3779 spin_unlock_irqrestore(&iommu_table_lock, flags);
3780
3781 /* Nothing there yet, allocate new irq remapping table */
3782 new_table = __alloc_irq_table();
3783 if (!new_table)
3784 return NULL;
3785
3786 spin_lock_irqsave(&iommu_table_lock, flags);
3787
3788 table = irq_lookup_table[devid];
3789 if (table)
3790 goto out_unlock;
3791
3792 table = irq_lookup_table[alias];
3793 if (table) {
3794 set_remap_table_entry(iommu, devid, table);
3795 goto out_wait;
3796 }
3797
3798 table = new_table;
3799 new_table = NULL;
3800
3801 set_remap_table_entry(iommu, devid, table);
3802 if (devid != alias)
3803 set_remap_table_entry(iommu, alias, table);
3804
3805out_wait:
3806 iommu_completion_wait(iommu);
3807
3808out_unlock:
3809 spin_unlock_irqrestore(&iommu_table_lock, flags);
3810
3811 if (new_table) {
3812 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3813 kfree(new_table);
3814 }
3815 return table;
3816}
3817
3818static int alloc_irq_index(u16 devid, int count, bool align)
3819{
3820 struct irq_remap_table *table;
3821 int index, c, alignment = 1;
3822 unsigned long flags;
3823 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3824
3825 if (!iommu)
3826 return -ENODEV;
3827
3828 table = alloc_irq_table(devid);
3829 if (!table)
3830 return -ENODEV;
3831
3832 if (align)
3833 alignment = roundup_pow_of_two(count);
3834
3835 raw_spin_lock_irqsave(&table->lock, flags);
3836
3837 /* Scan table for free entries */
3838 for (index = ALIGN(table->min_index, alignment), c = 0;
3839 index < MAX_IRQS_PER_TABLE;) {
3840 if (!iommu->irte_ops->is_allocated(table, index)) {
3841 c += 1;
3842 } else {
3843 c = 0;
3844 index = ALIGN(index + 1, alignment);
3845 continue;
3846 }
3847
3848 if (c == count) {
3849 for (; c != 0; --c)
3850 iommu->irte_ops->set_allocated(table, index - c + 1);
3851
3852 index -= count - 1;
3853 goto out;
3854 }
3855
3856 index++;
3857 }
3858
3859 index = -ENOSPC;
3860
3861out:
3862 raw_spin_unlock_irqrestore(&table->lock, flags);
3863
3864 return index;
3865}
3866
3867static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3868 struct amd_ir_data *data)
3869{
3870 struct irq_remap_table *table;
3871 struct amd_iommu *iommu;
3872 unsigned long flags;
3873 struct irte_ga *entry;
3874
3875 iommu = amd_iommu_rlookup_table[devid];
3876 if (iommu == NULL)
3877 return -EINVAL;
3878
3879 table = get_irq_table(devid);
3880 if (!table)
3881 return -ENOMEM;
3882
3883 raw_spin_lock_irqsave(&table->lock, flags);
3884
3885 entry = (struct irte_ga *)table->table;
3886 entry = &entry[index];
3887 entry->lo.fields_remap.valid = 0;
3888 entry->hi.val = irte->hi.val;
3889 entry->lo.val = irte->lo.val;
3890 entry->lo.fields_remap.valid = 1;
3891 if (data)
3892 data->ref = entry;
3893
3894 raw_spin_unlock_irqrestore(&table->lock, flags);
3895
3896 iommu_flush_irt(iommu, devid);
3897 iommu_completion_wait(iommu);
3898
3899 return 0;
3900}
3901
3902static int modify_irte(u16 devid, int index, union irte *irte)
3903{
3904 struct irq_remap_table *table;
3905 struct amd_iommu *iommu;
3906 unsigned long flags;
3907
3908 iommu = amd_iommu_rlookup_table[devid];
3909 if (iommu == NULL)
3910 return -EINVAL;
3911
3912 table = get_irq_table(devid);
3913 if (!table)
3914 return -ENOMEM;
3915
3916 raw_spin_lock_irqsave(&table->lock, flags);
3917 table->table[index] = irte->val;
3918 raw_spin_unlock_irqrestore(&table->lock, flags);
3919
3920 iommu_flush_irt(iommu, devid);
3921 iommu_completion_wait(iommu);
3922
3923 return 0;
3924}
3925
3926static void free_irte(u16 devid, int index)
3927{
3928 struct irq_remap_table *table;
3929 struct amd_iommu *iommu;
3930 unsigned long flags;
3931
3932 iommu = amd_iommu_rlookup_table[devid];
3933 if (iommu == NULL)
3934 return;
3935
3936 table = get_irq_table(devid);
3937 if (!table)
3938 return;
3939
3940 raw_spin_lock_irqsave(&table->lock, flags);
3941 iommu->irte_ops->clear_allocated(table, index);
3942 raw_spin_unlock_irqrestore(&table->lock, flags);
3943
3944 iommu_flush_irt(iommu, devid);
3945 iommu_completion_wait(iommu);
3946}
3947
3948static void irte_prepare(void *entry,
3949 u32 delivery_mode, u32 dest_mode,
3950 u8 vector, u32 dest_apicid, int devid)
3951{
3952 union irte *irte = (union irte *) entry;
3953
3954 irte->val = 0;
3955 irte->fields.vector = vector;
3956 irte->fields.int_type = delivery_mode;
3957 irte->fields.destination = dest_apicid;
3958 irte->fields.dm = dest_mode;
3959 irte->fields.valid = 1;
3960}
3961
3962static void irte_ga_prepare(void *entry,
3963 u32 delivery_mode, u32 dest_mode,
3964 u8 vector, u32 dest_apicid, int devid)
3965{
3966 struct irte_ga *irte = (struct irte_ga *) entry;
3967
3968 irte->lo.val = 0;
3969 irte->hi.val = 0;
3970 irte->lo.fields_remap.int_type = delivery_mode;
3971 irte->lo.fields_remap.dm = dest_mode;
3972 irte->hi.fields.vector = vector;
3973 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3974 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3975 irte->lo.fields_remap.valid = 1;
3976}
3977
3978static void irte_activate(void *entry, u16 devid, u16 index)
3979{
3980 union irte *irte = (union irte *) entry;
3981
3982 irte->fields.valid = 1;
3983 modify_irte(devid, index, irte);
3984}
3985
3986static void irte_ga_activate(void *entry, u16 devid, u16 index)
3987{
3988 struct irte_ga *irte = (struct irte_ga *) entry;
3989
3990 irte->lo.fields_remap.valid = 1;
3991 modify_irte_ga(devid, index, irte, NULL);
3992}
3993
3994static void irte_deactivate(void *entry, u16 devid, u16 index)
3995{
3996 union irte *irte = (union irte *) entry;
3997
3998 irte->fields.valid = 0;
3999 modify_irte(devid, index, irte);
4000}
4001
4002static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
4003{
4004 struct irte_ga *irte = (struct irte_ga *) entry;
4005
4006 irte->lo.fields_remap.valid = 0;
4007 modify_irte_ga(devid, index, irte, NULL);
4008}
4009
4010static void irte_set_affinity(void *entry, u16 devid, u16 index,
4011 u8 vector, u32 dest_apicid)
4012{
4013 union irte *irte = (union irte *) entry;
4014
4015 irte->fields.vector = vector;
4016 irte->fields.destination = dest_apicid;
4017 modify_irte(devid, index, irte);
4018}
4019
4020static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
4021 u8 vector, u32 dest_apicid)
4022{
4023 struct irte_ga *irte = (struct irte_ga *) entry;
4024
4025 if (!irte->lo.fields_remap.guest_mode) {
4026 irte->hi.fields.vector = vector;
4027 irte->lo.fields_remap.destination =
4028 APICID_TO_IRTE_DEST_LO(dest_apicid);
4029 irte->hi.fields.destination =
4030 APICID_TO_IRTE_DEST_HI(dest_apicid);
4031 modify_irte_ga(devid, index, irte, NULL);
4032 }
4033}
4034
4035#define IRTE_ALLOCATED (~1U)
4036static void irte_set_allocated(struct irq_remap_table *table, int index)
4037{
4038 table->table[index] = IRTE_ALLOCATED;
4039}
4040
4041static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
4042{
4043 struct irte_ga *ptr = (struct irte_ga *)table->table;
4044 struct irte_ga *irte = &ptr[index];
4045
4046 memset(&irte->lo.val, 0, sizeof(u64));
4047 memset(&irte->hi.val, 0, sizeof(u64));
4048 irte->hi.fields.vector = 0xff;
4049}
4050
4051static bool irte_is_allocated(struct irq_remap_table *table, int index)
4052{
4053 union irte *ptr = (union irte *)table->table;
4054 union irte *irte = &ptr[index];
4055
4056 return irte->val != 0;
4057}
4058
4059static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4060{
4061 struct irte_ga *ptr = (struct irte_ga *)table->table;
4062 struct irte_ga *irte = &ptr[index];
4063
4064 return irte->hi.fields.vector != 0;
4065}
4066
4067static void irte_clear_allocated(struct irq_remap_table *table, int index)
4068{
4069 table->table[index] = 0;
4070}
4071
4072static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4073{
4074 struct irte_ga *ptr = (struct irte_ga *)table->table;
4075 struct irte_ga *irte = &ptr[index];
4076
4077 memset(&irte->lo.val, 0, sizeof(u64));
4078 memset(&irte->hi.val, 0, sizeof(u64));
4079}
4080
4081static int get_devid(struct irq_alloc_info *info)
4082{
4083 int devid = -1;
4084
4085 switch (info->type) {
4086 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4087 devid = get_ioapic_devid(info->ioapic_id);
4088 break;
4089 case X86_IRQ_ALLOC_TYPE_HPET:
4090 devid = get_hpet_devid(info->hpet_id);
4091 break;
4092 case X86_IRQ_ALLOC_TYPE_MSI:
4093 case X86_IRQ_ALLOC_TYPE_MSIX:
4094 devid = get_device_id(&info->msi_dev->dev);
4095 break;
4096 default:
4097 BUG_ON(1);
4098 break;
4099 }
4100
4101 return devid;
4102}
4103
4104static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4105{
4106 struct amd_iommu *iommu;
4107 int devid;
4108
4109 if (!info)
4110 return NULL;
4111
4112 devid = get_devid(info);
4113 if (devid >= 0) {
4114 iommu = amd_iommu_rlookup_table[devid];
4115 if (iommu)
4116 return iommu->ir_domain;
4117 }
4118
4119 return NULL;
4120}
4121
4122static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4123{
4124 struct amd_iommu *iommu;
4125 int devid;
4126
4127 if (!info)
4128 return NULL;
4129
4130 switch (info->type) {
4131 case X86_IRQ_ALLOC_TYPE_MSI:
4132 case X86_IRQ_ALLOC_TYPE_MSIX:
4133 devid = get_device_id(&info->msi_dev->dev);
4134 if (devid < 0)
4135 return NULL;
4136
4137 iommu = amd_iommu_rlookup_table[devid];
4138 if (iommu)
4139 return iommu->msi_domain;
4140 break;
4141 default:
4142 break;
4143 }
4144
4145 return NULL;
4146}
4147
4148struct irq_remap_ops amd_iommu_irq_ops = {
4149 .prepare = amd_iommu_prepare,
4150 .enable = amd_iommu_enable,
4151 .disable = amd_iommu_disable,
4152 .reenable = amd_iommu_reenable,
4153 .enable_faulting = amd_iommu_enable_faulting,
4154 .get_ir_irq_domain = get_ir_irq_domain,
4155 .get_irq_domain = get_irq_domain,
4156};
4157
4158static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4159 struct irq_cfg *irq_cfg,
4160 struct irq_alloc_info *info,
4161 int devid, int index, int sub_handle)
4162{
4163 struct irq_2_irte *irte_info = &data->irq_2_irte;
4164 struct msi_msg *msg = &data->msi_entry;
4165 struct IO_APIC_route_entry *entry;
4166 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4167
4168 if (!iommu)
4169 return;
4170
4171 data->irq_2_irte.devid = devid;
4172 data->irq_2_irte.index = index + sub_handle;
4173 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4174 apic->irq_dest_mode, irq_cfg->vector,
4175 irq_cfg->dest_apicid, devid);
4176
4177 switch (info->type) {
4178 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4179 /* Setup IOAPIC entry */
4180 entry = info->ioapic_entry;
4181 info->ioapic_entry = NULL;
4182 memset(entry, 0, sizeof(*entry));
4183 entry->vector = index;
4184 entry->mask = 0;
4185 entry->trigger = info->ioapic_trigger;
4186 entry->polarity = info->ioapic_polarity;
4187 /* Mask level triggered irqs. */
4188 if (info->ioapic_trigger)
4189 entry->mask = 1;
4190 break;
4191
4192 case X86_IRQ_ALLOC_TYPE_HPET:
4193 case X86_IRQ_ALLOC_TYPE_MSI:
4194 case X86_IRQ_ALLOC_TYPE_MSIX:
4195 msg->address_hi = MSI_ADDR_BASE_HI;
4196 msg->address_lo = MSI_ADDR_BASE_LO;
4197 msg->data = irte_info->index;
4198 break;
4199
4200 default:
4201 BUG_ON(1);
4202 break;
4203 }
4204}
4205
4206struct amd_irte_ops irte_32_ops = {
4207 .prepare = irte_prepare,
4208 .activate = irte_activate,
4209 .deactivate = irte_deactivate,
4210 .set_affinity = irte_set_affinity,
4211 .set_allocated = irte_set_allocated,
4212 .is_allocated = irte_is_allocated,
4213 .clear_allocated = irte_clear_allocated,
4214};
4215
4216struct amd_irte_ops irte_128_ops = {
4217 .prepare = irte_ga_prepare,
4218 .activate = irte_ga_activate,
4219 .deactivate = irte_ga_deactivate,
4220 .set_affinity = irte_ga_set_affinity,
4221 .set_allocated = irte_ga_set_allocated,
4222 .is_allocated = irte_ga_is_allocated,
4223 .clear_allocated = irte_ga_clear_allocated,
4224};
4225
4226static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4227 unsigned int nr_irqs, void *arg)
4228{
4229 struct irq_alloc_info *info = arg;
4230 struct irq_data *irq_data;
4231 struct amd_ir_data *data = NULL;
4232 struct irq_cfg *cfg;
4233 int i, ret, devid;
4234 int index;
4235
4236 if (!info)
4237 return -EINVAL;
4238 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4239 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4240 return -EINVAL;
4241
4242 /*
4243 * With IRQ remapping enabled, don't need contiguous CPU vectors
4244 * to support multiple MSI interrupts.
4245 */
4246 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4247 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4248
4249 devid = get_devid(info);
4250 if (devid < 0)
4251 return -EINVAL;
4252
4253 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4254 if (ret < 0)
4255 return ret;
4256
4257 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4258 struct irq_remap_table *table;
4259 struct amd_iommu *iommu;
4260
4261 table = alloc_irq_table(devid);
4262 if (table) {
4263 if (!table->min_index) {
4264 /*
4265 * Keep the first 32 indexes free for IOAPIC
4266 * interrupts.
4267 */
4268 table->min_index = 32;
4269 iommu = amd_iommu_rlookup_table[devid];
4270 for (i = 0; i < 32; ++i)
4271 iommu->irte_ops->set_allocated(table, i);
4272 }
4273 WARN_ON(table->min_index != 32);
4274 index = info->ioapic_pin;
4275 } else {
4276 index = -ENOMEM;
4277 }
4278 } else {
4279 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4280
4281 index = alloc_irq_index(devid, nr_irqs, align);
4282 }
4283 if (index < 0) {
4284 pr_warn("Failed to allocate IRTE\n");
4285 ret = index;
4286 goto out_free_parent;
4287 }
4288
4289 for (i = 0; i < nr_irqs; i++) {
4290 irq_data = irq_domain_get_irq_data(domain, virq + i);
4291 cfg = irqd_cfg(irq_data);
4292 if (!irq_data || !cfg) {
4293 ret = -EINVAL;
4294 goto out_free_data;
4295 }
4296
4297 ret = -ENOMEM;
4298 data = kzalloc(sizeof(*data), GFP_KERNEL);
4299 if (!data)
4300 goto out_free_data;
4301
4302 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4303 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4304 else
4305 data->entry = kzalloc(sizeof(struct irte_ga),
4306 GFP_KERNEL);
4307 if (!data->entry) {
4308 kfree(data);
4309 goto out_free_data;
4310 }
4311
4312 irq_data->hwirq = (devid << 16) + i;
4313 irq_data->chip_data = data;
4314 irq_data->chip = &amd_ir_chip;
4315 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4316 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4317 }
4318
4319 return 0;
4320
4321out_free_data:
4322 for (i--; i >= 0; i--) {
4323 irq_data = irq_domain_get_irq_data(domain, virq + i);
4324 if (irq_data)
4325 kfree(irq_data->chip_data);
4326 }
4327 for (i = 0; i < nr_irqs; i++)
4328 free_irte(devid, index + i);
4329out_free_parent:
4330 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4331 return ret;
4332}
4333
4334static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4335 unsigned int nr_irqs)
4336{
4337 struct irq_2_irte *irte_info;
4338 struct irq_data *irq_data;
4339 struct amd_ir_data *data;
4340 int i;
4341
4342 for (i = 0; i < nr_irqs; i++) {
4343 irq_data = irq_domain_get_irq_data(domain, virq + i);
4344 if (irq_data && irq_data->chip_data) {
4345 data = irq_data->chip_data;
4346 irte_info = &data->irq_2_irte;
4347 free_irte(irte_info->devid, irte_info->index);
4348 kfree(data->entry);
4349 kfree(data);
4350 }
4351 }
4352 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4353}
4354
4355static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4356 struct amd_ir_data *ir_data,
4357 struct irq_2_irte *irte_info,
4358 struct irq_cfg *cfg);
4359
4360static int irq_remapping_activate(struct irq_domain *domain,
4361 struct irq_data *irq_data, bool reserve)
4362{
4363 struct amd_ir_data *data = irq_data->chip_data;
4364 struct irq_2_irte *irte_info = &data->irq_2_irte;
4365 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4366 struct irq_cfg *cfg = irqd_cfg(irq_data);
4367
4368 if (!iommu)
4369 return 0;
4370
4371 iommu->irte_ops->activate(data->entry, irte_info->devid,
4372 irte_info->index);
4373 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4374 return 0;
4375}
4376
4377static void irq_remapping_deactivate(struct irq_domain *domain,
4378 struct irq_data *irq_data)
4379{
4380 struct amd_ir_data *data = irq_data->chip_data;
4381 struct irq_2_irte *irte_info = &data->irq_2_irte;
4382 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4383
4384 if (iommu)
4385 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4386 irte_info->index);
4387}
4388
4389static const struct irq_domain_ops amd_ir_domain_ops = {
4390 .alloc = irq_remapping_alloc,
4391 .free = irq_remapping_free,
4392 .activate = irq_remapping_activate,
4393 .deactivate = irq_remapping_deactivate,
4394};
4395
4396int amd_iommu_activate_guest_mode(void *data)
4397{
4398 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4399 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4400
4401 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4402 !entry || entry->lo.fields_vapic.guest_mode)
4403 return 0;
4404
4405 entry->lo.val = 0;
4406 entry->hi.val = 0;
4407
4408 entry->lo.fields_vapic.guest_mode = 1;
4409 entry->lo.fields_vapic.ga_log_intr = 1;
4410 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
4411 entry->hi.fields.vector = ir_data->ga_vector;
4412 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
4413
4414 return modify_irte_ga(ir_data->irq_2_irte.devid,
4415 ir_data->irq_2_irte.index, entry, NULL);
4416}
4417EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
4418
4419int amd_iommu_deactivate_guest_mode(void *data)
4420{
4421 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4422 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4423 struct irq_cfg *cfg = ir_data->cfg;
4424
4425 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4426 !entry || !entry->lo.fields_vapic.guest_mode)
4427 return 0;
4428
4429 entry->lo.val = 0;
4430 entry->hi.val = 0;
4431
4432 entry->lo.fields_remap.dm = apic->irq_dest_mode;
4433 entry->lo.fields_remap.int_type = apic->irq_delivery_mode;
4434 entry->hi.fields.vector = cfg->vector;
4435 entry->lo.fields_remap.destination =
4436 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4437 entry->hi.fields.destination =
4438 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4439
4440 return modify_irte_ga(ir_data->irq_2_irte.devid,
4441 ir_data->irq_2_irte.index, entry, NULL);
4442}
4443EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
4444
4445static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4446{
4447 int ret;
4448 struct amd_iommu *iommu;
4449 struct amd_iommu_pi_data *pi_data = vcpu_info;
4450 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4451 struct amd_ir_data *ir_data = data->chip_data;
4452 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4453 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4454
4455 /* Note:
4456 * This device has never been set up for guest mode.
4457 * we should not modify the IRTE
4458 */
4459 if (!dev_data || !dev_data->use_vapic)
4460 return 0;
4461
4462 ir_data->cfg = irqd_cfg(data);
4463 pi_data->ir_data = ir_data;
4464
4465 /* Note:
4466 * SVM tries to set up for VAPIC mode, but we are in
4467 * legacy mode. So, we force legacy mode instead.
4468 */
4469 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4470 pr_debug("%s: Fall back to using intr legacy remap\n",
4471 __func__);
4472 pi_data->is_guest_mode = false;
4473 }
4474
4475 iommu = amd_iommu_rlookup_table[irte_info->devid];
4476 if (iommu == NULL)
4477 return -EINVAL;
4478
4479 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4480 if (pi_data->is_guest_mode) {
4481 ir_data->ga_root_ptr = (pi_data->base >> 12);
4482 ir_data->ga_vector = vcpu_pi_info->vector;
4483 ir_data->ga_tag = pi_data->ga_tag;
4484 ret = amd_iommu_activate_guest_mode(ir_data);
4485 if (!ret)
4486 ir_data->cached_ga_tag = pi_data->ga_tag;
4487 } else {
4488 ret = amd_iommu_deactivate_guest_mode(ir_data);
4489
4490 /*
4491 * This communicates the ga_tag back to the caller
4492 * so that it can do all the necessary clean up.
4493 */
4494 if (!ret)
4495 ir_data->cached_ga_tag = 0;
4496 }
4497
4498 return ret;
4499}
4500
4501
4502static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4503 struct amd_ir_data *ir_data,
4504 struct irq_2_irte *irte_info,
4505 struct irq_cfg *cfg)
4506{
4507
4508 /*
4509 * Atomically updates the IRTE with the new destination, vector
4510 * and flushes the interrupt entry cache.
4511 */
4512 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4513 irte_info->index, cfg->vector,
4514 cfg->dest_apicid);
4515}
4516
4517static int amd_ir_set_affinity(struct irq_data *data,
4518 const struct cpumask *mask, bool force)
4519{
4520 struct amd_ir_data *ir_data = data->chip_data;
4521 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4522 struct irq_cfg *cfg = irqd_cfg(data);
4523 struct irq_data *parent = data->parent_data;
4524 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4525 int ret;
4526
4527 if (!iommu)
4528 return -ENODEV;
4529
4530 ret = parent->chip->irq_set_affinity(parent, mask, force);
4531 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4532 return ret;
4533
4534 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4535 /*
4536 * After this point, all the interrupts will start arriving
4537 * at the new destination. So, time to cleanup the previous
4538 * vector allocation.
4539 */
4540 send_cleanup_vector(cfg);
4541
4542 return IRQ_SET_MASK_OK_DONE;
4543}
4544
4545static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4546{
4547 struct amd_ir_data *ir_data = irq_data->chip_data;
4548
4549 *msg = ir_data->msi_entry;
4550}
4551
4552static struct irq_chip amd_ir_chip = {
4553 .name = "AMD-IR",
4554 .irq_ack = apic_ack_irq,
4555 .irq_set_affinity = amd_ir_set_affinity,
4556 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4557 .irq_compose_msi_msg = ir_compose_msi_msg,
4558};
4559
4560int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4561{
4562 struct fwnode_handle *fn;
4563
4564 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4565 if (!fn)
4566 return -ENOMEM;
4567 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4568 irq_domain_free_fwnode(fn);
4569 if (!iommu->ir_domain)
4570 return -ENOMEM;
4571
4572 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4573 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4574 "AMD-IR-MSI",
4575 iommu->index);
4576 return 0;
4577}
4578
4579int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4580{
4581 unsigned long flags;
4582 struct amd_iommu *iommu;
4583 struct irq_remap_table *table;
4584 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4585 int devid = ir_data->irq_2_irte.devid;
4586 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4587 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4588
4589 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4590 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4591 return 0;
4592
4593 iommu = amd_iommu_rlookup_table[devid];
4594 if (!iommu)
4595 return -ENODEV;
4596
4597 table = get_irq_table(devid);
4598 if (!table)
4599 return -ENODEV;
4600
4601 raw_spin_lock_irqsave(&table->lock, flags);
4602
4603 if (ref->lo.fields_vapic.guest_mode) {
4604 if (cpu >= 0) {
4605 ref->lo.fields_vapic.destination =
4606 APICID_TO_IRTE_DEST_LO(cpu);
4607 ref->hi.fields.destination =
4608 APICID_TO_IRTE_DEST_HI(cpu);
4609 }
4610 ref->lo.fields_vapic.is_run = is_run;
4611 barrier();
4612 }
4613
4614 raw_spin_unlock_irqrestore(&table->lock, flags);
4615
4616 iommu_flush_irt(iommu, devid);
4617 iommu_completion_wait(iommu);
4618 return 0;
4619}
4620EXPORT_SYMBOL(amd_iommu_update_ga);
4621#endif