1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * Support for IDE interfaces on PowerMacs.
   4 *
   5 * These IDE interfaces are memory-mapped and have a DBDMA channel
   6 * for doing DMA.
   7 *
   8 *  Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
   9 *  Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
  10 *
  11 * Some code taken from drivers/ide/ide-dma.c:
  12 *
  13 *  Copyright (c) 1995-1998  Mark Lord
  14 *
  15 * TODO: - Use pre-calculated (kauai) timing tables all the time and
  16 * get rid of the "rounded" tables used previously, so we have the
  17 * same table format for all controllers and can then just have one
  18 * big table
  19 */
  20#include <linux/types.h>
  21#include <linux/kernel.h>
  22#include <linux/init.h>
  23#include <linux/delay.h>
  24#include <linux/ide.h>
  25#include <linux/notifier.h>
  26#include <linux/module.h>
  27#include <linux/reboot.h>
  28#include <linux/pci.h>
  29#include <linux/adb.h>
  30#include <linux/pmu.h>
  31#include <linux/scatterlist.h>
  32#include <linux/slab.h>
  33
  34#include <asm/prom.h>
  35#include <asm/io.h>
  36#include <asm/dbdma.h>
  37#include <asm/ide.h>
  38#include <asm/machdep.h>
  39#include <asm/pmac_feature.h>
  40#include <asm/sections.h>
  41#include <asm/irq.h>
  42#include <asm/mediabay.h>
  43
  44#define DRV_NAME "ide-pmac"
  45
  46#undef IDE_PMAC_DEBUG
  47
  48#define DMA_WAIT_TIMEOUT	50
  49
  50typedef struct pmac_ide_hwif {
  51	unsigned long			regbase;
  52	int				irq;
  53	int				kind;
  54	int				aapl_bus_id;
  55	unsigned			broken_dma : 1;
  56	unsigned			broken_dma_warn : 1;
  57	struct device_node*		node;
  58	struct macio_dev		*mdev;
  59	u32				timings[4];
  60	volatile u32 __iomem *		*kauai_fcr;
  61	ide_hwif_t			*hwif;
  62
  63	/* Those fields are duplicating what is in hwif. We currently
  64	 * can't use the hwif ones because of some assumptions that are
  65	 * beeing done by the generic code about the kind of dma controller
  66	 * and format of the dma table. This will have to be fixed though.
  67	 */
  68	volatile struct dbdma_regs __iomem *	dma_regs;
  69	struct dbdma_cmd*		dma_table_cpu;
  70} pmac_ide_hwif_t;
  71
  72enum {
  73	controller_ohare,	/* OHare based */
  74	controller_heathrow,	/* Heathrow/Paddington */
  75	controller_kl_ata3,	/* KeyLargo ATA-3 */
  76	controller_kl_ata4,	/* KeyLargo ATA-4 */
  77	controller_un_ata6,	/* UniNorth2 ATA-6 */
  78	controller_k2_ata6,	/* K2 ATA-6 */
  79	controller_sh_ata6,	/* Shasta ATA-6 */
  80};
  81
  82static const char* model_name[] = {
  83	"OHare ATA",		/* OHare based */
  84	"Heathrow ATA",		/* Heathrow/Paddington */
  85	"KeyLargo ATA-3",	/* KeyLargo ATA-3 (MDMA only) */
  86	"KeyLargo ATA-4",	/* KeyLargo ATA-4 (UDMA/66) */
  87	"UniNorth ATA-6",	/* UniNorth2 ATA-6 (UDMA/100) */
  88	"K2 ATA-6",		/* K2 ATA-6 (UDMA/100) */
  89	"Shasta ATA-6",		/* Shasta ATA-6 (UDMA/133) */
  90};
  91
  92/*
  93 * Extra registers, both 32-bit little-endian
  94 */
  95#define IDE_TIMING_CONFIG	0x200
  96#define IDE_INTERRUPT		0x300
  97
  98/* Kauai (U2) ATA has different register setup */
  99#define IDE_KAUAI_PIO_CONFIG	0x200
 100#define IDE_KAUAI_ULTRA_CONFIG	0x210
 101#define IDE_KAUAI_POLL_CONFIG	0x220
 102
 103/*
 104 * Timing configuration register definitions
 105 */
 106
 107/* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
 108#define SYSCLK_TICKS(t)		(((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
 109#define SYSCLK_TICKS_66(t)	(((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
 110#define IDE_SYSCLK_NS		30	/* 33Mhz cell */
 111#define IDE_SYSCLK_66_NS	15	/* 66Mhz cell */
 112
 113/* 133Mhz cell, found in shasta.
 114 * See comments about 100 Mhz Uninorth 2...
 115 * Note that PIO_MASK and MDMA_MASK seem to overlap
 116 */
 117#define TR_133_PIOREG_PIO_MASK		0xff000fff
 118#define TR_133_PIOREG_MDMA_MASK		0x00fff800
 119#define TR_133_UDMAREG_UDMA_MASK	0x0003ffff
 120#define TR_133_UDMAREG_UDMA_EN		0x00000001
 121
 122/* 100Mhz cell, found in Uninorth 2. I don't have much infos about
 123 * this one yet, it appears as a pci device (106b/0033) on uninorth
 124 * internal PCI bus and it's clock is controlled like gem or fw. It
 125 * appears to be an evolution of keylargo ATA4 with a timing register
 126 * extended to 2 32bits registers and a similar DBDMA channel. Other
 127 * registers seem to exist but I can't tell much about them.
 128 * 
 129 * So far, I'm using pre-calculated tables for this extracted from
 130 * the values used by the MacOS X driver.
 131 * 
 132 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
 133 * register controls the UDMA timings. At least, it seems bit 0
 134 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
 135 * cycle time in units of 10ns. Bits 8..15 are used by I don't
 136 * know their meaning yet
 137 */
 138#define TR_100_PIOREG_PIO_MASK		0xff000fff
 139#define TR_100_PIOREG_MDMA_MASK		0x00fff000
 140#define TR_100_UDMAREG_UDMA_MASK	0x0000ffff
 141#define TR_100_UDMAREG_UDMA_EN		0x00000001
 142
 143
 144/* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
 145 * 40 connector cable and to 4 on 80 connector one.
 146 * Clock unit is 15ns (66Mhz)
 147 * 
 148 * 3 Values can be programmed:
 149 *  - Write data setup, which appears to match the cycle time. They
 150 *    also call it DIOW setup.
 151 *  - Ready to pause time (from spec)
 152 *  - Address setup. That one is weird. I don't see where exactly
 153 *    it fits in UDMA cycles, I got it's name from an obscure piece
 154 *    of commented out code in Darwin. They leave it to 0, we do as
 155 *    well, despite a comment that would lead to think it has a
 156 *    min value of 45ns.
 157 * Apple also add 60ns to the write data setup (or cycle time ?) on
 158 * reads.
 159 */
 160#define TR_66_UDMA_MASK			0xfff00000
 161#define TR_66_UDMA_EN			0x00100000 /* Enable Ultra mode for DMA */
 162#define TR_66_UDMA_ADDRSETUP_MASK	0xe0000000 /* Address setup */
 163#define TR_66_UDMA_ADDRSETUP_SHIFT	29
 164#define TR_66_UDMA_RDY2PAUS_MASK	0x1e000000 /* Ready 2 pause time */
 165#define TR_66_UDMA_RDY2PAUS_SHIFT	25
 166#define TR_66_UDMA_WRDATASETUP_MASK	0x01e00000 /* Write data setup time */
 167#define TR_66_UDMA_WRDATASETUP_SHIFT	21
 168#define TR_66_MDMA_MASK			0x000ffc00
 169#define TR_66_MDMA_RECOVERY_MASK	0x000f8000
 170#define TR_66_MDMA_RECOVERY_SHIFT	15
 171#define TR_66_MDMA_ACCESS_MASK		0x00007c00
 172#define TR_66_MDMA_ACCESS_SHIFT		10
 173#define TR_66_PIO_MASK			0x000003ff
 174#define TR_66_PIO_RECOVERY_MASK		0x000003e0
 175#define TR_66_PIO_RECOVERY_SHIFT	5
 176#define TR_66_PIO_ACCESS_MASK		0x0000001f
 177#define TR_66_PIO_ACCESS_SHIFT		0
 178
 179/* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
 180 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
 181 * 
 182 * The access time and recovery time can be programmed. Some older
 183 * Darwin code base limit OHare to 150ns cycle time. I decided to do
 184 * the same here fore safety against broken old hardware ;)
 185 * The HalfTick bit, when set, adds half a clock (15ns) to the access
 186 * time and removes one from recovery. It's not supported on KeyLargo
 187 * implementation afaik. The E bit appears to be set for PIO mode 0 and
 188 * is used to reach long timings used in this mode.
 189 */
 190#define TR_33_MDMA_MASK			0x003ff800
 191#define TR_33_MDMA_RECOVERY_MASK	0x001f0000
 192#define TR_33_MDMA_RECOVERY_SHIFT	16
 193#define TR_33_MDMA_ACCESS_MASK		0x0000f800
 194#define TR_33_MDMA_ACCESS_SHIFT		11
 195#define TR_33_MDMA_HALFTICK		0x00200000
 196#define TR_33_PIO_MASK			0x000007ff
 197#define TR_33_PIO_E			0x00000400
 198#define TR_33_PIO_RECOVERY_MASK		0x000003e0
 199#define TR_33_PIO_RECOVERY_SHIFT	5
 200#define TR_33_PIO_ACCESS_MASK		0x0000001f
 201#define TR_33_PIO_ACCESS_SHIFT		0
 202
 203/*
 204 * Interrupt register definitions
 205 */
 206#define IDE_INTR_DMA			0x80000000
 207#define IDE_INTR_DEVICE			0x40000000
 208
 209/*
 210 * FCR Register on Kauai. Not sure what bit 0x4 is  ...
 211 */
 212#define KAUAI_FCR_UATA_MAGIC		0x00000004
 213#define KAUAI_FCR_UATA_RESET_N		0x00000002
 214#define KAUAI_FCR_UATA_ENABLE		0x00000001
 215
 216/* Rounded Multiword DMA timings
 217 * 
 218 * I gave up finding a generic formula for all controller
 219 * types and instead, built tables based on timing values
 220 * used by Apple in Darwin's implementation.
 221 */
 222struct mdma_timings_t {
 223	int	accessTime;
 224	int	recoveryTime;
 225	int	cycleTime;
 226};
 227
 228struct mdma_timings_t mdma_timings_33[] =
 229{
 230    { 240, 240, 480 },
 231    { 180, 180, 360 },
 232    { 135, 135, 270 },
 233    { 120, 120, 240 },
 234    { 105, 105, 210 },
 235    {  90,  90, 180 },
 236    {  75,  75, 150 },
 237    {  75,  45, 120 },
 238    {   0,   0,   0 }
 239};
 240
 241struct mdma_timings_t mdma_timings_33k[] =
 242{
 243    { 240, 240, 480 },
 244    { 180, 180, 360 },
 245    { 150, 150, 300 },
 246    { 120, 120, 240 },
 247    {  90, 120, 210 },
 248    {  90,  90, 180 },
 249    {  90,  60, 150 },
 250    {  90,  30, 120 },
 251    {   0,   0,   0 }
 252};
 253
 254struct mdma_timings_t mdma_timings_66[] =
 255{
 256    { 240, 240, 480 },
 257    { 180, 180, 360 },
 258    { 135, 135, 270 },
 259    { 120, 120, 240 },
 260    { 105, 105, 210 },
 261    {  90,  90, 180 },
 262    {  90,  75, 165 },
 263    {  75,  45, 120 },
 264    {   0,   0,   0 }
 265};
 266
 267/* KeyLargo ATA-4 Ultra DMA timings (rounded) */
 268struct {
 269	int	addrSetup; /* ??? */
 270	int	rdy2pause;
 271	int	wrDataSetup;
 272} kl66_udma_timings[] =
 273{
 274    {   0, 180,  120 },	/* Mode 0 */
 275    {   0, 150,  90 },	/*      1 */
 276    {   0, 120,  60 },	/*      2 */
 277    {   0, 90,   45 },	/*      3 */
 278    {   0, 90,   30 }	/*      4 */
 279};
 280
 281/* UniNorth 2 ATA/100 timings */
 282struct kauai_timing {
 283	int	cycle_time;
 284	u32	timing_reg;
 285};
 286
 287static struct kauai_timing	kauai_pio_timings[] =
 288{
 289	{ 930	, 0x08000fff },
 290	{ 600	, 0x08000a92 },
 291	{ 383	, 0x0800060f },
 292	{ 360	, 0x08000492 },
 293	{ 330	, 0x0800048f },
 294	{ 300	, 0x080003cf },
 295	{ 270	, 0x080003cc },
 296	{ 240	, 0x0800038b },
 297	{ 239	, 0x0800030c },
 298	{ 180	, 0x05000249 },
 299	{ 120	, 0x04000148 },
 300	{ 0	, 0 },
 301};
 302
 303static struct kauai_timing	kauai_mdma_timings[] =
 304{
 305	{ 1260	, 0x00fff000 },
 306	{ 480	, 0x00618000 },
 307	{ 360	, 0x00492000 },
 308	{ 270	, 0x0038e000 },
 309	{ 240	, 0x0030c000 },
 310	{ 210	, 0x002cb000 },
 311	{ 180	, 0x00249000 },
 312	{ 150	, 0x00209000 },
 313	{ 120	, 0x00148000 },
 314	{ 0	, 0 },
 315};
 316
 317static struct kauai_timing	kauai_udma_timings[] =
 318{
 319	{ 120	, 0x000070c0 },
 320	{ 90	, 0x00005d80 },
 321	{ 60	, 0x00004a60 },
 322	{ 45	, 0x00003a50 },
 323	{ 30	, 0x00002a30 },
 324	{ 20	, 0x00002921 },
 325	{ 0	, 0 },
 326};
 327
 328static struct kauai_timing	shasta_pio_timings[] =
 329{
 330	{ 930	, 0x08000fff },
 331	{ 600	, 0x0A000c97 },
 332	{ 383	, 0x07000712 },
 333	{ 360	, 0x040003cd },
 334	{ 330	, 0x040003cd },
 335	{ 300	, 0x040003cd },
 336	{ 270	, 0x040003cd },
 337	{ 240	, 0x040003cd },
 338	{ 239	, 0x040003cd },
 339	{ 180	, 0x0400028b },
 340	{ 120	, 0x0400010a },
 341	{ 0	, 0 },
 342};
 343
 344static struct kauai_timing	shasta_mdma_timings[] =
 345{
 346	{ 1260	, 0x00fff000 },
 347	{ 480	, 0x00820800 },
 348	{ 360	, 0x00820800 },
 349	{ 270	, 0x00820800 },
 350	{ 240	, 0x00820800 },
 351	{ 210	, 0x00820800 },
 352	{ 180	, 0x00820800 },
 353	{ 150	, 0x0028b000 },
 354	{ 120	, 0x001ca000 },
 355	{ 0	, 0 },
 356};
 357
 358static struct kauai_timing	shasta_udma133_timings[] =
 359{
 360	{ 120   , 0x00035901, },
 361	{ 90    , 0x000348b1, },
 362	{ 60    , 0x00033881, },
 363	{ 45    , 0x00033861, },
 364	{ 30    , 0x00033841, },
 365	{ 20    , 0x00033031, },
 366	{ 15    , 0x00033021, },
 367	{ 0	, 0 },
 368};
 369
 370
 371static inline u32
 372kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
 373{
 374	int i;
 375	
 376	for (i=0; table[i].cycle_time; i++)
 377		if (cycle_time > table[i+1].cycle_time)
 378			return table[i].timing_reg;
 379	BUG();
 380	return 0;
 381}
 382
 383/* allow up to 256 DBDMA commands per xfer */
 384#define MAX_DCMDS		256
 385
 386/* 
 387 * Wait 1s for disk to answer on IDE bus after a hard reset
 388 * of the device (via GPIO/FCR).
 389 * 
 390 * Some devices seem to "pollute" the bus even after dropping
 391 * the BSY bit (typically some combo drives slave on the UDMA
 392 * bus) after a hard reset. Since we hard reset all drives on
 393 * KeyLargo ATA66, we have to keep that delay around. I may end
 394 * up not hard resetting anymore on these and keep the delay only
 395 * for older interfaces instead (we have to reset when coming
 396 * from MacOS...) --BenH. 
 397 */
 398#define IDE_WAKEUP_DELAY	(1*HZ)
 399
 400static int pmac_ide_init_dma(ide_hwif_t *, const struct ide_port_info *);
 401
 402#define PMAC_IDE_REG(x) \
 403	((void __iomem *)((drive)->hwif->io_ports.data_addr + (x)))
 404
 405/*
 406 * Apply the timings of the proper unit (master/slave) to the shared
 407 * timing register when selecting that unit. This version is for
 408 * ASICs with a single timing register
 409 */
 410static void pmac_ide_apply_timings(ide_drive_t *drive)
 411{
 412	ide_hwif_t *hwif = drive->hwif;
 413	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 414
 415	if (drive->dn & 1)
 416		writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
 417	else
 418		writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
 419	(void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
 420}
 421
 422/*
 423 * Apply the timings of the proper unit (master/slave) to the shared
 424 * timing register when selecting that unit. This version is for
 425 * ASICs with a dual timing register (Kauai)
 426 */
 427static void pmac_ide_kauai_apply_timings(ide_drive_t *drive)
 428{
 429	ide_hwif_t *hwif = drive->hwif;
 430	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 431
 432	if (drive->dn & 1) {
 433		writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 434		writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
 435	} else {
 436		writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 437		writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
 438	}
 439	(void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
 440}
 441
 442/*
 443 * Force an update of controller timing values for a given drive
 444 */
 445static void
 446pmac_ide_do_update_timings(ide_drive_t *drive)
 447{
 448	ide_hwif_t *hwif = drive->hwif;
 449	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 450
 451	if (pmif->kind == controller_sh_ata6 ||
 452	    pmif->kind == controller_un_ata6 ||
 453	    pmif->kind == controller_k2_ata6)
 454		pmac_ide_kauai_apply_timings(drive);
 455	else
 456		pmac_ide_apply_timings(drive);
 457}
 458
 459static void pmac_dev_select(ide_drive_t *drive)
 460{
 461	pmac_ide_apply_timings(drive);
 462
 463	writeb(drive->select | ATA_DEVICE_OBS,
 464	       (void __iomem *)drive->hwif->io_ports.device_addr);
 465}
 466
 467static void pmac_kauai_dev_select(ide_drive_t *drive)
 468{
 469	pmac_ide_kauai_apply_timings(drive);
 470
 471	writeb(drive->select | ATA_DEVICE_OBS,
 472	       (void __iomem *)drive->hwif->io_ports.device_addr);
 473}
 474
 475static void pmac_exec_command(ide_hwif_t *hwif, u8 cmd)
 476{
 477	writeb(cmd, (void __iomem *)hwif->io_ports.command_addr);
 478	(void)readl((void __iomem *)(hwif->io_ports.data_addr
 479				     + IDE_TIMING_CONFIG));
 480}
 481
 482static void pmac_write_devctl(ide_hwif_t *hwif, u8 ctl)
 483{
 484	writeb(ctl, (void __iomem *)hwif->io_ports.ctl_addr);
 485	(void)readl((void __iomem *)(hwif->io_ports.data_addr
 486				     + IDE_TIMING_CONFIG));
 487}
 488
 489/*
 490 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
 491 */
 492static void pmac_ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 493{
 494	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 495	const u8 pio = drive->pio_mode - XFER_PIO_0;
 496	struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
 497	u32 *timings, t;
 498	unsigned accessTicks, recTicks;
 499	unsigned accessTime, recTime;
 500	unsigned int cycle_time;
 501
 502	/* which drive is it ? */
 503	timings = &pmif->timings[drive->dn & 1];
 504	t = *timings;
 505
 506	cycle_time = ide_pio_cycle_time(drive, pio);
 507
 508	switch (pmif->kind) {
 509	case controller_sh_ata6: {
 510		/* 133Mhz cell */
 511		u32 tr = kauai_lookup_timing(shasta_pio_timings, cycle_time);
 512		t = (t & ~TR_133_PIOREG_PIO_MASK) | tr;
 513		break;
 514		}
 515	case controller_un_ata6:
 516	case controller_k2_ata6: {
 517		/* 100Mhz cell */
 518		u32 tr = kauai_lookup_timing(kauai_pio_timings, cycle_time);
 519		t = (t & ~TR_100_PIOREG_PIO_MASK) | tr;
 520		break;
 521		}
 522	case controller_kl_ata4:
 523		/* 66Mhz cell */
 524		recTime = cycle_time - tim->active - tim->setup;
 525		recTime = max(recTime, 150U);
 526		accessTime = tim->active;
 527		accessTime = max(accessTime, 150U);
 528		accessTicks = SYSCLK_TICKS_66(accessTime);
 529		accessTicks = min(accessTicks, 0x1fU);
 530		recTicks = SYSCLK_TICKS_66(recTime);
 531		recTicks = min(recTicks, 0x1fU);
 532		t = (t & ~TR_66_PIO_MASK) |
 533			(accessTicks << TR_66_PIO_ACCESS_SHIFT) |
 534			(recTicks << TR_66_PIO_RECOVERY_SHIFT);
 535		break;
 536	default: {
 537		/* 33Mhz cell */
 538		int ebit = 0;
 539		recTime = cycle_time - tim->active - tim->setup;
 540		recTime = max(recTime, 150U);
 541		accessTime = tim->active;
 542		accessTime = max(accessTime, 150U);
 543		accessTicks = SYSCLK_TICKS(accessTime);
 544		accessTicks = min(accessTicks, 0x1fU);
 545		accessTicks = max(accessTicks, 4U);
 546		recTicks = SYSCLK_TICKS(recTime);
 547		recTicks = min(recTicks, 0x1fU);
 548		recTicks = max(recTicks, 5U) - 4;
 549		if (recTicks > 9) {
 550			recTicks--; /* guess, but it's only for PIO0, so... */
 551			ebit = 1;
 552		}
 553		t = (t & ~TR_33_PIO_MASK) |
 554				(accessTicks << TR_33_PIO_ACCESS_SHIFT) |
 555				(recTicks << TR_33_PIO_RECOVERY_SHIFT);
 556		if (ebit)
 557			t |= TR_33_PIO_E;
 558		break;
 559		}
 560	}
 561
 562#ifdef IDE_PMAC_DEBUG
 563	printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
 564		drive->name, pio,  *timings);
 565#endif	
 566
 567	*timings = t;
 568	pmac_ide_do_update_timings(drive);
 569}
 570
 571/*
 572 * Calculate KeyLargo ATA/66 UDMA timings
 573 */
 574static int
 575set_timings_udma_ata4(u32 *timings, u8 speed)
 576{
 577	unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
 578
 579	if (speed > XFER_UDMA_4)
 580		return 1;
 581
 582	rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
 583	wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
 584	addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
 585
 586	*timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
 587			(wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) | 
 588			(rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
 589			(addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
 590			TR_66_UDMA_EN;
 591#ifdef IDE_PMAC_DEBUG
 592	printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
 593		speed & 0xf,  *timings);
 594#endif	
 595
 596	return 0;
 597}
 598
 599/*
 600 * Calculate Kauai ATA/100 UDMA timings
 601 */
 602static int
 603set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
 604{
 605	struct ide_timing *t = ide_timing_find_mode(speed);
 606	u32 tr;
 607
 608	if (speed > XFER_UDMA_5 || t == NULL)
 609		return 1;
 610	tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
 611	*ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
 612	*ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
 613
 614	return 0;
 615}
 616
 617/*
 618 * Calculate Shasta ATA/133 UDMA timings
 619 */
 620static int
 621set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
 622{
 623	struct ide_timing *t = ide_timing_find_mode(speed);
 624	u32 tr;
 625
 626	if (speed > XFER_UDMA_6 || t == NULL)
 627		return 1;
 628	tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
 629	*ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
 630	*ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
 631
 632	return 0;
 633}
 634
 635/*
 636 * Calculate MDMA timings for all cells
 637 */
 638static void
 639set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
 640		 	u8 speed)
 641{
 642	u16 *id = drive->id;
 643	int cycleTime, accessTime = 0, recTime = 0;
 644	unsigned accessTicks, recTicks;
 645	struct mdma_timings_t* tm = NULL;
 646	int i;
 647
 648	/* Get default cycle time for mode */
 649	switch(speed & 0xf) {
 650		case 0: cycleTime = 480; break;
 651		case 1: cycleTime = 150; break;
 652		case 2: cycleTime = 120; break;
 653		default:
 654			BUG();
 655			break;
 656	}
 657
 658	/* Check if drive provides explicit DMA cycle time */
 659	if ((id[ATA_ID_FIELD_VALID] & 2) && id[ATA_ID_EIDE_DMA_TIME])
 660		cycleTime = max_t(int, id[ATA_ID_EIDE_DMA_TIME], cycleTime);
 661
 662	/* OHare limits according to some old Apple sources */	
 663	if ((intf_type == controller_ohare) && (cycleTime < 150))
 664		cycleTime = 150;
 665	/* Get the proper timing array for this controller */
 666	switch(intf_type) {
 667	        case controller_sh_ata6:
 668		case controller_un_ata6:
 669		case controller_k2_ata6:
 670			break;
 671		case controller_kl_ata4:
 672			tm = mdma_timings_66;
 673			break;
 674		case controller_kl_ata3:
 675			tm = mdma_timings_33k;
 676			break;
 677		default:
 678			tm = mdma_timings_33;
 679			break;
 680	}
 681	if (tm != NULL) {
 682		/* Lookup matching access & recovery times */
 683		i = -1;
 684		for (;;) {
 685			if (tm[i+1].cycleTime < cycleTime)
 686				break;
 687			i++;
 688		}
 689		cycleTime = tm[i].cycleTime;
 690		accessTime = tm[i].accessTime;
 691		recTime = tm[i].recoveryTime;
 692
 693#ifdef IDE_PMAC_DEBUG
 694		printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
 695			drive->name, cycleTime, accessTime, recTime);
 696#endif
 697	}
 698	switch(intf_type) {
 699	case controller_sh_ata6: {
 700		/* 133Mhz cell */
 701		u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
 702		*timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
 703		*timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
 704		}
 705		break;
 706	case controller_un_ata6:
 707	case controller_k2_ata6: {
 708		/* 100Mhz cell */
 709		u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
 710		*timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
 711		*timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
 712		}
 713		break;
 714	case controller_kl_ata4:
 715		/* 66Mhz cell */
 716		accessTicks = SYSCLK_TICKS_66(accessTime);
 717		accessTicks = min(accessTicks, 0x1fU);
 718		accessTicks = max(accessTicks, 0x1U);
 719		recTicks = SYSCLK_TICKS_66(recTime);
 720		recTicks = min(recTicks, 0x1fU);
 721		recTicks = max(recTicks, 0x3U);
 722		/* Clear out mdma bits and disable udma */
 723		*timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
 724			(accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
 725			(recTicks << TR_66_MDMA_RECOVERY_SHIFT);
 726		break;
 727	case controller_kl_ata3:
 728		/* 33Mhz cell on KeyLargo */
 729		accessTicks = SYSCLK_TICKS(accessTime);
 730		accessTicks = max(accessTicks, 1U);
 731		accessTicks = min(accessTicks, 0x1fU);
 732		accessTime = accessTicks * IDE_SYSCLK_NS;
 733		recTicks = SYSCLK_TICKS(recTime);
 734		recTicks = max(recTicks, 1U);
 735		recTicks = min(recTicks, 0x1fU);
 736		*timings = ((*timings) & ~TR_33_MDMA_MASK) |
 737				(accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
 738				(recTicks << TR_33_MDMA_RECOVERY_SHIFT);
 739		break;
 740	default: {
 741		/* 33Mhz cell on others */
 742		int halfTick = 0;
 743		int origAccessTime = accessTime;
 744		int origRecTime = recTime;
 745		
 746		accessTicks = SYSCLK_TICKS(accessTime);
 747		accessTicks = max(accessTicks, 1U);
 748		accessTicks = min(accessTicks, 0x1fU);
 749		accessTime = accessTicks * IDE_SYSCLK_NS;
 750		recTicks = SYSCLK_TICKS(recTime);
 751		recTicks = max(recTicks, 2U) - 1;
 752		recTicks = min(recTicks, 0x1fU);
 753		recTime = (recTicks + 1) * IDE_SYSCLK_NS;
 754		if ((accessTicks > 1) &&
 755		    ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
 756		    ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
 757            		halfTick = 1;
 758			accessTicks--;
 759		}
 760		*timings = ((*timings) & ~TR_33_MDMA_MASK) |
 761				(accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
 762				(recTicks << TR_33_MDMA_RECOVERY_SHIFT);
 763		if (halfTick)
 764			*timings |= TR_33_MDMA_HALFTICK;
 765		}
 766	}
 767#ifdef IDE_PMAC_DEBUG
 768	printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
 769		drive->name, speed & 0xf,  *timings);
 770#endif	
 771}
 772
 773static void pmac_ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 774{
 775	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 776	int ret = 0;
 777	u32 *timings, *timings2, tl[2];
 778	u8 unit = drive->dn & 1;
 779	const u8 speed = drive->dma_mode;
 780
 781	timings = &pmif->timings[unit];
 782	timings2 = &pmif->timings[unit+2];
 783
 784	/* Copy timings to local image */
 785	tl[0] = *timings;
 786	tl[1] = *timings2;
 787
 788	if (speed >= XFER_UDMA_0) {
 789		if (pmif->kind == controller_kl_ata4)
 790			ret = set_timings_udma_ata4(&tl[0], speed);
 791		else if (pmif->kind == controller_un_ata6
 792			 || pmif->kind == controller_k2_ata6)
 793			ret = set_timings_udma_ata6(&tl[0], &tl[1], speed);
 794		else if (pmif->kind == controller_sh_ata6)
 795			ret = set_timings_udma_shasta(&tl[0], &tl[1], speed);
 796		else
 797			ret = -1;
 798	} else
 799		set_timings_mdma(drive, pmif->kind, &tl[0], &tl[1], speed);
 800
 801	if (ret)
 802		return;
 803
 804	/* Apply timings to controller */
 805	*timings = tl[0];
 806	*timings2 = tl[1];
 807
 808	pmac_ide_do_update_timings(drive);	
 809}
 810
 811/*
 812 * Blast some well known "safe" values to the timing registers at init or
 813 * wakeup from sleep time, before we do real calculation
 814 */
 815static void
 816sanitize_timings(pmac_ide_hwif_t *pmif)
 817{
 818	unsigned int value, value2 = 0;
 819	
 820	switch(pmif->kind) {
 821		case controller_sh_ata6:
 822			value = 0x0a820c97;
 823			value2 = 0x00033031;
 824			break;
 825		case controller_un_ata6:
 826		case controller_k2_ata6:
 827			value = 0x08618a92;
 828			value2 = 0x00002921;
 829			break;
 830		case controller_kl_ata4:
 831			value = 0x0008438c;
 832			break;
 833		case controller_kl_ata3:
 834			value = 0x00084526;
 835			break;
 836		case controller_heathrow:
 837		case controller_ohare:
 838		default:
 839			value = 0x00074526;
 840			break;
 841	}
 842	pmif->timings[0] = pmif->timings[1] = value;
 843	pmif->timings[2] = pmif->timings[3] = value2;
 844}
 845
 846static int on_media_bay(pmac_ide_hwif_t *pmif)
 847{
 848	return pmif->mdev && pmif->mdev->media_bay != NULL;
 849}
 850
 851/* Suspend call back, should be called after the child devices
 852 * have actually been suspended
 853 */
 854static int pmac_ide_do_suspend(pmac_ide_hwif_t *pmif)
 855{
 856	/* We clear the timings */
 857	pmif->timings[0] = 0;
 858	pmif->timings[1] = 0;
 859	
 860	disable_irq(pmif->irq);
 861
 862	/* The media bay will handle itself just fine */
 863	if (on_media_bay(pmif))
 864		return 0;
 865	
 866	/* Kauai has bus control FCRs directly here */
 867	if (pmif->kauai_fcr) {
 868		u32 fcr = readl(pmif->kauai_fcr);
 869		fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
 870		writel(fcr, pmif->kauai_fcr);
 871	}
 872
 873	/* Disable the bus on older machines and the cell on kauai */
 874	ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
 875			    0);
 876
 877	return 0;
 878}
 879
 880/* Resume call back, should be called before the child devices
 881 * are resumed
 882 */
 883static int pmac_ide_do_resume(pmac_ide_hwif_t *pmif)
 884{
 885	/* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
 886	if (!on_media_bay(pmif)) {
 887		ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
 888		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
 889		msleep(10);
 890		ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
 891
 892		/* Kauai has it different */
 893		if (pmif->kauai_fcr) {
 894			u32 fcr = readl(pmif->kauai_fcr);
 895			fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
 896			writel(fcr, pmif->kauai_fcr);
 897		}
 898
 899		msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
 900	}
 901
 902	/* Sanitize drive timings */
 903	sanitize_timings(pmif);
 904
 905	enable_irq(pmif->irq);
 906
 907	return 0;
 908}
 909
 910static u8 pmac_ide_cable_detect(ide_hwif_t *hwif)
 911{
 912	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 913	struct device_node *np = pmif->node;
 914	const char *cable = of_get_property(np, "cable-type", NULL);
 915	struct device_node *root = of_find_node_by_path("/");
 916	const char *model = of_get_property(root, "model", NULL);
 917
 918	of_node_put(root);
 919	/* Get cable type from device-tree. */
 920	if (cable && !strncmp(cable, "80-", 3)) {
 921		/* Some drives fail to detect 80c cable in PowerBook */
 922		/* These machine use proprietary short IDE cable anyway */
 923		if (!strncmp(model, "PowerBook", 9))
 924			return ATA_CBL_PATA40_SHORT;
 925		else
 926			return ATA_CBL_PATA80;
 927	}
 928
 929	/*
 930	 * G5's seem to have incorrect cable type in device-tree.
 931	 * Let's assume they have a 80 conductor cable, this seem
 932	 * to be always the case unless the user mucked around.
 933	 */
 934	if (of_device_is_compatible(np, "K2-UATA") ||
 935	    of_device_is_compatible(np, "shasta-ata"))
 936		return ATA_CBL_PATA80;
 937
 938	return ATA_CBL_PATA40;
 939}
 940
 941static void pmac_ide_init_dev(ide_drive_t *drive)
 942{
 943	ide_hwif_t *hwif = drive->hwif;
 944	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
 945
 946	if (on_media_bay(pmif)) {
 947		if (check_media_bay(pmif->mdev->media_bay) == MB_CD) {
 948			drive->dev_flags &= ~IDE_DFLAG_NOPROBE;
 949			return;
 950		}
 951		drive->dev_flags |= IDE_DFLAG_NOPROBE;
 952	}
 953}
 954
 955static const struct ide_tp_ops pmac_tp_ops = {
 956	.exec_command		= pmac_exec_command,
 957	.read_status		= ide_read_status,
 958	.read_altstatus		= ide_read_altstatus,
 959	.write_devctl		= pmac_write_devctl,
 960
 961	.dev_select		= pmac_dev_select,
 962	.tf_load		= ide_tf_load,
 963	.tf_read		= ide_tf_read,
 964
 965	.input_data		= ide_input_data,
 966	.output_data		= ide_output_data,
 967};
 968
 969static const struct ide_tp_ops pmac_ata6_tp_ops = {
 970	.exec_command		= pmac_exec_command,
 971	.read_status		= ide_read_status,
 972	.read_altstatus		= ide_read_altstatus,
 973	.write_devctl		= pmac_write_devctl,
 974
 975	.dev_select		= pmac_kauai_dev_select,
 976	.tf_load		= ide_tf_load,
 977	.tf_read		= ide_tf_read,
 978
 979	.input_data		= ide_input_data,
 980	.output_data		= ide_output_data,
 981};
 982
 983static const struct ide_port_ops pmac_ide_ata4_port_ops = {
 984	.init_dev		= pmac_ide_init_dev,
 985	.set_pio_mode		= pmac_ide_set_pio_mode,
 986	.set_dma_mode		= pmac_ide_set_dma_mode,
 987	.cable_detect		= pmac_ide_cable_detect,
 988};
 989
 990static const struct ide_port_ops pmac_ide_port_ops = {
 991	.init_dev		= pmac_ide_init_dev,
 992	.set_pio_mode		= pmac_ide_set_pio_mode,
 993	.set_dma_mode		= pmac_ide_set_dma_mode,
 994};
 995
 996static const struct ide_dma_ops pmac_dma_ops;
 997
 998static const struct ide_port_info pmac_port_info = {
 999	.name			= DRV_NAME,
1000	.init_dma		= pmac_ide_init_dma,
1001	.chipset		= ide_pmac,
1002	.tp_ops			= &pmac_tp_ops,
1003	.port_ops		= &pmac_ide_port_ops,
1004	.dma_ops		= &pmac_dma_ops,
1005	.host_flags		= IDE_HFLAG_SET_PIO_MODE_KEEP_DMA |
1006				  IDE_HFLAG_POST_SET_MODE |
1007				  IDE_HFLAG_MMIO |
1008				  IDE_HFLAG_UNMASK_IRQS,
1009	.pio_mask		= ATA_PIO4,
1010	.mwdma_mask		= ATA_MWDMA2,
1011};
1012
1013/*
1014 * Setup, register & probe an IDE channel driven by this driver, this is
1015 * called by one of the 2 probe functions (macio or PCI).
1016 */
1017static int pmac_ide_setup_device(pmac_ide_hwif_t *pmif, struct ide_hw *hw)
1018{
1019	struct device_node *np = pmif->node;
1020	const int *bidp;
1021	struct ide_host *host;
 
1022	struct ide_hw *hws[] = { hw };
1023	struct ide_port_info d = pmac_port_info;
1024	int rc;
1025
1026	pmif->broken_dma = pmif->broken_dma_warn = 0;
1027	if (of_device_is_compatible(np, "shasta-ata")) {
1028		pmif->kind = controller_sh_ata6;
1029		d.tp_ops = &pmac_ata6_tp_ops;
1030		d.port_ops = &pmac_ide_ata4_port_ops;
1031		d.udma_mask = ATA_UDMA6;
1032	} else if (of_device_is_compatible(np, "kauai-ata")) {
1033		pmif->kind = controller_un_ata6;
1034		d.tp_ops = &pmac_ata6_tp_ops;
1035		d.port_ops = &pmac_ide_ata4_port_ops;
1036		d.udma_mask = ATA_UDMA5;
1037	} else if (of_device_is_compatible(np, "K2-UATA")) {
1038		pmif->kind = controller_k2_ata6;
1039		d.tp_ops = &pmac_ata6_tp_ops;
1040		d.port_ops = &pmac_ide_ata4_port_ops;
1041		d.udma_mask = ATA_UDMA5;
1042	} else if (of_device_is_compatible(np, "keylargo-ata")) {
1043		if (of_node_name_eq(np, "ata-4")) {
1044			pmif->kind = controller_kl_ata4;
1045			d.port_ops = &pmac_ide_ata4_port_ops;
1046			d.udma_mask = ATA_UDMA4;
1047		} else
1048			pmif->kind = controller_kl_ata3;
1049	} else if (of_device_is_compatible(np, "heathrow-ata")) {
1050		pmif->kind = controller_heathrow;
1051	} else {
1052		pmif->kind = controller_ohare;
1053		pmif->broken_dma = 1;
1054	}
1055
1056	bidp = of_get_property(np, "AAPL,bus-id", NULL);
1057	pmif->aapl_bus_id =  bidp ? *bidp : 0;
1058
1059	/* On Kauai-type controllers, we make sure the FCR is correct */
1060	if (pmif->kauai_fcr)
1061		writel(KAUAI_FCR_UATA_MAGIC |
1062		       KAUAI_FCR_UATA_RESET_N |
1063		       KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1064	
1065	/* Make sure we have sane timings */
1066	sanitize_timings(pmif);
1067
1068	/* If we are on a media bay, wait for it to settle and lock it */
1069	if (pmif->mdev)
1070		lock_media_bay(pmif->mdev->media_bay);
1071
1072	host = ide_host_alloc(&d, hws, 1);
1073	if (host == NULL) {
1074		rc = -ENOMEM;
1075		goto bail;
1076	}
1077	pmif->hwif = host->ports[0];
1078
1079	if (on_media_bay(pmif)) {
1080		/* Fixup bus ID for media bay */
1081		if (!bidp)
1082			pmif->aapl_bus_id = 1;
1083	} else if (pmif->kind == controller_ohare) {
1084		/* The code below is having trouble on some ohare machines
1085		 * (timing related ?). Until I can put my hand on one of these
1086		 * units, I keep the old way
1087		 */
1088		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1089	} else {
1090 		/* This is necessary to enable IDE when net-booting */
1091		ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1092		ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1093		msleep(10);
1094		ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1095		msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1096	}
1097
1098	printk(KERN_INFO DRV_NAME ": Found Apple %s controller (%s), "
1099	       "bus ID %d%s, irq %d\n", model_name[pmif->kind],
1100	       pmif->mdev ? "macio" : "PCI", pmif->aapl_bus_id,
1101	       on_media_bay(pmif) ? " (mediabay)" : "", hw->irq);
1102
1103	rc = ide_host_register(host, &d, hws);
1104	if (rc)
1105		pmif->hwif = NULL;
1106
1107	if (pmif->mdev)
1108		unlock_media_bay(pmif->mdev->media_bay);
1109
1110 bail:
1111	if (rc && host)
1112		ide_host_free(host);
1113	return rc;
1114}
1115
1116static void pmac_ide_init_ports(struct ide_hw *hw, unsigned long base)
1117{
1118	int i;
1119
1120	for (i = 0; i < 8; ++i)
1121		hw->io_ports_array[i] = base + i * 0x10;
1122
1123	hw->io_ports.ctl_addr = base + 0x160;
1124}
1125
1126/*
1127 * Attach to a macio probed interface
1128 */
1129static int pmac_ide_macio_attach(struct macio_dev *mdev,
1130				 const struct of_device_id *match)
1131{
1132	void __iomem *base;
1133	unsigned long regbase;
1134	pmac_ide_hwif_t *pmif;
1135	int irq, rc;
1136	struct ide_hw hw;
1137
1138	pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1139	if (pmif == NULL)
1140		return -ENOMEM;
1141
1142	if (macio_resource_count(mdev) == 0) {
1143		printk(KERN_WARNING "ide-pmac: no address for %pOF\n",
1144				    mdev->ofdev.dev.of_node);
1145		rc = -ENXIO;
1146		goto out_free_pmif;
1147	}
1148
1149	/* Request memory resource for IO ports */
1150	if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1151		printk(KERN_ERR "ide-pmac: can't request MMIO resource for "
1152				"%pOF!\n", mdev->ofdev.dev.of_node);
1153		rc = -EBUSY;
1154		goto out_free_pmif;
1155	}
1156			
1157	/* XXX This is bogus. Should be fixed in the registry by checking
1158	 * the kind of host interrupt controller, a bit like gatwick
1159	 * fixes in irq.c. That works well enough for the single case
1160	 * where that happens though...
1161	 */
1162	if (macio_irq_count(mdev) == 0) {
1163		printk(KERN_WARNING "ide-pmac: no intrs for device %pOF, using "
1164				    "13\n", mdev->ofdev.dev.of_node);
1165		irq = irq_create_mapping(NULL, 13);
1166	} else
1167		irq = macio_irq(mdev, 0);
1168
1169	base = ioremap(macio_resource_start(mdev, 0), 0x400);
1170	regbase = (unsigned long) base;
1171
1172	pmif->mdev = mdev;
1173	pmif->node = mdev->ofdev.dev.of_node;
1174	pmif->regbase = regbase;
1175	pmif->irq = irq;
1176	pmif->kauai_fcr = NULL;
1177
1178	if (macio_resource_count(mdev) >= 2) {
1179		if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1180			printk(KERN_WARNING "ide-pmac: can't request DMA "
1181					    "resource for %pOF!\n",
1182					    mdev->ofdev.dev.of_node);
1183		else
1184			pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1185	} else
1186		pmif->dma_regs = NULL;
1187
1188	dev_set_drvdata(&mdev->ofdev.dev, pmif);
1189
1190	memset(&hw, 0, sizeof(hw));
1191	pmac_ide_init_ports(&hw, pmif->regbase);
1192	hw.irq = irq;
1193	hw.dev = &mdev->bus->pdev->dev;
1194	hw.parent = &mdev->ofdev.dev;
1195
1196	rc = pmac_ide_setup_device(pmif, &hw);
1197	if (rc != 0) {
1198		/* The inteface is released to the common IDE layer */
1199		dev_set_drvdata(&mdev->ofdev.dev, NULL);
1200		iounmap(base);
1201		if (pmif->dma_regs) {
1202			iounmap(pmif->dma_regs);
1203			macio_release_resource(mdev, 1);
1204		}
1205		macio_release_resource(mdev, 0);
1206		kfree(pmif);
1207	}
1208
1209	return rc;
1210
1211out_free_pmif:
1212	kfree(pmif);
1213	return rc;
1214}
1215
1216static int
1217pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t mesg)
1218{
1219	pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1220	int rc = 0;
1221
1222	if (mesg.event != mdev->ofdev.dev.power.power_state.event
1223			&& (mesg.event & PM_EVENT_SLEEP)) {
1224		rc = pmac_ide_do_suspend(pmif);
1225		if (rc == 0)
1226			mdev->ofdev.dev.power.power_state = mesg;
1227	}
1228
1229	return rc;
1230}
1231
1232static int
1233pmac_ide_macio_resume(struct macio_dev *mdev)
1234{
1235	pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1236	int rc = 0;
1237
1238	if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1239		rc = pmac_ide_do_resume(pmif);
1240		if (rc == 0)
1241			mdev->ofdev.dev.power.power_state = PMSG_ON;
1242	}
1243
1244	return rc;
1245}
1246
1247/*
1248 * Attach to a PCI probed interface
1249 */
1250static int pmac_ide_pci_attach(struct pci_dev *pdev,
1251			       const struct pci_device_id *id)
1252{
1253	struct device_node *np;
1254	pmac_ide_hwif_t *pmif;
1255	void __iomem *base;
1256	unsigned long rbase, rlen;
1257	int rc;
1258	struct ide_hw hw;
1259
1260	np = pci_device_to_OF_node(pdev);
1261	if (np == NULL) {
1262		printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1263		return -ENODEV;
1264	}
1265
1266	pmif = kzalloc(sizeof(*pmif), GFP_KERNEL);
1267	if (pmif == NULL)
1268		return -ENOMEM;
1269
1270	if (pci_enable_device(pdev)) {
1271		printk(KERN_WARNING "ide-pmac: Can't enable PCI device for "
1272				    "%pOF\n", np);
1273		rc = -ENXIO;
1274		goto out_free_pmif;
1275	}
1276	pci_set_master(pdev);
1277			
1278	if (pci_request_regions(pdev, "Kauai ATA")) {
1279		printk(KERN_ERR "ide-pmac: Cannot obtain PCI resources for "
1280				"%pOF\n", np);
1281		rc = -ENXIO;
1282		goto out_free_pmif;
1283	}
1284
1285	pmif->mdev = NULL;
1286	pmif->node = np;
1287
1288	rbase = pci_resource_start(pdev, 0);
1289	rlen = pci_resource_len(pdev, 0);
1290
1291	base = ioremap(rbase, rlen);
1292	pmif->regbase = (unsigned long) base + 0x2000;
1293	pmif->dma_regs = base + 0x1000;
1294	pmif->kauai_fcr = base;
1295	pmif->irq = pdev->irq;
1296
1297	pci_set_drvdata(pdev, pmif);
1298
1299	memset(&hw, 0, sizeof(hw));
1300	pmac_ide_init_ports(&hw, pmif->regbase);
1301	hw.irq = pdev->irq;
1302	hw.dev = &pdev->dev;
1303
1304	rc = pmac_ide_setup_device(pmif, &hw);
1305	if (rc != 0) {
1306		/* The inteface is released to the common IDE layer */
1307		iounmap(base);
1308		pci_release_regions(pdev);
1309		kfree(pmif);
1310	}
1311
1312	return rc;
1313
1314out_free_pmif:
1315	kfree(pmif);
1316	return rc;
1317}
1318
1319static int
1320pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t mesg)
1321{
1322	pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1323	int rc = 0;
1324
1325	if (mesg.event != pdev->dev.power.power_state.event
1326			&& (mesg.event & PM_EVENT_SLEEP)) {
1327		rc = pmac_ide_do_suspend(pmif);
1328		if (rc == 0)
1329			pdev->dev.power.power_state = mesg;
1330	}
1331
1332	return rc;
1333}
1334
1335static int
1336pmac_ide_pci_resume(struct pci_dev *pdev)
1337{
1338	pmac_ide_hwif_t *pmif = pci_get_drvdata(pdev);
1339	int rc = 0;
1340
1341	if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1342		rc = pmac_ide_do_resume(pmif);
1343		if (rc == 0)
1344			pdev->dev.power.power_state = PMSG_ON;
1345	}
1346
1347	return rc;
1348}
1349
1350#ifdef CONFIG_PMAC_MEDIABAY
1351static void pmac_ide_macio_mb_event(struct macio_dev* mdev, int mb_state)
1352{
1353	pmac_ide_hwif_t *pmif = dev_get_drvdata(&mdev->ofdev.dev);
1354
1355	switch(mb_state) {
1356	case MB_CD:
1357		if (!pmif->hwif->present)
1358			ide_port_scan(pmif->hwif);
1359		break;
1360	default:
1361		if (pmif->hwif->present)
1362			ide_port_unregister_devices(pmif->hwif);
1363	}
1364}
1365#endif /* CONFIG_PMAC_MEDIABAY */
1366
1367
1368static struct of_device_id pmac_ide_macio_match[] = 
1369{
1370	{
1371	.name 		= "IDE",
1372	},
1373	{
1374	.name 		= "ATA",
1375	},
1376	{
1377	.type		= "ide",
1378	},
1379	{
1380	.type		= "ata",
1381	},
1382	{},
1383};
1384
1385static struct macio_driver pmac_ide_macio_driver = 
1386{
1387	.driver = {
1388		.name 		= "ide-pmac",
1389		.owner		= THIS_MODULE,
1390		.of_match_table	= pmac_ide_macio_match,
1391	},
1392	.probe		= pmac_ide_macio_attach,
1393	.suspend	= pmac_ide_macio_suspend,
1394	.resume		= pmac_ide_macio_resume,
1395#ifdef CONFIG_PMAC_MEDIABAY
1396	.mediabay_event	= pmac_ide_macio_mb_event,
1397#endif
1398};
1399
1400static const struct pci_device_id pmac_ide_pci_match[] = {
1401	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA),	0 },
1402	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100),	0 },
1403	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100),	0 },
1404	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_SH_ATA),	0 },
1405	{ PCI_VDEVICE(APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA),	0 },
1406	{},
1407};
1408
1409static struct pci_driver pmac_ide_pci_driver = {
1410	.name		= "ide-pmac",
1411	.id_table	= pmac_ide_pci_match,
1412	.probe		= pmac_ide_pci_attach,
1413	.suspend	= pmac_ide_pci_suspend,
1414	.resume		= pmac_ide_pci_resume,
1415};
1416MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1417
1418int __init pmac_ide_probe(void)
1419{
1420	int error;
1421
1422	if (!machine_is(powermac))
1423		return -ENODEV;
1424
1425#ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1426	error = pci_register_driver(&pmac_ide_pci_driver);
1427	if (error)
1428		goto out;
1429	error = macio_register_driver(&pmac_ide_macio_driver);
1430	if (error) {
1431		pci_unregister_driver(&pmac_ide_pci_driver);
1432		goto out;
1433	}
1434#else
1435	error = macio_register_driver(&pmac_ide_macio_driver);
1436	if (error)
1437		goto out;
1438	error = pci_register_driver(&pmac_ide_pci_driver);
1439	if (error) {
1440		macio_unregister_driver(&pmac_ide_macio_driver);
1441		goto out;
1442	}
1443#endif
1444out:
1445	return error;
1446}
1447
1448/*
1449 * pmac_ide_build_dmatable builds the DBDMA command list
1450 * for a transfer and sets the DBDMA channel to point to it.
1451 */
1452static int pmac_ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
1453{
1454	ide_hwif_t *hwif = drive->hwif;
1455	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1456	struct dbdma_cmd *table;
1457	volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1458	struct scatterlist *sg;
1459	int wr = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1460	int i = cmd->sg_nents, count = 0;
1461
1462	/* DMA table is already aligned */
1463	table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1464
1465	/* Make sure DMA controller is stopped (necessary ?) */
1466	writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1467	while (readl(&dma->status) & RUN)
1468		udelay(1);
1469
1470	/* Build DBDMA commands list */
1471	sg = hwif->sg_table;
1472	while (i && sg_dma_len(sg)) {
1473		u32 cur_addr;
1474		u32 cur_len;
1475
1476		cur_addr = sg_dma_address(sg);
1477		cur_len = sg_dma_len(sg);
1478
1479		if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1480			if (pmif->broken_dma_warn == 0) {
1481				printk(KERN_WARNING "%s: DMA on non aligned address, "
1482				       "switching to PIO on Ohare chipset\n", drive->name);
1483				pmif->broken_dma_warn = 1;
1484			}
1485			return 0;
1486		}
1487		while (cur_len) {
1488			unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1489
1490			if (count++ >= MAX_DCMDS) {
1491				printk(KERN_WARNING "%s: DMA table too small\n",
1492				       drive->name);
1493				return 0;
1494			}
1495			table->command = cpu_to_le16(wr? OUTPUT_MORE: INPUT_MORE);
1496			table->req_count = cpu_to_le16(tc);
1497			table->phy_addr = cpu_to_le32(cur_addr);
1498			table->cmd_dep = 0;
1499			table->xfer_status = 0;
1500			table->res_count = 0;
1501			cur_addr += tc;
1502			cur_len -= tc;
1503			++table;
1504		}
1505		sg = sg_next(sg);
1506		i--;
1507	}
1508
1509	/* convert the last command to an input/output last command */
1510	if (count) {
1511		table[-1].command = cpu_to_le16(wr? OUTPUT_LAST: INPUT_LAST);
1512		/* add the stop command to the end of the list */
1513		memset(table, 0, sizeof(struct dbdma_cmd));
1514		table->command = cpu_to_le16(DBDMA_STOP);
1515		mb();
1516		writel(hwif->dmatable_dma, &dma->cmdptr);
1517		return 1;
1518	}
1519
1520	printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1521
1522	return 0; /* revert to PIO for this request */
1523}
1524
1525/*
1526 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1527 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1528 */
1529static int pmac_ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
1530{
1531	ide_hwif_t *hwif = drive->hwif;
1532	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1533	u8 unit = drive->dn & 1, ata4 = (pmif->kind == controller_kl_ata4);
1534	u8 write = !!(cmd->tf_flags & IDE_TFLAG_WRITE);
1535
1536	if (pmac_ide_build_dmatable(drive, cmd) == 0)
1537		return 1;
1538
1539	/* Apple adds 60ns to wrDataSetup on reads */
1540	if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1541		writel(pmif->timings[unit] + (write ? 0 : 0x00800000UL),
1542			PMAC_IDE_REG(IDE_TIMING_CONFIG));
1543		(void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1544	}
1545
1546	return 0;
1547}
1548
1549/*
1550 * Kick the DMA controller into life after the DMA command has been issued
1551 * to the drive.
1552 */
1553static void
1554pmac_ide_dma_start(ide_drive_t *drive)
1555{
1556	ide_hwif_t *hwif = drive->hwif;
1557	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1558	volatile struct dbdma_regs __iomem *dma;
1559
1560	dma = pmif->dma_regs;
1561
1562	writel((RUN << 16) | RUN, &dma->control);
1563	/* Make sure it gets to the controller right now */
1564	(void)readl(&dma->control);
1565}
1566
1567/*
1568 * After a DMA transfer, make sure the controller is stopped
1569 */
1570static int
1571pmac_ide_dma_end (ide_drive_t *drive)
1572{
1573	ide_hwif_t *hwif = drive->hwif;
1574	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1575	volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1576	u32 dstat;
1577
1578	dstat = readl(&dma->status);
1579	writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1580
1581	/* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1582	 * in theory, but with ATAPI decices doing buffer underruns, that would
1583	 * cause us to disable DMA, which isn't what we want
1584	 */
1585	return (dstat & (RUN|DEAD)) != RUN;
1586}
1587
1588/*
1589 * Check out that the interrupt we got was for us. We can't always know this
1590 * for sure with those Apple interfaces (well, we could on the recent ones but
1591 * that's not implemented yet), on the other hand, we don't have shared interrupts
1592 * so it's not really a problem
1593 */
1594static int
1595pmac_ide_dma_test_irq (ide_drive_t *drive)
1596{
1597	ide_hwif_t *hwif = drive->hwif;
1598	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1599	volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1600	unsigned long status, timeout;
1601
1602	/* We have to things to deal with here:
1603	 * 
1604	 * - The dbdma won't stop if the command was started
1605	 * but completed with an error without transferring all
1606	 * datas. This happens when bad blocks are met during
1607	 * a multi-block transfer.
1608	 * 
1609	 * - The dbdma fifo hasn't yet finished flushing to
1610	 * to system memory when the disk interrupt occurs.
1611	 * 
1612	 */
1613
1614	/* If ACTIVE is cleared, the STOP command have passed and
1615	 * transfer is complete.
1616	 */
1617	status = readl(&dma->status);
1618	if (!(status & ACTIVE))
1619		return 1;
1620
1621	/* If dbdma didn't execute the STOP command yet, the
1622	 * active bit is still set. We consider that we aren't
1623	 * sharing interrupts (which is hopefully the case with
1624	 * those controllers) and so we just try to flush the
1625	 * channel for pending data in the fifo
1626	 */
1627	udelay(1);
1628	writel((FLUSH << 16) | FLUSH, &dma->control);
1629	timeout = 0;
1630	for (;;) {
1631		udelay(1);
1632		status = readl(&dma->status);
1633		if ((status & FLUSH) == 0)
1634			break;
1635		if (++timeout > 100) {
1636			printk(KERN_WARNING "ide%d, ide_dma_test_irq timeout flushing channel\n",
1637			       hwif->index);
1638			break;
1639		}
1640	}	
1641	return 1;
1642}
1643
1644static void pmac_ide_dma_host_set(ide_drive_t *drive, int on)
1645{
1646}
1647
1648static void
1649pmac_ide_dma_lost_irq (ide_drive_t *drive)
1650{
1651	ide_hwif_t *hwif = drive->hwif;
1652	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1653	volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1654	unsigned long status = readl(&dma->status);
1655
1656	printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
1657}
1658
1659static const struct ide_dma_ops pmac_dma_ops = {
1660	.dma_host_set		= pmac_ide_dma_host_set,
1661	.dma_setup		= pmac_ide_dma_setup,
1662	.dma_start		= pmac_ide_dma_start,
1663	.dma_end		= pmac_ide_dma_end,
1664	.dma_test_irq		= pmac_ide_dma_test_irq,
1665	.dma_lost_irq		= pmac_ide_dma_lost_irq,
1666};
1667
1668/*
1669 * Allocate the data structures needed for using DMA with an interface
1670 * and fill the proper list of functions pointers
1671 */
1672static int pmac_ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
1673{
1674	pmac_ide_hwif_t *pmif = dev_get_drvdata(hwif->gendev.parent);
1675	struct pci_dev *dev = to_pci_dev(hwif->dev);
1676
1677	/* We won't need pci_dev if we switch to generic consistent
1678	 * DMA routines ...
1679	 */
1680	if (dev == NULL || pmif->dma_regs == 0)
1681		return -ENODEV;
1682	/*
1683	 * Allocate space for the DBDMA commands.
1684	 * The +2 is +1 for the stop command and +1 to allow for
1685	 * aligning the start address to a multiple of 16 bytes.
1686	 */
1687	pmif->dma_table_cpu = dma_alloc_coherent(&dev->dev,
1688		(MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
1689		&hwif->dmatable_dma, GFP_KERNEL);
1690	if (pmif->dma_table_cpu == NULL) {
1691		printk(KERN_ERR "%s: unable to allocate DMA command list\n",
1692		       hwif->name);
1693		return -ENOMEM;
1694	}
1695
1696	hwif->sg_max_nents = MAX_DCMDS;
1697
1698	return 0;
1699}
1700
1701module_init(pmac_ide_probe);
1702
1703MODULE_LICENSE("GPL");