1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
  4 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
  5 *
  6 */
  7
  8#include <linux/module.h>
  9#include <linux/types.h>
 10#include <linux/pci.h>
 11#include <linux/ide.h>
 12#include <linux/init.h>
 13
 14#include <asm/io.h>
 15
 16#define DRV_NAME "aec62xx"
 17
 18struct chipset_bus_clock_list_entry {
 19	u8 xfer_speed;
 20	u8 chipset_settings;
 21	u8 ultra_settings;
 22};
 23
 24static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
 25	{	XFER_UDMA_6,	0x31,	0x07	},
 26	{	XFER_UDMA_5,	0x31,	0x06	},
 27	{	XFER_UDMA_4,	0x31,	0x05	},
 28	{	XFER_UDMA_3,	0x31,	0x04	},
 29	{	XFER_UDMA_2,	0x31,	0x03	},
 30	{	XFER_UDMA_1,	0x31,	0x02	},
 31	{	XFER_UDMA_0,	0x31,	0x01	},
 32
 33	{	XFER_MW_DMA_2,	0x31,	0x00	},
 34	{	XFER_MW_DMA_1,	0x31,	0x00	},
 35	{	XFER_MW_DMA_0,	0x0a,	0x00	},
 36	{	XFER_PIO_4,	0x31,	0x00	},
 37	{	XFER_PIO_3,	0x33,	0x00	},
 38	{	XFER_PIO_2,	0x08,	0x00	},
 39	{	XFER_PIO_1,	0x0a,	0x00	},
 40	{	XFER_PIO_0,	0x00,	0x00	},
 41	{	0,		0x00,	0x00	}
 42};
 43
 44static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
 45	{	XFER_UDMA_6,	0x41,	0x06	},
 46	{	XFER_UDMA_5,	0x41,	0x05	},
 47	{	XFER_UDMA_4,	0x41,	0x04	},
 48	{	XFER_UDMA_3,	0x41,	0x03	},
 49	{	XFER_UDMA_2,	0x41,	0x02	},
 50	{	XFER_UDMA_1,	0x41,	0x01	},
 51	{	XFER_UDMA_0,	0x41,	0x01	},
 52
 53	{	XFER_MW_DMA_2,	0x41,	0x00	},
 54	{	XFER_MW_DMA_1,	0x42,	0x00	},
 55	{	XFER_MW_DMA_0,	0x7a,	0x00	},
 56	{	XFER_PIO_4,	0x41,	0x00	},
 57	{	XFER_PIO_3,	0x43,	0x00	},
 58	{	XFER_PIO_2,	0x78,	0x00	},
 59	{	XFER_PIO_1,	0x7a,	0x00	},
 60	{	XFER_PIO_0,	0x70,	0x00	},
 61	{	0,		0x00,	0x00	}
 62};
 63
 64/*
 65 * TO DO: active tuning and correction of cards without a bios.
 66 */
 67static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 68{
 69	for ( ; chipset_table->xfer_speed ; chipset_table++)
 70		if (chipset_table->xfer_speed == speed) {
 71			return chipset_table->chipset_settings;
 72		}
 73	return chipset_table->chipset_settings;
 74}
 75
 76static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 77{
 78	for ( ; chipset_table->xfer_speed ; chipset_table++)
 79		if (chipset_table->xfer_speed == speed) {
 80			return chipset_table->ultra_settings;
 81		}
 82	return chipset_table->ultra_settings;
 83}
 84
 85static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 86{
 87	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 88	struct ide_host *host	= pci_get_drvdata(dev);
 89	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
 90	u16 d_conf		= 0;
 91	u8 ultra = 0, ultra_conf = 0;
 92	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
 93	const u8 speed = drive->dma_mode;
 94	unsigned long flags;
 95
 96	local_irq_save(flags);
 97	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 98	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 99	tmp0 = pci_bus_clock_list(speed, bus_clock);
100	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
101	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
102
103	tmp1 = 0x00;
104	tmp2 = 0x00;
105	pci_read_config_byte(dev, 0x54, &ultra);
106	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
107	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
108	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
109	pci_write_config_byte(dev, 0x54, tmp2);
110	local_irq_restore(flags);
111}
112
113static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
114{
115	struct pci_dev *dev	= to_pci_dev(hwif->dev);
116	struct ide_host *host	= pci_get_drvdata(dev);
117	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
118	u8 unit			= drive->dn & 1;
119	u8 tmp1 = 0, tmp2 = 0;
120	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
121	const u8 speed = drive->dma_mode;
122	unsigned long flags;
123
124	local_irq_save(flags);
125	/* high 4-bits: Active, low 4-bits: Recovery */
126	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
127	drive_conf = pci_bus_clock_list(speed, bus_clock);
128	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
129
130	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
131	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
132	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
133	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
134	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
135	local_irq_restore(flags);
136}
137
138static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
139{
140	drive->dma_mode = drive->pio_mode;
141	hwif->port_ops->set_dma_mode(hwif, drive);
142}
143
144static int init_chipset_aec62xx(struct pci_dev *dev)
145{
146	/* These are necessary to get AEC6280 Macintosh cards to work */
147	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
148	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
149		u8 reg49h = 0, reg4ah = 0;
150		/* Clear reset and test bits.  */
151		pci_read_config_byte(dev, 0x49, &reg49h);
152		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
153		/* Enable chip interrupt output.  */
154		pci_read_config_byte(dev, 0x4a, &reg4ah);
155		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
156		/* Enable burst mode. */
157		pci_read_config_byte(dev, 0x4a, &reg4ah);
158		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
159	}
160
161	return 0;
162}
163
164static u8 atp86x_cable_detect(ide_hwif_t *hwif)
165{
166	struct pci_dev *dev = to_pci_dev(hwif->dev);
167	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
168
169	pci_read_config_byte(dev, 0x49, &ata66);
170
171	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
172}
173
174static const struct ide_port_ops atp850_port_ops = {
175	.set_pio_mode		= aec_set_pio_mode,
176	.set_dma_mode		= aec6210_set_mode,
177};
178
179static const struct ide_port_ops atp86x_port_ops = {
180	.set_pio_mode		= aec_set_pio_mode,
181	.set_dma_mode		= aec6260_set_mode,
182	.cable_detect		= atp86x_cable_detect,
183};
184
185static const struct ide_port_info aec62xx_chipsets[] = {
186	{	/* 0: AEC6210 */
187		.name		= DRV_NAME,
188		.init_chipset	= init_chipset_aec62xx,
189		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
190		.port_ops	= &atp850_port_ops,
191		.host_flags	= IDE_HFLAG_SERIALIZE |
192				  IDE_HFLAG_NO_ATAPI_DMA |
193				  IDE_HFLAG_NO_DSC |
194				  IDE_HFLAG_OFF_BOARD,
195		.pio_mask	= ATA_PIO4,
196		.mwdma_mask	= ATA_MWDMA2,
197		.udma_mask	= ATA_UDMA2,
198	},
199	{	/* 1: AEC6260 */
200		.name		= DRV_NAME,
201		.init_chipset	= init_chipset_aec62xx,
202		.port_ops	= &atp86x_port_ops,
203		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
204				  IDE_HFLAG_OFF_BOARD,
205		.pio_mask	= ATA_PIO4,
206		.mwdma_mask	= ATA_MWDMA2,
207		.udma_mask	= ATA_UDMA4,
208	},
209	{	/* 2: AEC6260R */
210		.name		= DRV_NAME,
211		.init_chipset	= init_chipset_aec62xx,
212		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
213		.port_ops	= &atp86x_port_ops,
214		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
215				  IDE_HFLAG_NON_BOOTABLE,
216		.pio_mask	= ATA_PIO4,
217		.mwdma_mask	= ATA_MWDMA2,
218		.udma_mask	= ATA_UDMA4,
219	},
220	{	/* 3: AEC6280 */
221		.name		= DRV_NAME,
222		.init_chipset	= init_chipset_aec62xx,
223		.port_ops	= &atp86x_port_ops,
224		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
225				  IDE_HFLAG_OFF_BOARD,
226		.pio_mask	= ATA_PIO4,
227		.mwdma_mask	= ATA_MWDMA2,
228		.udma_mask	= ATA_UDMA5,
229	},
230	{	/* 4: AEC6280R */
231		.name		= DRV_NAME,
232		.init_chipset	= init_chipset_aec62xx,
233		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
234		.port_ops	= &atp86x_port_ops,
235		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
236				  IDE_HFLAG_OFF_BOARD,
237		.pio_mask	= ATA_PIO4,
238		.mwdma_mask	= ATA_MWDMA2,
239		.udma_mask	= ATA_UDMA5,
240	}
241};
242
243/**
244 *	aec62xx_init_one	-	called when a AEC is found
245 *	@dev: the aec62xx device
246 *	@id: the matching pci id
247 *
248 *	Called when the PCI registration layer (or the IDE initialization)
249 *	finds a device matching our IDE device tables.
250 *
251 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
252 *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
253 */
254
255static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
256{
257	const struct chipset_bus_clock_list_entry *bus_clock;
258	struct ide_port_info d;
259	u8 idx = id->driver_data;
260	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
261	int err;
262
263	if (bus_speed <= 33)
264		bus_clock = aec6xxx_33_base;
265	else
266		bus_clock = aec6xxx_34_base;
267
268	err = pci_enable_device(dev);
269	if (err)
270		return err;
271
272	d = aec62xx_chipsets[idx];
273
274	if (idx == 3 || idx == 4) {
275		unsigned long dma_base = pci_resource_start(dev, 4);
276
277		if (inb(dma_base + 2) & 0x10) {
278			printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
279				"\n", pci_name(dev), (idx == 4) ? "R" : "");
280			d.udma_mask = ATA_UDMA6;
281		}
282	}
283
284	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
285	if (err)
286		pci_disable_device(dev);
287
288	return err;
289}
290
291static void aec62xx_remove(struct pci_dev *dev)
292{
293	ide_pci_remove(dev);
294	pci_disable_device(dev);
295}
296
297static const struct pci_device_id aec62xx_pci_tbl[] = {
298	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
299	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
300	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
301	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
302	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
303	{ 0, },
304};
305MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
306
307static struct pci_driver aec62xx_pci_driver = {
308	.name		= "AEC62xx_IDE",
309	.id_table	= aec62xx_pci_tbl,
310	.probe		= aec62xx_init_one,
311	.remove		= aec62xx_remove,
312	.suspend	= ide_pci_suspend,
313	.resume		= ide_pci_resume,
314};
315
316static int __init aec62xx_ide_init(void)
317{
318	return ide_pci_register_driver(&aec62xx_pci_driver);
319}
320
321static void __exit aec62xx_ide_exit(void)
322{
323	pci_unregister_driver(&aec62xx_pci_driver);
324}
325
326module_init(aec62xx_ide_init);
327module_exit(aec62xx_ide_exit);
328
329MODULE_AUTHOR("Andre Hedrick");
330MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
331MODULE_LICENSE("GPL");

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Copyright (C) 1999-2002	Andre Hedrick <andre@linux-ide.org>
  4 * Copyright (C) 2007		MontaVista Software, Inc. <source@mvista.com>
  5 *
  6 */
  7
  8#include <linux/module.h>
  9#include <linux/types.h>
 10#include <linux/pci.h>
 11#include <linux/ide.h>
 12#include <linux/init.h>
 13
 14#include <asm/io.h>
 15
 16#define DRV_NAME "aec62xx"
 17
 18struct chipset_bus_clock_list_entry {
 19	u8 xfer_speed;
 20	u8 chipset_settings;
 21	u8 ultra_settings;
 22};
 23
 24static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
 25	{	XFER_UDMA_6,	0x31,	0x07	},
 26	{	XFER_UDMA_5,	0x31,	0x06	},
 27	{	XFER_UDMA_4,	0x31,	0x05	},
 28	{	XFER_UDMA_3,	0x31,	0x04	},
 29	{	XFER_UDMA_2,	0x31,	0x03	},
 30	{	XFER_UDMA_1,	0x31,	0x02	},
 31	{	XFER_UDMA_0,	0x31,	0x01	},
 32
 33	{	XFER_MW_DMA_2,	0x31,	0x00	},
 34	{	XFER_MW_DMA_1,	0x31,	0x00	},
 35	{	XFER_MW_DMA_0,	0x0a,	0x00	},
 36	{	XFER_PIO_4,	0x31,	0x00	},
 37	{	XFER_PIO_3,	0x33,	0x00	},
 38	{	XFER_PIO_2,	0x08,	0x00	},
 39	{	XFER_PIO_1,	0x0a,	0x00	},
 40	{	XFER_PIO_0,	0x00,	0x00	},
 41	{	0,		0x00,	0x00	}
 42};
 43
 44static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
 45	{	XFER_UDMA_6,	0x41,	0x06	},
 46	{	XFER_UDMA_5,	0x41,	0x05	},
 47	{	XFER_UDMA_4,	0x41,	0x04	},
 48	{	XFER_UDMA_3,	0x41,	0x03	},
 49	{	XFER_UDMA_2,	0x41,	0x02	},
 50	{	XFER_UDMA_1,	0x41,	0x01	},
 51	{	XFER_UDMA_0,	0x41,	0x01	},
 52
 53	{	XFER_MW_DMA_2,	0x41,	0x00	},
 54	{	XFER_MW_DMA_1,	0x42,	0x00	},
 55	{	XFER_MW_DMA_0,	0x7a,	0x00	},
 56	{	XFER_PIO_4,	0x41,	0x00	},
 57	{	XFER_PIO_3,	0x43,	0x00	},
 58	{	XFER_PIO_2,	0x78,	0x00	},
 59	{	XFER_PIO_1,	0x7a,	0x00	},
 60	{	XFER_PIO_0,	0x70,	0x00	},
 61	{	0,		0x00,	0x00	}
 62};
 63
 64/*
 65 * TO DO: active tuning and correction of cards without a bios.
 66 */
 67static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 68{
 69	for ( ; chipset_table->xfer_speed ; chipset_table++)
 70		if (chipset_table->xfer_speed == speed) {
 71			return chipset_table->chipset_settings;
 72		}
 73	return chipset_table->chipset_settings;
 74}
 75
 76static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 77{
 78	for ( ; chipset_table->xfer_speed ; chipset_table++)
 79		if (chipset_table->xfer_speed == speed) {
 80			return chipset_table->ultra_settings;
 81		}
 82	return chipset_table->ultra_settings;
 83}
 84
 85static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
 86{
 87	struct pci_dev *dev	= to_pci_dev(hwif->dev);
 88	struct ide_host *host	= pci_get_drvdata(dev);
 89	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
 90	u16 d_conf		= 0;
 91	u8 ultra = 0, ultra_conf = 0;
 92	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
 93	const u8 speed = drive->dma_mode;
 94	unsigned long flags;
 95
 96	local_irq_save(flags);
 97	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
 98	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
 99	tmp0 = pci_bus_clock_list(speed, bus_clock);
100	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
101	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
102
103	tmp1 = 0x00;
104	tmp2 = 0x00;
105	pci_read_config_byte(dev, 0x54, &ultra);
106	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
107	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
108	tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
109	pci_write_config_byte(dev, 0x54, tmp2);
110	local_irq_restore(flags);
111}
112
113static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
114{
115	struct pci_dev *dev	= to_pci_dev(hwif->dev);
116	struct ide_host *host	= pci_get_drvdata(dev);
117	struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
118	u8 unit			= drive->dn & 1;
119	u8 tmp1 = 0, tmp2 = 0;
120	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
121	const u8 speed = drive->dma_mode;
122	unsigned long flags;
123
124	local_irq_save(flags);
125	/* high 4-bits: Active, low 4-bits: Recovery */
126	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
127	drive_conf = pci_bus_clock_list(speed, bus_clock);
128	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
129
130	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
131	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
132	ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
133	tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
134	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
135	local_irq_restore(flags);
136}
137
138static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
139{
140	drive->dma_mode = drive->pio_mode;
141	hwif->port_ops->set_dma_mode(hwif, drive);
142}
143
144static int init_chipset_aec62xx(struct pci_dev *dev)
145{
146	/* These are necessary to get AEC6280 Macintosh cards to work */
147	if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
148	    (dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
149		u8 reg49h = 0, reg4ah = 0;
150		/* Clear reset and test bits.  */
151		pci_read_config_byte(dev, 0x49, &reg49h);
152		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
153		/* Enable chip interrupt output.  */
154		pci_read_config_byte(dev, 0x4a, &reg4ah);
155		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
156		/* Enable burst mode. */
157		pci_read_config_byte(dev, 0x4a, &reg4ah);
158		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
159	}
160
161	return 0;
162}
163
164static u8 atp86x_cable_detect(ide_hwif_t *hwif)
165{
166	struct pci_dev *dev = to_pci_dev(hwif->dev);
167	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
168
169	pci_read_config_byte(dev, 0x49, &ata66);
170
171	return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
172}
173
174static const struct ide_port_ops atp850_port_ops = {
175	.set_pio_mode		= aec_set_pio_mode,
176	.set_dma_mode		= aec6210_set_mode,
177};
178
179static const struct ide_port_ops atp86x_port_ops = {
180	.set_pio_mode		= aec_set_pio_mode,
181	.set_dma_mode		= aec6260_set_mode,
182	.cable_detect		= atp86x_cable_detect,
183};
184
185static const struct ide_port_info aec62xx_chipsets[] = {
186	{	/* 0: AEC6210 */
187		.name		= DRV_NAME,
188		.init_chipset	= init_chipset_aec62xx,
189		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
190		.port_ops	= &atp850_port_ops,
191		.host_flags	= IDE_HFLAG_SERIALIZE |
192				  IDE_HFLAG_NO_ATAPI_DMA |
193				  IDE_HFLAG_NO_DSC |
194				  IDE_HFLAG_OFF_BOARD,
195		.pio_mask	= ATA_PIO4,
196		.mwdma_mask	= ATA_MWDMA2,
197		.udma_mask	= ATA_UDMA2,
198	},
199	{	/* 1: AEC6260 */
200		.name		= DRV_NAME,
201		.init_chipset	= init_chipset_aec62xx,
202		.port_ops	= &atp86x_port_ops,
203		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
204				  IDE_HFLAG_OFF_BOARD,
205		.pio_mask	= ATA_PIO4,
206		.mwdma_mask	= ATA_MWDMA2,
207		.udma_mask	= ATA_UDMA4,
208	},
209	{	/* 2: AEC6260R */
210		.name		= DRV_NAME,
211		.init_chipset	= init_chipset_aec62xx,
212		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
213		.port_ops	= &atp86x_port_ops,
214		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
215				  IDE_HFLAG_NON_BOOTABLE,
216		.pio_mask	= ATA_PIO4,
217		.mwdma_mask	= ATA_MWDMA2,
218		.udma_mask	= ATA_UDMA4,
219	},
220	{	/* 3: AEC6280 */
221		.name		= DRV_NAME,
222		.init_chipset	= init_chipset_aec62xx,
223		.port_ops	= &atp86x_port_ops,
224		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
225				  IDE_HFLAG_OFF_BOARD,
226		.pio_mask	= ATA_PIO4,
227		.mwdma_mask	= ATA_MWDMA2,
228		.udma_mask	= ATA_UDMA5,
229	},
230	{	/* 4: AEC6280R */
231		.name		= DRV_NAME,
232		.init_chipset	= init_chipset_aec62xx,
233		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
234		.port_ops	= &atp86x_port_ops,
235		.host_flags	= IDE_HFLAG_NO_ATAPI_DMA |
236				  IDE_HFLAG_OFF_BOARD,
237		.pio_mask	= ATA_PIO4,
238		.mwdma_mask	= ATA_MWDMA2,
239		.udma_mask	= ATA_UDMA5,
240	}
241};
242
243/**
244 *	aec62xx_init_one	-	called when a AEC is found
245 *	@dev: the aec62xx device
246 *	@id: the matching pci id
247 *
248 *	Called when the PCI registration layer (or the IDE initialization)
249 *	finds a device matching our IDE device tables.
250 *
251 *	NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
252 *	chips, pass a local copy of 'struct ide_port_info' down the call chain.
253 */
254
255static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
256{
257	const struct chipset_bus_clock_list_entry *bus_clock;
258	struct ide_port_info d;
259	u8 idx = id->driver_data;
260	int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
261	int err;
262
263	if (bus_speed <= 33)
264		bus_clock = aec6xxx_33_base;
265	else
266		bus_clock = aec6xxx_34_base;
267
268	err = pci_enable_device(dev);
269	if (err)
270		return err;
271
272	d = aec62xx_chipsets[idx];
273
274	if (idx == 3 || idx == 4) {
275		unsigned long dma_base = pci_resource_start(dev, 4);
276
277		if (inb(dma_base + 2) & 0x10) {
278			printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
279				"\n", pci_name(dev), (idx == 4) ? "R" : "");
280			d.udma_mask = ATA_UDMA6;
281		}
282	}
283
284	err = ide_pci_init_one(dev, &d, (void *)bus_clock);
285	if (err)
286		pci_disable_device(dev);
287
288	return err;
289}
290
291static void aec62xx_remove(struct pci_dev *dev)
292{
293	ide_pci_remove(dev);
294	pci_disable_device(dev);
295}
296
297static const struct pci_device_id aec62xx_pci_tbl[] = {
298	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
299	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860),   1 },
300	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R),  2 },
301	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865),   3 },
302	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R),  4 },
303	{ 0, },
304};
305MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
306
307static struct pci_driver aec62xx_pci_driver = {
308	.name		= "AEC62xx_IDE",
309	.id_table	= aec62xx_pci_tbl,
310	.probe		= aec62xx_init_one,
311	.remove		= aec62xx_remove,
312	.suspend	= ide_pci_suspend,
313	.resume		= ide_pci_resume,
314};
315
316static int __init aec62xx_ide_init(void)
317{
318	return ide_pci_register_driver(&aec62xx_pci_driver);
319}
320
321static void __exit aec62xx_ide_exit(void)
322{
323	pci_unregister_driver(&aec62xx_pci_driver);
324}
325
326module_init(aec62xx_ide_init);
327module_exit(aec62xx_ide_exit);
328
329MODULE_AUTHOR("Andre Hedrick");
330MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
331MODULE_LICENSE("GPL");