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1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/circ_buf.h>
32#include <linux/slab.h>
33#include <linux/sysrq.h>
34
35#include <drm/drm_drv.h>
36#include <drm/drm_irq.h>
37
38#include "display/intel_display_types.h"
39#include "display/intel_fifo_underrun.h"
40#include "display/intel_hotplug.h"
41#include "display/intel_lpe_audio.h"
42#include "display/intel_psr.h"
43
44#include "gt/intel_gt.h"
45#include "gt/intel_gt_irq.h"
46#include "gt/intel_gt_pm_irq.h"
47#include "gt/intel_rps.h"
48
49#include "i915_drv.h"
50#include "i915_irq.h"
51#include "i915_trace.h"
52#include "intel_pm.h"
53
54/**
55 * DOC: interrupt handling
56 *
57 * These functions provide the basic support for enabling and disabling the
58 * interrupt handling support. There's a lot more functionality in i915_irq.c
59 * and related files, but that will be described in separate chapters.
60 */
61
62typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
63
64static const u32 hpd_ilk[HPD_NUM_PINS] = {
65 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
66};
67
68static const u32 hpd_ivb[HPD_NUM_PINS] = {
69 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
70};
71
72static const u32 hpd_bdw[HPD_NUM_PINS] = {
73 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
74};
75
76static const u32 hpd_ibx[HPD_NUM_PINS] = {
77 [HPD_CRT] = SDE_CRT_HOTPLUG,
78 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
79 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
80 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
81 [HPD_PORT_D] = SDE_PORTD_HOTPLUG,
82};
83
84static const u32 hpd_cpt[HPD_NUM_PINS] = {
85 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
86 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
87 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
88 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
89 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
90};
91
92static const u32 hpd_spt[HPD_NUM_PINS] = {
93 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
94 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
95 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
96 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
97 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT,
98};
99
100static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
101 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
102 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
103 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
104 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
105 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
106 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN,
107};
108
109static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
110 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
111 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
112 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
113 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
114 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
115 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
116};
117
118static const u32 hpd_status_i915[HPD_NUM_PINS] = {
119 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
120 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
121 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
122 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
123 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
124 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS,
125};
126
127static const u32 hpd_bxt[HPD_NUM_PINS] = {
128 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
129 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
130 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC,
131};
132
133static const u32 hpd_gen11[HPD_NUM_PINS] = {
134 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
135 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
136 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
137 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
138};
139
140static const u32 hpd_gen12[HPD_NUM_PINS] = {
141 [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
142 [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
143 [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
144 [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
145 [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
146 [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG,
147};
148
149static const u32 hpd_icp[HPD_NUM_PINS] = {
150 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
151 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
152 [HPD_PORT_C] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
153 [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
154 [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
155 [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
156};
157
158static const u32 hpd_tgp[HPD_NUM_PINS] = {
159 [HPD_PORT_A] = SDE_DDI_HOTPLUG_ICP(PORT_A),
160 [HPD_PORT_B] = SDE_DDI_HOTPLUG_ICP(PORT_B),
161 [HPD_PORT_C] = SDE_DDI_HOTPLUG_ICP(PORT_C),
162 [HPD_PORT_D] = SDE_TC_HOTPLUG_ICP(PORT_TC1),
163 [HPD_PORT_E] = SDE_TC_HOTPLUG_ICP(PORT_TC2),
164 [HPD_PORT_F] = SDE_TC_HOTPLUG_ICP(PORT_TC3),
165 [HPD_PORT_G] = SDE_TC_HOTPLUG_ICP(PORT_TC4),
166 [HPD_PORT_H] = SDE_TC_HOTPLUG_ICP(PORT_TC5),
167 [HPD_PORT_I] = SDE_TC_HOTPLUG_ICP(PORT_TC6),
168};
169
170static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
171{
172 struct i915_hotplug *hpd = &dev_priv->hotplug;
173
174 if (HAS_GMCH(dev_priv)) {
175 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
176 IS_CHERRYVIEW(dev_priv))
177 hpd->hpd = hpd_status_g4x;
178 else
179 hpd->hpd = hpd_status_i915;
180 return;
181 }
182
183 if (INTEL_GEN(dev_priv) >= 12)
184 hpd->hpd = hpd_gen12;
185 else if (INTEL_GEN(dev_priv) >= 11)
186 hpd->hpd = hpd_gen11;
187 else if (IS_GEN9_LP(dev_priv))
188 hpd->hpd = hpd_bxt;
189 else if (INTEL_GEN(dev_priv) >= 8)
190 hpd->hpd = hpd_bdw;
191 else if (INTEL_GEN(dev_priv) >= 7)
192 hpd->hpd = hpd_ivb;
193 else
194 hpd->hpd = hpd_ilk;
195
196 if (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))
197 return;
198
199 if (HAS_PCH_TGP(dev_priv) || HAS_PCH_JSP(dev_priv))
200 hpd->pch_hpd = hpd_tgp;
201 else if (HAS_PCH_ICP(dev_priv) || HAS_PCH_MCC(dev_priv))
202 hpd->pch_hpd = hpd_icp;
203 else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv))
204 hpd->pch_hpd = hpd_spt;
205 else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_CPT(dev_priv))
206 hpd->pch_hpd = hpd_cpt;
207 else if (HAS_PCH_IBX(dev_priv))
208 hpd->pch_hpd = hpd_ibx;
209 else
210 MISSING_CASE(INTEL_PCH_TYPE(dev_priv));
211}
212
213static void
214intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
215{
216 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
217
218 drm_crtc_handle_vblank(&crtc->base);
219}
220
221void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
222 i915_reg_t iir, i915_reg_t ier)
223{
224 intel_uncore_write(uncore, imr, 0xffffffff);
225 intel_uncore_posting_read(uncore, imr);
226
227 intel_uncore_write(uncore, ier, 0);
228
229 /* IIR can theoretically queue up two events. Be paranoid. */
230 intel_uncore_write(uncore, iir, 0xffffffff);
231 intel_uncore_posting_read(uncore, iir);
232 intel_uncore_write(uncore, iir, 0xffffffff);
233 intel_uncore_posting_read(uncore, iir);
234}
235
236void gen2_irq_reset(struct intel_uncore *uncore)
237{
238 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
239 intel_uncore_posting_read16(uncore, GEN2_IMR);
240
241 intel_uncore_write16(uncore, GEN2_IER, 0);
242
243 /* IIR can theoretically queue up two events. Be paranoid. */
244 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
245 intel_uncore_posting_read16(uncore, GEN2_IIR);
246 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
247 intel_uncore_posting_read16(uncore, GEN2_IIR);
248}
249
250/*
251 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
252 */
253static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
254{
255 u32 val = intel_uncore_read(uncore, reg);
256
257 if (val == 0)
258 return;
259
260 drm_WARN(&uncore->i915->drm, 1,
261 "Interrupt register 0x%x is not zero: 0x%08x\n",
262 i915_mmio_reg_offset(reg), val);
263 intel_uncore_write(uncore, reg, 0xffffffff);
264 intel_uncore_posting_read(uncore, reg);
265 intel_uncore_write(uncore, reg, 0xffffffff);
266 intel_uncore_posting_read(uncore, reg);
267}
268
269static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
270{
271 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
272
273 if (val == 0)
274 return;
275
276 drm_WARN(&uncore->i915->drm, 1,
277 "Interrupt register 0x%x is not zero: 0x%08x\n",
278 i915_mmio_reg_offset(GEN2_IIR), val);
279 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
280 intel_uncore_posting_read16(uncore, GEN2_IIR);
281 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
282 intel_uncore_posting_read16(uncore, GEN2_IIR);
283}
284
285void gen3_irq_init(struct intel_uncore *uncore,
286 i915_reg_t imr, u32 imr_val,
287 i915_reg_t ier, u32 ier_val,
288 i915_reg_t iir)
289{
290 gen3_assert_iir_is_zero(uncore, iir);
291
292 intel_uncore_write(uncore, ier, ier_val);
293 intel_uncore_write(uncore, imr, imr_val);
294 intel_uncore_posting_read(uncore, imr);
295}
296
297void gen2_irq_init(struct intel_uncore *uncore,
298 u32 imr_val, u32 ier_val)
299{
300 gen2_assert_iir_is_zero(uncore);
301
302 intel_uncore_write16(uncore, GEN2_IER, ier_val);
303 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
304 intel_uncore_posting_read16(uncore, GEN2_IMR);
305}
306
307/* For display hotplug interrupt */
308static inline void
309i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
310 u32 mask,
311 u32 bits)
312{
313 u32 val;
314
315 lockdep_assert_held(&dev_priv->irq_lock);
316 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
317
318 val = I915_READ(PORT_HOTPLUG_EN);
319 val &= ~mask;
320 val |= bits;
321 I915_WRITE(PORT_HOTPLUG_EN, val);
322}
323
324/**
325 * i915_hotplug_interrupt_update - update hotplug interrupt enable
326 * @dev_priv: driver private
327 * @mask: bits to update
328 * @bits: bits to enable
329 * NOTE: the HPD enable bits are modified both inside and outside
330 * of an interrupt context. To avoid that read-modify-write cycles
331 * interfer, these bits are protected by a spinlock. Since this
332 * function is usually not called from a context where the lock is
333 * held already, this function acquires the lock itself. A non-locking
334 * version is also available.
335 */
336void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
337 u32 mask,
338 u32 bits)
339{
340 spin_lock_irq(&dev_priv->irq_lock);
341 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
342 spin_unlock_irq(&dev_priv->irq_lock);
343}
344
345/**
346 * ilk_update_display_irq - update DEIMR
347 * @dev_priv: driver private
348 * @interrupt_mask: mask of interrupt bits to update
349 * @enabled_irq_mask: mask of interrupt bits to enable
350 */
351void ilk_update_display_irq(struct drm_i915_private *dev_priv,
352 u32 interrupt_mask,
353 u32 enabled_irq_mask)
354{
355 u32 new_val;
356
357 lockdep_assert_held(&dev_priv->irq_lock);
358
359 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
360
361 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
362 return;
363
364 new_val = dev_priv->irq_mask;
365 new_val &= ~interrupt_mask;
366 new_val |= (~enabled_irq_mask & interrupt_mask);
367
368 if (new_val != dev_priv->irq_mask) {
369 dev_priv->irq_mask = new_val;
370 I915_WRITE(DEIMR, dev_priv->irq_mask);
371 POSTING_READ(DEIMR);
372 }
373}
374
375/**
376 * bdw_update_port_irq - update DE port interrupt
377 * @dev_priv: driver private
378 * @interrupt_mask: mask of interrupt bits to update
379 * @enabled_irq_mask: mask of interrupt bits to enable
380 */
381static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
382 u32 interrupt_mask,
383 u32 enabled_irq_mask)
384{
385 u32 new_val;
386 u32 old_val;
387
388 lockdep_assert_held(&dev_priv->irq_lock);
389
390 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
391
392 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
393 return;
394
395 old_val = I915_READ(GEN8_DE_PORT_IMR);
396
397 new_val = old_val;
398 new_val &= ~interrupt_mask;
399 new_val |= (~enabled_irq_mask & interrupt_mask);
400
401 if (new_val != old_val) {
402 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
403 POSTING_READ(GEN8_DE_PORT_IMR);
404 }
405}
406
407/**
408 * bdw_update_pipe_irq - update DE pipe interrupt
409 * @dev_priv: driver private
410 * @pipe: pipe whose interrupt to update
411 * @interrupt_mask: mask of interrupt bits to update
412 * @enabled_irq_mask: mask of interrupt bits to enable
413 */
414void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
415 enum pipe pipe,
416 u32 interrupt_mask,
417 u32 enabled_irq_mask)
418{
419 u32 new_val;
420
421 lockdep_assert_held(&dev_priv->irq_lock);
422
423 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
424
425 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
426 return;
427
428 new_val = dev_priv->de_irq_mask[pipe];
429 new_val &= ~interrupt_mask;
430 new_val |= (~enabled_irq_mask & interrupt_mask);
431
432 if (new_val != dev_priv->de_irq_mask[pipe]) {
433 dev_priv->de_irq_mask[pipe] = new_val;
434 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
435 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
436 }
437}
438
439/**
440 * ibx_display_interrupt_update - update SDEIMR
441 * @dev_priv: driver private
442 * @interrupt_mask: mask of interrupt bits to update
443 * @enabled_irq_mask: mask of interrupt bits to enable
444 */
445void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
446 u32 interrupt_mask,
447 u32 enabled_irq_mask)
448{
449 u32 sdeimr = I915_READ(SDEIMR);
450 sdeimr &= ~interrupt_mask;
451 sdeimr |= (~enabled_irq_mask & interrupt_mask);
452
453 drm_WARN_ON(&dev_priv->drm, enabled_irq_mask & ~interrupt_mask);
454
455 lockdep_assert_held(&dev_priv->irq_lock);
456
457 if (drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv)))
458 return;
459
460 I915_WRITE(SDEIMR, sdeimr);
461 POSTING_READ(SDEIMR);
462}
463
464u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
465 enum pipe pipe)
466{
467 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
468 u32 enable_mask = status_mask << 16;
469
470 lockdep_assert_held(&dev_priv->irq_lock);
471
472 if (INTEL_GEN(dev_priv) < 5)
473 goto out;
474
475 /*
476 * On pipe A we don't support the PSR interrupt yet,
477 * on pipe B and C the same bit MBZ.
478 */
479 if (drm_WARN_ON_ONCE(&dev_priv->drm,
480 status_mask & PIPE_A_PSR_STATUS_VLV))
481 return 0;
482 /*
483 * On pipe B and C we don't support the PSR interrupt yet, on pipe
484 * A the same bit is for perf counters which we don't use either.
485 */
486 if (drm_WARN_ON_ONCE(&dev_priv->drm,
487 status_mask & PIPE_B_PSR_STATUS_VLV))
488 return 0;
489
490 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
491 SPRITE0_FLIP_DONE_INT_EN_VLV |
492 SPRITE1_FLIP_DONE_INT_EN_VLV);
493 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
494 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
495 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
496 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
497
498out:
499 drm_WARN_ONCE(&dev_priv->drm,
500 enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
501 status_mask & ~PIPESTAT_INT_STATUS_MASK,
502 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
503 pipe_name(pipe), enable_mask, status_mask);
504
505 return enable_mask;
506}
507
508void i915_enable_pipestat(struct drm_i915_private *dev_priv,
509 enum pipe pipe, u32 status_mask)
510{
511 i915_reg_t reg = PIPESTAT(pipe);
512 u32 enable_mask;
513
514 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
515 "pipe %c: status_mask=0x%x\n",
516 pipe_name(pipe), status_mask);
517
518 lockdep_assert_held(&dev_priv->irq_lock);
519 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
520
521 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
522 return;
523
524 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
525 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
526
527 I915_WRITE(reg, enable_mask | status_mask);
528 POSTING_READ(reg);
529}
530
531void i915_disable_pipestat(struct drm_i915_private *dev_priv,
532 enum pipe pipe, u32 status_mask)
533{
534 i915_reg_t reg = PIPESTAT(pipe);
535 u32 enable_mask;
536
537 drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK,
538 "pipe %c: status_mask=0x%x\n",
539 pipe_name(pipe), status_mask);
540
541 lockdep_assert_held(&dev_priv->irq_lock);
542 drm_WARN_ON(&dev_priv->drm, !intel_irqs_enabled(dev_priv));
543
544 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
545 return;
546
547 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
548 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
549
550 I915_WRITE(reg, enable_mask | status_mask);
551 POSTING_READ(reg);
552}
553
554static bool i915_has_asle(struct drm_i915_private *dev_priv)
555{
556 if (!dev_priv->opregion.asle)
557 return false;
558
559 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
560}
561
562/**
563 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
564 * @dev_priv: i915 device private
565 */
566static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
567{
568 if (!i915_has_asle(dev_priv))
569 return;
570
571 spin_lock_irq(&dev_priv->irq_lock);
572
573 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
574 if (INTEL_GEN(dev_priv) >= 4)
575 i915_enable_pipestat(dev_priv, PIPE_A,
576 PIPE_LEGACY_BLC_EVENT_STATUS);
577
578 spin_unlock_irq(&dev_priv->irq_lock);
579}
580
581/*
582 * This timing diagram depicts the video signal in and
583 * around the vertical blanking period.
584 *
585 * Assumptions about the fictitious mode used in this example:
586 * vblank_start >= 3
587 * vsync_start = vblank_start + 1
588 * vsync_end = vblank_start + 2
589 * vtotal = vblank_start + 3
590 *
591 * start of vblank:
592 * latch double buffered registers
593 * increment frame counter (ctg+)
594 * generate start of vblank interrupt (gen4+)
595 * |
596 * | frame start:
597 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
598 * | may be shifted forward 1-3 extra lines via PIPECONF
599 * | |
600 * | | start of vsync:
601 * | | generate vsync interrupt
602 * | | |
603 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
604 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
605 * ----va---> <-----------------vb--------------------> <--------va-------------
606 * | | <----vs-----> |
607 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
608 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
609 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
610 * | | |
611 * last visible pixel first visible pixel
612 * | increment frame counter (gen3/4)
613 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
614 *
615 * x = horizontal active
616 * _ = horizontal blanking
617 * hs = horizontal sync
618 * va = vertical active
619 * vb = vertical blanking
620 * vs = vertical sync
621 * vbs = vblank_start (number)
622 *
623 * Summary:
624 * - most events happen at the start of horizontal sync
625 * - frame start happens at the start of horizontal blank, 1-4 lines
626 * (depending on PIPECONF settings) after the start of vblank
627 * - gen3/4 pixel and frame counter are synchronized with the start
628 * of horizontal active on the first line of vertical active
629 */
630
631/* Called from drm generic code, passed a 'crtc', which
632 * we use as a pipe index
633 */
634u32 i915_get_vblank_counter(struct drm_crtc *crtc)
635{
636 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
637 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
638 const struct drm_display_mode *mode = &vblank->hwmode;
639 enum pipe pipe = to_intel_crtc(crtc)->pipe;
640 i915_reg_t high_frame, low_frame;
641 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
642 unsigned long irqflags;
643
644 /*
645 * On i965gm TV output the frame counter only works up to
646 * the point when we enable the TV encoder. After that the
647 * frame counter ceases to work and reads zero. We need a
648 * vblank wait before enabling the TV encoder and so we
649 * have to enable vblank interrupts while the frame counter
650 * is still in a working state. However the core vblank code
651 * does not like us returning non-zero frame counter values
652 * when we've told it that we don't have a working frame
653 * counter. Thus we must stop non-zero values leaking out.
654 */
655 if (!vblank->max_vblank_count)
656 return 0;
657
658 htotal = mode->crtc_htotal;
659 hsync_start = mode->crtc_hsync_start;
660 vbl_start = mode->crtc_vblank_start;
661 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
662 vbl_start = DIV_ROUND_UP(vbl_start, 2);
663
664 /* Convert to pixel count */
665 vbl_start *= htotal;
666
667 /* Start of vblank event occurs at start of hsync */
668 vbl_start -= htotal - hsync_start;
669
670 high_frame = PIPEFRAME(pipe);
671 low_frame = PIPEFRAMEPIXEL(pipe);
672
673 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
674
675 /*
676 * High & low register fields aren't synchronized, so make sure
677 * we get a low value that's stable across two reads of the high
678 * register.
679 */
680 do {
681 high1 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
682 low = intel_de_read_fw(dev_priv, low_frame);
683 high2 = intel_de_read_fw(dev_priv, high_frame) & PIPE_FRAME_HIGH_MASK;
684 } while (high1 != high2);
685
686 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
687
688 high1 >>= PIPE_FRAME_HIGH_SHIFT;
689 pixel = low & PIPE_PIXEL_MASK;
690 low >>= PIPE_FRAME_LOW_SHIFT;
691
692 /*
693 * The frame counter increments at beginning of active.
694 * Cook up a vblank counter by also checking the pixel
695 * counter against vblank start.
696 */
697 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
698}
699
700u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
701{
702 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
703 enum pipe pipe = to_intel_crtc(crtc)->pipe;
704
705 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
706}
707
708/*
709 * On certain encoders on certain platforms, pipe
710 * scanline register will not work to get the scanline,
711 * since the timings are driven from the PORT or issues
712 * with scanline register updates.
713 * This function will use Framestamp and current
714 * timestamp registers to calculate the scanline.
715 */
716static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
717{
718 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
719 struct drm_vblank_crtc *vblank =
720 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
721 const struct drm_display_mode *mode = &vblank->hwmode;
722 u32 vblank_start = mode->crtc_vblank_start;
723 u32 vtotal = mode->crtc_vtotal;
724 u32 htotal = mode->crtc_htotal;
725 u32 clock = mode->crtc_clock;
726 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
727
728 /*
729 * To avoid the race condition where we might cross into the
730 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
731 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
732 * during the same frame.
733 */
734 do {
735 /*
736 * This field provides read back of the display
737 * pipe frame time stamp. The time stamp value
738 * is sampled at every start of vertical blank.
739 */
740 scan_prev_time = intel_de_read_fw(dev_priv,
741 PIPE_FRMTMSTMP(crtc->pipe));
742
743 /*
744 * The TIMESTAMP_CTR register has the current
745 * time stamp value.
746 */
747 scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR);
748
749 scan_post_time = intel_de_read_fw(dev_priv,
750 PIPE_FRMTMSTMP(crtc->pipe));
751 } while (scan_post_time != scan_prev_time);
752
753 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
754 clock), 1000 * htotal);
755 scanline = min(scanline, vtotal - 1);
756 scanline = (scanline + vblank_start) % vtotal;
757
758 return scanline;
759}
760
761/*
762 * intel_de_read_fw(), only for fast reads of display block, no need for
763 * forcewake etc.
764 */
765static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
766{
767 struct drm_device *dev = crtc->base.dev;
768 struct drm_i915_private *dev_priv = to_i915(dev);
769 const struct drm_display_mode *mode;
770 struct drm_vblank_crtc *vblank;
771 enum pipe pipe = crtc->pipe;
772 int position, vtotal;
773
774 if (!crtc->active)
775 return -1;
776
777 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
778 mode = &vblank->hwmode;
779
780 if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
781 return __intel_get_crtc_scanline_from_timestamp(crtc);
782
783 vtotal = mode->crtc_vtotal;
784 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
785 vtotal /= 2;
786
787 if (IS_GEN(dev_priv, 2))
788 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
789 else
790 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
791
792 /*
793 * On HSW, the DSL reg (0x70000) appears to return 0 if we
794 * read it just before the start of vblank. So try it again
795 * so we don't accidentally end up spanning a vblank frame
796 * increment, causing the pipe_update_end() code to squak at us.
797 *
798 * The nature of this problem means we can't simply check the ISR
799 * bit and return the vblank start value; nor can we use the scanline
800 * debug register in the transcoder as it appears to have the same
801 * problem. We may need to extend this to include other platforms,
802 * but so far testing only shows the problem on HSW.
803 */
804 if (HAS_DDI(dev_priv) && !position) {
805 int i, temp;
806
807 for (i = 0; i < 100; i++) {
808 udelay(1);
809 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
810 if (temp != position) {
811 position = temp;
812 break;
813 }
814 }
815 }
816
817 /*
818 * See update_scanline_offset() for the details on the
819 * scanline_offset adjustment.
820 */
821 return (position + crtc->scanline_offset) % vtotal;
822}
823
824static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
825 bool in_vblank_irq,
826 int *vpos, int *hpos,
827 ktime_t *stime, ktime_t *etime,
828 const struct drm_display_mode *mode)
829{
830 struct drm_device *dev = _crtc->dev;
831 struct drm_i915_private *dev_priv = to_i915(dev);
832 struct intel_crtc *crtc = to_intel_crtc(_crtc);
833 enum pipe pipe = crtc->pipe;
834 int position;
835 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
836 unsigned long irqflags;
837 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
838 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
839 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
840
841 if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) {
842 drm_dbg(&dev_priv->drm,
843 "trying to get scanoutpos for disabled "
844 "pipe %c\n", pipe_name(pipe));
845 return false;
846 }
847
848 htotal = mode->crtc_htotal;
849 hsync_start = mode->crtc_hsync_start;
850 vtotal = mode->crtc_vtotal;
851 vbl_start = mode->crtc_vblank_start;
852 vbl_end = mode->crtc_vblank_end;
853
854 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
855 vbl_start = DIV_ROUND_UP(vbl_start, 2);
856 vbl_end /= 2;
857 vtotal /= 2;
858 }
859
860 /*
861 * Lock uncore.lock, as we will do multiple timing critical raw
862 * register reads, potentially with preemption disabled, so the
863 * following code must not block on uncore.lock.
864 */
865 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
866
867 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
868
869 /* Get optional system timestamp before query. */
870 if (stime)
871 *stime = ktime_get();
872
873 if (use_scanline_counter) {
874 /* No obvious pixelcount register. Only query vertical
875 * scanout position from Display scan line register.
876 */
877 position = __intel_get_crtc_scanline(crtc);
878 } else {
879 /* Have access to pixelcount since start of frame.
880 * We can split this into vertical and horizontal
881 * scanout position.
882 */
883 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
884
885 /* convert to pixel counts */
886 vbl_start *= htotal;
887 vbl_end *= htotal;
888 vtotal *= htotal;
889
890 /*
891 * In interlaced modes, the pixel counter counts all pixels,
892 * so one field will have htotal more pixels. In order to avoid
893 * the reported position from jumping backwards when the pixel
894 * counter is beyond the length of the shorter field, just
895 * clamp the position the length of the shorter field. This
896 * matches how the scanline counter based position works since
897 * the scanline counter doesn't count the two half lines.
898 */
899 if (position >= vtotal)
900 position = vtotal - 1;
901
902 /*
903 * Start of vblank interrupt is triggered at start of hsync,
904 * just prior to the first active line of vblank. However we
905 * consider lines to start at the leading edge of horizontal
906 * active. So, should we get here before we've crossed into
907 * the horizontal active of the first line in vblank, we would
908 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
909 * always add htotal-hsync_start to the current pixel position.
910 */
911 position = (position + htotal - hsync_start) % vtotal;
912 }
913
914 /* Get optional system timestamp after query. */
915 if (etime)
916 *etime = ktime_get();
917
918 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
919
920 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
921
922 /*
923 * While in vblank, position will be negative
924 * counting up towards 0 at vbl_end. And outside
925 * vblank, position will be positive counting
926 * up since vbl_end.
927 */
928 if (position >= vbl_start)
929 position -= vbl_end;
930 else
931 position += vtotal - vbl_end;
932
933 if (use_scanline_counter) {
934 *vpos = position;
935 *hpos = 0;
936 } else {
937 *vpos = position / htotal;
938 *hpos = position - (*vpos * htotal);
939 }
940
941 return true;
942}
943
944bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
945 ktime_t *vblank_time, bool in_vblank_irq)
946{
947 return drm_crtc_vblank_helper_get_vblank_timestamp_internal(
948 crtc, max_error, vblank_time, in_vblank_irq,
949 i915_get_crtc_scanoutpos);
950}
951
952int intel_get_crtc_scanline(struct intel_crtc *crtc)
953{
954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
955 unsigned long irqflags;
956 int position;
957
958 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
959 position = __intel_get_crtc_scanline(crtc);
960 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
961
962 return position;
963}
964
965/**
966 * ivb_parity_work - Workqueue called when a parity error interrupt
967 * occurred.
968 * @work: workqueue struct
969 *
970 * Doesn't actually do anything except notify userspace. As a consequence of
971 * this event, userspace should try to remap the bad rows since statistically
972 * it is likely the same row is more likely to go bad again.
973 */
974static void ivb_parity_work(struct work_struct *work)
975{
976 struct drm_i915_private *dev_priv =
977 container_of(work, typeof(*dev_priv), l3_parity.error_work);
978 struct intel_gt *gt = &dev_priv->gt;
979 u32 error_status, row, bank, subbank;
980 char *parity_event[6];
981 u32 misccpctl;
982 u8 slice = 0;
983
984 /* We must turn off DOP level clock gating to access the L3 registers.
985 * In order to prevent a get/put style interface, acquire struct mutex
986 * any time we access those registers.
987 */
988 mutex_lock(&dev_priv->drm.struct_mutex);
989
990 /* If we've screwed up tracking, just let the interrupt fire again */
991 if (drm_WARN_ON(&dev_priv->drm, !dev_priv->l3_parity.which_slice))
992 goto out;
993
994 misccpctl = I915_READ(GEN7_MISCCPCTL);
995 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
996 POSTING_READ(GEN7_MISCCPCTL);
997
998 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
999 i915_reg_t reg;
1000
1001 slice--;
1002 if (drm_WARN_ON_ONCE(&dev_priv->drm,
1003 slice >= NUM_L3_SLICES(dev_priv)))
1004 break;
1005
1006 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1007
1008 reg = GEN7_L3CDERRST1(slice);
1009
1010 error_status = I915_READ(reg);
1011 row = GEN7_PARITY_ERROR_ROW(error_status);
1012 bank = GEN7_PARITY_ERROR_BANK(error_status);
1013 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1014
1015 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1016 POSTING_READ(reg);
1017
1018 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1019 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1020 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1021 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1022 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1023 parity_event[5] = NULL;
1024
1025 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1026 KOBJ_CHANGE, parity_event);
1027
1028 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1029 slice, row, bank, subbank);
1030
1031 kfree(parity_event[4]);
1032 kfree(parity_event[3]);
1033 kfree(parity_event[2]);
1034 kfree(parity_event[1]);
1035 }
1036
1037 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1038
1039out:
1040 drm_WARN_ON(&dev_priv->drm, dev_priv->l3_parity.which_slice);
1041 spin_lock_irq(>->irq_lock);
1042 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1043 spin_unlock_irq(>->irq_lock);
1044
1045 mutex_unlock(&dev_priv->drm.struct_mutex);
1046}
1047
1048static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1049{
1050 switch (pin) {
1051 case HPD_PORT_C:
1052 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1053 case HPD_PORT_D:
1054 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1055 case HPD_PORT_E:
1056 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1057 case HPD_PORT_F:
1058 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1059 default:
1060 return false;
1061 }
1062}
1063
1064static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1065{
1066 switch (pin) {
1067 case HPD_PORT_D:
1068 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1069 case HPD_PORT_E:
1070 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1071 case HPD_PORT_F:
1072 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1073 case HPD_PORT_G:
1074 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1075 case HPD_PORT_H:
1076 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1077 case HPD_PORT_I:
1078 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1079 default:
1080 return false;
1081 }
1082}
1083
1084static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1085{
1086 switch (pin) {
1087 case HPD_PORT_A:
1088 return val & PORTA_HOTPLUG_LONG_DETECT;
1089 case HPD_PORT_B:
1090 return val & PORTB_HOTPLUG_LONG_DETECT;
1091 case HPD_PORT_C:
1092 return val & PORTC_HOTPLUG_LONG_DETECT;
1093 default:
1094 return false;
1095 }
1096}
1097
1098static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1099{
1100 switch (pin) {
1101 case HPD_PORT_A:
1102 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_A);
1103 case HPD_PORT_B:
1104 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_B);
1105 case HPD_PORT_C:
1106 return val & SHOTPLUG_CTL_DDI_HPD_LONG_DETECT(PORT_C);
1107 default:
1108 return false;
1109 }
1110}
1111
1112static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1113{
1114 switch (pin) {
1115 case HPD_PORT_C:
1116 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1117 case HPD_PORT_D:
1118 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1119 case HPD_PORT_E:
1120 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1121 case HPD_PORT_F:
1122 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1123 default:
1124 return false;
1125 }
1126}
1127
1128static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1129{
1130 switch (pin) {
1131 case HPD_PORT_D:
1132 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1133 case HPD_PORT_E:
1134 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1135 case HPD_PORT_F:
1136 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1137 case HPD_PORT_G:
1138 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1139 case HPD_PORT_H:
1140 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1141 case HPD_PORT_I:
1142 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1143 default:
1144 return false;
1145 }
1146}
1147
1148static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1149{
1150 switch (pin) {
1151 case HPD_PORT_E:
1152 return val & PORTE_HOTPLUG_LONG_DETECT;
1153 default:
1154 return false;
1155 }
1156}
1157
1158static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1159{
1160 switch (pin) {
1161 case HPD_PORT_A:
1162 return val & PORTA_HOTPLUG_LONG_DETECT;
1163 case HPD_PORT_B:
1164 return val & PORTB_HOTPLUG_LONG_DETECT;
1165 case HPD_PORT_C:
1166 return val & PORTC_HOTPLUG_LONG_DETECT;
1167 case HPD_PORT_D:
1168 return val & PORTD_HOTPLUG_LONG_DETECT;
1169 default:
1170 return false;
1171 }
1172}
1173
1174static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1175{
1176 switch (pin) {
1177 case HPD_PORT_A:
1178 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1179 default:
1180 return false;
1181 }
1182}
1183
1184static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1185{
1186 switch (pin) {
1187 case HPD_PORT_B:
1188 return val & PORTB_HOTPLUG_LONG_DETECT;
1189 case HPD_PORT_C:
1190 return val & PORTC_HOTPLUG_LONG_DETECT;
1191 case HPD_PORT_D:
1192 return val & PORTD_HOTPLUG_LONG_DETECT;
1193 default:
1194 return false;
1195 }
1196}
1197
1198static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1199{
1200 switch (pin) {
1201 case HPD_PORT_B:
1202 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1203 case HPD_PORT_C:
1204 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1205 case HPD_PORT_D:
1206 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1207 default:
1208 return false;
1209 }
1210}
1211
1212/*
1213 * Get a bit mask of pins that have triggered, and which ones may be long.
1214 * This can be called multiple times with the same masks to accumulate
1215 * hotplug detection results from several registers.
1216 *
1217 * Note that the caller is expected to zero out the masks initially.
1218 */
1219static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1220 u32 *pin_mask, u32 *long_mask,
1221 u32 hotplug_trigger, u32 dig_hotplug_reg,
1222 const u32 hpd[HPD_NUM_PINS],
1223 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1224{
1225 enum hpd_pin pin;
1226
1227 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1228
1229 for_each_hpd_pin(pin) {
1230 if ((hpd[pin] & hotplug_trigger) == 0)
1231 continue;
1232
1233 *pin_mask |= BIT(pin);
1234
1235 if (long_pulse_detect(pin, dig_hotplug_reg))
1236 *long_mask |= BIT(pin);
1237 }
1238
1239 drm_dbg(&dev_priv->drm,
1240 "hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1241 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1242
1243}
1244
1245static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1246{
1247 wake_up_all(&dev_priv->gmbus_wait_queue);
1248}
1249
1250static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1251{
1252 wake_up_all(&dev_priv->gmbus_wait_queue);
1253}
1254
1255#if defined(CONFIG_DEBUG_FS)
1256static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1257 enum pipe pipe,
1258 u32 crc0, u32 crc1,
1259 u32 crc2, u32 crc3,
1260 u32 crc4)
1261{
1262 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1263 struct intel_pipe_crc *pipe_crc = &crtc->pipe_crc;
1264 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1265
1266 trace_intel_pipe_crc(crtc, crcs);
1267
1268 spin_lock(&pipe_crc->lock);
1269 /*
1270 * For some not yet identified reason, the first CRC is
1271 * bonkers. So let's just wait for the next vblank and read
1272 * out the buggy result.
1273 *
1274 * On GEN8+ sometimes the second CRC is bonkers as well, so
1275 * don't trust that one either.
1276 */
1277 if (pipe_crc->skipped <= 0 ||
1278 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1279 pipe_crc->skipped++;
1280 spin_unlock(&pipe_crc->lock);
1281 return;
1282 }
1283 spin_unlock(&pipe_crc->lock);
1284
1285 drm_crtc_add_crc_entry(&crtc->base, true,
1286 drm_crtc_accurate_vblank_count(&crtc->base),
1287 crcs);
1288}
1289#else
1290static inline void
1291display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1292 enum pipe pipe,
1293 u32 crc0, u32 crc1,
1294 u32 crc2, u32 crc3,
1295 u32 crc4) {}
1296#endif
1297
1298
1299static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301{
1302 display_pipe_crc_irq_handler(dev_priv, pipe,
1303 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1304 0, 0, 0, 0);
1305}
1306
1307static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1308 enum pipe pipe)
1309{
1310 display_pipe_crc_irq_handler(dev_priv, pipe,
1311 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1312 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1313 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1314 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1315 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1316}
1317
1318static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1319 enum pipe pipe)
1320{
1321 u32 res1, res2;
1322
1323 if (INTEL_GEN(dev_priv) >= 3)
1324 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1325 else
1326 res1 = 0;
1327
1328 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1329 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1330 else
1331 res2 = 0;
1332
1333 display_pipe_crc_irq_handler(dev_priv, pipe,
1334 I915_READ(PIPE_CRC_RES_RED(pipe)),
1335 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1336 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1337 res1, res2);
1338}
1339
1340static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1341{
1342 enum pipe pipe;
1343
1344 for_each_pipe(dev_priv, pipe) {
1345 I915_WRITE(PIPESTAT(pipe),
1346 PIPESTAT_INT_STATUS_MASK |
1347 PIPE_FIFO_UNDERRUN_STATUS);
1348
1349 dev_priv->pipestat_irq_mask[pipe] = 0;
1350 }
1351}
1352
1353static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1354 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1355{
1356 enum pipe pipe;
1357
1358 spin_lock(&dev_priv->irq_lock);
1359
1360 if (!dev_priv->display_irqs_enabled) {
1361 spin_unlock(&dev_priv->irq_lock);
1362 return;
1363 }
1364
1365 for_each_pipe(dev_priv, pipe) {
1366 i915_reg_t reg;
1367 u32 status_mask, enable_mask, iir_bit = 0;
1368
1369 /*
1370 * PIPESTAT bits get signalled even when the interrupt is
1371 * disabled with the mask bits, and some of the status bits do
1372 * not generate interrupts at all (like the underrun bit). Hence
1373 * we need to be careful that we only handle what we want to
1374 * handle.
1375 */
1376
1377 /* fifo underruns are filterered in the underrun handler. */
1378 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1379
1380 switch (pipe) {
1381 default:
1382 case PIPE_A:
1383 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1384 break;
1385 case PIPE_B:
1386 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1387 break;
1388 case PIPE_C:
1389 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1390 break;
1391 }
1392 if (iir & iir_bit)
1393 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1394
1395 if (!status_mask)
1396 continue;
1397
1398 reg = PIPESTAT(pipe);
1399 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1400 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1401
1402 /*
1403 * Clear the PIPE*STAT regs before the IIR
1404 *
1405 * Toggle the enable bits to make sure we get an
1406 * edge in the ISR pipe event bit if we don't clear
1407 * all the enabled status bits. Otherwise the edge
1408 * triggered IIR on i965/g4x wouldn't notice that
1409 * an interrupt is still pending.
1410 */
1411 if (pipe_stats[pipe]) {
1412 I915_WRITE(reg, pipe_stats[pipe]);
1413 I915_WRITE(reg, enable_mask);
1414 }
1415 }
1416 spin_unlock(&dev_priv->irq_lock);
1417}
1418
1419static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1420 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1421{
1422 enum pipe pipe;
1423
1424 for_each_pipe(dev_priv, pipe) {
1425 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1426 intel_handle_vblank(dev_priv, pipe);
1427
1428 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1429 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1430
1431 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1432 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1433 }
1434}
1435
1436static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1437 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1438{
1439 bool blc_event = false;
1440 enum pipe pipe;
1441
1442 for_each_pipe(dev_priv, pipe) {
1443 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1444 intel_handle_vblank(dev_priv, pipe);
1445
1446 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1447 blc_event = true;
1448
1449 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1450 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1451
1452 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1453 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1454 }
1455
1456 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1457 intel_opregion_asle_intr(dev_priv);
1458}
1459
1460static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1461 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1462{
1463 bool blc_event = false;
1464 enum pipe pipe;
1465
1466 for_each_pipe(dev_priv, pipe) {
1467 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1468 intel_handle_vblank(dev_priv, pipe);
1469
1470 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1471 blc_event = true;
1472
1473 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1474 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1475
1476 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1477 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1478 }
1479
1480 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1481 intel_opregion_asle_intr(dev_priv);
1482
1483 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1484 gmbus_irq_handler(dev_priv);
1485}
1486
1487static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1488 u32 pipe_stats[I915_MAX_PIPES])
1489{
1490 enum pipe pipe;
1491
1492 for_each_pipe(dev_priv, pipe) {
1493 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1494 intel_handle_vblank(dev_priv, pipe);
1495
1496 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1497 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1498
1499 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1500 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1501 }
1502
1503 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1504 gmbus_irq_handler(dev_priv);
1505}
1506
1507static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1508{
1509 u32 hotplug_status = 0, hotplug_status_mask;
1510 int i;
1511
1512 if (IS_G4X(dev_priv) ||
1513 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1514 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1515 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1516 else
1517 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1518
1519 /*
1520 * We absolutely have to clear all the pending interrupt
1521 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1522 * interrupt bit won't have an edge, and the i965/g4x
1523 * edge triggered IIR will not notice that an interrupt
1524 * is still pending. We can't use PORT_HOTPLUG_EN to
1525 * guarantee the edge as the act of toggling the enable
1526 * bits can itself generate a new hotplug interrupt :(
1527 */
1528 for (i = 0; i < 10; i++) {
1529 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1530
1531 if (tmp == 0)
1532 return hotplug_status;
1533
1534 hotplug_status |= tmp;
1535 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1536 }
1537
1538 drm_WARN_ONCE(&dev_priv->drm, 1,
1539 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1540 I915_READ(PORT_HOTPLUG_STAT));
1541
1542 return hotplug_status;
1543}
1544
1545static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1546 u32 hotplug_status)
1547{
1548 u32 pin_mask = 0, long_mask = 0;
1549 u32 hotplug_trigger;
1550
1551 if (IS_G4X(dev_priv) ||
1552 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1553 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1554 else
1555 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1556
1557 if (hotplug_trigger) {
1558 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1559 hotplug_trigger, hotplug_trigger,
1560 dev_priv->hotplug.hpd,
1561 i9xx_port_hotplug_long_detect);
1562
1563 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1564 }
1565
1566 if ((IS_G4X(dev_priv) ||
1567 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1568 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1569 dp_aux_irq_handler(dev_priv);
1570}
1571
1572static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1573{
1574 struct drm_i915_private *dev_priv = arg;
1575 irqreturn_t ret = IRQ_NONE;
1576
1577 if (!intel_irqs_enabled(dev_priv))
1578 return IRQ_NONE;
1579
1580 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1581 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1582
1583 do {
1584 u32 iir, gt_iir, pm_iir;
1585 u32 pipe_stats[I915_MAX_PIPES] = {};
1586 u32 hotplug_status = 0;
1587 u32 ier = 0;
1588
1589 gt_iir = I915_READ(GTIIR);
1590 pm_iir = I915_READ(GEN6_PMIIR);
1591 iir = I915_READ(VLV_IIR);
1592
1593 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1594 break;
1595
1596 ret = IRQ_HANDLED;
1597
1598 /*
1599 * Theory on interrupt generation, based on empirical evidence:
1600 *
1601 * x = ((VLV_IIR & VLV_IER) ||
1602 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1603 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1604 *
1605 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1606 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1607 * guarantee the CPU interrupt will be raised again even if we
1608 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1609 * bits this time around.
1610 */
1611 I915_WRITE(VLV_MASTER_IER, 0);
1612 ier = I915_READ(VLV_IER);
1613 I915_WRITE(VLV_IER, 0);
1614
1615 if (gt_iir)
1616 I915_WRITE(GTIIR, gt_iir);
1617 if (pm_iir)
1618 I915_WRITE(GEN6_PMIIR, pm_iir);
1619
1620 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1621 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1622
1623 /* Call regardless, as some status bits might not be
1624 * signalled in iir */
1625 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1626
1627 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1628 I915_LPE_PIPE_B_INTERRUPT))
1629 intel_lpe_audio_irq_handler(dev_priv);
1630
1631 /*
1632 * VLV_IIR is single buffered, and reflects the level
1633 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1634 */
1635 if (iir)
1636 I915_WRITE(VLV_IIR, iir);
1637
1638 I915_WRITE(VLV_IER, ier);
1639 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1640
1641 if (gt_iir)
1642 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
1643 if (pm_iir)
1644 gen6_rps_irq_handler(&dev_priv->gt.rps, pm_iir);
1645
1646 if (hotplug_status)
1647 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1648
1649 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1650 } while (0);
1651
1652 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1653
1654 return ret;
1655}
1656
1657static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1658{
1659 struct drm_i915_private *dev_priv = arg;
1660 irqreturn_t ret = IRQ_NONE;
1661
1662 if (!intel_irqs_enabled(dev_priv))
1663 return IRQ_NONE;
1664
1665 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1666 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1667
1668 do {
1669 u32 master_ctl, iir;
1670 u32 pipe_stats[I915_MAX_PIPES] = {};
1671 u32 hotplug_status = 0;
1672 u32 ier = 0;
1673
1674 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1675 iir = I915_READ(VLV_IIR);
1676
1677 if (master_ctl == 0 && iir == 0)
1678 break;
1679
1680 ret = IRQ_HANDLED;
1681
1682 /*
1683 * Theory on interrupt generation, based on empirical evidence:
1684 *
1685 * x = ((VLV_IIR & VLV_IER) ||
1686 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
1687 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
1688 *
1689 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1690 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
1691 * guarantee the CPU interrupt will be raised again even if we
1692 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
1693 * bits this time around.
1694 */
1695 I915_WRITE(GEN8_MASTER_IRQ, 0);
1696 ier = I915_READ(VLV_IER);
1697 I915_WRITE(VLV_IER, 0);
1698
1699 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
1700
1701 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1702 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1703
1704 /* Call regardless, as some status bits might not be
1705 * signalled in iir */
1706 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1707
1708 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1709 I915_LPE_PIPE_B_INTERRUPT |
1710 I915_LPE_PIPE_C_INTERRUPT))
1711 intel_lpe_audio_irq_handler(dev_priv);
1712
1713 /*
1714 * VLV_IIR is single buffered, and reflects the level
1715 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
1716 */
1717 if (iir)
1718 I915_WRITE(VLV_IIR, iir);
1719
1720 I915_WRITE(VLV_IER, ier);
1721 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
1722
1723 if (hotplug_status)
1724 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
1725
1726 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
1727 } while (0);
1728
1729 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1730
1731 return ret;
1732}
1733
1734static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1735 u32 hotplug_trigger)
1736{
1737 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1738
1739 /*
1740 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
1741 * unless we touch the hotplug register, even if hotplug_trigger is
1742 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
1743 * errors.
1744 */
1745 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1746 if (!hotplug_trigger) {
1747 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
1748 PORTD_HOTPLUG_STATUS_MASK |
1749 PORTC_HOTPLUG_STATUS_MASK |
1750 PORTB_HOTPLUG_STATUS_MASK;
1751 dig_hotplug_reg &= ~mask;
1752 }
1753
1754 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1755 if (!hotplug_trigger)
1756 return;
1757
1758 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1759 hotplug_trigger, dig_hotplug_reg,
1760 dev_priv->hotplug.pch_hpd,
1761 pch_port_hotplug_long_detect);
1762
1763 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1764}
1765
1766static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1767{
1768 enum pipe pipe;
1769 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
1770
1771 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1772
1773 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1774 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1775 SDE_AUDIO_POWER_SHIFT);
1776 drm_dbg(&dev_priv->drm, "PCH audio power change on port %d\n",
1777 port_name(port));
1778 }
1779
1780 if (pch_iir & SDE_AUX_MASK)
1781 dp_aux_irq_handler(dev_priv);
1782
1783 if (pch_iir & SDE_GMBUS)
1784 gmbus_irq_handler(dev_priv);
1785
1786 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1787 drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
1788
1789 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1790 drm_dbg(&dev_priv->drm, "PCH transcoder audio interrupt\n");
1791
1792 if (pch_iir & SDE_POISON)
1793 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1794
1795 if (pch_iir & SDE_FDI_MASK) {
1796 for_each_pipe(dev_priv, pipe)
1797 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1798 pipe_name(pipe),
1799 I915_READ(FDI_RX_IIR(pipe)));
1800 }
1801
1802 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1803 drm_dbg(&dev_priv->drm, "PCH transcoder CRC done interrupt\n");
1804
1805 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1806 drm_dbg(&dev_priv->drm,
1807 "PCH transcoder CRC error interrupt\n");
1808
1809 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
1810 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
1811
1812 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
1813 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
1814}
1815
1816static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
1817{
1818 u32 err_int = I915_READ(GEN7_ERR_INT);
1819 enum pipe pipe;
1820
1821 if (err_int & ERR_INT_POISON)
1822 drm_err(&dev_priv->drm, "Poison interrupt\n");
1823
1824 for_each_pipe(dev_priv, pipe) {
1825 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1826 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1827
1828 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1829 if (IS_IVYBRIDGE(dev_priv))
1830 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1831 else
1832 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1833 }
1834 }
1835
1836 I915_WRITE(GEN7_ERR_INT, err_int);
1837}
1838
1839static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
1840{
1841 u32 serr_int = I915_READ(SERR_INT);
1842 enum pipe pipe;
1843
1844 if (serr_int & SERR_INT_POISON)
1845 drm_err(&dev_priv->drm, "PCH poison interrupt\n");
1846
1847 for_each_pipe(dev_priv, pipe)
1848 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1849 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1850
1851 I915_WRITE(SERR_INT, serr_int);
1852}
1853
1854static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1855{
1856 enum pipe pipe;
1857 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
1858
1859 ibx_hpd_irq_handler(dev_priv, hotplug_trigger);
1860
1861 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1862 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1863 SDE_AUDIO_POWER_SHIFT_CPT);
1864 drm_dbg(&dev_priv->drm, "PCH audio power change on port %c\n",
1865 port_name(port));
1866 }
1867
1868 if (pch_iir & SDE_AUX_MASK_CPT)
1869 dp_aux_irq_handler(dev_priv);
1870
1871 if (pch_iir & SDE_GMBUS_CPT)
1872 gmbus_irq_handler(dev_priv);
1873
1874 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1875 drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
1876
1877 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
1878 drm_dbg(&dev_priv->drm, "Audio CP change interrupt\n");
1879
1880 if (pch_iir & SDE_FDI_MASK_CPT) {
1881 for_each_pipe(dev_priv, pipe)
1882 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1883 pipe_name(pipe),
1884 I915_READ(FDI_RX_IIR(pipe)));
1885 }
1886
1887 if (pch_iir & SDE_ERROR_CPT)
1888 cpt_serr_int_handler(dev_priv);
1889}
1890
1891static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1892{
1893 u32 ddi_hotplug_trigger, tc_hotplug_trigger;
1894 u32 pin_mask = 0, long_mask = 0;
1895 bool (*tc_port_hotplug_long_detect)(enum hpd_pin pin, u32 val);
1896
1897 if (HAS_PCH_TGP(dev_priv)) {
1898 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1899 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
1900 tc_port_hotplug_long_detect = tgp_tc_port_hotplug_long_detect;
1901 } else if (HAS_PCH_JSP(dev_priv)) {
1902 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
1903 tc_hotplug_trigger = 0;
1904 } else if (HAS_PCH_MCC(dev_priv)) {
1905 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1906 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_ICP(PORT_TC1);
1907 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1908 } else {
1909 drm_WARN(&dev_priv->drm, !HAS_PCH_ICP(dev_priv),
1910 "Unrecognized PCH type 0x%x\n",
1911 INTEL_PCH_TYPE(dev_priv));
1912
1913 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
1914 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
1915 tc_port_hotplug_long_detect = icp_tc_port_hotplug_long_detect;
1916 }
1917
1918 if (ddi_hotplug_trigger) {
1919 u32 dig_hotplug_reg;
1920
1921 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
1922 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
1923
1924 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1925 ddi_hotplug_trigger, dig_hotplug_reg,
1926 dev_priv->hotplug.pch_hpd,
1927 icp_ddi_port_hotplug_long_detect);
1928 }
1929
1930 if (tc_hotplug_trigger) {
1931 u32 dig_hotplug_reg;
1932
1933 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
1934 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
1935
1936 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1937 tc_hotplug_trigger, dig_hotplug_reg,
1938 dev_priv->hotplug.pch_hpd,
1939 tc_port_hotplug_long_detect);
1940 }
1941
1942 if (pin_mask)
1943 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1944
1945 if (pch_iir & SDE_GMBUS_ICP)
1946 gmbus_irq_handler(dev_priv);
1947}
1948
1949static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
1950{
1951 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
1952 ~SDE_PORTE_HOTPLUG_SPT;
1953 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
1954 u32 pin_mask = 0, long_mask = 0;
1955
1956 if (hotplug_trigger) {
1957 u32 dig_hotplug_reg;
1958
1959 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1960 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1961
1962 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1963 hotplug_trigger, dig_hotplug_reg,
1964 dev_priv->hotplug.pch_hpd,
1965 spt_port_hotplug_long_detect);
1966 }
1967
1968 if (hotplug2_trigger) {
1969 u32 dig_hotplug_reg;
1970
1971 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
1972 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
1973
1974 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1975 hotplug2_trigger, dig_hotplug_reg,
1976 dev_priv->hotplug.pch_hpd,
1977 spt_port_hotplug2_long_detect);
1978 }
1979
1980 if (pin_mask)
1981 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1982
1983 if (pch_iir & SDE_GMBUS_CPT)
1984 gmbus_irq_handler(dev_priv);
1985}
1986
1987static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
1988 u32 hotplug_trigger)
1989{
1990 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
1991
1992 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
1993 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
1994
1995 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1996 hotplug_trigger, dig_hotplug_reg,
1997 dev_priv->hotplug.hpd,
1998 ilk_port_hotplug_long_detect);
1999
2000 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2001}
2002
2003static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2004 u32 de_iir)
2005{
2006 enum pipe pipe;
2007 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2008
2009 if (hotplug_trigger)
2010 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2011
2012 if (de_iir & DE_AUX_CHANNEL_A)
2013 dp_aux_irq_handler(dev_priv);
2014
2015 if (de_iir & DE_GSE)
2016 intel_opregion_asle_intr(dev_priv);
2017
2018 if (de_iir & DE_POISON)
2019 drm_err(&dev_priv->drm, "Poison interrupt\n");
2020
2021 for_each_pipe(dev_priv, pipe) {
2022 if (de_iir & DE_PIPE_VBLANK(pipe))
2023 intel_handle_vblank(dev_priv, pipe);
2024
2025 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2026 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2027
2028 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2029 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2030 }
2031
2032 /* check event from PCH */
2033 if (de_iir & DE_PCH_EVENT) {
2034 u32 pch_iir = I915_READ(SDEIIR);
2035
2036 if (HAS_PCH_CPT(dev_priv))
2037 cpt_irq_handler(dev_priv, pch_iir);
2038 else
2039 ibx_irq_handler(dev_priv, pch_iir);
2040
2041 /* should clear PCH hotplug event before clear CPU irq */
2042 I915_WRITE(SDEIIR, pch_iir);
2043 }
2044
2045 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2046 gen5_rps_irq_handler(&dev_priv->gt.rps);
2047}
2048
2049static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2050 u32 de_iir)
2051{
2052 enum pipe pipe;
2053 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2054
2055 if (hotplug_trigger)
2056 ilk_hpd_irq_handler(dev_priv, hotplug_trigger);
2057
2058 if (de_iir & DE_ERR_INT_IVB)
2059 ivb_err_int_handler(dev_priv);
2060
2061 if (de_iir & DE_EDP_PSR_INT_HSW) {
2062 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2063
2064 intel_psr_irq_handler(dev_priv, psr_iir);
2065 I915_WRITE(EDP_PSR_IIR, psr_iir);
2066 }
2067
2068 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2069 dp_aux_irq_handler(dev_priv);
2070
2071 if (de_iir & DE_GSE_IVB)
2072 intel_opregion_asle_intr(dev_priv);
2073
2074 for_each_pipe(dev_priv, pipe) {
2075 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2076 intel_handle_vblank(dev_priv, pipe);
2077 }
2078
2079 /* check event from PCH */
2080 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2081 u32 pch_iir = I915_READ(SDEIIR);
2082
2083 cpt_irq_handler(dev_priv, pch_iir);
2084
2085 /* clear PCH hotplug event before clear CPU irq */
2086 I915_WRITE(SDEIIR, pch_iir);
2087 }
2088}
2089
2090/*
2091 * To handle irqs with the minimum potential races with fresh interrupts, we:
2092 * 1 - Disable Master Interrupt Control.
2093 * 2 - Find the source(s) of the interrupt.
2094 * 3 - Clear the Interrupt Identity bits (IIR).
2095 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2096 * 5 - Re-enable Master Interrupt Control.
2097 */
2098static irqreturn_t ilk_irq_handler(int irq, void *arg)
2099{
2100 struct drm_i915_private *i915 = arg;
2101 void __iomem * const regs = i915->uncore.regs;
2102 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2103 irqreturn_t ret = IRQ_NONE;
2104
2105 if (unlikely(!intel_irqs_enabled(i915)))
2106 return IRQ_NONE;
2107
2108 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2109 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2110
2111 /* disable master interrupt before clearing iir */
2112 de_ier = raw_reg_read(regs, DEIER);
2113 raw_reg_write(regs, DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2114
2115 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2116 * interrupts will will be stored on its back queue, and then we'll be
2117 * able to process them after we restore SDEIER (as soon as we restore
2118 * it, we'll get an interrupt if SDEIIR still has something to process
2119 * due to its back queue). */
2120 if (!HAS_PCH_NOP(i915)) {
2121 sde_ier = raw_reg_read(regs, SDEIER);
2122 raw_reg_write(regs, SDEIER, 0);
2123 }
2124
2125 /* Find, clear, then process each source of interrupt */
2126
2127 gt_iir = raw_reg_read(regs, GTIIR);
2128 if (gt_iir) {
2129 raw_reg_write(regs, GTIIR, gt_iir);
2130 if (INTEL_GEN(i915) >= 6)
2131 gen6_gt_irq_handler(&i915->gt, gt_iir);
2132 else
2133 gen5_gt_irq_handler(&i915->gt, gt_iir);
2134 ret = IRQ_HANDLED;
2135 }
2136
2137 de_iir = raw_reg_read(regs, DEIIR);
2138 if (de_iir) {
2139 raw_reg_write(regs, DEIIR, de_iir);
2140 if (INTEL_GEN(i915) >= 7)
2141 ivb_display_irq_handler(i915, de_iir);
2142 else
2143 ilk_display_irq_handler(i915, de_iir);
2144 ret = IRQ_HANDLED;
2145 }
2146
2147 if (INTEL_GEN(i915) >= 6) {
2148 u32 pm_iir = raw_reg_read(regs, GEN6_PMIIR);
2149 if (pm_iir) {
2150 raw_reg_write(regs, GEN6_PMIIR, pm_iir);
2151 gen6_rps_irq_handler(&i915->gt.rps, pm_iir);
2152 ret = IRQ_HANDLED;
2153 }
2154 }
2155
2156 raw_reg_write(regs, DEIER, de_ier);
2157 if (sde_ier)
2158 raw_reg_write(regs, SDEIER, sde_ier);
2159
2160 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2161 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2162
2163 return ret;
2164}
2165
2166static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2167 u32 hotplug_trigger)
2168{
2169 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2170
2171 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2172 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2173
2174 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2175 hotplug_trigger, dig_hotplug_reg,
2176 dev_priv->hotplug.hpd,
2177 bxt_port_hotplug_long_detect);
2178
2179 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2180}
2181
2182static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2183{
2184 u32 pin_mask = 0, long_mask = 0;
2185 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2186 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2187 long_pulse_detect_func long_pulse_detect;
2188
2189 if (INTEL_GEN(dev_priv) >= 12)
2190 long_pulse_detect = gen12_port_hotplug_long_detect;
2191 else
2192 long_pulse_detect = gen11_port_hotplug_long_detect;
2193
2194 if (trigger_tc) {
2195 u32 dig_hotplug_reg;
2196
2197 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2198 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2199
2200 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2201 trigger_tc, dig_hotplug_reg,
2202 dev_priv->hotplug.hpd,
2203 long_pulse_detect);
2204 }
2205
2206 if (trigger_tbt) {
2207 u32 dig_hotplug_reg;
2208
2209 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2210 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2211
2212 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2213 trigger_tbt, dig_hotplug_reg,
2214 dev_priv->hotplug.hpd,
2215 long_pulse_detect);
2216 }
2217
2218 if (pin_mask)
2219 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2220 else
2221 drm_err(&dev_priv->drm,
2222 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2223}
2224
2225static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2226{
2227 u32 mask;
2228
2229 if (INTEL_GEN(dev_priv) >= 12)
2230 return TGL_DE_PORT_AUX_DDIA |
2231 TGL_DE_PORT_AUX_DDIB |
2232 TGL_DE_PORT_AUX_DDIC |
2233 TGL_DE_PORT_AUX_USBC1 |
2234 TGL_DE_PORT_AUX_USBC2 |
2235 TGL_DE_PORT_AUX_USBC3 |
2236 TGL_DE_PORT_AUX_USBC4 |
2237 TGL_DE_PORT_AUX_USBC5 |
2238 TGL_DE_PORT_AUX_USBC6;
2239
2240
2241 mask = GEN8_AUX_CHANNEL_A;
2242 if (INTEL_GEN(dev_priv) >= 9)
2243 mask |= GEN9_AUX_CHANNEL_B |
2244 GEN9_AUX_CHANNEL_C |
2245 GEN9_AUX_CHANNEL_D;
2246
2247 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2248 mask |= CNL_AUX_CHANNEL_F;
2249
2250 if (IS_GEN(dev_priv, 11))
2251 mask |= ICL_AUX_CHANNEL_E;
2252
2253 return mask;
2254}
2255
2256static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2257{
2258 if (IS_ROCKETLAKE(dev_priv))
2259 return RKL_DE_PIPE_IRQ_FAULT_ERRORS;
2260 else if (INTEL_GEN(dev_priv) >= 11)
2261 return GEN11_DE_PIPE_IRQ_FAULT_ERRORS;
2262 else if (INTEL_GEN(dev_priv) >= 9)
2263 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2264 else
2265 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2266}
2267
2268static void
2269gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2270{
2271 bool found = false;
2272
2273 if (iir & GEN8_DE_MISC_GSE) {
2274 intel_opregion_asle_intr(dev_priv);
2275 found = true;
2276 }
2277
2278 if (iir & GEN8_DE_EDP_PSR) {
2279 u32 psr_iir;
2280 i915_reg_t iir_reg;
2281
2282 if (INTEL_GEN(dev_priv) >= 12)
2283 iir_reg = TRANS_PSR_IIR(dev_priv->psr.transcoder);
2284 else
2285 iir_reg = EDP_PSR_IIR;
2286
2287 psr_iir = I915_READ(iir_reg);
2288 I915_WRITE(iir_reg, psr_iir);
2289
2290 if (psr_iir)
2291 found = true;
2292
2293 intel_psr_irq_handler(dev_priv, psr_iir);
2294 }
2295
2296 if (!found)
2297 drm_err(&dev_priv->drm, "Unexpected DE Misc interrupt\n");
2298}
2299
2300static irqreturn_t
2301gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2302{
2303 irqreturn_t ret = IRQ_NONE;
2304 u32 iir;
2305 enum pipe pipe;
2306
2307 if (master_ctl & GEN8_DE_MISC_IRQ) {
2308 iir = I915_READ(GEN8_DE_MISC_IIR);
2309 if (iir) {
2310 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2311 ret = IRQ_HANDLED;
2312 gen8_de_misc_irq_handler(dev_priv, iir);
2313 } else {
2314 drm_err(&dev_priv->drm,
2315 "The master control interrupt lied (DE MISC)!\n");
2316 }
2317 }
2318
2319 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2320 iir = I915_READ(GEN11_DE_HPD_IIR);
2321 if (iir) {
2322 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2323 ret = IRQ_HANDLED;
2324 gen11_hpd_irq_handler(dev_priv, iir);
2325 } else {
2326 drm_err(&dev_priv->drm,
2327 "The master control interrupt lied, (DE HPD)!\n");
2328 }
2329 }
2330
2331 if (master_ctl & GEN8_DE_PORT_IRQ) {
2332 iir = I915_READ(GEN8_DE_PORT_IIR);
2333 if (iir) {
2334 u32 tmp_mask;
2335 bool found = false;
2336
2337 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2338 ret = IRQ_HANDLED;
2339
2340 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2341 dp_aux_irq_handler(dev_priv);
2342 found = true;
2343 }
2344
2345 if (IS_GEN9_LP(dev_priv)) {
2346 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2347 if (tmp_mask) {
2348 bxt_hpd_irq_handler(dev_priv, tmp_mask);
2349 found = true;
2350 }
2351 } else if (IS_BROADWELL(dev_priv)) {
2352 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2353 if (tmp_mask) {
2354 ilk_hpd_irq_handler(dev_priv, tmp_mask);
2355 found = true;
2356 }
2357 }
2358
2359 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2360 gmbus_irq_handler(dev_priv);
2361 found = true;
2362 }
2363
2364 if (!found)
2365 drm_err(&dev_priv->drm,
2366 "Unexpected DE Port interrupt\n");
2367 }
2368 else
2369 drm_err(&dev_priv->drm,
2370 "The master control interrupt lied (DE PORT)!\n");
2371 }
2372
2373 for_each_pipe(dev_priv, pipe) {
2374 u32 fault_errors;
2375
2376 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2377 continue;
2378
2379 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2380 if (!iir) {
2381 drm_err(&dev_priv->drm,
2382 "The master control interrupt lied (DE PIPE)!\n");
2383 continue;
2384 }
2385
2386 ret = IRQ_HANDLED;
2387 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2388
2389 if (iir & GEN8_PIPE_VBLANK)
2390 intel_handle_vblank(dev_priv, pipe);
2391
2392 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2393 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2394
2395 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2396 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2397
2398 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2399 if (fault_errors)
2400 drm_err(&dev_priv->drm,
2401 "Fault errors on pipe %c: 0x%08x\n",
2402 pipe_name(pipe),
2403 fault_errors);
2404 }
2405
2406 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2407 master_ctl & GEN8_DE_PCH_IRQ) {
2408 /*
2409 * FIXME(BDW): Assume for now that the new interrupt handling
2410 * scheme also closed the SDE interrupt handling race we've seen
2411 * on older pch-split platforms. But this needs testing.
2412 */
2413 iir = I915_READ(SDEIIR);
2414 if (iir) {
2415 I915_WRITE(SDEIIR, iir);
2416 ret = IRQ_HANDLED;
2417
2418 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2419 icp_irq_handler(dev_priv, iir);
2420 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2421 spt_irq_handler(dev_priv, iir);
2422 else
2423 cpt_irq_handler(dev_priv, iir);
2424 } else {
2425 /*
2426 * Like on previous PCH there seems to be something
2427 * fishy going on with forwarding PCH interrupts.
2428 */
2429 drm_dbg(&dev_priv->drm,
2430 "The master control interrupt lied (SDE)!\n");
2431 }
2432 }
2433
2434 return ret;
2435}
2436
2437static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2438{
2439 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2440
2441 /*
2442 * Now with master disabled, get a sample of level indications
2443 * for this interrupt. Indications will be cleared on related acks.
2444 * New indications can and will light up during processing,
2445 * and will generate new interrupt after enabling master.
2446 */
2447 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2448}
2449
2450static inline void gen8_master_intr_enable(void __iomem * const regs)
2451{
2452 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2453}
2454
2455static irqreturn_t gen8_irq_handler(int irq, void *arg)
2456{
2457 struct drm_i915_private *dev_priv = arg;
2458 void __iomem * const regs = dev_priv->uncore.regs;
2459 u32 master_ctl;
2460
2461 if (!intel_irqs_enabled(dev_priv))
2462 return IRQ_NONE;
2463
2464 master_ctl = gen8_master_intr_disable(regs);
2465 if (!master_ctl) {
2466 gen8_master_intr_enable(regs);
2467 return IRQ_NONE;
2468 }
2469
2470 /* Find, queue (onto bottom-halves), then clear each source */
2471 gen8_gt_irq_handler(&dev_priv->gt, master_ctl);
2472
2473 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2474 if (master_ctl & ~GEN8_GT_IRQS) {
2475 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2476 gen8_de_irq_handler(dev_priv, master_ctl);
2477 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2478 }
2479
2480 gen8_master_intr_enable(regs);
2481
2482 return IRQ_HANDLED;
2483}
2484
2485static u32
2486gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2487{
2488 void __iomem * const regs = gt->uncore->regs;
2489 u32 iir;
2490
2491 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2492 return 0;
2493
2494 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2495 if (likely(iir))
2496 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2497
2498 return iir;
2499}
2500
2501static void
2502gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2503{
2504 if (iir & GEN11_GU_MISC_GSE)
2505 intel_opregion_asle_intr(gt->i915);
2506}
2507
2508static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2509{
2510 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2511
2512 /*
2513 * Now with master disabled, get a sample of level indications
2514 * for this interrupt. Indications will be cleared on related acks.
2515 * New indications can and will light up during processing,
2516 * and will generate new interrupt after enabling master.
2517 */
2518 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2519}
2520
2521static inline void gen11_master_intr_enable(void __iomem * const regs)
2522{
2523 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2524}
2525
2526static void
2527gen11_display_irq_handler(struct drm_i915_private *i915)
2528{
2529 void __iomem * const regs = i915->uncore.regs;
2530 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2531
2532 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2533 /*
2534 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2535 * for the display related bits.
2536 */
2537 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL, 0x0);
2538 gen8_de_irq_handler(i915, disp_ctl);
2539 raw_reg_write(regs, GEN11_DISPLAY_INT_CTL,
2540 GEN11_DISPLAY_IRQ_ENABLE);
2541
2542 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2543}
2544
2545static __always_inline irqreturn_t
2546__gen11_irq_handler(struct drm_i915_private * const i915,
2547 u32 (*intr_disable)(void __iomem * const regs),
2548 void (*intr_enable)(void __iomem * const regs))
2549{
2550 void __iomem * const regs = i915->uncore.regs;
2551 struct intel_gt *gt = &i915->gt;
2552 u32 master_ctl;
2553 u32 gu_misc_iir;
2554
2555 if (!intel_irqs_enabled(i915))
2556 return IRQ_NONE;
2557
2558 master_ctl = intr_disable(regs);
2559 if (!master_ctl) {
2560 intr_enable(regs);
2561 return IRQ_NONE;
2562 }
2563
2564 /* Find, queue (onto bottom-halves), then clear each source */
2565 gen11_gt_irq_handler(gt, master_ctl);
2566
2567 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2568 if (master_ctl & GEN11_DISPLAY_IRQ)
2569 gen11_display_irq_handler(i915);
2570
2571 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2572
2573 intr_enable(regs);
2574
2575 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2576
2577 return IRQ_HANDLED;
2578}
2579
2580static irqreturn_t gen11_irq_handler(int irq, void *arg)
2581{
2582 return __gen11_irq_handler(arg,
2583 gen11_master_intr_disable,
2584 gen11_master_intr_enable);
2585}
2586
2587static u32 dg1_master_intr_disable_and_ack(void __iomem * const regs)
2588{
2589 u32 val;
2590
2591 /* First disable interrupts */
2592 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, 0);
2593
2594 /* Get the indication levels and ack the master unit */
2595 val = raw_reg_read(regs, DG1_MSTR_UNIT_INTR);
2596 if (unlikely(!val))
2597 return 0;
2598
2599 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, val);
2600
2601 /*
2602 * Now with master disabled, get a sample of level indications
2603 * for this interrupt and ack them right away - we keep GEN11_MASTER_IRQ
2604 * out as this bit doesn't exist anymore for DG1
2605 */
2606 val = raw_reg_read(regs, GEN11_GFX_MSTR_IRQ) & ~GEN11_MASTER_IRQ;
2607 if (unlikely(!val))
2608 return 0;
2609
2610 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, val);
2611
2612 return val;
2613}
2614
2615static inline void dg1_master_intr_enable(void __iomem * const regs)
2616{
2617 raw_reg_write(regs, DG1_MSTR_UNIT_INTR, DG1_MSTR_IRQ);
2618}
2619
2620static irqreturn_t dg1_irq_handler(int irq, void *arg)
2621{
2622 return __gen11_irq_handler(arg,
2623 dg1_master_intr_disable_and_ack,
2624 dg1_master_intr_enable);
2625}
2626
2627/* Called from drm generic code, passed 'crtc' which
2628 * we use as a pipe index
2629 */
2630int i8xx_enable_vblank(struct drm_crtc *crtc)
2631{
2632 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2633 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2634 unsigned long irqflags;
2635
2636 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2637 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2638 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2639
2640 return 0;
2641}
2642
2643int i915gm_enable_vblank(struct drm_crtc *crtc)
2644{
2645 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2646
2647 /*
2648 * Vblank interrupts fail to wake the device up from C2+.
2649 * Disabling render clock gating during C-states avoids
2650 * the problem. There is a small power cost so we do this
2651 * only when vblank interrupts are actually enabled.
2652 */
2653 if (dev_priv->vblank_enabled++ == 0)
2654 I915_WRITE(SCPD0, _MASKED_BIT_ENABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2655
2656 return i8xx_enable_vblank(crtc);
2657}
2658
2659int i965_enable_vblank(struct drm_crtc *crtc)
2660{
2661 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2662 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2663 unsigned long irqflags;
2664
2665 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2666 i915_enable_pipestat(dev_priv, pipe,
2667 PIPE_START_VBLANK_INTERRUPT_STATUS);
2668 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2669
2670 return 0;
2671}
2672
2673int ilk_enable_vblank(struct drm_crtc *crtc)
2674{
2675 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2676 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2677 unsigned long irqflags;
2678 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2679 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2680
2681 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2682 ilk_enable_display_irq(dev_priv, bit);
2683 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2684
2685 /* Even though there is no DMC, frame counter can get stuck when
2686 * PSR is active as no frames are generated.
2687 */
2688 if (HAS_PSR(dev_priv))
2689 drm_crtc_vblank_restore(crtc);
2690
2691 return 0;
2692}
2693
2694int bdw_enable_vblank(struct drm_crtc *crtc)
2695{
2696 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2697 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2698 unsigned long irqflags;
2699
2700 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2701 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2702 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2703
2704 /* Even if there is no DMC, frame counter can get stuck when
2705 * PSR is active as no frames are generated, so check only for PSR.
2706 */
2707 if (HAS_PSR(dev_priv))
2708 drm_crtc_vblank_restore(crtc);
2709
2710 return 0;
2711}
2712
2713/* Called from drm generic code, passed 'crtc' which
2714 * we use as a pipe index
2715 */
2716void i8xx_disable_vblank(struct drm_crtc *crtc)
2717{
2718 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2719 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2720 unsigned long irqflags;
2721
2722 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2723 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2724 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2725}
2726
2727void i915gm_disable_vblank(struct drm_crtc *crtc)
2728{
2729 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2730
2731 i8xx_disable_vblank(crtc);
2732
2733 if (--dev_priv->vblank_enabled == 0)
2734 I915_WRITE(SCPD0, _MASKED_BIT_DISABLE(CSTATE_RENDER_CLOCK_GATE_DISABLE));
2735}
2736
2737void i965_disable_vblank(struct drm_crtc *crtc)
2738{
2739 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2740 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2741 unsigned long irqflags;
2742
2743 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2744 i915_disable_pipestat(dev_priv, pipe,
2745 PIPE_START_VBLANK_INTERRUPT_STATUS);
2746 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2747}
2748
2749void ilk_disable_vblank(struct drm_crtc *crtc)
2750{
2751 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2752 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2753 unsigned long irqflags;
2754 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2755 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2756
2757 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2758 ilk_disable_display_irq(dev_priv, bit);
2759 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2760}
2761
2762void bdw_disable_vblank(struct drm_crtc *crtc)
2763{
2764 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2765 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2766 unsigned long irqflags;
2767
2768 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2769 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2770 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2771}
2772
2773static void ibx_irq_reset(struct drm_i915_private *dev_priv)
2774{
2775 struct intel_uncore *uncore = &dev_priv->uncore;
2776
2777 if (HAS_PCH_NOP(dev_priv))
2778 return;
2779
2780 GEN3_IRQ_RESET(uncore, SDE);
2781
2782 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
2783 I915_WRITE(SERR_INT, 0xffffffff);
2784}
2785
2786/*
2787 * SDEIER is also touched by the interrupt handler to work around missed PCH
2788 * interrupts. Hence we can't update it after the interrupt handler is enabled -
2789 * instead we unconditionally enable all PCH interrupt sources here, but then
2790 * only unmask them as needed with SDEIMR.
2791 *
2792 * This function needs to be called before interrupts are enabled.
2793 */
2794static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
2795{
2796 if (HAS_PCH_NOP(dev_priv))
2797 return;
2798
2799 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
2800 I915_WRITE(SDEIER, 0xffffffff);
2801 POSTING_READ(SDEIER);
2802}
2803
2804static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
2805{
2806 struct intel_uncore *uncore = &dev_priv->uncore;
2807
2808 if (IS_CHERRYVIEW(dev_priv))
2809 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
2810 else
2811 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
2812
2813 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
2814 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2815
2816 i9xx_pipestat_irq_reset(dev_priv);
2817
2818 GEN3_IRQ_RESET(uncore, VLV_);
2819 dev_priv->irq_mask = ~0u;
2820}
2821
2822static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
2823{
2824 struct intel_uncore *uncore = &dev_priv->uncore;
2825
2826 u32 pipestat_mask;
2827 u32 enable_mask;
2828 enum pipe pipe;
2829
2830 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
2831
2832 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
2833 for_each_pipe(dev_priv, pipe)
2834 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2835
2836 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
2837 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2838 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2839 I915_LPE_PIPE_A_INTERRUPT |
2840 I915_LPE_PIPE_B_INTERRUPT;
2841
2842 if (IS_CHERRYVIEW(dev_priv))
2843 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
2844 I915_LPE_PIPE_C_INTERRUPT;
2845
2846 drm_WARN_ON(&dev_priv->drm, dev_priv->irq_mask != ~0u);
2847
2848 dev_priv->irq_mask = ~enable_mask;
2849
2850 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
2851}
2852
2853/* drm_dma.h hooks
2854*/
2855static void ilk_irq_reset(struct drm_i915_private *dev_priv)
2856{
2857 struct intel_uncore *uncore = &dev_priv->uncore;
2858
2859 GEN3_IRQ_RESET(uncore, DE);
2860 if (IS_GEN(dev_priv, 7))
2861 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
2862
2863 if (IS_HASWELL(dev_priv)) {
2864 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2865 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2866 }
2867
2868 gen5_gt_irq_reset(&dev_priv->gt);
2869
2870 ibx_irq_reset(dev_priv);
2871}
2872
2873static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
2874{
2875 I915_WRITE(VLV_MASTER_IER, 0);
2876 POSTING_READ(VLV_MASTER_IER);
2877
2878 gen5_gt_irq_reset(&dev_priv->gt);
2879
2880 spin_lock_irq(&dev_priv->irq_lock);
2881 if (dev_priv->display_irqs_enabled)
2882 vlv_display_irq_reset(dev_priv);
2883 spin_unlock_irq(&dev_priv->irq_lock);
2884}
2885
2886static void gen8_irq_reset(struct drm_i915_private *dev_priv)
2887{
2888 struct intel_uncore *uncore = &dev_priv->uncore;
2889 enum pipe pipe;
2890
2891 gen8_master_intr_disable(dev_priv->uncore.regs);
2892
2893 gen8_gt_irq_reset(&dev_priv->gt);
2894
2895 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2896 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2897
2898 for_each_pipe(dev_priv, pipe)
2899 if (intel_display_power_is_enabled(dev_priv,
2900 POWER_DOMAIN_PIPE(pipe)))
2901 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2902
2903 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2904 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2905 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2906
2907 if (HAS_PCH_SPLIT(dev_priv))
2908 ibx_irq_reset(dev_priv);
2909}
2910
2911static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
2912{
2913 struct intel_uncore *uncore = &dev_priv->uncore;
2914 enum pipe pipe;
2915 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
2916 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
2917
2918 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
2919
2920 if (INTEL_GEN(dev_priv) >= 12) {
2921 enum transcoder trans;
2922
2923 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
2924 enum intel_display_power_domain domain;
2925
2926 domain = POWER_DOMAIN_TRANSCODER(trans);
2927 if (!intel_display_power_is_enabled(dev_priv, domain))
2928 continue;
2929
2930 intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff);
2931 intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff);
2932 }
2933 } else {
2934 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
2935 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
2936 }
2937
2938 for_each_pipe(dev_priv, pipe)
2939 if (intel_display_power_is_enabled(dev_priv,
2940 POWER_DOMAIN_PIPE(pipe)))
2941 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2942
2943 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
2944 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
2945 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
2946
2947 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2948 GEN3_IRQ_RESET(uncore, SDE);
2949
2950 /* Wa_14010685332:icl,jsl,ehl,tgl,rkl */
2951 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
2952 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2953 SBCLK_RUN_REFCLK_DIS, SBCLK_RUN_REFCLK_DIS);
2954 intel_uncore_rmw(uncore, SOUTH_CHICKEN1,
2955 SBCLK_RUN_REFCLK_DIS, 0);
2956 }
2957}
2958
2959static void gen11_irq_reset(struct drm_i915_private *dev_priv)
2960{
2961 struct intel_uncore *uncore = &dev_priv->uncore;
2962
2963 if (HAS_MASTER_UNIT_IRQ(dev_priv))
2964 dg1_master_intr_disable_and_ack(dev_priv->uncore.regs);
2965 else
2966 gen11_master_intr_disable(dev_priv->uncore.regs);
2967
2968 gen11_gt_irq_reset(&dev_priv->gt);
2969 gen11_display_irq_reset(dev_priv);
2970
2971 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
2972 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
2973}
2974
2975void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
2976 u8 pipe_mask)
2977{
2978 struct intel_uncore *uncore = &dev_priv->uncore;
2979
2980 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
2981 enum pipe pipe;
2982
2983 spin_lock_irq(&dev_priv->irq_lock);
2984
2985 if (!intel_irqs_enabled(dev_priv)) {
2986 spin_unlock_irq(&dev_priv->irq_lock);
2987 return;
2988 }
2989
2990 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2991 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
2992 dev_priv->de_irq_mask[pipe],
2993 ~dev_priv->de_irq_mask[pipe] | extra_ier);
2994
2995 spin_unlock_irq(&dev_priv->irq_lock);
2996}
2997
2998void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
2999 u8 pipe_mask)
3000{
3001 struct intel_uncore *uncore = &dev_priv->uncore;
3002 enum pipe pipe;
3003
3004 spin_lock_irq(&dev_priv->irq_lock);
3005
3006 if (!intel_irqs_enabled(dev_priv)) {
3007 spin_unlock_irq(&dev_priv->irq_lock);
3008 return;
3009 }
3010
3011 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3012 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3013
3014 spin_unlock_irq(&dev_priv->irq_lock);
3015
3016 /* make sure we're done processing display irqs */
3017 intel_synchronize_irq(dev_priv);
3018}
3019
3020static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3021{
3022 struct intel_uncore *uncore = &dev_priv->uncore;
3023
3024 I915_WRITE(GEN8_MASTER_IRQ, 0);
3025 POSTING_READ(GEN8_MASTER_IRQ);
3026
3027 gen8_gt_irq_reset(&dev_priv->gt);
3028
3029 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3030
3031 spin_lock_irq(&dev_priv->irq_lock);
3032 if (dev_priv->display_irqs_enabled)
3033 vlv_display_irq_reset(dev_priv);
3034 spin_unlock_irq(&dev_priv->irq_lock);
3035}
3036
3037static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3038 const u32 hpd[HPD_NUM_PINS])
3039{
3040 struct intel_encoder *encoder;
3041 u32 enabled_irqs = 0;
3042
3043 for_each_intel_encoder(&dev_priv->drm, encoder)
3044 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3045 enabled_irqs |= hpd[encoder->hpd_pin];
3046
3047 return enabled_irqs;
3048}
3049
3050static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3051{
3052 u32 hotplug;
3053
3054 /*
3055 * Enable digital hotplug on the PCH, and configure the DP short pulse
3056 * duration to 2ms (which is the minimum in the Display Port spec).
3057 * The pulse duration bits are reserved on LPT+.
3058 */
3059 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3060 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3061 PORTC_PULSE_DURATION_MASK |
3062 PORTD_PULSE_DURATION_MASK);
3063 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3064 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3065 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3066 /*
3067 * When CPU and PCH are on the same package, port A
3068 * HPD must be enabled in both north and south.
3069 */
3070 if (HAS_PCH_LPT_LP(dev_priv))
3071 hotplug |= PORTA_HOTPLUG_ENABLE;
3072 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3073}
3074
3075static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3076{
3077 u32 hotplug_irqs, enabled_irqs;
3078
3079 if (HAS_PCH_IBX(dev_priv))
3080 hotplug_irqs = SDE_HOTPLUG_MASK;
3081 else
3082 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3083
3084 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3085
3086 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3087
3088 ibx_hpd_detection_setup(dev_priv);
3089}
3090
3091static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
3092 u32 ddi_hotplug_enable_mask,
3093 u32 tc_hotplug_enable_mask)
3094{
3095 u32 hotplug;
3096
3097 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3098 hotplug |= ddi_hotplug_enable_mask;
3099 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3100
3101 if (tc_hotplug_enable_mask) {
3102 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3103 hotplug |= tc_hotplug_enable_mask;
3104 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3105 }
3106}
3107
3108static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv,
3109 u32 sde_ddi_mask, u32 sde_tc_mask,
3110 u32 ddi_enable_mask, u32 tc_enable_mask)
3111{
3112 u32 hotplug_irqs, enabled_irqs;
3113
3114 hotplug_irqs = sde_ddi_mask | sde_tc_mask;
3115 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3116
3117 if (INTEL_PCH_TYPE(dev_priv) <= PCH_TGP)
3118 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3119
3120 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3121
3122 icp_hpd_detection_setup(dev_priv, ddi_enable_mask, tc_enable_mask);
3123}
3124
3125/*
3126 * EHL doesn't need most of gen11_hpd_irq_setup, it's handling only the
3127 * equivalent of SDE.
3128 */
3129static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3130{
3131 icp_hpd_irq_setup(dev_priv,
3132 SDE_DDI_MASK_ICP, SDE_TC_HOTPLUG_ICP(PORT_TC1),
3133 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE(PORT_TC1));
3134}
3135
3136/*
3137 * JSP behaves exactly the same as MCC above except that port C is mapped to
3138 * the DDI-C pins instead of the TC1 pins. This means we should follow TGP's
3139 * masks & tables rather than ICP's masks & tables.
3140 */
3141static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3142{
3143 icp_hpd_irq_setup(dev_priv,
3144 SDE_DDI_MASK_TGP, 0,
3145 TGP_DDI_HPD_ENABLE_MASK, 0);
3146}
3147
3148static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3149{
3150 u32 hotplug;
3151
3152 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3153 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3154 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3155 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3156 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3157 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3158
3159 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3160 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3161 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3162 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3163 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3164 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3165}
3166
3167static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3168{
3169 u32 hotplug_irqs, enabled_irqs;
3170 u32 val;
3171
3172 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3173 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3174
3175 val = I915_READ(GEN11_DE_HPD_IMR);
3176 val &= ~hotplug_irqs;
3177 val |= ~enabled_irqs & hotplug_irqs;
3178 I915_WRITE(GEN11_DE_HPD_IMR, val);
3179 POSTING_READ(GEN11_DE_HPD_IMR);
3180
3181 gen11_hpd_detection_setup(dev_priv);
3182
3183 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3184 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_TGP, SDE_TC_MASK_TGP,
3185 TGP_DDI_HPD_ENABLE_MASK, TGP_TC_HPD_ENABLE_MASK);
3186 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3187 icp_hpd_irq_setup(dev_priv, SDE_DDI_MASK_ICP, SDE_TC_MASK_ICP,
3188 ICP_DDI_HPD_ENABLE_MASK, ICP_TC_HPD_ENABLE_MASK);
3189}
3190
3191static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3192{
3193 u32 val, hotplug;
3194
3195 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3196 if (HAS_PCH_CNP(dev_priv)) {
3197 val = I915_READ(SOUTH_CHICKEN1);
3198 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3199 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3200 I915_WRITE(SOUTH_CHICKEN1, val);
3201 }
3202
3203 /* Enable digital hotplug on the PCH */
3204 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3205 hotplug |= PORTA_HOTPLUG_ENABLE |
3206 PORTB_HOTPLUG_ENABLE |
3207 PORTC_HOTPLUG_ENABLE |
3208 PORTD_HOTPLUG_ENABLE;
3209 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3210
3211 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3212 hotplug |= PORTE_HOTPLUG_ENABLE;
3213 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3214}
3215
3216static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3217{
3218 u32 hotplug_irqs, enabled_irqs;
3219
3220 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3221 I915_WRITE(SHPD_FILTER_CNT, SHPD_FILTER_CNT_500_ADJ);
3222
3223 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3224 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.pch_hpd);
3225
3226 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3227
3228 spt_hpd_detection_setup(dev_priv);
3229}
3230
3231static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3232{
3233 u32 hotplug;
3234
3235 /*
3236 * Enable digital hotplug on the CPU, and configure the DP short pulse
3237 * duration to 2ms (which is the minimum in the Display Port spec)
3238 * The pulse duration bits are reserved on HSW+.
3239 */
3240 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3241 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3242 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3243 DIGITAL_PORTA_PULSE_DURATION_2ms;
3244 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3245}
3246
3247static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3248{
3249 u32 hotplug_irqs, enabled_irqs;
3250
3251 if (INTEL_GEN(dev_priv) >= 8) {
3252 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3253 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3254
3255 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3256 } else if (INTEL_GEN(dev_priv) >= 7) {
3257 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3258 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3259
3260 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3261 } else {
3262 hotplug_irqs = DE_DP_A_HOTPLUG;
3263 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3264
3265 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3266 }
3267
3268 ilk_hpd_detection_setup(dev_priv);
3269
3270 ibx_hpd_irq_setup(dev_priv);
3271}
3272
3273static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3274 u32 enabled_irqs)
3275{
3276 u32 hotplug;
3277
3278 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3279 hotplug |= PORTA_HOTPLUG_ENABLE |
3280 PORTB_HOTPLUG_ENABLE |
3281 PORTC_HOTPLUG_ENABLE;
3282
3283 drm_dbg_kms(&dev_priv->drm,
3284 "Invert bit setting: hp_ctl:%x hp_port:%x\n",
3285 hotplug, enabled_irqs);
3286 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3287
3288 /*
3289 * For BXT invert bit has to be set based on AOB design
3290 * for HPD detection logic, update it based on VBT fields.
3291 */
3292 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3293 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3294 hotplug |= BXT_DDIA_HPD_INVERT;
3295 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3296 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3297 hotplug |= BXT_DDIB_HPD_INVERT;
3298 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3299 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3300 hotplug |= BXT_DDIC_HPD_INVERT;
3301
3302 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3303}
3304
3305static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3306{
3307 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3308}
3309
3310static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3311{
3312 u32 hotplug_irqs, enabled_irqs;
3313
3314 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, dev_priv->hotplug.hpd);
3315 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3316
3317 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3318
3319 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3320}
3321
3322static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3323{
3324 u32 mask;
3325
3326 if (HAS_PCH_NOP(dev_priv))
3327 return;
3328
3329 if (HAS_PCH_IBX(dev_priv))
3330 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3331 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3332 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3333 else
3334 mask = SDE_GMBUS_CPT;
3335
3336 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3337 I915_WRITE(SDEIMR, ~mask);
3338
3339 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3340 HAS_PCH_LPT(dev_priv))
3341 ibx_hpd_detection_setup(dev_priv);
3342 else
3343 spt_hpd_detection_setup(dev_priv);
3344}
3345
3346static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)
3347{
3348 struct intel_uncore *uncore = &dev_priv->uncore;
3349 u32 display_mask, extra_mask;
3350
3351 if (INTEL_GEN(dev_priv) >= 7) {
3352 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3353 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3354 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3355 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3356 DE_DP_A_HOTPLUG_IVB);
3357 } else {
3358 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3359 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3360 DE_PIPEA_CRC_DONE | DE_POISON);
3361 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3362 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3363 DE_DP_A_HOTPLUG);
3364 }
3365
3366 if (IS_HASWELL(dev_priv)) {
3367 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3368 display_mask |= DE_EDP_PSR_INT_HSW;
3369 }
3370
3371 dev_priv->irq_mask = ~display_mask;
3372
3373 ibx_irq_pre_postinstall(dev_priv);
3374
3375 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3376 display_mask | extra_mask);
3377
3378 gen5_gt_irq_postinstall(&dev_priv->gt);
3379
3380 ilk_hpd_detection_setup(dev_priv);
3381
3382 ibx_irq_postinstall(dev_priv);
3383
3384 if (IS_IRONLAKE_M(dev_priv)) {
3385 /* Enable PCU event interrupts
3386 *
3387 * spinlocking not required here for correctness since interrupt
3388 * setup is guaranteed to run in single-threaded context. But we
3389 * need it to make the assert_spin_locked happy. */
3390 spin_lock_irq(&dev_priv->irq_lock);
3391 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3392 spin_unlock_irq(&dev_priv->irq_lock);
3393 }
3394}
3395
3396void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3397{
3398 lockdep_assert_held(&dev_priv->irq_lock);
3399
3400 if (dev_priv->display_irqs_enabled)
3401 return;
3402
3403 dev_priv->display_irqs_enabled = true;
3404
3405 if (intel_irqs_enabled(dev_priv)) {
3406 vlv_display_irq_reset(dev_priv);
3407 vlv_display_irq_postinstall(dev_priv);
3408 }
3409}
3410
3411void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3412{
3413 lockdep_assert_held(&dev_priv->irq_lock);
3414
3415 if (!dev_priv->display_irqs_enabled)
3416 return;
3417
3418 dev_priv->display_irqs_enabled = false;
3419
3420 if (intel_irqs_enabled(dev_priv))
3421 vlv_display_irq_reset(dev_priv);
3422}
3423
3424
3425static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3426{
3427 gen5_gt_irq_postinstall(&dev_priv->gt);
3428
3429 spin_lock_irq(&dev_priv->irq_lock);
3430 if (dev_priv->display_irqs_enabled)
3431 vlv_display_irq_postinstall(dev_priv);
3432 spin_unlock_irq(&dev_priv->irq_lock);
3433
3434 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3435 POSTING_READ(VLV_MASTER_IER);
3436}
3437
3438static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3439{
3440 struct intel_uncore *uncore = &dev_priv->uncore;
3441
3442 u32 de_pipe_masked = gen8_de_pipe_fault_mask(dev_priv) |
3443 GEN8_PIPE_CDCLK_CRC_DONE;
3444 u32 de_pipe_enables;
3445 u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
3446 u32 de_port_enables;
3447 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3448 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3449 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3450 enum pipe pipe;
3451
3452 if (INTEL_GEN(dev_priv) <= 10)
3453 de_misc_masked |= GEN8_DE_MISC_GSE;
3454
3455 if (IS_GEN9_LP(dev_priv))
3456 de_port_masked |= BXT_DE_PORT_GMBUS;
3457
3458 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3459 GEN8_PIPE_FIFO_UNDERRUN;
3460
3461 de_port_enables = de_port_masked;
3462 if (IS_GEN9_LP(dev_priv))
3463 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3464 else if (IS_BROADWELL(dev_priv))
3465 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3466
3467 if (INTEL_GEN(dev_priv) >= 12) {
3468 enum transcoder trans;
3469
3470 for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
3471 enum intel_display_power_domain domain;
3472
3473 domain = POWER_DOMAIN_TRANSCODER(trans);
3474 if (!intel_display_power_is_enabled(dev_priv, domain))
3475 continue;
3476
3477 gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
3478 }
3479 } else {
3480 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3481 }
3482
3483 for_each_pipe(dev_priv, pipe) {
3484 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3485
3486 if (intel_display_power_is_enabled(dev_priv,
3487 POWER_DOMAIN_PIPE(pipe)))
3488 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3489 dev_priv->de_irq_mask[pipe],
3490 de_pipe_enables);
3491 }
3492
3493 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3494 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3495
3496 if (INTEL_GEN(dev_priv) >= 11) {
3497 u32 de_hpd_masked = 0;
3498 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3499 GEN11_DE_TBT_HOTPLUG_MASK;
3500
3501 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3502 de_hpd_enables);
3503 gen11_hpd_detection_setup(dev_priv);
3504 } else if (IS_GEN9_LP(dev_priv)) {
3505 bxt_hpd_detection_setup(dev_priv);
3506 } else if (IS_BROADWELL(dev_priv)) {
3507 ilk_hpd_detection_setup(dev_priv);
3508 }
3509}
3510
3511static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3512{
3513 if (HAS_PCH_SPLIT(dev_priv))
3514 ibx_irq_pre_postinstall(dev_priv);
3515
3516 gen8_gt_irq_postinstall(&dev_priv->gt);
3517 gen8_de_irq_postinstall(dev_priv);
3518
3519 if (HAS_PCH_SPLIT(dev_priv))
3520 ibx_irq_postinstall(dev_priv);
3521
3522 gen8_master_intr_enable(dev_priv->uncore.regs);
3523}
3524
3525static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3526{
3527 u32 mask = SDE_GMBUS_ICP;
3528
3529 drm_WARN_ON(&dev_priv->drm, I915_READ(SDEIER) != 0);
3530 I915_WRITE(SDEIER, 0xffffffff);
3531 POSTING_READ(SDEIER);
3532
3533 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3534 I915_WRITE(SDEIMR, ~mask);
3535
3536 if (HAS_PCH_TGP(dev_priv))
3537 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3538 TGP_TC_HPD_ENABLE_MASK);
3539 else if (HAS_PCH_JSP(dev_priv))
3540 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3541 else if (HAS_PCH_MCC(dev_priv))
3542 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3543 ICP_TC_HPD_ENABLE(PORT_TC1));
3544 else
3545 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3546 ICP_TC_HPD_ENABLE_MASK);
3547}
3548
3549static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3550{
3551 struct intel_uncore *uncore = &dev_priv->uncore;
3552 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3553
3554 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3555 icp_irq_postinstall(dev_priv);
3556
3557 gen11_gt_irq_postinstall(&dev_priv->gt);
3558 gen8_de_irq_postinstall(dev_priv);
3559
3560 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3561
3562 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3563
3564 if (HAS_MASTER_UNIT_IRQ(dev_priv)) {
3565 dg1_master_intr_enable(uncore->regs);
3566 POSTING_READ(DG1_MSTR_UNIT_INTR);
3567 } else {
3568 gen11_master_intr_enable(uncore->regs);
3569 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3570 }
3571}
3572
3573static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3574{
3575 gen8_gt_irq_postinstall(&dev_priv->gt);
3576
3577 spin_lock_irq(&dev_priv->irq_lock);
3578 if (dev_priv->display_irqs_enabled)
3579 vlv_display_irq_postinstall(dev_priv);
3580 spin_unlock_irq(&dev_priv->irq_lock);
3581
3582 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3583 POSTING_READ(GEN8_MASTER_IRQ);
3584}
3585
3586static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3587{
3588 struct intel_uncore *uncore = &dev_priv->uncore;
3589
3590 i9xx_pipestat_irq_reset(dev_priv);
3591
3592 GEN2_IRQ_RESET(uncore);
3593}
3594
3595static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3596{
3597 struct intel_uncore *uncore = &dev_priv->uncore;
3598 u16 enable_mask;
3599
3600 intel_uncore_write16(uncore,
3601 EMR,
3602 ~(I915_ERROR_PAGE_TABLE |
3603 I915_ERROR_MEMORY_REFRESH));
3604
3605 /* Unmask the interrupts that we always want on. */
3606 dev_priv->irq_mask =
3607 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3608 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3609 I915_MASTER_ERROR_INTERRUPT);
3610
3611 enable_mask =
3612 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3613 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3614 I915_MASTER_ERROR_INTERRUPT |
3615 I915_USER_INTERRUPT;
3616
3617 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3618
3619 /* Interrupt setup is already guaranteed to be single-threaded, this is
3620 * just to make the assert_spin_locked check happy. */
3621 spin_lock_irq(&dev_priv->irq_lock);
3622 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3623 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3624 spin_unlock_irq(&dev_priv->irq_lock);
3625}
3626
3627static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3628 u16 *eir, u16 *eir_stuck)
3629{
3630 struct intel_uncore *uncore = &i915->uncore;
3631 u16 emr;
3632
3633 *eir = intel_uncore_read16(uncore, EIR);
3634
3635 if (*eir)
3636 intel_uncore_write16(uncore, EIR, *eir);
3637
3638 *eir_stuck = intel_uncore_read16(uncore, EIR);
3639 if (*eir_stuck == 0)
3640 return;
3641
3642 /*
3643 * Toggle all EMR bits to make sure we get an edge
3644 * in the ISR master error bit if we don't clear
3645 * all the EIR bits. Otherwise the edge triggered
3646 * IIR on i965/g4x wouldn't notice that an interrupt
3647 * is still pending. Also some EIR bits can't be
3648 * cleared except by handling the underlying error
3649 * (or by a GPU reset) so we mask any bit that
3650 * remains set.
3651 */
3652 emr = intel_uncore_read16(uncore, EMR);
3653 intel_uncore_write16(uncore, EMR, 0xffff);
3654 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3655}
3656
3657static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3658 u16 eir, u16 eir_stuck)
3659{
3660 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3661
3662 if (eir_stuck)
3663 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%04x, masked\n",
3664 eir_stuck);
3665}
3666
3667static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3668 u32 *eir, u32 *eir_stuck)
3669{
3670 u32 emr;
3671
3672 *eir = I915_READ(EIR);
3673
3674 I915_WRITE(EIR, *eir);
3675
3676 *eir_stuck = I915_READ(EIR);
3677 if (*eir_stuck == 0)
3678 return;
3679
3680 /*
3681 * Toggle all EMR bits to make sure we get an edge
3682 * in the ISR master error bit if we don't clear
3683 * all the EIR bits. Otherwise the edge triggered
3684 * IIR on i965/g4x wouldn't notice that an interrupt
3685 * is still pending. Also some EIR bits can't be
3686 * cleared except by handling the underlying error
3687 * (or by a GPU reset) so we mask any bit that
3688 * remains set.
3689 */
3690 emr = I915_READ(EMR);
3691 I915_WRITE(EMR, 0xffffffff);
3692 I915_WRITE(EMR, emr | *eir_stuck);
3693}
3694
3695static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
3696 u32 eir, u32 eir_stuck)
3697{
3698 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
3699
3700 if (eir_stuck)
3701 drm_dbg(&dev_priv->drm, "EIR stuck: 0x%08x, masked\n",
3702 eir_stuck);
3703}
3704
3705static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3706{
3707 struct drm_i915_private *dev_priv = arg;
3708 irqreturn_t ret = IRQ_NONE;
3709
3710 if (!intel_irqs_enabled(dev_priv))
3711 return IRQ_NONE;
3712
3713 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3714 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3715
3716 do {
3717 u32 pipe_stats[I915_MAX_PIPES] = {};
3718 u16 eir = 0, eir_stuck = 0;
3719 u16 iir;
3720
3721 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3722 if (iir == 0)
3723 break;
3724
3725 ret = IRQ_HANDLED;
3726
3727 /* Call regardless, as some status bits might not be
3728 * signalled in iir */
3729 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3730
3731 if (iir & I915_MASTER_ERROR_INTERRUPT)
3732 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3733
3734 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3735
3736 if (iir & I915_USER_INTERRUPT)
3737 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3738
3739 if (iir & I915_MASTER_ERROR_INTERRUPT)
3740 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
3741
3742 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3743 } while (0);
3744
3745 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3746
3747 return ret;
3748}
3749
3750static void i915_irq_reset(struct drm_i915_private *dev_priv)
3751{
3752 struct intel_uncore *uncore = &dev_priv->uncore;
3753
3754 if (I915_HAS_HOTPLUG(dev_priv)) {
3755 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3756 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3757 }
3758
3759 i9xx_pipestat_irq_reset(dev_priv);
3760
3761 GEN3_IRQ_RESET(uncore, GEN2_);
3762}
3763
3764static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
3765{
3766 struct intel_uncore *uncore = &dev_priv->uncore;
3767 u32 enable_mask;
3768
3769 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
3770 I915_ERROR_MEMORY_REFRESH));
3771
3772 /* Unmask the interrupts that we always want on. */
3773 dev_priv->irq_mask =
3774 ~(I915_ASLE_INTERRUPT |
3775 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3776 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3777 I915_MASTER_ERROR_INTERRUPT);
3778
3779 enable_mask =
3780 I915_ASLE_INTERRUPT |
3781 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3782 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3783 I915_MASTER_ERROR_INTERRUPT |
3784 I915_USER_INTERRUPT;
3785
3786 if (I915_HAS_HOTPLUG(dev_priv)) {
3787 /* Enable in IER... */
3788 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3789 /* and unmask in IMR */
3790 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3791 }
3792
3793 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3794
3795 /* Interrupt setup is already guaranteed to be single-threaded, this is
3796 * just to make the assert_spin_locked check happy. */
3797 spin_lock_irq(&dev_priv->irq_lock);
3798 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3799 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3800 spin_unlock_irq(&dev_priv->irq_lock);
3801
3802 i915_enable_asle_pipestat(dev_priv);
3803}
3804
3805static irqreturn_t i915_irq_handler(int irq, void *arg)
3806{
3807 struct drm_i915_private *dev_priv = arg;
3808 irqreturn_t ret = IRQ_NONE;
3809
3810 if (!intel_irqs_enabled(dev_priv))
3811 return IRQ_NONE;
3812
3813 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3814 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3815
3816 do {
3817 u32 pipe_stats[I915_MAX_PIPES] = {};
3818 u32 eir = 0, eir_stuck = 0;
3819 u32 hotplug_status = 0;
3820 u32 iir;
3821
3822 iir = I915_READ(GEN2_IIR);
3823 if (iir == 0)
3824 break;
3825
3826 ret = IRQ_HANDLED;
3827
3828 if (I915_HAS_HOTPLUG(dev_priv) &&
3829 iir & I915_DISPLAY_PORT_INTERRUPT)
3830 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3831
3832 /* Call regardless, as some status bits might not be
3833 * signalled in iir */
3834 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3835
3836 if (iir & I915_MASTER_ERROR_INTERRUPT)
3837 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3838
3839 I915_WRITE(GEN2_IIR, iir);
3840
3841 if (iir & I915_USER_INTERRUPT)
3842 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3843
3844 if (iir & I915_MASTER_ERROR_INTERRUPT)
3845 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3846
3847 if (hotplug_status)
3848 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3849
3850 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3851 } while (0);
3852
3853 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3854
3855 return ret;
3856}
3857
3858static void i965_irq_reset(struct drm_i915_private *dev_priv)
3859{
3860 struct intel_uncore *uncore = &dev_priv->uncore;
3861
3862 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
3863 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3864
3865 i9xx_pipestat_irq_reset(dev_priv);
3866
3867 GEN3_IRQ_RESET(uncore, GEN2_);
3868}
3869
3870static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
3871{
3872 struct intel_uncore *uncore = &dev_priv->uncore;
3873 u32 enable_mask;
3874 u32 error_mask;
3875
3876 /*
3877 * Enable some error detection, note the instruction error mask
3878 * bit is reserved, so we leave it masked.
3879 */
3880 if (IS_G4X(dev_priv)) {
3881 error_mask = ~(GM45_ERROR_PAGE_TABLE |
3882 GM45_ERROR_MEM_PRIV |
3883 GM45_ERROR_CP_PRIV |
3884 I915_ERROR_MEMORY_REFRESH);
3885 } else {
3886 error_mask = ~(I915_ERROR_PAGE_TABLE |
3887 I915_ERROR_MEMORY_REFRESH);
3888 }
3889 I915_WRITE(EMR, error_mask);
3890
3891 /* Unmask the interrupts that we always want on. */
3892 dev_priv->irq_mask =
3893 ~(I915_ASLE_INTERRUPT |
3894 I915_DISPLAY_PORT_INTERRUPT |
3895 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3896 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3897 I915_MASTER_ERROR_INTERRUPT);
3898
3899 enable_mask =
3900 I915_ASLE_INTERRUPT |
3901 I915_DISPLAY_PORT_INTERRUPT |
3902 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3903 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3904 I915_MASTER_ERROR_INTERRUPT |
3905 I915_USER_INTERRUPT;
3906
3907 if (IS_G4X(dev_priv))
3908 enable_mask |= I915_BSD_USER_INTERRUPT;
3909
3910 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
3911
3912 /* Interrupt setup is already guaranteed to be single-threaded, this is
3913 * just to make the assert_spin_locked check happy. */
3914 spin_lock_irq(&dev_priv->irq_lock);
3915 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3916 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3917 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3918 spin_unlock_irq(&dev_priv->irq_lock);
3919
3920 i915_enable_asle_pipestat(dev_priv);
3921}
3922
3923static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
3924{
3925 u32 hotplug_en;
3926
3927 lockdep_assert_held(&dev_priv->irq_lock);
3928
3929 /* Note HDMI and DP share hotplug bits */
3930 /* enable bits are the same for all generations */
3931 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
3932 /* Programming the CRT detection parameters tends
3933 to generate a spurious hotplug event about three
3934 seconds later. So just do it once.
3935 */
3936 if (IS_G4X(dev_priv))
3937 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
3938 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
3939
3940 /* Ignore TV since it's buggy */
3941 i915_hotplug_interrupt_update_locked(dev_priv,
3942 HOTPLUG_INT_EN_MASK |
3943 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
3944 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
3945 hotplug_en);
3946}
3947
3948static irqreturn_t i965_irq_handler(int irq, void *arg)
3949{
3950 struct drm_i915_private *dev_priv = arg;
3951 irqreturn_t ret = IRQ_NONE;
3952
3953 if (!intel_irqs_enabled(dev_priv))
3954 return IRQ_NONE;
3955
3956 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
3957 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3958
3959 do {
3960 u32 pipe_stats[I915_MAX_PIPES] = {};
3961 u32 eir = 0, eir_stuck = 0;
3962 u32 hotplug_status = 0;
3963 u32 iir;
3964
3965 iir = I915_READ(GEN2_IIR);
3966 if (iir == 0)
3967 break;
3968
3969 ret = IRQ_HANDLED;
3970
3971 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3972 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
3973
3974 /* Call regardless, as some status bits might not be
3975 * signalled in iir */
3976 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3977
3978 if (iir & I915_MASTER_ERROR_INTERRUPT)
3979 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
3980
3981 I915_WRITE(GEN2_IIR, iir);
3982
3983 if (iir & I915_USER_INTERRUPT)
3984 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[RCS0]);
3985
3986 if (iir & I915_BSD_USER_INTERRUPT)
3987 intel_engine_signal_breadcrumbs(dev_priv->gt.engine[VCS0]);
3988
3989 if (iir & I915_MASTER_ERROR_INTERRUPT)
3990 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
3991
3992 if (hotplug_status)
3993 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
3994
3995 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3996 } while (0);
3997
3998 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
3999
4000 return ret;
4001}
4002
4003/**
4004 * intel_irq_init - initializes irq support
4005 * @dev_priv: i915 device instance
4006 *
4007 * This function initializes all the irq support including work items, timers
4008 * and all the vtables. It does not setup the interrupt itself though.
4009 */
4010void intel_irq_init(struct drm_i915_private *dev_priv)
4011{
4012 struct drm_device *dev = &dev_priv->drm;
4013 int i;
4014
4015 intel_hpd_init_pins(dev_priv);
4016
4017 intel_hpd_init_work(dev_priv);
4018
4019 INIT_WORK(&dev_priv->l3_parity.error_work, ivb_parity_work);
4020 for (i = 0; i < MAX_L3_SLICES; ++i)
4021 dev_priv->l3_parity.remap_info[i] = NULL;
4022
4023 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4024 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4025 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4026
4027 dev->vblank_disable_immediate = true;
4028
4029 /* Most platforms treat the display irq block as an always-on
4030 * power domain. vlv/chv can disable it at runtime and need
4031 * special care to avoid writing any of the display block registers
4032 * outside of the power domain. We defer setting up the display irqs
4033 * in this case to the runtime pm.
4034 */
4035 dev_priv->display_irqs_enabled = true;
4036 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4037 dev_priv->display_irqs_enabled = false;
4038
4039 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4040 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4041 * detection, as short HPD storms will occur as a natural part of
4042 * sideband messaging with MST.
4043 * On older platforms however, IRQ storms can occur with both long and
4044 * short pulses, as seen on some G4x systems.
4045 */
4046 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4047
4048 if (HAS_GMCH(dev_priv)) {
4049 if (I915_HAS_HOTPLUG(dev_priv))
4050 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4051 } else {
4052 if (HAS_PCH_JSP(dev_priv))
4053 dev_priv->display.hpd_irq_setup = jsp_hpd_irq_setup;
4054 else if (HAS_PCH_MCC(dev_priv))
4055 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4056 else if (INTEL_GEN(dev_priv) >= 11)
4057 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4058 else if (IS_GEN9_LP(dev_priv))
4059 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4060 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4061 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4062 else
4063 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4064 }
4065}
4066
4067/**
4068 * intel_irq_fini - deinitializes IRQ support
4069 * @i915: i915 device instance
4070 *
4071 * This function deinitializes all the IRQ support.
4072 */
4073void intel_irq_fini(struct drm_i915_private *i915)
4074{
4075 int i;
4076
4077 for (i = 0; i < MAX_L3_SLICES; ++i)
4078 kfree(i915->l3_parity.remap_info[i]);
4079}
4080
4081static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4082{
4083 if (HAS_GMCH(dev_priv)) {
4084 if (IS_CHERRYVIEW(dev_priv))
4085 return cherryview_irq_handler;
4086 else if (IS_VALLEYVIEW(dev_priv))
4087 return valleyview_irq_handler;
4088 else if (IS_GEN(dev_priv, 4))
4089 return i965_irq_handler;
4090 else if (IS_GEN(dev_priv, 3))
4091 return i915_irq_handler;
4092 else
4093 return i8xx_irq_handler;
4094 } else {
4095 if (HAS_MASTER_UNIT_IRQ(dev_priv))
4096 return dg1_irq_handler;
4097 if (INTEL_GEN(dev_priv) >= 11)
4098 return gen11_irq_handler;
4099 else if (INTEL_GEN(dev_priv) >= 8)
4100 return gen8_irq_handler;
4101 else
4102 return ilk_irq_handler;
4103 }
4104}
4105
4106static void intel_irq_reset(struct drm_i915_private *dev_priv)
4107{
4108 if (HAS_GMCH(dev_priv)) {
4109 if (IS_CHERRYVIEW(dev_priv))
4110 cherryview_irq_reset(dev_priv);
4111 else if (IS_VALLEYVIEW(dev_priv))
4112 valleyview_irq_reset(dev_priv);
4113 else if (IS_GEN(dev_priv, 4))
4114 i965_irq_reset(dev_priv);
4115 else if (IS_GEN(dev_priv, 3))
4116 i915_irq_reset(dev_priv);
4117 else
4118 i8xx_irq_reset(dev_priv);
4119 } else {
4120 if (INTEL_GEN(dev_priv) >= 11)
4121 gen11_irq_reset(dev_priv);
4122 else if (INTEL_GEN(dev_priv) >= 8)
4123 gen8_irq_reset(dev_priv);
4124 else
4125 ilk_irq_reset(dev_priv);
4126 }
4127}
4128
4129static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4130{
4131 if (HAS_GMCH(dev_priv)) {
4132 if (IS_CHERRYVIEW(dev_priv))
4133 cherryview_irq_postinstall(dev_priv);
4134 else if (IS_VALLEYVIEW(dev_priv))
4135 valleyview_irq_postinstall(dev_priv);
4136 else if (IS_GEN(dev_priv, 4))
4137 i965_irq_postinstall(dev_priv);
4138 else if (IS_GEN(dev_priv, 3))
4139 i915_irq_postinstall(dev_priv);
4140 else
4141 i8xx_irq_postinstall(dev_priv);
4142 } else {
4143 if (INTEL_GEN(dev_priv) >= 11)
4144 gen11_irq_postinstall(dev_priv);
4145 else if (INTEL_GEN(dev_priv) >= 8)
4146 gen8_irq_postinstall(dev_priv);
4147 else
4148 ilk_irq_postinstall(dev_priv);
4149 }
4150}
4151
4152/**
4153 * intel_irq_install - enables the hardware interrupt
4154 * @dev_priv: i915 device instance
4155 *
4156 * This function enables the hardware interrupt handling, but leaves the hotplug
4157 * handling still disabled. It is called after intel_irq_init().
4158 *
4159 * In the driver load and resume code we need working interrupts in a few places
4160 * but don't want to deal with the hassle of concurrent probe and hotplug
4161 * workers. Hence the split into this two-stage approach.
4162 */
4163int intel_irq_install(struct drm_i915_private *dev_priv)
4164{
4165 int irq = dev_priv->drm.pdev->irq;
4166 int ret;
4167
4168 /*
4169 * We enable some interrupt sources in our postinstall hooks, so mark
4170 * interrupts as enabled _before_ actually enabling them to avoid
4171 * special cases in our ordering checks.
4172 */
4173 dev_priv->runtime_pm.irqs_enabled = true;
4174
4175 dev_priv->drm.irq_enabled = true;
4176
4177 intel_irq_reset(dev_priv);
4178
4179 ret = request_irq(irq, intel_irq_handler(dev_priv),
4180 IRQF_SHARED, DRIVER_NAME, dev_priv);
4181 if (ret < 0) {
4182 dev_priv->drm.irq_enabled = false;
4183 return ret;
4184 }
4185
4186 intel_irq_postinstall(dev_priv);
4187
4188 return ret;
4189}
4190
4191/**
4192 * intel_irq_uninstall - finilizes all irq handling
4193 * @dev_priv: i915 device instance
4194 *
4195 * This stops interrupt and hotplug handling and unregisters and frees all
4196 * resources acquired in the init functions.
4197 */
4198void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4199{
4200 int irq = dev_priv->drm.pdev->irq;
4201
4202 /*
4203 * FIXME we can get called twice during driver probe
4204 * error handling as well as during driver remove due to
4205 * intel_modeset_driver_remove() calling us out of sequence.
4206 * Would be nice if it didn't do that...
4207 */
4208 if (!dev_priv->drm.irq_enabled)
4209 return;
4210
4211 dev_priv->drm.irq_enabled = false;
4212
4213 intel_irq_reset(dev_priv);
4214
4215 free_irq(irq, dev_priv);
4216
4217 intel_hpd_cancel_work(dev_priv);
4218 dev_priv->runtime_pm.irqs_enabled = false;
4219}
4220
4221/**
4222 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4223 * @dev_priv: i915 device instance
4224 *
4225 * This function is used to disable interrupts at runtime, both in the runtime
4226 * pm and the system suspend/resume code.
4227 */
4228void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4229{
4230 intel_irq_reset(dev_priv);
4231 dev_priv->runtime_pm.irqs_enabled = false;
4232 intel_synchronize_irq(dev_priv);
4233}
4234
4235/**
4236 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4237 * @dev_priv: i915 device instance
4238 *
4239 * This function is used to enable interrupts at runtime, both in the runtime
4240 * pm and the system suspend/resume code.
4241 */
4242void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4243{
4244 dev_priv->runtime_pm.irqs_enabled = true;
4245 intel_irq_reset(dev_priv);
4246 intel_irq_postinstall(dev_priv);
4247}
4248
4249bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4250{
4251 /*
4252 * We only use drm_irq_uninstall() at unload and VT switch, so
4253 * this is the only thing we need to check.
4254 */
4255 return dev_priv->runtime_pm.irqs_enabled;
4256}
4257
4258void intel_synchronize_irq(struct drm_i915_private *i915)
4259{
4260 synchronize_irq(i915->drm.pdev->irq);
4261}
1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3/*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/circ_buf.h>
32#include <linux/cpuidle.h>
33#include <linux/slab.h>
34#include <linux/sysrq.h>
35
36#include <drm/drm_drv.h>
37#include <drm/drm_irq.h>
38#include <drm/i915_drm.h>
39
40#include "display/intel_display_types.h"
41#include "display/intel_fifo_underrun.h"
42#include "display/intel_hotplug.h"
43#include "display/intel_lpe_audio.h"
44#include "display/intel_psr.h"
45
46#include "gt/intel_gt.h"
47#include "gt/intel_gt_irq.h"
48#include "gt/intel_gt_pm_irq.h"
49
50#include "i915_drv.h"
51#include "i915_irq.h"
52#include "i915_trace.h"
53#include "intel_pm.h"
54
55/**
56 * DOC: interrupt handling
57 *
58 * These functions provide the basic support for enabling and disabling the
59 * interrupt handling support. There's a lot more functionality in i915_irq.c
60 * and related files, but that will be described in separate chapters.
61 */
62
63typedef bool (*long_pulse_detect_func)(enum hpd_pin pin, u32 val);
64
65static const u32 hpd_ilk[HPD_NUM_PINS] = {
66 [HPD_PORT_A] = DE_DP_A_HOTPLUG,
67};
68
69static const u32 hpd_ivb[HPD_NUM_PINS] = {
70 [HPD_PORT_A] = DE_DP_A_HOTPLUG_IVB,
71};
72
73static const u32 hpd_bdw[HPD_NUM_PINS] = {
74 [HPD_PORT_A] = GEN8_PORT_DP_A_HOTPLUG,
75};
76
77static const u32 hpd_ibx[HPD_NUM_PINS] = {
78 [HPD_CRT] = SDE_CRT_HOTPLUG,
79 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
80 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
81 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
82 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
83};
84
85static const u32 hpd_cpt[HPD_NUM_PINS] = {
86 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
87 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
88 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
89 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
90 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
91};
92
93static const u32 hpd_spt[HPD_NUM_PINS] = {
94 [HPD_PORT_A] = SDE_PORTA_HOTPLUG_SPT,
95 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
96 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
97 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT,
98 [HPD_PORT_E] = SDE_PORTE_HOTPLUG_SPT
99};
100
101static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
102 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
103 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
104 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
105 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
106 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
107 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
108};
109
110static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
111 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
112 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
113 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
114 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
115 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
116 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
117};
118
119static const u32 hpd_status_i915[HPD_NUM_PINS] = {
120 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
121 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
122 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
123 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
124 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
125 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
126};
127
128/* BXT hpd list */
129static const u32 hpd_bxt[HPD_NUM_PINS] = {
130 [HPD_PORT_A] = BXT_DE_PORT_HP_DDIA,
131 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
132 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
133};
134
135static const u32 hpd_gen11[HPD_NUM_PINS] = {
136 [HPD_PORT_C] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
137 [HPD_PORT_D] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
138 [HPD_PORT_E] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
139 [HPD_PORT_F] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG
140};
141
142static const u32 hpd_gen12[HPD_NUM_PINS] = {
143 [HPD_PORT_D] = GEN11_TC1_HOTPLUG | GEN11_TBT1_HOTPLUG,
144 [HPD_PORT_E] = GEN11_TC2_HOTPLUG | GEN11_TBT2_HOTPLUG,
145 [HPD_PORT_F] = GEN11_TC3_HOTPLUG | GEN11_TBT3_HOTPLUG,
146 [HPD_PORT_G] = GEN11_TC4_HOTPLUG | GEN11_TBT4_HOTPLUG,
147 [HPD_PORT_H] = GEN12_TC5_HOTPLUG | GEN12_TBT5_HOTPLUG,
148 [HPD_PORT_I] = GEN12_TC6_HOTPLUG | GEN12_TBT6_HOTPLUG
149};
150
151static const u32 hpd_icp[HPD_NUM_PINS] = {
152 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
153 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
154 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP,
155 [HPD_PORT_D] = SDE_TC2_HOTPLUG_ICP,
156 [HPD_PORT_E] = SDE_TC3_HOTPLUG_ICP,
157 [HPD_PORT_F] = SDE_TC4_HOTPLUG_ICP
158};
159
160static const u32 hpd_mcc[HPD_NUM_PINS] = {
161 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
162 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
163 [HPD_PORT_C] = SDE_TC1_HOTPLUG_ICP
164};
165
166static const u32 hpd_tgp[HPD_NUM_PINS] = {
167 [HPD_PORT_A] = SDE_DDIA_HOTPLUG_ICP,
168 [HPD_PORT_B] = SDE_DDIB_HOTPLUG_ICP,
169 [HPD_PORT_C] = SDE_DDIC_HOTPLUG_TGP,
170 [HPD_PORT_D] = SDE_TC1_HOTPLUG_ICP,
171 [HPD_PORT_E] = SDE_TC2_HOTPLUG_ICP,
172 [HPD_PORT_F] = SDE_TC3_HOTPLUG_ICP,
173 [HPD_PORT_G] = SDE_TC4_HOTPLUG_ICP,
174 [HPD_PORT_H] = SDE_TC5_HOTPLUG_TGP,
175 [HPD_PORT_I] = SDE_TC6_HOTPLUG_TGP,
176};
177
178void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
179 i915_reg_t iir, i915_reg_t ier)
180{
181 intel_uncore_write(uncore, imr, 0xffffffff);
182 intel_uncore_posting_read(uncore, imr);
183
184 intel_uncore_write(uncore, ier, 0);
185
186 /* IIR can theoretically queue up two events. Be paranoid. */
187 intel_uncore_write(uncore, iir, 0xffffffff);
188 intel_uncore_posting_read(uncore, iir);
189 intel_uncore_write(uncore, iir, 0xffffffff);
190 intel_uncore_posting_read(uncore, iir);
191}
192
193void gen2_irq_reset(struct intel_uncore *uncore)
194{
195 intel_uncore_write16(uncore, GEN2_IMR, 0xffff);
196 intel_uncore_posting_read16(uncore, GEN2_IMR);
197
198 intel_uncore_write16(uncore, GEN2_IER, 0);
199
200 /* IIR can theoretically queue up two events. Be paranoid. */
201 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
202 intel_uncore_posting_read16(uncore, GEN2_IIR);
203 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
204 intel_uncore_posting_read16(uncore, GEN2_IIR);
205}
206
207/*
208 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
209 */
210static void gen3_assert_iir_is_zero(struct intel_uncore *uncore, i915_reg_t reg)
211{
212 u32 val = intel_uncore_read(uncore, reg);
213
214 if (val == 0)
215 return;
216
217 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
218 i915_mmio_reg_offset(reg), val);
219 intel_uncore_write(uncore, reg, 0xffffffff);
220 intel_uncore_posting_read(uncore, reg);
221 intel_uncore_write(uncore, reg, 0xffffffff);
222 intel_uncore_posting_read(uncore, reg);
223}
224
225static void gen2_assert_iir_is_zero(struct intel_uncore *uncore)
226{
227 u16 val = intel_uncore_read16(uncore, GEN2_IIR);
228
229 if (val == 0)
230 return;
231
232 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n",
233 i915_mmio_reg_offset(GEN2_IIR), val);
234 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
235 intel_uncore_posting_read16(uncore, GEN2_IIR);
236 intel_uncore_write16(uncore, GEN2_IIR, 0xffff);
237 intel_uncore_posting_read16(uncore, GEN2_IIR);
238}
239
240void gen3_irq_init(struct intel_uncore *uncore,
241 i915_reg_t imr, u32 imr_val,
242 i915_reg_t ier, u32 ier_val,
243 i915_reg_t iir)
244{
245 gen3_assert_iir_is_zero(uncore, iir);
246
247 intel_uncore_write(uncore, ier, ier_val);
248 intel_uncore_write(uncore, imr, imr_val);
249 intel_uncore_posting_read(uncore, imr);
250}
251
252void gen2_irq_init(struct intel_uncore *uncore,
253 u32 imr_val, u32 ier_val)
254{
255 gen2_assert_iir_is_zero(uncore);
256
257 intel_uncore_write16(uncore, GEN2_IER, ier_val);
258 intel_uncore_write16(uncore, GEN2_IMR, imr_val);
259 intel_uncore_posting_read16(uncore, GEN2_IMR);
260}
261
262/* For display hotplug interrupt */
263static inline void
264i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv,
265 u32 mask,
266 u32 bits)
267{
268 u32 val;
269
270 lockdep_assert_held(&dev_priv->irq_lock);
271 WARN_ON(bits & ~mask);
272
273 val = I915_READ(PORT_HOTPLUG_EN);
274 val &= ~mask;
275 val |= bits;
276 I915_WRITE(PORT_HOTPLUG_EN, val);
277}
278
279/**
280 * i915_hotplug_interrupt_update - update hotplug interrupt enable
281 * @dev_priv: driver private
282 * @mask: bits to update
283 * @bits: bits to enable
284 * NOTE: the HPD enable bits are modified both inside and outside
285 * of an interrupt context. To avoid that read-modify-write cycles
286 * interfer, these bits are protected by a spinlock. Since this
287 * function is usually not called from a context where the lock is
288 * held already, this function acquires the lock itself. A non-locking
289 * version is also available.
290 */
291void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
292 u32 mask,
293 u32 bits)
294{
295 spin_lock_irq(&dev_priv->irq_lock);
296 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
297 spin_unlock_irq(&dev_priv->irq_lock);
298}
299
300/**
301 * ilk_update_display_irq - update DEIMR
302 * @dev_priv: driver private
303 * @interrupt_mask: mask of interrupt bits to update
304 * @enabled_irq_mask: mask of interrupt bits to enable
305 */
306void ilk_update_display_irq(struct drm_i915_private *dev_priv,
307 u32 interrupt_mask,
308 u32 enabled_irq_mask)
309{
310 u32 new_val;
311
312 lockdep_assert_held(&dev_priv->irq_lock);
313
314 WARN_ON(enabled_irq_mask & ~interrupt_mask);
315
316 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
317 return;
318
319 new_val = dev_priv->irq_mask;
320 new_val &= ~interrupt_mask;
321 new_val |= (~enabled_irq_mask & interrupt_mask);
322
323 if (new_val != dev_priv->irq_mask) {
324 dev_priv->irq_mask = new_val;
325 I915_WRITE(DEIMR, dev_priv->irq_mask);
326 POSTING_READ(DEIMR);
327 }
328}
329
330static i915_reg_t gen6_pm_iir(struct drm_i915_private *dev_priv)
331{
332 WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11);
333
334 return INTEL_GEN(dev_priv) >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
335}
336
337void gen11_reset_rps_interrupts(struct drm_i915_private *dev_priv)
338{
339 struct intel_gt *gt = &dev_priv->gt;
340
341 spin_lock_irq(>->irq_lock);
342
343 while (gen11_gt_reset_one_iir(gt, 0, GEN11_GTPM))
344 ;
345
346 dev_priv->gt_pm.rps.pm_iir = 0;
347
348 spin_unlock_irq(>->irq_lock);
349}
350
351void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
352{
353 struct intel_gt *gt = &dev_priv->gt;
354
355 spin_lock_irq(>->irq_lock);
356 gen6_gt_pm_reset_iir(gt, GEN6_PM_RPS_EVENTS);
357 dev_priv->gt_pm.rps.pm_iir = 0;
358 spin_unlock_irq(>->irq_lock);
359}
360
361void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
362{
363 struct intel_gt *gt = &dev_priv->gt;
364 struct intel_rps *rps = &dev_priv->gt_pm.rps;
365
366 if (READ_ONCE(rps->interrupts_enabled))
367 return;
368
369 spin_lock_irq(>->irq_lock);
370 WARN_ON_ONCE(rps->pm_iir);
371
372 if (INTEL_GEN(dev_priv) >= 11)
373 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GTPM));
374 else
375 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
376
377 rps->interrupts_enabled = true;
378 gen6_gt_pm_enable_irq(gt, dev_priv->pm_rps_events);
379
380 spin_unlock_irq(>->irq_lock);
381}
382
383u32 gen6_sanitize_rps_pm_mask(const struct drm_i915_private *i915, u32 mask)
384{
385 return mask & ~i915->gt_pm.rps.pm_intrmsk_mbz;
386}
387
388void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
389{
390 struct intel_rps *rps = &dev_priv->gt_pm.rps;
391 struct intel_gt *gt = &dev_priv->gt;
392
393 if (!READ_ONCE(rps->interrupts_enabled))
394 return;
395
396 spin_lock_irq(>->irq_lock);
397 rps->interrupts_enabled = false;
398
399 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0u));
400
401 gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
402
403 spin_unlock_irq(>->irq_lock);
404 intel_synchronize_irq(dev_priv);
405
406 /* Now that we will not be generating any more work, flush any
407 * outstanding tasks. As we are called on the RPS idle path,
408 * we will reset the GPU to minimum frequencies, so the current
409 * state of the worker can be discarded.
410 */
411 cancel_work_sync(&rps->work);
412 if (INTEL_GEN(dev_priv) >= 11)
413 gen11_reset_rps_interrupts(dev_priv);
414 else
415 gen6_reset_rps_interrupts(dev_priv);
416}
417
418void gen9_reset_guc_interrupts(struct intel_guc *guc)
419{
420 struct intel_gt *gt = guc_to_gt(guc);
421
422 assert_rpm_wakelock_held(>->i915->runtime_pm);
423
424 spin_lock_irq(>->irq_lock);
425 gen6_gt_pm_reset_iir(gt, gt->pm_guc_events);
426 spin_unlock_irq(>->irq_lock);
427}
428
429void gen9_enable_guc_interrupts(struct intel_guc *guc)
430{
431 struct intel_gt *gt = guc_to_gt(guc);
432
433 assert_rpm_wakelock_held(>->i915->runtime_pm);
434
435 spin_lock_irq(>->irq_lock);
436 if (!guc->interrupts.enabled) {
437 WARN_ON_ONCE(intel_uncore_read(gt->uncore,
438 gen6_pm_iir(gt->i915)) &
439 gt->pm_guc_events);
440 guc->interrupts.enabled = true;
441 gen6_gt_pm_enable_irq(gt, gt->pm_guc_events);
442 }
443 spin_unlock_irq(>->irq_lock);
444}
445
446void gen9_disable_guc_interrupts(struct intel_guc *guc)
447{
448 struct intel_gt *gt = guc_to_gt(guc);
449
450 assert_rpm_wakelock_held(>->i915->runtime_pm);
451
452 spin_lock_irq(>->irq_lock);
453 guc->interrupts.enabled = false;
454
455 gen6_gt_pm_disable_irq(gt, gt->pm_guc_events);
456
457 spin_unlock_irq(>->irq_lock);
458 intel_synchronize_irq(gt->i915);
459
460 gen9_reset_guc_interrupts(guc);
461}
462
463void gen11_reset_guc_interrupts(struct intel_guc *guc)
464{
465 struct intel_gt *gt = guc_to_gt(guc);
466
467 spin_lock_irq(>->irq_lock);
468 gen11_gt_reset_one_iir(gt, 0, GEN11_GUC);
469 spin_unlock_irq(>->irq_lock);
470}
471
472void gen11_enable_guc_interrupts(struct intel_guc *guc)
473{
474 struct intel_gt *gt = guc_to_gt(guc);
475
476 spin_lock_irq(>->irq_lock);
477 if (!guc->interrupts.enabled) {
478 u32 events = REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST);
479
480 WARN_ON_ONCE(gen11_gt_reset_one_iir(gt, 0, GEN11_GUC));
481 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, events);
482 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~events);
483 guc->interrupts.enabled = true;
484 }
485 spin_unlock_irq(>->irq_lock);
486}
487
488void gen11_disable_guc_interrupts(struct intel_guc *guc)
489{
490 struct intel_gt *gt = guc_to_gt(guc);
491
492 spin_lock_irq(>->irq_lock);
493 guc->interrupts.enabled = false;
494
495 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_MASK, ~0);
496 intel_uncore_write(gt->uncore, GEN11_GUC_SG_INTR_ENABLE, 0);
497
498 spin_unlock_irq(>->irq_lock);
499 intel_synchronize_irq(gt->i915);
500
501 gen11_reset_guc_interrupts(guc);
502}
503
504/**
505 * bdw_update_port_irq - update DE port interrupt
506 * @dev_priv: driver private
507 * @interrupt_mask: mask of interrupt bits to update
508 * @enabled_irq_mask: mask of interrupt bits to enable
509 */
510static void bdw_update_port_irq(struct drm_i915_private *dev_priv,
511 u32 interrupt_mask,
512 u32 enabled_irq_mask)
513{
514 u32 new_val;
515 u32 old_val;
516
517 lockdep_assert_held(&dev_priv->irq_lock);
518
519 WARN_ON(enabled_irq_mask & ~interrupt_mask);
520
521 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
522 return;
523
524 old_val = I915_READ(GEN8_DE_PORT_IMR);
525
526 new_val = old_val;
527 new_val &= ~interrupt_mask;
528 new_val |= (~enabled_irq_mask & interrupt_mask);
529
530 if (new_val != old_val) {
531 I915_WRITE(GEN8_DE_PORT_IMR, new_val);
532 POSTING_READ(GEN8_DE_PORT_IMR);
533 }
534}
535
536/**
537 * bdw_update_pipe_irq - update DE pipe interrupt
538 * @dev_priv: driver private
539 * @pipe: pipe whose interrupt to update
540 * @interrupt_mask: mask of interrupt bits to update
541 * @enabled_irq_mask: mask of interrupt bits to enable
542 */
543void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
544 enum pipe pipe,
545 u32 interrupt_mask,
546 u32 enabled_irq_mask)
547{
548 u32 new_val;
549
550 lockdep_assert_held(&dev_priv->irq_lock);
551
552 WARN_ON(enabled_irq_mask & ~interrupt_mask);
553
554 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
555 return;
556
557 new_val = dev_priv->de_irq_mask[pipe];
558 new_val &= ~interrupt_mask;
559 new_val |= (~enabled_irq_mask & interrupt_mask);
560
561 if (new_val != dev_priv->de_irq_mask[pipe]) {
562 dev_priv->de_irq_mask[pipe] = new_val;
563 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
564 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
565 }
566}
567
568/**
569 * ibx_display_interrupt_update - update SDEIMR
570 * @dev_priv: driver private
571 * @interrupt_mask: mask of interrupt bits to update
572 * @enabled_irq_mask: mask of interrupt bits to enable
573 */
574void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
575 u32 interrupt_mask,
576 u32 enabled_irq_mask)
577{
578 u32 sdeimr = I915_READ(SDEIMR);
579 sdeimr &= ~interrupt_mask;
580 sdeimr |= (~enabled_irq_mask & interrupt_mask);
581
582 WARN_ON(enabled_irq_mask & ~interrupt_mask);
583
584 lockdep_assert_held(&dev_priv->irq_lock);
585
586 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
587 return;
588
589 I915_WRITE(SDEIMR, sdeimr);
590 POSTING_READ(SDEIMR);
591}
592
593u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
594 enum pipe pipe)
595{
596 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
597 u32 enable_mask = status_mask << 16;
598
599 lockdep_assert_held(&dev_priv->irq_lock);
600
601 if (INTEL_GEN(dev_priv) < 5)
602 goto out;
603
604 /*
605 * On pipe A we don't support the PSR interrupt yet,
606 * on pipe B and C the same bit MBZ.
607 */
608 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
609 return 0;
610 /*
611 * On pipe B and C we don't support the PSR interrupt yet, on pipe
612 * A the same bit is for perf counters which we don't use either.
613 */
614 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
615 return 0;
616
617 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
618 SPRITE0_FLIP_DONE_INT_EN_VLV |
619 SPRITE1_FLIP_DONE_INT_EN_VLV);
620 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
621 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
622 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
623 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
624
625out:
626 WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
627 status_mask & ~PIPESTAT_INT_STATUS_MASK,
628 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
629 pipe_name(pipe), enable_mask, status_mask);
630
631 return enable_mask;
632}
633
634void i915_enable_pipestat(struct drm_i915_private *dev_priv,
635 enum pipe pipe, u32 status_mask)
636{
637 i915_reg_t reg = PIPESTAT(pipe);
638 u32 enable_mask;
639
640 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
641 "pipe %c: status_mask=0x%x\n",
642 pipe_name(pipe), status_mask);
643
644 lockdep_assert_held(&dev_priv->irq_lock);
645 WARN_ON(!intel_irqs_enabled(dev_priv));
646
647 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
648 return;
649
650 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
651 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
652
653 I915_WRITE(reg, enable_mask | status_mask);
654 POSTING_READ(reg);
655}
656
657void i915_disable_pipestat(struct drm_i915_private *dev_priv,
658 enum pipe pipe, u32 status_mask)
659{
660 i915_reg_t reg = PIPESTAT(pipe);
661 u32 enable_mask;
662
663 WARN_ONCE(status_mask & ~PIPESTAT_INT_STATUS_MASK,
664 "pipe %c: status_mask=0x%x\n",
665 pipe_name(pipe), status_mask);
666
667 lockdep_assert_held(&dev_priv->irq_lock);
668 WARN_ON(!intel_irqs_enabled(dev_priv));
669
670 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
671 return;
672
673 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
674 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
675
676 I915_WRITE(reg, enable_mask | status_mask);
677 POSTING_READ(reg);
678}
679
680static bool i915_has_asle(struct drm_i915_private *dev_priv)
681{
682 if (!dev_priv->opregion.asle)
683 return false;
684
685 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
686}
687
688/**
689 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
690 * @dev_priv: i915 device private
691 */
692static void i915_enable_asle_pipestat(struct drm_i915_private *dev_priv)
693{
694 if (!i915_has_asle(dev_priv))
695 return;
696
697 spin_lock_irq(&dev_priv->irq_lock);
698
699 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
700 if (INTEL_GEN(dev_priv) >= 4)
701 i915_enable_pipestat(dev_priv, PIPE_A,
702 PIPE_LEGACY_BLC_EVENT_STATUS);
703
704 spin_unlock_irq(&dev_priv->irq_lock);
705}
706
707/*
708 * This timing diagram depicts the video signal in and
709 * around the vertical blanking period.
710 *
711 * Assumptions about the fictitious mode used in this example:
712 * vblank_start >= 3
713 * vsync_start = vblank_start + 1
714 * vsync_end = vblank_start + 2
715 * vtotal = vblank_start + 3
716 *
717 * start of vblank:
718 * latch double buffered registers
719 * increment frame counter (ctg+)
720 * generate start of vblank interrupt (gen4+)
721 * |
722 * | frame start:
723 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
724 * | may be shifted forward 1-3 extra lines via PIPECONF
725 * | |
726 * | | start of vsync:
727 * | | generate vsync interrupt
728 * | | |
729 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
730 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
731 * ----va---> <-----------------vb--------------------> <--------va-------------
732 * | | <----vs-----> |
733 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
734 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
735 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
736 * | | |
737 * last visible pixel first visible pixel
738 * | increment frame counter (gen3/4)
739 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
740 *
741 * x = horizontal active
742 * _ = horizontal blanking
743 * hs = horizontal sync
744 * va = vertical active
745 * vb = vertical blanking
746 * vs = vertical sync
747 * vbs = vblank_start (number)
748 *
749 * Summary:
750 * - most events happen at the start of horizontal sync
751 * - frame start happens at the start of horizontal blank, 1-4 lines
752 * (depending on PIPECONF settings) after the start of vblank
753 * - gen3/4 pixel and frame counter are synchronized with the start
754 * of horizontal active on the first line of vertical active
755 */
756
757/* Called from drm generic code, passed a 'crtc', which
758 * we use as a pipe index
759 */
760u32 i915_get_vblank_counter(struct drm_crtc *crtc)
761{
762 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
763 struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)];
764 const struct drm_display_mode *mode = &vblank->hwmode;
765 enum pipe pipe = to_intel_crtc(crtc)->pipe;
766 i915_reg_t high_frame, low_frame;
767 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
768 unsigned long irqflags;
769
770 /*
771 * On i965gm TV output the frame counter only works up to
772 * the point when we enable the TV encoder. After that the
773 * frame counter ceases to work and reads zero. We need a
774 * vblank wait before enabling the TV encoder and so we
775 * have to enable vblank interrupts while the frame counter
776 * is still in a working state. However the core vblank code
777 * does not like us returning non-zero frame counter values
778 * when we've told it that we don't have a working frame
779 * counter. Thus we must stop non-zero values leaking out.
780 */
781 if (!vblank->max_vblank_count)
782 return 0;
783
784 htotal = mode->crtc_htotal;
785 hsync_start = mode->crtc_hsync_start;
786 vbl_start = mode->crtc_vblank_start;
787 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
788 vbl_start = DIV_ROUND_UP(vbl_start, 2);
789
790 /* Convert to pixel count */
791 vbl_start *= htotal;
792
793 /* Start of vblank event occurs at start of hsync */
794 vbl_start -= htotal - hsync_start;
795
796 high_frame = PIPEFRAME(pipe);
797 low_frame = PIPEFRAMEPIXEL(pipe);
798
799 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
800
801 /*
802 * High & low register fields aren't synchronized, so make sure
803 * we get a low value that's stable across two reads of the high
804 * register.
805 */
806 do {
807 high1 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
808 low = I915_READ_FW(low_frame);
809 high2 = I915_READ_FW(high_frame) & PIPE_FRAME_HIGH_MASK;
810 } while (high1 != high2);
811
812 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
813
814 high1 >>= PIPE_FRAME_HIGH_SHIFT;
815 pixel = low & PIPE_PIXEL_MASK;
816 low >>= PIPE_FRAME_LOW_SHIFT;
817
818 /*
819 * The frame counter increments at beginning of active.
820 * Cook up a vblank counter by also checking the pixel
821 * counter against vblank start.
822 */
823 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
824}
825
826u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
827{
828 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
829 enum pipe pipe = to_intel_crtc(crtc)->pipe;
830
831 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
832}
833
834/*
835 * On certain encoders on certain platforms, pipe
836 * scanline register will not work to get the scanline,
837 * since the timings are driven from the PORT or issues
838 * with scanline register updates.
839 * This function will use Framestamp and current
840 * timestamp registers to calculate the scanline.
841 */
842static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc)
843{
844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
845 struct drm_vblank_crtc *vblank =
846 &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
847 const struct drm_display_mode *mode = &vblank->hwmode;
848 u32 vblank_start = mode->crtc_vblank_start;
849 u32 vtotal = mode->crtc_vtotal;
850 u32 htotal = mode->crtc_htotal;
851 u32 clock = mode->crtc_clock;
852 u32 scanline, scan_prev_time, scan_curr_time, scan_post_time;
853
854 /*
855 * To avoid the race condition where we might cross into the
856 * next vblank just between the PIPE_FRMTMSTMP and TIMESTAMP_CTR
857 * reads. We make sure we read PIPE_FRMTMSTMP and TIMESTAMP_CTR
858 * during the same frame.
859 */
860 do {
861 /*
862 * This field provides read back of the display
863 * pipe frame time stamp. The time stamp value
864 * is sampled at every start of vertical blank.
865 */
866 scan_prev_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
867
868 /*
869 * The TIMESTAMP_CTR register has the current
870 * time stamp value.
871 */
872 scan_curr_time = I915_READ_FW(IVB_TIMESTAMP_CTR);
873
874 scan_post_time = I915_READ_FW(PIPE_FRMTMSTMP(crtc->pipe));
875 } while (scan_post_time != scan_prev_time);
876
877 scanline = div_u64(mul_u32_u32(scan_curr_time - scan_prev_time,
878 clock), 1000 * htotal);
879 scanline = min(scanline, vtotal - 1);
880 scanline = (scanline + vblank_start) % vtotal;
881
882 return scanline;
883}
884
885/* I915_READ_FW, only for fast reads of display block, no need for forcewake etc. */
886static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
887{
888 struct drm_device *dev = crtc->base.dev;
889 struct drm_i915_private *dev_priv = to_i915(dev);
890 const struct drm_display_mode *mode;
891 struct drm_vblank_crtc *vblank;
892 enum pipe pipe = crtc->pipe;
893 int position, vtotal;
894
895 if (!crtc->active)
896 return -1;
897
898 vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)];
899 mode = &vblank->hwmode;
900
901 if (mode->private_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP)
902 return __intel_get_crtc_scanline_from_timestamp(crtc);
903
904 vtotal = mode->crtc_vtotal;
905 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
906 vtotal /= 2;
907
908 if (IS_GEN(dev_priv, 2))
909 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
910 else
911 position = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
912
913 /*
914 * On HSW, the DSL reg (0x70000) appears to return 0 if we
915 * read it just before the start of vblank. So try it again
916 * so we don't accidentally end up spanning a vblank frame
917 * increment, causing the pipe_update_end() code to squak at us.
918 *
919 * The nature of this problem means we can't simply check the ISR
920 * bit and return the vblank start value; nor can we use the scanline
921 * debug register in the transcoder as it appears to have the same
922 * problem. We may need to extend this to include other platforms,
923 * but so far testing only shows the problem on HSW.
924 */
925 if (HAS_DDI(dev_priv) && !position) {
926 int i, temp;
927
928 for (i = 0; i < 100; i++) {
929 udelay(1);
930 temp = I915_READ_FW(PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
931 if (temp != position) {
932 position = temp;
933 break;
934 }
935 }
936 }
937
938 /*
939 * See update_scanline_offset() for the details on the
940 * scanline_offset adjustment.
941 */
942 return (position + crtc->scanline_offset) % vtotal;
943}
944
945bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
946 bool in_vblank_irq, int *vpos, int *hpos,
947 ktime_t *stime, ktime_t *etime,
948 const struct drm_display_mode *mode)
949{
950 struct drm_i915_private *dev_priv = to_i915(dev);
951 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
952 pipe);
953 int position;
954 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
955 unsigned long irqflags;
956 bool use_scanline_counter = INTEL_GEN(dev_priv) >= 5 ||
957 IS_G4X(dev_priv) || IS_GEN(dev_priv, 2) ||
958 mode->private_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER;
959
960 if (WARN_ON(!mode->crtc_clock)) {
961 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
962 "pipe %c\n", pipe_name(pipe));
963 return false;
964 }
965
966 htotal = mode->crtc_htotal;
967 hsync_start = mode->crtc_hsync_start;
968 vtotal = mode->crtc_vtotal;
969 vbl_start = mode->crtc_vblank_start;
970 vbl_end = mode->crtc_vblank_end;
971
972 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
973 vbl_start = DIV_ROUND_UP(vbl_start, 2);
974 vbl_end /= 2;
975 vtotal /= 2;
976 }
977
978 /*
979 * Lock uncore.lock, as we will do multiple timing critical raw
980 * register reads, potentially with preemption disabled, so the
981 * following code must not block on uncore.lock.
982 */
983 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
984
985 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
986
987 /* Get optional system timestamp before query. */
988 if (stime)
989 *stime = ktime_get();
990
991 if (use_scanline_counter) {
992 /* No obvious pixelcount register. Only query vertical
993 * scanout position from Display scan line register.
994 */
995 position = __intel_get_crtc_scanline(intel_crtc);
996 } else {
997 /* Have access to pixelcount since start of frame.
998 * We can split this into vertical and horizontal
999 * scanout position.
1000 */
1001 position = (I915_READ_FW(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1002
1003 /* convert to pixel counts */
1004 vbl_start *= htotal;
1005 vbl_end *= htotal;
1006 vtotal *= htotal;
1007
1008 /*
1009 * In interlaced modes, the pixel counter counts all pixels,
1010 * so one field will have htotal more pixels. In order to avoid
1011 * the reported position from jumping backwards when the pixel
1012 * counter is beyond the length of the shorter field, just
1013 * clamp the position the length of the shorter field. This
1014 * matches how the scanline counter based position works since
1015 * the scanline counter doesn't count the two half lines.
1016 */
1017 if (position >= vtotal)
1018 position = vtotal - 1;
1019
1020 /*
1021 * Start of vblank interrupt is triggered at start of hsync,
1022 * just prior to the first active line of vblank. However we
1023 * consider lines to start at the leading edge of horizontal
1024 * active. So, should we get here before we've crossed into
1025 * the horizontal active of the first line in vblank, we would
1026 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
1027 * always add htotal-hsync_start to the current pixel position.
1028 */
1029 position = (position + htotal - hsync_start) % vtotal;
1030 }
1031
1032 /* Get optional system timestamp after query. */
1033 if (etime)
1034 *etime = ktime_get();
1035
1036 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
1037
1038 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1039
1040 /*
1041 * While in vblank, position will be negative
1042 * counting up towards 0 at vbl_end. And outside
1043 * vblank, position will be positive counting
1044 * up since vbl_end.
1045 */
1046 if (position >= vbl_start)
1047 position -= vbl_end;
1048 else
1049 position += vtotal - vbl_end;
1050
1051 if (use_scanline_counter) {
1052 *vpos = position;
1053 *hpos = 0;
1054 } else {
1055 *vpos = position / htotal;
1056 *hpos = position - (*vpos * htotal);
1057 }
1058
1059 return true;
1060}
1061
1062int intel_get_crtc_scanline(struct intel_crtc *crtc)
1063{
1064 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1065 unsigned long irqflags;
1066 int position;
1067
1068 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
1069 position = __intel_get_crtc_scanline(crtc);
1070 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
1071
1072 return position;
1073}
1074
1075static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv)
1076{
1077 struct intel_uncore *uncore = &dev_priv->uncore;
1078 u32 busy_up, busy_down, max_avg, min_avg;
1079 u8 new_delay;
1080
1081 spin_lock(&mchdev_lock);
1082
1083 intel_uncore_write16(uncore,
1084 MEMINTRSTS,
1085 intel_uncore_read(uncore, MEMINTRSTS));
1086
1087 new_delay = dev_priv->ips.cur_delay;
1088
1089 intel_uncore_write16(uncore, MEMINTRSTS, MEMINT_EVAL_CHG);
1090 busy_up = intel_uncore_read(uncore, RCPREVBSYTUPAVG);
1091 busy_down = intel_uncore_read(uncore, RCPREVBSYTDNAVG);
1092 max_avg = intel_uncore_read(uncore, RCBMAXAVG);
1093 min_avg = intel_uncore_read(uncore, RCBMINAVG);
1094
1095 /* Handle RCS change request from hw */
1096 if (busy_up > max_avg) {
1097 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
1098 new_delay = dev_priv->ips.cur_delay - 1;
1099 if (new_delay < dev_priv->ips.max_delay)
1100 new_delay = dev_priv->ips.max_delay;
1101 } else if (busy_down < min_avg) {
1102 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
1103 new_delay = dev_priv->ips.cur_delay + 1;
1104 if (new_delay > dev_priv->ips.min_delay)
1105 new_delay = dev_priv->ips.min_delay;
1106 }
1107
1108 if (ironlake_set_drps(dev_priv, new_delay))
1109 dev_priv->ips.cur_delay = new_delay;
1110
1111 spin_unlock(&mchdev_lock);
1112
1113 return;
1114}
1115
1116static void vlv_c0_read(struct drm_i915_private *dev_priv,
1117 struct intel_rps_ei *ei)
1118{
1119 ei->ktime = ktime_get_raw();
1120 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1121 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
1122}
1123
1124void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1125{
1126 memset(&dev_priv->gt_pm.rps.ei, 0, sizeof(dev_priv->gt_pm.rps.ei));
1127}
1128
1129static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1130{
1131 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1132 const struct intel_rps_ei *prev = &rps->ei;
1133 struct intel_rps_ei now;
1134 u32 events = 0;
1135
1136 if ((pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) == 0)
1137 return 0;
1138
1139 vlv_c0_read(dev_priv, &now);
1140
1141 if (prev->ktime) {
1142 u64 time, c0;
1143 u32 render, media;
1144
1145 time = ktime_us_delta(now.ktime, prev->ktime);
1146
1147 time *= dev_priv->czclk_freq;
1148
1149 /* Workload can be split between render + media,
1150 * e.g. SwapBuffers being blitted in X after being rendered in
1151 * mesa. To account for this we need to combine both engines
1152 * into our activity counter.
1153 */
1154 render = now.render_c0 - prev->render_c0;
1155 media = now.media_c0 - prev->media_c0;
1156 c0 = max(render, media);
1157 c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */
1158
1159 if (c0 > time * rps->power.up_threshold)
1160 events = GEN6_PM_RP_UP_THRESHOLD;
1161 else if (c0 < time * rps->power.down_threshold)
1162 events = GEN6_PM_RP_DOWN_THRESHOLD;
1163 }
1164
1165 rps->ei = now;
1166 return events;
1167}
1168
1169static void gen6_pm_rps_work(struct work_struct *work)
1170{
1171 struct drm_i915_private *dev_priv =
1172 container_of(work, struct drm_i915_private, gt_pm.rps.work);
1173 struct intel_gt *gt = &dev_priv->gt;
1174 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1175 bool client_boost = false;
1176 int new_delay, adj, min, max;
1177 u32 pm_iir = 0;
1178
1179 spin_lock_irq(>->irq_lock);
1180 if (rps->interrupts_enabled) {
1181 pm_iir = fetch_and_zero(&rps->pm_iir);
1182 client_boost = atomic_read(&rps->num_waiters);
1183 }
1184 spin_unlock_irq(>->irq_lock);
1185
1186 /* Make sure we didn't queue anything we're not going to process. */
1187 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
1188 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
1189 goto out;
1190
1191 mutex_lock(&rps->lock);
1192
1193 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1194
1195 adj = rps->last_adj;
1196 new_delay = rps->cur_freq;
1197 min = rps->min_freq_softlimit;
1198 max = rps->max_freq_softlimit;
1199 if (client_boost)
1200 max = rps->max_freq;
1201 if (client_boost && new_delay < rps->boost_freq) {
1202 new_delay = rps->boost_freq;
1203 adj = 0;
1204 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
1205 if (adj > 0)
1206 adj *= 2;
1207 else /* CHV needs even encode values */
1208 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
1209
1210 if (new_delay >= rps->max_freq_softlimit)
1211 adj = 0;
1212 } else if (client_boost) {
1213 adj = 0;
1214 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
1215 if (rps->cur_freq > rps->efficient_freq)
1216 new_delay = rps->efficient_freq;
1217 else if (rps->cur_freq > rps->min_freq_softlimit)
1218 new_delay = rps->min_freq_softlimit;
1219 adj = 0;
1220 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1221 if (adj < 0)
1222 adj *= 2;
1223 else /* CHV needs even encode values */
1224 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
1225
1226 if (new_delay <= rps->min_freq_softlimit)
1227 adj = 0;
1228 } else { /* unknown event */
1229 adj = 0;
1230 }
1231
1232 rps->last_adj = adj;
1233
1234 /*
1235 * Limit deboosting and boosting to keep ourselves at the extremes
1236 * when in the respective power modes (i.e. slowly decrease frequencies
1237 * while in the HIGH_POWER zone and slowly increase frequencies while
1238 * in the LOW_POWER zone). On idle, we will hit the timeout and drop
1239 * to the next level quickly, and conversely if busy we expect to
1240 * hit a waitboost and rapidly switch into max power.
1241 */
1242 if ((adj < 0 && rps->power.mode == HIGH_POWER) ||
1243 (adj > 0 && rps->power.mode == LOW_POWER))
1244 rps->last_adj = 0;
1245
1246 /* sysfs frequency interfaces may have snuck in while servicing the
1247 * interrupt
1248 */
1249 new_delay += adj;
1250 new_delay = clamp_t(int, new_delay, min, max);
1251
1252 if (intel_set_rps(dev_priv, new_delay)) {
1253 DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
1254 rps->last_adj = 0;
1255 }
1256
1257 mutex_unlock(&rps->lock);
1258
1259out:
1260 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1261 spin_lock_irq(>->irq_lock);
1262 if (rps->interrupts_enabled)
1263 gen6_gt_pm_unmask_irq(gt, dev_priv->pm_rps_events);
1264 spin_unlock_irq(>->irq_lock);
1265}
1266
1267
1268/**
1269 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1270 * occurred.
1271 * @work: workqueue struct
1272 *
1273 * Doesn't actually do anything except notify userspace. As a consequence of
1274 * this event, userspace should try to remap the bad rows since statistically
1275 * it is likely the same row is more likely to go bad again.
1276 */
1277static void ivybridge_parity_work(struct work_struct *work)
1278{
1279 struct drm_i915_private *dev_priv =
1280 container_of(work, typeof(*dev_priv), l3_parity.error_work);
1281 struct intel_gt *gt = &dev_priv->gt;
1282 u32 error_status, row, bank, subbank;
1283 char *parity_event[6];
1284 u32 misccpctl;
1285 u8 slice = 0;
1286
1287 /* We must turn off DOP level clock gating to access the L3 registers.
1288 * In order to prevent a get/put style interface, acquire struct mutex
1289 * any time we access those registers.
1290 */
1291 mutex_lock(&dev_priv->drm.struct_mutex);
1292
1293 /* If we've screwed up tracking, just let the interrupt fire again */
1294 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1295 goto out;
1296
1297 misccpctl = I915_READ(GEN7_MISCCPCTL);
1298 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1299 POSTING_READ(GEN7_MISCCPCTL);
1300
1301 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1302 i915_reg_t reg;
1303
1304 slice--;
1305 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv)))
1306 break;
1307
1308 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1309
1310 reg = GEN7_L3CDERRST1(slice);
1311
1312 error_status = I915_READ(reg);
1313 row = GEN7_PARITY_ERROR_ROW(error_status);
1314 bank = GEN7_PARITY_ERROR_BANK(error_status);
1315 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1316
1317 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1318 POSTING_READ(reg);
1319
1320 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1321 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1322 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1323 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1324 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1325 parity_event[5] = NULL;
1326
1327 kobject_uevent_env(&dev_priv->drm.primary->kdev->kobj,
1328 KOBJ_CHANGE, parity_event);
1329
1330 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1331 slice, row, bank, subbank);
1332
1333 kfree(parity_event[4]);
1334 kfree(parity_event[3]);
1335 kfree(parity_event[2]);
1336 kfree(parity_event[1]);
1337 }
1338
1339 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1340
1341out:
1342 WARN_ON(dev_priv->l3_parity.which_slice);
1343 spin_lock_irq(>->irq_lock);
1344 gen5_gt_enable_irq(gt, GT_PARITY_ERROR(dev_priv));
1345 spin_unlock_irq(>->irq_lock);
1346
1347 mutex_unlock(&dev_priv->drm.struct_mutex);
1348}
1349
1350static bool gen11_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1351{
1352 switch (pin) {
1353 case HPD_PORT_C:
1354 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1355 case HPD_PORT_D:
1356 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1357 case HPD_PORT_E:
1358 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1359 case HPD_PORT_F:
1360 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1361 default:
1362 return false;
1363 }
1364}
1365
1366static bool gen12_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1367{
1368 switch (pin) {
1369 case HPD_PORT_D:
1370 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC1);
1371 case HPD_PORT_E:
1372 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC2);
1373 case HPD_PORT_F:
1374 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC3);
1375 case HPD_PORT_G:
1376 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC4);
1377 case HPD_PORT_H:
1378 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC5);
1379 case HPD_PORT_I:
1380 return val & GEN11_HOTPLUG_CTL_LONG_DETECT(PORT_TC6);
1381 default:
1382 return false;
1383 }
1384}
1385
1386static bool bxt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1387{
1388 switch (pin) {
1389 case HPD_PORT_A:
1390 return val & PORTA_HOTPLUG_LONG_DETECT;
1391 case HPD_PORT_B:
1392 return val & PORTB_HOTPLUG_LONG_DETECT;
1393 case HPD_PORT_C:
1394 return val & PORTC_HOTPLUG_LONG_DETECT;
1395 default:
1396 return false;
1397 }
1398}
1399
1400static bool icp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1401{
1402 switch (pin) {
1403 case HPD_PORT_A:
1404 return val & ICP_DDIA_HPD_LONG_DETECT;
1405 case HPD_PORT_B:
1406 return val & ICP_DDIB_HPD_LONG_DETECT;
1407 case HPD_PORT_C:
1408 return val & TGP_DDIC_HPD_LONG_DETECT;
1409 default:
1410 return false;
1411 }
1412}
1413
1414static bool icp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1415{
1416 switch (pin) {
1417 case HPD_PORT_C:
1418 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1419 case HPD_PORT_D:
1420 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1421 case HPD_PORT_E:
1422 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1423 case HPD_PORT_F:
1424 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1425 default:
1426 return false;
1427 }
1428}
1429
1430static bool tgp_ddi_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1431{
1432 switch (pin) {
1433 case HPD_PORT_A:
1434 return val & ICP_DDIA_HPD_LONG_DETECT;
1435 case HPD_PORT_B:
1436 return val & ICP_DDIB_HPD_LONG_DETECT;
1437 case HPD_PORT_C:
1438 return val & TGP_DDIC_HPD_LONG_DETECT;
1439 default:
1440 return false;
1441 }
1442}
1443
1444static bool tgp_tc_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1445{
1446 switch (pin) {
1447 case HPD_PORT_D:
1448 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC1);
1449 case HPD_PORT_E:
1450 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC2);
1451 case HPD_PORT_F:
1452 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC3);
1453 case HPD_PORT_G:
1454 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC4);
1455 case HPD_PORT_H:
1456 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC5);
1457 case HPD_PORT_I:
1458 return val & ICP_TC_HPD_LONG_DETECT(PORT_TC6);
1459 default:
1460 return false;
1461 }
1462}
1463
1464static bool spt_port_hotplug2_long_detect(enum hpd_pin pin, u32 val)
1465{
1466 switch (pin) {
1467 case HPD_PORT_E:
1468 return val & PORTE_HOTPLUG_LONG_DETECT;
1469 default:
1470 return false;
1471 }
1472}
1473
1474static bool spt_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1475{
1476 switch (pin) {
1477 case HPD_PORT_A:
1478 return val & PORTA_HOTPLUG_LONG_DETECT;
1479 case HPD_PORT_B:
1480 return val & PORTB_HOTPLUG_LONG_DETECT;
1481 case HPD_PORT_C:
1482 return val & PORTC_HOTPLUG_LONG_DETECT;
1483 case HPD_PORT_D:
1484 return val & PORTD_HOTPLUG_LONG_DETECT;
1485 default:
1486 return false;
1487 }
1488}
1489
1490static bool ilk_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1491{
1492 switch (pin) {
1493 case HPD_PORT_A:
1494 return val & DIGITAL_PORTA_HOTPLUG_LONG_DETECT;
1495 default:
1496 return false;
1497 }
1498}
1499
1500static bool pch_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1501{
1502 switch (pin) {
1503 case HPD_PORT_B:
1504 return val & PORTB_HOTPLUG_LONG_DETECT;
1505 case HPD_PORT_C:
1506 return val & PORTC_HOTPLUG_LONG_DETECT;
1507 case HPD_PORT_D:
1508 return val & PORTD_HOTPLUG_LONG_DETECT;
1509 default:
1510 return false;
1511 }
1512}
1513
1514static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
1515{
1516 switch (pin) {
1517 case HPD_PORT_B:
1518 return val & PORTB_HOTPLUG_INT_LONG_PULSE;
1519 case HPD_PORT_C:
1520 return val & PORTC_HOTPLUG_INT_LONG_PULSE;
1521 case HPD_PORT_D:
1522 return val & PORTD_HOTPLUG_INT_LONG_PULSE;
1523 default:
1524 return false;
1525 }
1526}
1527
1528/*
1529 * Get a bit mask of pins that have triggered, and which ones may be long.
1530 * This can be called multiple times with the same masks to accumulate
1531 * hotplug detection results from several registers.
1532 *
1533 * Note that the caller is expected to zero out the masks initially.
1534 */
1535static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
1536 u32 *pin_mask, u32 *long_mask,
1537 u32 hotplug_trigger, u32 dig_hotplug_reg,
1538 const u32 hpd[HPD_NUM_PINS],
1539 bool long_pulse_detect(enum hpd_pin pin, u32 val))
1540{
1541 enum hpd_pin pin;
1542
1543 BUILD_BUG_ON(BITS_PER_TYPE(*pin_mask) < HPD_NUM_PINS);
1544
1545 for_each_hpd_pin(pin) {
1546 if ((hpd[pin] & hotplug_trigger) == 0)
1547 continue;
1548
1549 *pin_mask |= BIT(pin);
1550
1551 if (long_pulse_detect(pin, dig_hotplug_reg))
1552 *long_mask |= BIT(pin);
1553 }
1554
1555 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x, long 0x%08x\n",
1556 hotplug_trigger, dig_hotplug_reg, *pin_mask, *long_mask);
1557
1558}
1559
1560static void gmbus_irq_handler(struct drm_i915_private *dev_priv)
1561{
1562 wake_up_all(&dev_priv->gmbus_wait_queue);
1563}
1564
1565static void dp_aux_irq_handler(struct drm_i915_private *dev_priv)
1566{
1567 wake_up_all(&dev_priv->gmbus_wait_queue);
1568}
1569
1570#if defined(CONFIG_DEBUG_FS)
1571static void display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1572 enum pipe pipe,
1573 u32 crc0, u32 crc1,
1574 u32 crc2, u32 crc3,
1575 u32 crc4)
1576{
1577 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1578 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1579 u32 crcs[5] = { crc0, crc1, crc2, crc3, crc4 };
1580
1581 trace_intel_pipe_crc(crtc, crcs);
1582
1583 spin_lock(&pipe_crc->lock);
1584 /*
1585 * For some not yet identified reason, the first CRC is
1586 * bonkers. So let's just wait for the next vblank and read
1587 * out the buggy result.
1588 *
1589 * On GEN8+ sometimes the second CRC is bonkers as well, so
1590 * don't trust that one either.
1591 */
1592 if (pipe_crc->skipped <= 0 ||
1593 (INTEL_GEN(dev_priv) >= 8 && pipe_crc->skipped == 1)) {
1594 pipe_crc->skipped++;
1595 spin_unlock(&pipe_crc->lock);
1596 return;
1597 }
1598 spin_unlock(&pipe_crc->lock);
1599
1600 drm_crtc_add_crc_entry(&crtc->base, true,
1601 drm_crtc_accurate_vblank_count(&crtc->base),
1602 crcs);
1603}
1604#else
1605static inline void
1606display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1607 enum pipe pipe,
1608 u32 crc0, u32 crc1,
1609 u32 crc2, u32 crc3,
1610 u32 crc4) {}
1611#endif
1612
1613
1614static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1615 enum pipe pipe)
1616{
1617 display_pipe_crc_irq_handler(dev_priv, pipe,
1618 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1619 0, 0, 0, 0);
1620}
1621
1622static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1623 enum pipe pipe)
1624{
1625 display_pipe_crc_irq_handler(dev_priv, pipe,
1626 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1627 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1628 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1629 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1630 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1631}
1632
1633static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
1634 enum pipe pipe)
1635{
1636 u32 res1, res2;
1637
1638 if (INTEL_GEN(dev_priv) >= 3)
1639 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1640 else
1641 res1 = 0;
1642
1643 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
1644 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1645 else
1646 res2 = 0;
1647
1648 display_pipe_crc_irq_handler(dev_priv, pipe,
1649 I915_READ(PIPE_CRC_RES_RED(pipe)),
1650 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1651 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1652 res1, res2);
1653}
1654
1655/* The RPS events need forcewake, so we add them to a work queue and mask their
1656 * IMR bits until the work is done. Other interrupts can be processed without
1657 * the work queue. */
1658void gen11_rps_irq_handler(struct intel_gt *gt, u32 pm_iir)
1659{
1660 struct drm_i915_private *i915 = gt->i915;
1661 struct intel_rps *rps = &i915->gt_pm.rps;
1662 const u32 events = i915->pm_rps_events & pm_iir;
1663
1664 lockdep_assert_held(>->irq_lock);
1665
1666 if (unlikely(!events))
1667 return;
1668
1669 gen6_gt_pm_mask_irq(gt, events);
1670
1671 if (!rps->interrupts_enabled)
1672 return;
1673
1674 rps->pm_iir |= events;
1675 schedule_work(&rps->work);
1676}
1677
1678void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
1679{
1680 struct intel_rps *rps = &dev_priv->gt_pm.rps;
1681 struct intel_gt *gt = &dev_priv->gt;
1682
1683 if (pm_iir & dev_priv->pm_rps_events) {
1684 spin_lock(>->irq_lock);
1685 gen6_gt_pm_mask_irq(gt, pm_iir & dev_priv->pm_rps_events);
1686 if (rps->interrupts_enabled) {
1687 rps->pm_iir |= pm_iir & dev_priv->pm_rps_events;
1688 schedule_work(&rps->work);
1689 }
1690 spin_unlock(>->irq_lock);
1691 }
1692
1693 if (INTEL_GEN(dev_priv) >= 8)
1694 return;
1695
1696 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
1697 intel_engine_breadcrumbs_irq(dev_priv->engine[VECS0]);
1698
1699 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1700 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
1701}
1702
1703static void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv)
1704{
1705 enum pipe pipe;
1706
1707 for_each_pipe(dev_priv, pipe) {
1708 I915_WRITE(PIPESTAT(pipe),
1709 PIPESTAT_INT_STATUS_MASK |
1710 PIPE_FIFO_UNDERRUN_STATUS);
1711
1712 dev_priv->pipestat_irq_mask[pipe] = 0;
1713 }
1714}
1715
1716static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv,
1717 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1718{
1719 int pipe;
1720
1721 spin_lock(&dev_priv->irq_lock);
1722
1723 if (!dev_priv->display_irqs_enabled) {
1724 spin_unlock(&dev_priv->irq_lock);
1725 return;
1726 }
1727
1728 for_each_pipe(dev_priv, pipe) {
1729 i915_reg_t reg;
1730 u32 status_mask, enable_mask, iir_bit = 0;
1731
1732 /*
1733 * PIPESTAT bits get signalled even when the interrupt is
1734 * disabled with the mask bits, and some of the status bits do
1735 * not generate interrupts at all (like the underrun bit). Hence
1736 * we need to be careful that we only handle what we want to
1737 * handle.
1738 */
1739
1740 /* fifo underruns are filterered in the underrun handler. */
1741 status_mask = PIPE_FIFO_UNDERRUN_STATUS;
1742
1743 switch (pipe) {
1744 case PIPE_A:
1745 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1746 break;
1747 case PIPE_B:
1748 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1749 break;
1750 case PIPE_C:
1751 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1752 break;
1753 }
1754 if (iir & iir_bit)
1755 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1756
1757 if (!status_mask)
1758 continue;
1759
1760 reg = PIPESTAT(pipe);
1761 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1762 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1763
1764 /*
1765 * Clear the PIPE*STAT regs before the IIR
1766 *
1767 * Toggle the enable bits to make sure we get an
1768 * edge in the ISR pipe event bit if we don't clear
1769 * all the enabled status bits. Otherwise the edge
1770 * triggered IIR on i965/g4x wouldn't notice that
1771 * an interrupt is still pending.
1772 */
1773 if (pipe_stats[pipe]) {
1774 I915_WRITE(reg, pipe_stats[pipe]);
1775 I915_WRITE(reg, enable_mask);
1776 }
1777 }
1778 spin_unlock(&dev_priv->irq_lock);
1779}
1780
1781static void i8xx_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1782 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1783{
1784 enum pipe pipe;
1785
1786 for_each_pipe(dev_priv, pipe) {
1787 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1788 drm_handle_vblank(&dev_priv->drm, pipe);
1789
1790 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1791 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1792
1793 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1794 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1795 }
1796}
1797
1798static void i915_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1799 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1800{
1801 bool blc_event = false;
1802 enum pipe pipe;
1803
1804 for_each_pipe(dev_priv, pipe) {
1805 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1806 drm_handle_vblank(&dev_priv->drm, pipe);
1807
1808 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1809 blc_event = true;
1810
1811 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1812 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1813
1814 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1815 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1816 }
1817
1818 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1819 intel_opregion_asle_intr(dev_priv);
1820}
1821
1822static void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1823 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1824{
1825 bool blc_event = false;
1826 enum pipe pipe;
1827
1828 for_each_pipe(dev_priv, pipe) {
1829 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1830 drm_handle_vblank(&dev_priv->drm, pipe);
1831
1832 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1833 blc_event = true;
1834
1835 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1836 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1837
1838 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1839 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1840 }
1841
1842 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1843 intel_opregion_asle_intr(dev_priv);
1844
1845 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1846 gmbus_irq_handler(dev_priv);
1847}
1848
1849static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
1850 u32 pipe_stats[I915_MAX_PIPES])
1851{
1852 enum pipe pipe;
1853
1854 for_each_pipe(dev_priv, pipe) {
1855 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1856 drm_handle_vblank(&dev_priv->drm, pipe);
1857
1858 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1859 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1860
1861 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1862 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1863 }
1864
1865 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1866 gmbus_irq_handler(dev_priv);
1867}
1868
1869static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv)
1870{
1871 u32 hotplug_status = 0, hotplug_status_mask;
1872 int i;
1873
1874 if (IS_G4X(dev_priv) ||
1875 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1876 hotplug_status_mask = HOTPLUG_INT_STATUS_G4X |
1877 DP_AUX_CHANNEL_MASK_INT_STATUS_G4X;
1878 else
1879 hotplug_status_mask = HOTPLUG_INT_STATUS_I915;
1880
1881 /*
1882 * We absolutely have to clear all the pending interrupt
1883 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1884 * interrupt bit won't have an edge, and the i965/g4x
1885 * edge triggered IIR will not notice that an interrupt
1886 * is still pending. We can't use PORT_HOTPLUG_EN to
1887 * guarantee the edge as the act of toggling the enable
1888 * bits can itself generate a new hotplug interrupt :(
1889 */
1890 for (i = 0; i < 10; i++) {
1891 u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask;
1892
1893 if (tmp == 0)
1894 return hotplug_status;
1895
1896 hotplug_status |= tmp;
1897 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1898 }
1899
1900 WARN_ONCE(1,
1901 "PORT_HOTPLUG_STAT did not clear (0x%08x)\n",
1902 I915_READ(PORT_HOTPLUG_STAT));
1903
1904 return hotplug_status;
1905}
1906
1907static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
1908 u32 hotplug_status)
1909{
1910 u32 pin_mask = 0, long_mask = 0;
1911
1912 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
1913 IS_CHERRYVIEW(dev_priv)) {
1914 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
1915
1916 if (hotplug_trigger) {
1917 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1918 hotplug_trigger, hotplug_trigger,
1919 hpd_status_g4x,
1920 i9xx_port_hotplug_long_detect);
1921
1922 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1923 }
1924
1925 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1926 dp_aux_irq_handler(dev_priv);
1927 } else {
1928 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
1929
1930 if (hotplug_trigger) {
1931 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
1932 hotplug_trigger, hotplug_trigger,
1933 hpd_status_i915,
1934 i9xx_port_hotplug_long_detect);
1935 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
1936 }
1937 }
1938}
1939
1940static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1941{
1942 struct drm_i915_private *dev_priv = arg;
1943 irqreturn_t ret = IRQ_NONE;
1944
1945 if (!intel_irqs_enabled(dev_priv))
1946 return IRQ_NONE;
1947
1948 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
1949 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1950
1951 do {
1952 u32 iir, gt_iir, pm_iir;
1953 u32 pipe_stats[I915_MAX_PIPES] = {};
1954 u32 hotplug_status = 0;
1955 u32 ier = 0;
1956
1957 gt_iir = I915_READ(GTIIR);
1958 pm_iir = I915_READ(GEN6_PMIIR);
1959 iir = I915_READ(VLV_IIR);
1960
1961 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1962 break;
1963
1964 ret = IRQ_HANDLED;
1965
1966 /*
1967 * Theory on interrupt generation, based on empirical evidence:
1968 *
1969 * x = ((VLV_IIR & VLV_IER) ||
1970 * (((GT_IIR & GT_IER) || (GEN6_PMIIR & GEN6_PMIER)) &&
1971 * (VLV_MASTER_IER & MASTER_INTERRUPT_ENABLE)));
1972 *
1973 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
1974 * Hence we clear MASTER_INTERRUPT_ENABLE and VLV_IER to
1975 * guarantee the CPU interrupt will be raised again even if we
1976 * don't end up clearing all the VLV_IIR, GT_IIR, GEN6_PMIIR
1977 * bits this time around.
1978 */
1979 I915_WRITE(VLV_MASTER_IER, 0);
1980 ier = I915_READ(VLV_IER);
1981 I915_WRITE(VLV_IER, 0);
1982
1983 if (gt_iir)
1984 I915_WRITE(GTIIR, gt_iir);
1985 if (pm_iir)
1986 I915_WRITE(GEN6_PMIIR, pm_iir);
1987
1988 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1989 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
1990
1991 /* Call regardless, as some status bits might not be
1992 * signalled in iir */
1993 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1994
1995 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1996 I915_LPE_PIPE_B_INTERRUPT))
1997 intel_lpe_audio_irq_handler(dev_priv);
1998
1999 /*
2000 * VLV_IIR is single buffered, and reflects the level
2001 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2002 */
2003 if (iir)
2004 I915_WRITE(VLV_IIR, iir);
2005
2006 I915_WRITE(VLV_IER, ier);
2007 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2008
2009 if (gt_iir)
2010 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2011 if (pm_iir)
2012 gen6_rps_irq_handler(dev_priv, pm_iir);
2013
2014 if (hotplug_status)
2015 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2016
2017 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2018 } while (0);
2019
2020 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2021
2022 return ret;
2023}
2024
2025static irqreturn_t cherryview_irq_handler(int irq, void *arg)
2026{
2027 struct drm_i915_private *dev_priv = arg;
2028 irqreturn_t ret = IRQ_NONE;
2029
2030 if (!intel_irqs_enabled(dev_priv))
2031 return IRQ_NONE;
2032
2033 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2034 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2035
2036 do {
2037 u32 master_ctl, iir;
2038 u32 pipe_stats[I915_MAX_PIPES] = {};
2039 u32 hotplug_status = 0;
2040 u32 gt_iir[4];
2041 u32 ier = 0;
2042
2043 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
2044 iir = I915_READ(VLV_IIR);
2045
2046 if (master_ctl == 0 && iir == 0)
2047 break;
2048
2049 ret = IRQ_HANDLED;
2050
2051 /*
2052 * Theory on interrupt generation, based on empirical evidence:
2053 *
2054 * x = ((VLV_IIR & VLV_IER) ||
2055 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) &&
2056 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL)));
2057 *
2058 * A CPU interrupt will only be raised when 'x' has a 0->1 edge.
2059 * Hence we clear GEN8_MASTER_IRQ_CONTROL and VLV_IER to
2060 * guarantee the CPU interrupt will be raised again even if we
2061 * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL
2062 * bits this time around.
2063 */
2064 I915_WRITE(GEN8_MASTER_IRQ, 0);
2065 ier = I915_READ(VLV_IER);
2066 I915_WRITE(VLV_IER, 0);
2067
2068 gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
2069
2070 if (iir & I915_DISPLAY_PORT_INTERRUPT)
2071 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
2072
2073 /* Call regardless, as some status bits might not be
2074 * signalled in iir */
2075 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
2076
2077 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
2078 I915_LPE_PIPE_B_INTERRUPT |
2079 I915_LPE_PIPE_C_INTERRUPT))
2080 intel_lpe_audio_irq_handler(dev_priv);
2081
2082 /*
2083 * VLV_IIR is single buffered, and reflects the level
2084 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last.
2085 */
2086 if (iir)
2087 I915_WRITE(VLV_IIR, iir);
2088
2089 I915_WRITE(VLV_IER, ier);
2090 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2091
2092 gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
2093
2094 if (hotplug_status)
2095 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
2096
2097 valleyview_pipestat_irq_handler(dev_priv, pipe_stats);
2098 } while (0);
2099
2100 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2101
2102 return ret;
2103}
2104
2105static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
2106 u32 hotplug_trigger,
2107 const u32 hpd[HPD_NUM_PINS])
2108{
2109 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2110
2111 /*
2112 * Somehow the PCH doesn't seem to really ack the interrupt to the CPU
2113 * unless we touch the hotplug register, even if hotplug_trigger is
2114 * zero. Not acking leads to "The master control interrupt lied (SDE)!"
2115 * errors.
2116 */
2117 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2118 if (!hotplug_trigger) {
2119 u32 mask = PORTA_HOTPLUG_STATUS_MASK |
2120 PORTD_HOTPLUG_STATUS_MASK |
2121 PORTC_HOTPLUG_STATUS_MASK |
2122 PORTB_HOTPLUG_STATUS_MASK;
2123 dig_hotplug_reg &= ~mask;
2124 }
2125
2126 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2127 if (!hotplug_trigger)
2128 return;
2129
2130 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2131 dig_hotplug_reg, hpd,
2132 pch_port_hotplug_long_detect);
2133
2134 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2135}
2136
2137static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2138{
2139 int pipe;
2140 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
2141
2142 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
2143
2144 if (pch_iir & SDE_AUDIO_POWER_MASK) {
2145 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
2146 SDE_AUDIO_POWER_SHIFT);
2147 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
2148 port_name(port));
2149 }
2150
2151 if (pch_iir & SDE_AUX_MASK)
2152 dp_aux_irq_handler(dev_priv);
2153
2154 if (pch_iir & SDE_GMBUS)
2155 gmbus_irq_handler(dev_priv);
2156
2157 if (pch_iir & SDE_AUDIO_HDCP_MASK)
2158 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
2159
2160 if (pch_iir & SDE_AUDIO_TRANS_MASK)
2161 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
2162
2163 if (pch_iir & SDE_POISON)
2164 DRM_ERROR("PCH poison interrupt\n");
2165
2166 if (pch_iir & SDE_FDI_MASK)
2167 for_each_pipe(dev_priv, pipe)
2168 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2169 pipe_name(pipe),
2170 I915_READ(FDI_RX_IIR(pipe)));
2171
2172 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
2173 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
2174
2175 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
2176 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
2177
2178 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
2179 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_A);
2180
2181 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
2182 intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
2183}
2184
2185static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
2186{
2187 u32 err_int = I915_READ(GEN7_ERR_INT);
2188 enum pipe pipe;
2189
2190 if (err_int & ERR_INT_POISON)
2191 DRM_ERROR("Poison interrupt\n");
2192
2193 for_each_pipe(dev_priv, pipe) {
2194 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
2195 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2196
2197 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
2198 if (IS_IVYBRIDGE(dev_priv))
2199 ivb_pipe_crc_irq_handler(dev_priv, pipe);
2200 else
2201 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2202 }
2203 }
2204
2205 I915_WRITE(GEN7_ERR_INT, err_int);
2206}
2207
2208static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
2209{
2210 u32 serr_int = I915_READ(SERR_INT);
2211 enum pipe pipe;
2212
2213 if (serr_int & SERR_INT_POISON)
2214 DRM_ERROR("PCH poison interrupt\n");
2215
2216 for_each_pipe(dev_priv, pipe)
2217 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
2218 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
2219
2220 I915_WRITE(SERR_INT, serr_int);
2221}
2222
2223static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2224{
2225 int pipe;
2226 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
2227
2228 ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
2229
2230 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
2231 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
2232 SDE_AUDIO_POWER_SHIFT_CPT);
2233 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
2234 port_name(port));
2235 }
2236
2237 if (pch_iir & SDE_AUX_MASK_CPT)
2238 dp_aux_irq_handler(dev_priv);
2239
2240 if (pch_iir & SDE_GMBUS_CPT)
2241 gmbus_irq_handler(dev_priv);
2242
2243 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
2244 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
2245
2246 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2247 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2248
2249 if (pch_iir & SDE_FDI_MASK_CPT)
2250 for_each_pipe(dev_priv, pipe)
2251 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2252 pipe_name(pipe),
2253 I915_READ(FDI_RX_IIR(pipe)));
2254
2255 if (pch_iir & SDE_ERROR_CPT)
2256 cpt_serr_int_handler(dev_priv);
2257}
2258
2259static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir,
2260 const u32 *pins)
2261{
2262 u32 ddi_hotplug_trigger;
2263 u32 tc_hotplug_trigger;
2264 u32 pin_mask = 0, long_mask = 0;
2265
2266 if (HAS_PCH_MCC(dev_priv)) {
2267 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
2268 tc_hotplug_trigger = 0;
2269 } else {
2270 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
2271 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
2272 }
2273
2274 if (ddi_hotplug_trigger) {
2275 u32 dig_hotplug_reg;
2276
2277 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2278 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2279
2280 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2281 ddi_hotplug_trigger,
2282 dig_hotplug_reg, pins,
2283 icp_ddi_port_hotplug_long_detect);
2284 }
2285
2286 if (tc_hotplug_trigger) {
2287 u32 dig_hotplug_reg;
2288
2289 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2290 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2291
2292 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2293 tc_hotplug_trigger,
2294 dig_hotplug_reg, pins,
2295 icp_tc_port_hotplug_long_detect);
2296 }
2297
2298 if (pin_mask)
2299 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2300
2301 if (pch_iir & SDE_GMBUS_ICP)
2302 gmbus_irq_handler(dev_priv);
2303}
2304
2305static void tgp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2306{
2307 u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_TGP;
2308 u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_TGP;
2309 u32 pin_mask = 0, long_mask = 0;
2310
2311 if (ddi_hotplug_trigger) {
2312 u32 dig_hotplug_reg;
2313
2314 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
2315 I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
2316
2317 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2318 ddi_hotplug_trigger,
2319 dig_hotplug_reg, hpd_tgp,
2320 tgp_ddi_port_hotplug_long_detect);
2321 }
2322
2323 if (tc_hotplug_trigger) {
2324 u32 dig_hotplug_reg;
2325
2326 dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
2327 I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
2328
2329 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2330 tc_hotplug_trigger,
2331 dig_hotplug_reg, hpd_tgp,
2332 tgp_tc_port_hotplug_long_detect);
2333 }
2334
2335 if (pin_mask)
2336 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2337
2338 if (pch_iir & SDE_GMBUS_ICP)
2339 gmbus_irq_handler(dev_priv);
2340}
2341
2342static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
2343{
2344 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
2345 ~SDE_PORTE_HOTPLUG_SPT;
2346 u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
2347 u32 pin_mask = 0, long_mask = 0;
2348
2349 if (hotplug_trigger) {
2350 u32 dig_hotplug_reg;
2351
2352 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2353 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2354
2355 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2356 hotplug_trigger, dig_hotplug_reg, hpd_spt,
2357 spt_port_hotplug_long_detect);
2358 }
2359
2360 if (hotplug2_trigger) {
2361 u32 dig_hotplug_reg;
2362
2363 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
2364 I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
2365
2366 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
2367 hotplug2_trigger, dig_hotplug_reg, hpd_spt,
2368 spt_port_hotplug2_long_detect);
2369 }
2370
2371 if (pin_mask)
2372 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2373
2374 if (pch_iir & SDE_GMBUS_CPT)
2375 gmbus_irq_handler(dev_priv);
2376}
2377
2378static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
2379 u32 hotplug_trigger,
2380 const u32 hpd[HPD_NUM_PINS])
2381{
2382 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2383
2384 dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
2385 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
2386
2387 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2388 dig_hotplug_reg, hpd,
2389 ilk_port_hotplug_long_detect);
2390
2391 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2392}
2393
2394static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
2395 u32 de_iir)
2396{
2397 enum pipe pipe;
2398 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
2399
2400 if (hotplug_trigger)
2401 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
2402
2403 if (de_iir & DE_AUX_CHANNEL_A)
2404 dp_aux_irq_handler(dev_priv);
2405
2406 if (de_iir & DE_GSE)
2407 intel_opregion_asle_intr(dev_priv);
2408
2409 if (de_iir & DE_POISON)
2410 DRM_ERROR("Poison interrupt\n");
2411
2412 for_each_pipe(dev_priv, pipe) {
2413 if (de_iir & DE_PIPE_VBLANK(pipe))
2414 drm_handle_vblank(&dev_priv->drm, pipe);
2415
2416 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
2417 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2418
2419 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2420 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
2421 }
2422
2423 /* check event from PCH */
2424 if (de_iir & DE_PCH_EVENT) {
2425 u32 pch_iir = I915_READ(SDEIIR);
2426
2427 if (HAS_PCH_CPT(dev_priv))
2428 cpt_irq_handler(dev_priv, pch_iir);
2429 else
2430 ibx_irq_handler(dev_priv, pch_iir);
2431
2432 /* should clear PCH hotplug event before clear CPU irq */
2433 I915_WRITE(SDEIIR, pch_iir);
2434 }
2435
2436 if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
2437 ironlake_rps_change_irq_handler(dev_priv);
2438}
2439
2440static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
2441 u32 de_iir)
2442{
2443 enum pipe pipe;
2444 u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
2445
2446 if (hotplug_trigger)
2447 ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
2448
2449 if (de_iir & DE_ERR_INT_IVB)
2450 ivb_err_int_handler(dev_priv);
2451
2452 if (de_iir & DE_EDP_PSR_INT_HSW) {
2453 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2454
2455 intel_psr_irq_handler(dev_priv, psr_iir);
2456 I915_WRITE(EDP_PSR_IIR, psr_iir);
2457 }
2458
2459 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2460 dp_aux_irq_handler(dev_priv);
2461
2462 if (de_iir & DE_GSE_IVB)
2463 intel_opregion_asle_intr(dev_priv);
2464
2465 for_each_pipe(dev_priv, pipe) {
2466 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2467 drm_handle_vblank(&dev_priv->drm, pipe);
2468 }
2469
2470 /* check event from PCH */
2471 if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
2472 u32 pch_iir = I915_READ(SDEIIR);
2473
2474 cpt_irq_handler(dev_priv, pch_iir);
2475
2476 /* clear PCH hotplug event before clear CPU irq */
2477 I915_WRITE(SDEIIR, pch_iir);
2478 }
2479}
2480
2481/*
2482 * To handle irqs with the minimum potential races with fresh interrupts, we:
2483 * 1 - Disable Master Interrupt Control.
2484 * 2 - Find the source(s) of the interrupt.
2485 * 3 - Clear the Interrupt Identity bits (IIR).
2486 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2487 * 5 - Re-enable Master Interrupt Control.
2488 */
2489static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2490{
2491 struct drm_i915_private *dev_priv = arg;
2492 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2493 irqreturn_t ret = IRQ_NONE;
2494
2495 if (!intel_irqs_enabled(dev_priv))
2496 return IRQ_NONE;
2497
2498 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2499 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2500
2501 /* disable master interrupt before clearing iir */
2502 de_ier = I915_READ(DEIER);
2503 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
2504
2505 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2506 * interrupts will will be stored on its back queue, and then we'll be
2507 * able to process them after we restore SDEIER (as soon as we restore
2508 * it, we'll get an interrupt if SDEIIR still has something to process
2509 * due to its back queue). */
2510 if (!HAS_PCH_NOP(dev_priv)) {
2511 sde_ier = I915_READ(SDEIER);
2512 I915_WRITE(SDEIER, 0);
2513 }
2514
2515 /* Find, clear, then process each source of interrupt */
2516
2517 gt_iir = I915_READ(GTIIR);
2518 if (gt_iir) {
2519 I915_WRITE(GTIIR, gt_iir);
2520 ret = IRQ_HANDLED;
2521 if (INTEL_GEN(dev_priv) >= 6)
2522 gen6_gt_irq_handler(&dev_priv->gt, gt_iir);
2523 else
2524 gen5_gt_irq_handler(&dev_priv->gt, gt_iir);
2525 }
2526
2527 de_iir = I915_READ(DEIIR);
2528 if (de_iir) {
2529 I915_WRITE(DEIIR, de_iir);
2530 ret = IRQ_HANDLED;
2531 if (INTEL_GEN(dev_priv) >= 7)
2532 ivb_display_irq_handler(dev_priv, de_iir);
2533 else
2534 ilk_display_irq_handler(dev_priv, de_iir);
2535 }
2536
2537 if (INTEL_GEN(dev_priv) >= 6) {
2538 u32 pm_iir = I915_READ(GEN6_PMIIR);
2539 if (pm_iir) {
2540 I915_WRITE(GEN6_PMIIR, pm_iir);
2541 ret = IRQ_HANDLED;
2542 gen6_rps_irq_handler(dev_priv, pm_iir);
2543 }
2544 }
2545
2546 I915_WRITE(DEIER, de_ier);
2547 if (!HAS_PCH_NOP(dev_priv))
2548 I915_WRITE(SDEIER, sde_ier);
2549
2550 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2551 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2552
2553 return ret;
2554}
2555
2556static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
2557 u32 hotplug_trigger,
2558 const u32 hpd[HPD_NUM_PINS])
2559{
2560 u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
2561
2562 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
2563 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
2564
2565 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
2566 dig_hotplug_reg, hpd,
2567 bxt_port_hotplug_long_detect);
2568
2569 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2570}
2571
2572static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2573{
2574 u32 pin_mask = 0, long_mask = 0;
2575 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2576 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2577 long_pulse_detect_func long_pulse_detect;
2578 const u32 *hpd;
2579
2580 if (INTEL_GEN(dev_priv) >= 12) {
2581 long_pulse_detect = gen12_port_hotplug_long_detect;
2582 hpd = hpd_gen12;
2583 } else {
2584 long_pulse_detect = gen11_port_hotplug_long_detect;
2585 hpd = hpd_gen11;
2586 }
2587
2588 if (trigger_tc) {
2589 u32 dig_hotplug_reg;
2590
2591 dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
2592 I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
2593
2594 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
2595 dig_hotplug_reg, hpd, long_pulse_detect);
2596 }
2597
2598 if (trigger_tbt) {
2599 u32 dig_hotplug_reg;
2600
2601 dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
2602 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
2603
2604 intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
2605 dig_hotplug_reg, hpd, long_pulse_detect);
2606 }
2607
2608 if (pin_mask)
2609 intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
2610 else
2611 DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
2612}
2613
2614static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
2615{
2616 u32 mask;
2617
2618 if (INTEL_GEN(dev_priv) >= 12)
2619 /* TODO: Add AUX entries for USBC */
2620 return TGL_DE_PORT_AUX_DDIA |
2621 TGL_DE_PORT_AUX_DDIB |
2622 TGL_DE_PORT_AUX_DDIC;
2623
2624 mask = GEN8_AUX_CHANNEL_A;
2625 if (INTEL_GEN(dev_priv) >= 9)
2626 mask |= GEN9_AUX_CHANNEL_B |
2627 GEN9_AUX_CHANNEL_C |
2628 GEN9_AUX_CHANNEL_D;
2629
2630 if (IS_CNL_WITH_PORT_F(dev_priv) || IS_GEN(dev_priv, 11))
2631 mask |= CNL_AUX_CHANNEL_F;
2632
2633 if (IS_GEN(dev_priv, 11))
2634 mask |= ICL_AUX_CHANNEL_E;
2635
2636 return mask;
2637}
2638
2639static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
2640{
2641 if (INTEL_GEN(dev_priv) >= 9)
2642 return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2643 else
2644 return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2645}
2646
2647static void
2648gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2649{
2650 bool found = false;
2651
2652 if (iir & GEN8_DE_MISC_GSE) {
2653 intel_opregion_asle_intr(dev_priv);
2654 found = true;
2655 }
2656
2657 if (iir & GEN8_DE_EDP_PSR) {
2658 u32 psr_iir = I915_READ(EDP_PSR_IIR);
2659
2660 intel_psr_irq_handler(dev_priv, psr_iir);
2661 I915_WRITE(EDP_PSR_IIR, psr_iir);
2662 found = true;
2663 }
2664
2665 if (!found)
2666 DRM_ERROR("Unexpected DE Misc interrupt\n");
2667}
2668
2669static irqreturn_t
2670gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
2671{
2672 irqreturn_t ret = IRQ_NONE;
2673 u32 iir;
2674 enum pipe pipe;
2675
2676 if (master_ctl & GEN8_DE_MISC_IRQ) {
2677 iir = I915_READ(GEN8_DE_MISC_IIR);
2678 if (iir) {
2679 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2680 ret = IRQ_HANDLED;
2681 gen8_de_misc_irq_handler(dev_priv, iir);
2682 } else {
2683 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
2684 }
2685 }
2686
2687 if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
2688 iir = I915_READ(GEN11_DE_HPD_IIR);
2689 if (iir) {
2690 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2691 ret = IRQ_HANDLED;
2692 gen11_hpd_irq_handler(dev_priv, iir);
2693 } else {
2694 DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
2695 }
2696 }
2697
2698 if (master_ctl & GEN8_DE_PORT_IRQ) {
2699 iir = I915_READ(GEN8_DE_PORT_IIR);
2700 if (iir) {
2701 u32 tmp_mask;
2702 bool found = false;
2703
2704 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2705 ret = IRQ_HANDLED;
2706
2707 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2708 dp_aux_irq_handler(dev_priv);
2709 found = true;
2710 }
2711
2712 if (IS_GEN9_LP(dev_priv)) {
2713 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2714 if (tmp_mask) {
2715 bxt_hpd_irq_handler(dev_priv, tmp_mask,
2716 hpd_bxt);
2717 found = true;
2718 }
2719 } else if (IS_BROADWELL(dev_priv)) {
2720 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2721 if (tmp_mask) {
2722 ilk_hpd_irq_handler(dev_priv,
2723 tmp_mask, hpd_bdw);
2724 found = true;
2725 }
2726 }
2727
2728 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2729 gmbus_irq_handler(dev_priv);
2730 found = true;
2731 }
2732
2733 if (!found)
2734 DRM_ERROR("Unexpected DE Port interrupt\n");
2735 }
2736 else
2737 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
2738 }
2739
2740 for_each_pipe(dev_priv, pipe) {
2741 u32 fault_errors;
2742
2743 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2744 continue;
2745
2746 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2747 if (!iir) {
2748 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2749 continue;
2750 }
2751
2752 ret = IRQ_HANDLED;
2753 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2754
2755 if (iir & GEN8_PIPE_VBLANK)
2756 drm_handle_vblank(&dev_priv->drm, pipe);
2757
2758 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2759 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2760
2761 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2762 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2763
2764 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2765 if (fault_errors)
2766 DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
2767 pipe_name(pipe),
2768 fault_errors);
2769 }
2770
2771 if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
2772 master_ctl & GEN8_DE_PCH_IRQ) {
2773 /*
2774 * FIXME(BDW): Assume for now that the new interrupt handling
2775 * scheme also closed the SDE interrupt handling race we've seen
2776 * on older pch-split platforms. But this needs testing.
2777 */
2778 iir = I915_READ(SDEIIR);
2779 if (iir) {
2780 I915_WRITE(SDEIIR, iir);
2781 ret = IRQ_HANDLED;
2782
2783 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
2784 tgp_irq_handler(dev_priv, iir);
2785 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MCC)
2786 icp_irq_handler(dev_priv, iir, hpd_mcc);
2787 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2788 icp_irq_handler(dev_priv, iir, hpd_icp);
2789 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
2790 spt_irq_handler(dev_priv, iir);
2791 else
2792 cpt_irq_handler(dev_priv, iir);
2793 } else {
2794 /*
2795 * Like on previous PCH there seems to be something
2796 * fishy going on with forwarding PCH interrupts.
2797 */
2798 DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
2799 }
2800 }
2801
2802 return ret;
2803}
2804
2805static inline u32 gen8_master_intr_disable(void __iomem * const regs)
2806{
2807 raw_reg_write(regs, GEN8_MASTER_IRQ, 0);
2808
2809 /*
2810 * Now with master disabled, get a sample of level indications
2811 * for this interrupt. Indications will be cleared on related acks.
2812 * New indications can and will light up during processing,
2813 * and will generate new interrupt after enabling master.
2814 */
2815 return raw_reg_read(regs, GEN8_MASTER_IRQ);
2816}
2817
2818static inline void gen8_master_intr_enable(void __iomem * const regs)
2819{
2820 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2821}
2822
2823static irqreturn_t gen8_irq_handler(int irq, void *arg)
2824{
2825 struct drm_i915_private *dev_priv = arg;
2826 void __iomem * const regs = dev_priv->uncore.regs;
2827 u32 master_ctl;
2828 u32 gt_iir[4];
2829
2830 if (!intel_irqs_enabled(dev_priv))
2831 return IRQ_NONE;
2832
2833 master_ctl = gen8_master_intr_disable(regs);
2834 if (!master_ctl) {
2835 gen8_master_intr_enable(regs);
2836 return IRQ_NONE;
2837 }
2838
2839 /* Find, clear, then process each source of interrupt */
2840 gen8_gt_irq_ack(&dev_priv->gt, master_ctl, gt_iir);
2841
2842 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2843 if (master_ctl & ~GEN8_GT_IRQS) {
2844 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2845 gen8_de_irq_handler(dev_priv, master_ctl);
2846 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
2847 }
2848
2849 gen8_master_intr_enable(regs);
2850
2851 gen8_gt_irq_handler(&dev_priv->gt, master_ctl, gt_iir);
2852
2853 return IRQ_HANDLED;
2854}
2855
2856static u32
2857gen11_gu_misc_irq_ack(struct intel_gt *gt, const u32 master_ctl)
2858{
2859 void __iomem * const regs = gt->uncore->regs;
2860 u32 iir;
2861
2862 if (!(master_ctl & GEN11_GU_MISC_IRQ))
2863 return 0;
2864
2865 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2866 if (likely(iir))
2867 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2868
2869 return iir;
2870}
2871
2872static void
2873gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2874{
2875 if (iir & GEN11_GU_MISC_GSE)
2876 intel_opregion_asle_intr(gt->i915);
2877}
2878
2879static inline u32 gen11_master_intr_disable(void __iomem * const regs)
2880{
2881 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, 0);
2882
2883 /*
2884 * Now with master disabled, get a sample of level indications
2885 * for this interrupt. Indications will be cleared on related acks.
2886 * New indications can and will light up during processing,
2887 * and will generate new interrupt after enabling master.
2888 */
2889 return raw_reg_read(regs, GEN11_GFX_MSTR_IRQ);
2890}
2891
2892static inline void gen11_master_intr_enable(void __iomem * const regs)
2893{
2894 raw_reg_write(regs, GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ);
2895}
2896
2897static irqreturn_t gen11_irq_handler(int irq, void *arg)
2898{
2899 struct drm_i915_private * const i915 = arg;
2900 void __iomem * const regs = i915->uncore.regs;
2901 struct intel_gt *gt = &i915->gt;
2902 u32 master_ctl;
2903 u32 gu_misc_iir;
2904
2905 if (!intel_irqs_enabled(i915))
2906 return IRQ_NONE;
2907
2908 master_ctl = gen11_master_intr_disable(regs);
2909 if (!master_ctl) {
2910 gen11_master_intr_enable(regs);
2911 return IRQ_NONE;
2912 }
2913
2914 /* Find, clear, then process each source of interrupt. */
2915 gen11_gt_irq_handler(gt, master_ctl);
2916
2917 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
2918 if (master_ctl & GEN11_DISPLAY_IRQ) {
2919 const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
2920
2921 disable_rpm_wakeref_asserts(&i915->runtime_pm);
2922 /*
2923 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
2924 * for the display related bits.
2925 */
2926 gen8_de_irq_handler(i915, disp_ctl);
2927 enable_rpm_wakeref_asserts(&i915->runtime_pm);
2928 }
2929
2930 gu_misc_iir = gen11_gu_misc_irq_ack(gt, master_ctl);
2931
2932 gen11_master_intr_enable(regs);
2933
2934 gen11_gu_misc_irq_handler(gt, gu_misc_iir);
2935
2936 return IRQ_HANDLED;
2937}
2938
2939/* Called from drm generic code, passed 'crtc' which
2940 * we use as a pipe index
2941 */
2942int i8xx_enable_vblank(struct drm_crtc *crtc)
2943{
2944 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2945 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2946 unsigned long irqflags;
2947
2948 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2949 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2950 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2951
2952 return 0;
2953}
2954
2955int i945gm_enable_vblank(struct drm_crtc *crtc)
2956{
2957 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2958
2959 if (dev_priv->i945gm_vblank.enabled++ == 0)
2960 schedule_work(&dev_priv->i945gm_vblank.work);
2961
2962 return i8xx_enable_vblank(crtc);
2963}
2964
2965int i965_enable_vblank(struct drm_crtc *crtc)
2966{
2967 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2968 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2969 unsigned long irqflags;
2970
2971 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2972 i915_enable_pipestat(dev_priv, pipe,
2973 PIPE_START_VBLANK_INTERRUPT_STATUS);
2974 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2975
2976 return 0;
2977}
2978
2979int ilk_enable_vblank(struct drm_crtc *crtc)
2980{
2981 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
2982 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2983 unsigned long irqflags;
2984 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
2985 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2986
2987 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2988 ilk_enable_display_irq(dev_priv, bit);
2989 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2990
2991 /* Even though there is no DMC, frame counter can get stuck when
2992 * PSR is active as no frames are generated.
2993 */
2994 if (HAS_PSR(dev_priv))
2995 drm_crtc_vblank_restore(crtc);
2996
2997 return 0;
2998}
2999
3000int bdw_enable_vblank(struct drm_crtc *crtc)
3001{
3002 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3003 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3004 unsigned long irqflags;
3005
3006 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3007 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3008 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3009
3010 /* Even if there is no DMC, frame counter can get stuck when
3011 * PSR is active as no frames are generated, so check only for PSR.
3012 */
3013 if (HAS_PSR(dev_priv))
3014 drm_crtc_vblank_restore(crtc);
3015
3016 return 0;
3017}
3018
3019/* Called from drm generic code, passed 'crtc' which
3020 * we use as a pipe index
3021 */
3022void i8xx_disable_vblank(struct drm_crtc *crtc)
3023{
3024 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3025 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3026 unsigned long irqflags;
3027
3028 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3029 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
3030 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3031}
3032
3033void i945gm_disable_vblank(struct drm_crtc *crtc)
3034{
3035 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3036
3037 i8xx_disable_vblank(crtc);
3038
3039 if (--dev_priv->i945gm_vblank.enabled == 0)
3040 schedule_work(&dev_priv->i945gm_vblank.work);
3041}
3042
3043void i965_disable_vblank(struct drm_crtc *crtc)
3044{
3045 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3047 unsigned long irqflags;
3048
3049 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3050 i915_disable_pipestat(dev_priv, pipe,
3051 PIPE_START_VBLANK_INTERRUPT_STATUS);
3052 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3053}
3054
3055void ilk_disable_vblank(struct drm_crtc *crtc)
3056{
3057 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3058 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3059 unsigned long irqflags;
3060 u32 bit = INTEL_GEN(dev_priv) >= 7 ?
3061 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
3062
3063 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3064 ilk_disable_display_irq(dev_priv, bit);
3065 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3066}
3067
3068void bdw_disable_vblank(struct drm_crtc *crtc)
3069{
3070 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3071 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3072 unsigned long irqflags;
3073
3074 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3075 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
3076 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3077}
3078
3079static void i945gm_vblank_work_func(struct work_struct *work)
3080{
3081 struct drm_i915_private *dev_priv =
3082 container_of(work, struct drm_i915_private, i945gm_vblank.work);
3083
3084 /*
3085 * Vblank interrupts fail to wake up the device from C3,
3086 * hence we want to prevent C3 usage while vblank interrupts
3087 * are enabled.
3088 */
3089 pm_qos_update_request(&dev_priv->i945gm_vblank.pm_qos,
3090 READ_ONCE(dev_priv->i945gm_vblank.enabled) ?
3091 dev_priv->i945gm_vblank.c3_disable_latency :
3092 PM_QOS_DEFAULT_VALUE);
3093}
3094
3095static int cstate_disable_latency(const char *name)
3096{
3097 const struct cpuidle_driver *drv;
3098 int i;
3099
3100 drv = cpuidle_get_driver();
3101 if (!drv)
3102 return 0;
3103
3104 for (i = 0; i < drv->state_count; i++) {
3105 const struct cpuidle_state *state = &drv->states[i];
3106
3107 if (!strcmp(state->name, name))
3108 return state->exit_latency ?
3109 state->exit_latency - 1 : 0;
3110 }
3111
3112 return 0;
3113}
3114
3115static void i945gm_vblank_work_init(struct drm_i915_private *dev_priv)
3116{
3117 INIT_WORK(&dev_priv->i945gm_vblank.work,
3118 i945gm_vblank_work_func);
3119
3120 dev_priv->i945gm_vblank.c3_disable_latency =
3121 cstate_disable_latency("C3");
3122 pm_qos_add_request(&dev_priv->i945gm_vblank.pm_qos,
3123 PM_QOS_CPU_DMA_LATENCY,
3124 PM_QOS_DEFAULT_VALUE);
3125}
3126
3127static void i945gm_vblank_work_fini(struct drm_i915_private *dev_priv)
3128{
3129 cancel_work_sync(&dev_priv->i945gm_vblank.work);
3130 pm_qos_remove_request(&dev_priv->i945gm_vblank.pm_qos);
3131}
3132
3133static void ibx_irq_reset(struct drm_i915_private *dev_priv)
3134{
3135 struct intel_uncore *uncore = &dev_priv->uncore;
3136
3137 if (HAS_PCH_NOP(dev_priv))
3138 return;
3139
3140 GEN3_IRQ_RESET(uncore, SDE);
3141
3142 if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3143 I915_WRITE(SERR_INT, 0xffffffff);
3144}
3145
3146/*
3147 * SDEIER is also touched by the interrupt handler to work around missed PCH
3148 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3149 * instead we unconditionally enable all PCH interrupt sources here, but then
3150 * only unmask them as needed with SDEIMR.
3151 *
3152 * This function needs to be called before interrupts are enabled.
3153 */
3154static void ibx_irq_pre_postinstall(struct drm_i915_private *dev_priv)
3155{
3156 if (HAS_PCH_NOP(dev_priv))
3157 return;
3158
3159 WARN_ON(I915_READ(SDEIER) != 0);
3160 I915_WRITE(SDEIER, 0xffffffff);
3161 POSTING_READ(SDEIER);
3162}
3163
3164static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3165{
3166 struct intel_uncore *uncore = &dev_priv->uncore;
3167
3168 if (IS_CHERRYVIEW(dev_priv))
3169 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3170 else
3171 intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK);
3172
3173 i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0);
3174 intel_uncore_write(uncore, PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3175
3176 i9xx_pipestat_irq_reset(dev_priv);
3177
3178 GEN3_IRQ_RESET(uncore, VLV_);
3179 dev_priv->irq_mask = ~0u;
3180}
3181
3182static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
3183{
3184 struct intel_uncore *uncore = &dev_priv->uncore;
3185
3186 u32 pipestat_mask;
3187 u32 enable_mask;
3188 enum pipe pipe;
3189
3190 pipestat_mask = PIPE_CRC_DONE_INTERRUPT_STATUS;
3191
3192 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3193 for_each_pipe(dev_priv, pipe)
3194 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
3195
3196 enable_mask = I915_DISPLAY_PORT_INTERRUPT |
3197 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3198 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3199 I915_LPE_PIPE_A_INTERRUPT |
3200 I915_LPE_PIPE_B_INTERRUPT;
3201
3202 if (IS_CHERRYVIEW(dev_priv))
3203 enable_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT |
3204 I915_LPE_PIPE_C_INTERRUPT;
3205
3206 WARN_ON(dev_priv->irq_mask != ~0u);
3207
3208 dev_priv->irq_mask = ~enable_mask;
3209
3210 GEN3_IRQ_INIT(uncore, VLV_, dev_priv->irq_mask, enable_mask);
3211}
3212
3213/* drm_dma.h hooks
3214*/
3215static void ironlake_irq_reset(struct drm_i915_private *dev_priv)
3216{
3217 struct intel_uncore *uncore = &dev_priv->uncore;
3218
3219 GEN3_IRQ_RESET(uncore, DE);
3220 if (IS_GEN(dev_priv, 7))
3221 intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
3222
3223 if (IS_HASWELL(dev_priv)) {
3224 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3225 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3226 }
3227
3228 gen5_gt_irq_reset(&dev_priv->gt);
3229
3230 ibx_irq_reset(dev_priv);
3231}
3232
3233static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
3234{
3235 I915_WRITE(VLV_MASTER_IER, 0);
3236 POSTING_READ(VLV_MASTER_IER);
3237
3238 gen5_gt_irq_reset(&dev_priv->gt);
3239
3240 spin_lock_irq(&dev_priv->irq_lock);
3241 if (dev_priv->display_irqs_enabled)
3242 vlv_display_irq_reset(dev_priv);
3243 spin_unlock_irq(&dev_priv->irq_lock);
3244}
3245
3246static void gen8_irq_reset(struct drm_i915_private *dev_priv)
3247{
3248 struct intel_uncore *uncore = &dev_priv->uncore;
3249 int pipe;
3250
3251 gen8_master_intr_disable(dev_priv->uncore.regs);
3252
3253 gen8_gt_irq_reset(&dev_priv->gt);
3254
3255 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3256 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3257
3258 for_each_pipe(dev_priv, pipe)
3259 if (intel_display_power_is_enabled(dev_priv,
3260 POWER_DOMAIN_PIPE(pipe)))
3261 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3262
3263 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3264 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3265 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3266
3267 if (HAS_PCH_SPLIT(dev_priv))
3268 ibx_irq_reset(dev_priv);
3269}
3270
3271static void gen11_irq_reset(struct drm_i915_private *dev_priv)
3272{
3273 struct intel_uncore *uncore = &dev_priv->uncore;
3274 int pipe;
3275
3276 gen11_master_intr_disable(dev_priv->uncore.regs);
3277
3278 gen11_gt_irq_reset(&dev_priv->gt);
3279
3280 intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
3281
3282 intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
3283 intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
3284
3285 for_each_pipe(dev_priv, pipe)
3286 if (intel_display_power_is_enabled(dev_priv,
3287 POWER_DOMAIN_PIPE(pipe)))
3288 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3289
3290 GEN3_IRQ_RESET(uncore, GEN8_DE_PORT_);
3291 GEN3_IRQ_RESET(uncore, GEN8_DE_MISC_);
3292 GEN3_IRQ_RESET(uncore, GEN11_DE_HPD_);
3293 GEN3_IRQ_RESET(uncore, GEN11_GU_MISC_);
3294 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3295
3296 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3297 GEN3_IRQ_RESET(uncore, SDE);
3298}
3299
3300void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3301 u8 pipe_mask)
3302{
3303 struct intel_uncore *uncore = &dev_priv->uncore;
3304
3305 u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
3306 enum pipe pipe;
3307
3308 spin_lock_irq(&dev_priv->irq_lock);
3309
3310 if (!intel_irqs_enabled(dev_priv)) {
3311 spin_unlock_irq(&dev_priv->irq_lock);
3312 return;
3313 }
3314
3315 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3316 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3317 dev_priv->de_irq_mask[pipe],
3318 ~dev_priv->de_irq_mask[pipe] | extra_ier);
3319
3320 spin_unlock_irq(&dev_priv->irq_lock);
3321}
3322
3323void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
3324 u8 pipe_mask)
3325{
3326 struct intel_uncore *uncore = &dev_priv->uncore;
3327 enum pipe pipe;
3328
3329 spin_lock_irq(&dev_priv->irq_lock);
3330
3331 if (!intel_irqs_enabled(dev_priv)) {
3332 spin_unlock_irq(&dev_priv->irq_lock);
3333 return;
3334 }
3335
3336 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
3337 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3338
3339 spin_unlock_irq(&dev_priv->irq_lock);
3340
3341 /* make sure we're done processing display irqs */
3342 intel_synchronize_irq(dev_priv);
3343}
3344
3345static void cherryview_irq_reset(struct drm_i915_private *dev_priv)
3346{
3347 struct intel_uncore *uncore = &dev_priv->uncore;
3348
3349 I915_WRITE(GEN8_MASTER_IRQ, 0);
3350 POSTING_READ(GEN8_MASTER_IRQ);
3351
3352 gen8_gt_irq_reset(&dev_priv->gt);
3353
3354 GEN3_IRQ_RESET(uncore, GEN8_PCU_);
3355
3356 spin_lock_irq(&dev_priv->irq_lock);
3357 if (dev_priv->display_irqs_enabled)
3358 vlv_display_irq_reset(dev_priv);
3359 spin_unlock_irq(&dev_priv->irq_lock);
3360}
3361
3362static u32 intel_hpd_enabled_irqs(struct drm_i915_private *dev_priv,
3363 const u32 hpd[HPD_NUM_PINS])
3364{
3365 struct intel_encoder *encoder;
3366 u32 enabled_irqs = 0;
3367
3368 for_each_intel_encoder(&dev_priv->drm, encoder)
3369 if (dev_priv->hotplug.stats[encoder->hpd_pin].state == HPD_ENABLED)
3370 enabled_irqs |= hpd[encoder->hpd_pin];
3371
3372 return enabled_irqs;
3373}
3374
3375static void ibx_hpd_detection_setup(struct drm_i915_private *dev_priv)
3376{
3377 u32 hotplug;
3378
3379 /*
3380 * Enable digital hotplug on the PCH, and configure the DP short pulse
3381 * duration to 2ms (which is the minimum in the Display Port spec).
3382 * The pulse duration bits are reserved on LPT+.
3383 */
3384 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3385 hotplug &= ~(PORTB_PULSE_DURATION_MASK |
3386 PORTC_PULSE_DURATION_MASK |
3387 PORTD_PULSE_DURATION_MASK);
3388 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3389 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3390 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3391 /*
3392 * When CPU and PCH are on the same package, port A
3393 * HPD must be enabled in both north and south.
3394 */
3395 if (HAS_PCH_LPT_LP(dev_priv))
3396 hotplug |= PORTA_HOTPLUG_ENABLE;
3397 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3398}
3399
3400static void ibx_hpd_irq_setup(struct drm_i915_private *dev_priv)
3401{
3402 u32 hotplug_irqs, enabled_irqs;
3403
3404 if (HAS_PCH_IBX(dev_priv)) {
3405 hotplug_irqs = SDE_HOTPLUG_MASK;
3406 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ibx);
3407 } else {
3408 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
3409 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_cpt);
3410 }
3411
3412 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3413
3414 ibx_hpd_detection_setup(dev_priv);
3415}
3416
3417static void icp_hpd_detection_setup(struct drm_i915_private *dev_priv,
3418 u32 ddi_hotplug_enable_mask,
3419 u32 tc_hotplug_enable_mask)
3420{
3421 u32 hotplug;
3422
3423 hotplug = I915_READ(SHOTPLUG_CTL_DDI);
3424 hotplug |= ddi_hotplug_enable_mask;
3425 I915_WRITE(SHOTPLUG_CTL_DDI, hotplug);
3426
3427 if (tc_hotplug_enable_mask) {
3428 hotplug = I915_READ(SHOTPLUG_CTL_TC);
3429 hotplug |= tc_hotplug_enable_mask;
3430 I915_WRITE(SHOTPLUG_CTL_TC, hotplug);
3431 }
3432}
3433
3434static void icp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3435{
3436 u32 hotplug_irqs, enabled_irqs;
3437
3438 hotplug_irqs = SDE_DDI_MASK_ICP | SDE_TC_MASK_ICP;
3439 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_icp);
3440
3441 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3442
3443 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3444 ICP_TC_HPD_ENABLE_MASK);
3445}
3446
3447static void mcc_hpd_irq_setup(struct drm_i915_private *dev_priv)
3448{
3449 u32 hotplug_irqs, enabled_irqs;
3450
3451 hotplug_irqs = SDE_DDI_MASK_TGP;
3452 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_mcc);
3453
3454 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3455
3456 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3457}
3458
3459static void tgp_hpd_irq_setup(struct drm_i915_private *dev_priv)
3460{
3461 u32 hotplug_irqs, enabled_irqs;
3462
3463 hotplug_irqs = SDE_DDI_MASK_TGP | SDE_TC_MASK_TGP;
3464 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_tgp);
3465
3466 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3467
3468 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3469 TGP_TC_HPD_ENABLE_MASK);
3470}
3471
3472static void gen11_hpd_detection_setup(struct drm_i915_private *dev_priv)
3473{
3474 u32 hotplug;
3475
3476 hotplug = I915_READ(GEN11_TC_HOTPLUG_CTL);
3477 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3478 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3479 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3480 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3481 I915_WRITE(GEN11_TC_HOTPLUG_CTL, hotplug);
3482
3483 hotplug = I915_READ(GEN11_TBT_HOTPLUG_CTL);
3484 hotplug |= GEN11_HOTPLUG_CTL_ENABLE(PORT_TC1) |
3485 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC2) |
3486 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC3) |
3487 GEN11_HOTPLUG_CTL_ENABLE(PORT_TC4);
3488 I915_WRITE(GEN11_TBT_HOTPLUG_CTL, hotplug);
3489}
3490
3491static void gen11_hpd_irq_setup(struct drm_i915_private *dev_priv)
3492{
3493 u32 hotplug_irqs, enabled_irqs;
3494 const u32 *hpd;
3495 u32 val;
3496
3497 hpd = INTEL_GEN(dev_priv) >= 12 ? hpd_gen12 : hpd_gen11;
3498 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd);
3499 hotplug_irqs = GEN11_DE_TC_HOTPLUG_MASK | GEN11_DE_TBT_HOTPLUG_MASK;
3500
3501 val = I915_READ(GEN11_DE_HPD_IMR);
3502 val &= ~hotplug_irqs;
3503 I915_WRITE(GEN11_DE_HPD_IMR, val);
3504 POSTING_READ(GEN11_DE_HPD_IMR);
3505
3506 gen11_hpd_detection_setup(dev_priv);
3507
3508 if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP)
3509 tgp_hpd_irq_setup(dev_priv);
3510 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3511 icp_hpd_irq_setup(dev_priv);
3512}
3513
3514static void spt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3515{
3516 u32 val, hotplug;
3517
3518 /* Display WA #1179 WaHardHangonHotPlug: cnp */
3519 if (HAS_PCH_CNP(dev_priv)) {
3520 val = I915_READ(SOUTH_CHICKEN1);
3521 val &= ~CHASSIS_CLK_REQ_DURATION_MASK;
3522 val |= CHASSIS_CLK_REQ_DURATION(0xf);
3523 I915_WRITE(SOUTH_CHICKEN1, val);
3524 }
3525
3526 /* Enable digital hotplug on the PCH */
3527 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3528 hotplug |= PORTA_HOTPLUG_ENABLE |
3529 PORTB_HOTPLUG_ENABLE |
3530 PORTC_HOTPLUG_ENABLE |
3531 PORTD_HOTPLUG_ENABLE;
3532 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3533
3534 hotplug = I915_READ(PCH_PORT_HOTPLUG2);
3535 hotplug |= PORTE_HOTPLUG_ENABLE;
3536 I915_WRITE(PCH_PORT_HOTPLUG2, hotplug);
3537}
3538
3539static void spt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3540{
3541 u32 hotplug_irqs, enabled_irqs;
3542
3543 hotplug_irqs = SDE_HOTPLUG_MASK_SPT;
3544 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_spt);
3545
3546 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
3547
3548 spt_hpd_detection_setup(dev_priv);
3549}
3550
3551static void ilk_hpd_detection_setup(struct drm_i915_private *dev_priv)
3552{
3553 u32 hotplug;
3554
3555 /*
3556 * Enable digital hotplug on the CPU, and configure the DP short pulse
3557 * duration to 2ms (which is the minimum in the Display Port spec)
3558 * The pulse duration bits are reserved on HSW+.
3559 */
3560 hotplug = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
3561 hotplug &= ~DIGITAL_PORTA_PULSE_DURATION_MASK;
3562 hotplug |= DIGITAL_PORTA_HOTPLUG_ENABLE |
3563 DIGITAL_PORTA_PULSE_DURATION_2ms;
3564 I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hotplug);
3565}
3566
3567static void ilk_hpd_irq_setup(struct drm_i915_private *dev_priv)
3568{
3569 u32 hotplug_irqs, enabled_irqs;
3570
3571 if (INTEL_GEN(dev_priv) >= 8) {
3572 hotplug_irqs = GEN8_PORT_DP_A_HOTPLUG;
3573 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bdw);
3574
3575 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3576 } else if (INTEL_GEN(dev_priv) >= 7) {
3577 hotplug_irqs = DE_DP_A_HOTPLUG_IVB;
3578 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ivb);
3579
3580 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3581 } else {
3582 hotplug_irqs = DE_DP_A_HOTPLUG;
3583 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_ilk);
3584
3585 ilk_update_display_irq(dev_priv, hotplug_irqs, enabled_irqs);
3586 }
3587
3588 ilk_hpd_detection_setup(dev_priv);
3589
3590 ibx_hpd_irq_setup(dev_priv);
3591}
3592
3593static void __bxt_hpd_detection_setup(struct drm_i915_private *dev_priv,
3594 u32 enabled_irqs)
3595{
3596 u32 hotplug;
3597
3598 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3599 hotplug |= PORTA_HOTPLUG_ENABLE |
3600 PORTB_HOTPLUG_ENABLE |
3601 PORTC_HOTPLUG_ENABLE;
3602
3603 DRM_DEBUG_KMS("Invert bit setting: hp_ctl:%x hp_port:%x\n",
3604 hotplug, enabled_irqs);
3605 hotplug &= ~BXT_DDI_HPD_INVERT_MASK;
3606
3607 /*
3608 * For BXT invert bit has to be set based on AOB design
3609 * for HPD detection logic, update it based on VBT fields.
3610 */
3611 if ((enabled_irqs & BXT_DE_PORT_HP_DDIA) &&
3612 intel_bios_is_port_hpd_inverted(dev_priv, PORT_A))
3613 hotplug |= BXT_DDIA_HPD_INVERT;
3614 if ((enabled_irqs & BXT_DE_PORT_HP_DDIB) &&
3615 intel_bios_is_port_hpd_inverted(dev_priv, PORT_B))
3616 hotplug |= BXT_DDIB_HPD_INVERT;
3617 if ((enabled_irqs & BXT_DE_PORT_HP_DDIC) &&
3618 intel_bios_is_port_hpd_inverted(dev_priv, PORT_C))
3619 hotplug |= BXT_DDIC_HPD_INVERT;
3620
3621 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3622}
3623
3624static void bxt_hpd_detection_setup(struct drm_i915_private *dev_priv)
3625{
3626 __bxt_hpd_detection_setup(dev_priv, BXT_DE_PORT_HOTPLUG_MASK);
3627}
3628
3629static void bxt_hpd_irq_setup(struct drm_i915_private *dev_priv)
3630{
3631 u32 hotplug_irqs, enabled_irqs;
3632
3633 enabled_irqs = intel_hpd_enabled_irqs(dev_priv, hpd_bxt);
3634 hotplug_irqs = BXT_DE_PORT_HOTPLUG_MASK;
3635
3636 bdw_update_port_irq(dev_priv, hotplug_irqs, enabled_irqs);
3637
3638 __bxt_hpd_detection_setup(dev_priv, enabled_irqs);
3639}
3640
3641static void ibx_irq_postinstall(struct drm_i915_private *dev_priv)
3642{
3643 u32 mask;
3644
3645 if (HAS_PCH_NOP(dev_priv))
3646 return;
3647
3648 if (HAS_PCH_IBX(dev_priv))
3649 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
3650 else if (HAS_PCH_CPT(dev_priv) || HAS_PCH_LPT(dev_priv))
3651 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
3652 else
3653 mask = SDE_GMBUS_CPT;
3654
3655 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3656 I915_WRITE(SDEIMR, ~mask);
3657
3658 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
3659 HAS_PCH_LPT(dev_priv))
3660 ibx_hpd_detection_setup(dev_priv);
3661 else
3662 spt_hpd_detection_setup(dev_priv);
3663}
3664
3665static void ironlake_irq_postinstall(struct drm_i915_private *dev_priv)
3666{
3667 struct intel_uncore *uncore = &dev_priv->uncore;
3668 u32 display_mask, extra_mask;
3669
3670 if (INTEL_GEN(dev_priv) >= 7) {
3671 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3672 DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);
3673 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
3674 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |
3675 DE_DP_A_HOTPLUG_IVB);
3676 } else {
3677 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3678 DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |
3679 DE_PIPEA_CRC_DONE | DE_POISON);
3680 extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3681 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |
3682 DE_DP_A_HOTPLUG);
3683 }
3684
3685 if (IS_HASWELL(dev_priv)) {
3686 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3687 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3688 display_mask |= DE_EDP_PSR_INT_HSW;
3689 }
3690
3691 dev_priv->irq_mask = ~display_mask;
3692
3693 ibx_irq_pre_postinstall(dev_priv);
3694
3695 GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,
3696 display_mask | extra_mask);
3697
3698 gen5_gt_irq_postinstall(&dev_priv->gt);
3699
3700 ilk_hpd_detection_setup(dev_priv);
3701
3702 ibx_irq_postinstall(dev_priv);
3703
3704 if (IS_IRONLAKE_M(dev_priv)) {
3705 /* Enable PCU event interrupts
3706 *
3707 * spinlocking not required here for correctness since interrupt
3708 * setup is guaranteed to run in single-threaded context. But we
3709 * need it to make the assert_spin_locked happy. */
3710 spin_lock_irq(&dev_priv->irq_lock);
3711 ilk_enable_display_irq(dev_priv, DE_PCU_EVENT);
3712 spin_unlock_irq(&dev_priv->irq_lock);
3713 }
3714}
3715
3716void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3717{
3718 lockdep_assert_held(&dev_priv->irq_lock);
3719
3720 if (dev_priv->display_irqs_enabled)
3721 return;
3722
3723 dev_priv->display_irqs_enabled = true;
3724
3725 if (intel_irqs_enabled(dev_priv)) {
3726 vlv_display_irq_reset(dev_priv);
3727 vlv_display_irq_postinstall(dev_priv);
3728 }
3729}
3730
3731void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3732{
3733 lockdep_assert_held(&dev_priv->irq_lock);
3734
3735 if (!dev_priv->display_irqs_enabled)
3736 return;
3737
3738 dev_priv->display_irqs_enabled = false;
3739
3740 if (intel_irqs_enabled(dev_priv))
3741 vlv_display_irq_reset(dev_priv);
3742}
3743
3744
3745static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)
3746{
3747 gen5_gt_irq_postinstall(&dev_priv->gt);
3748
3749 spin_lock_irq(&dev_priv->irq_lock);
3750 if (dev_priv->display_irqs_enabled)
3751 vlv_display_irq_postinstall(dev_priv);
3752 spin_unlock_irq(&dev_priv->irq_lock);
3753
3754 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
3755 POSTING_READ(VLV_MASTER_IER);
3756}
3757
3758static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3759{
3760 struct intel_uncore *uncore = &dev_priv->uncore;
3761
3762 u32 de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3763 u32 de_pipe_enables;
3764 u32 de_port_masked = GEN8_AUX_CHANNEL_A;
3765 u32 de_port_enables;
3766 u32 de_misc_masked = GEN8_DE_EDP_PSR;
3767 enum pipe pipe;
3768
3769 if (INTEL_GEN(dev_priv) <= 10)
3770 de_misc_masked |= GEN8_DE_MISC_GSE;
3771
3772 if (INTEL_GEN(dev_priv) >= 9) {
3773 de_pipe_masked |= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
3774 de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
3775 GEN9_AUX_CHANNEL_D;
3776 if (IS_GEN9_LP(dev_priv))
3777 de_port_masked |= BXT_DE_PORT_GMBUS;
3778 } else {
3779 de_pipe_masked |= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3780 }
3781
3782 if (INTEL_GEN(dev_priv) >= 11)
3783 de_port_masked |= ICL_AUX_CHANNEL_E;
3784
3785 if (IS_CNL_WITH_PORT_F(dev_priv) || INTEL_GEN(dev_priv) >= 11)
3786 de_port_masked |= CNL_AUX_CHANNEL_F;
3787
3788 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3789 GEN8_PIPE_FIFO_UNDERRUN;
3790
3791 de_port_enables = de_port_masked;
3792 if (IS_GEN9_LP(dev_priv))
3793 de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
3794 else if (IS_BROADWELL(dev_priv))
3795 de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
3796
3797 gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
3798 intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
3799
3800 for_each_pipe(dev_priv, pipe) {
3801 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3802
3803 if (intel_display_power_is_enabled(dev_priv,
3804 POWER_DOMAIN_PIPE(pipe)))
3805 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3806 dev_priv->de_irq_mask[pipe],
3807 de_pipe_enables);
3808 }
3809
3810 GEN3_IRQ_INIT(uncore, GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
3811 GEN3_IRQ_INIT(uncore, GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
3812
3813 if (INTEL_GEN(dev_priv) >= 11) {
3814 u32 de_hpd_masked = 0;
3815 u32 de_hpd_enables = GEN11_DE_TC_HOTPLUG_MASK |
3816 GEN11_DE_TBT_HOTPLUG_MASK;
3817
3818 GEN3_IRQ_INIT(uncore, GEN11_DE_HPD_, ~de_hpd_masked,
3819 de_hpd_enables);
3820 gen11_hpd_detection_setup(dev_priv);
3821 } else if (IS_GEN9_LP(dev_priv)) {
3822 bxt_hpd_detection_setup(dev_priv);
3823 } else if (IS_BROADWELL(dev_priv)) {
3824 ilk_hpd_detection_setup(dev_priv);
3825 }
3826}
3827
3828static void gen8_irq_postinstall(struct drm_i915_private *dev_priv)
3829{
3830 if (HAS_PCH_SPLIT(dev_priv))
3831 ibx_irq_pre_postinstall(dev_priv);
3832
3833 gen8_gt_irq_postinstall(&dev_priv->gt);
3834 gen8_de_irq_postinstall(dev_priv);
3835
3836 if (HAS_PCH_SPLIT(dev_priv))
3837 ibx_irq_postinstall(dev_priv);
3838
3839 gen8_master_intr_enable(dev_priv->uncore.regs);
3840}
3841
3842static void icp_irq_postinstall(struct drm_i915_private *dev_priv)
3843{
3844 u32 mask = SDE_GMBUS_ICP;
3845
3846 WARN_ON(I915_READ(SDEIER) != 0);
3847 I915_WRITE(SDEIER, 0xffffffff);
3848 POSTING_READ(SDEIER);
3849
3850 gen3_assert_iir_is_zero(&dev_priv->uncore, SDEIIR);
3851 I915_WRITE(SDEIMR, ~mask);
3852
3853 if (HAS_PCH_TGP(dev_priv))
3854 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK,
3855 TGP_TC_HPD_ENABLE_MASK);
3856 else if (HAS_PCH_MCC(dev_priv))
3857 icp_hpd_detection_setup(dev_priv, TGP_DDI_HPD_ENABLE_MASK, 0);
3858 else
3859 icp_hpd_detection_setup(dev_priv, ICP_DDI_HPD_ENABLE_MASK,
3860 ICP_TC_HPD_ENABLE_MASK);
3861}
3862
3863static void gen11_irq_postinstall(struct drm_i915_private *dev_priv)
3864{
3865 struct intel_uncore *uncore = &dev_priv->uncore;
3866 u32 gu_misc_masked = GEN11_GU_MISC_GSE;
3867
3868 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3869 icp_irq_postinstall(dev_priv);
3870
3871 gen11_gt_irq_postinstall(&dev_priv->gt);
3872 gen8_de_irq_postinstall(dev_priv);
3873
3874 GEN3_IRQ_INIT(uncore, GEN11_GU_MISC_, ~gu_misc_masked, gu_misc_masked);
3875
3876 I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE);
3877
3878 gen11_master_intr_enable(uncore->regs);
3879 POSTING_READ(GEN11_GFX_MSTR_IRQ);
3880}
3881
3882static void cherryview_irq_postinstall(struct drm_i915_private *dev_priv)
3883{
3884 gen8_gt_irq_postinstall(&dev_priv->gt);
3885
3886 spin_lock_irq(&dev_priv->irq_lock);
3887 if (dev_priv->display_irqs_enabled)
3888 vlv_display_irq_postinstall(dev_priv);
3889 spin_unlock_irq(&dev_priv->irq_lock);
3890
3891 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
3892 POSTING_READ(GEN8_MASTER_IRQ);
3893}
3894
3895static void i8xx_irq_reset(struct drm_i915_private *dev_priv)
3896{
3897 struct intel_uncore *uncore = &dev_priv->uncore;
3898
3899 i9xx_pipestat_irq_reset(dev_priv);
3900
3901 GEN2_IRQ_RESET(uncore);
3902}
3903
3904static void i8xx_irq_postinstall(struct drm_i915_private *dev_priv)
3905{
3906 struct intel_uncore *uncore = &dev_priv->uncore;
3907 u16 enable_mask;
3908
3909 intel_uncore_write16(uncore,
3910 EMR,
3911 ~(I915_ERROR_PAGE_TABLE |
3912 I915_ERROR_MEMORY_REFRESH));
3913
3914 /* Unmask the interrupts that we always want on. */
3915 dev_priv->irq_mask =
3916 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3917 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3918 I915_MASTER_ERROR_INTERRUPT);
3919
3920 enable_mask =
3921 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3922 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3923 I915_MASTER_ERROR_INTERRUPT |
3924 I915_USER_INTERRUPT;
3925
3926 GEN2_IRQ_INIT(uncore, dev_priv->irq_mask, enable_mask);
3927
3928 /* Interrupt setup is already guaranteed to be single-threaded, this is
3929 * just to make the assert_spin_locked check happy. */
3930 spin_lock_irq(&dev_priv->irq_lock);
3931 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3932 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
3933 spin_unlock_irq(&dev_priv->irq_lock);
3934}
3935
3936static void i8xx_error_irq_ack(struct drm_i915_private *i915,
3937 u16 *eir, u16 *eir_stuck)
3938{
3939 struct intel_uncore *uncore = &i915->uncore;
3940 u16 emr;
3941
3942 *eir = intel_uncore_read16(uncore, EIR);
3943
3944 if (*eir)
3945 intel_uncore_write16(uncore, EIR, *eir);
3946
3947 *eir_stuck = intel_uncore_read16(uncore, EIR);
3948 if (*eir_stuck == 0)
3949 return;
3950
3951 /*
3952 * Toggle all EMR bits to make sure we get an edge
3953 * in the ISR master error bit if we don't clear
3954 * all the EIR bits. Otherwise the edge triggered
3955 * IIR on i965/g4x wouldn't notice that an interrupt
3956 * is still pending. Also some EIR bits can't be
3957 * cleared except by handling the underlying error
3958 * (or by a GPU reset) so we mask any bit that
3959 * remains set.
3960 */
3961 emr = intel_uncore_read16(uncore, EMR);
3962 intel_uncore_write16(uncore, EMR, 0xffff);
3963 intel_uncore_write16(uncore, EMR, emr | *eir_stuck);
3964}
3965
3966static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv,
3967 u16 eir, u16 eir_stuck)
3968{
3969 DRM_DEBUG("Master Error: EIR 0x%04x\n", eir);
3970
3971 if (eir_stuck)
3972 DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck);
3973}
3974
3975static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv,
3976 u32 *eir, u32 *eir_stuck)
3977{
3978 u32 emr;
3979
3980 *eir = I915_READ(EIR);
3981
3982 I915_WRITE(EIR, *eir);
3983
3984 *eir_stuck = I915_READ(EIR);
3985 if (*eir_stuck == 0)
3986 return;
3987
3988 /*
3989 * Toggle all EMR bits to make sure we get an edge
3990 * in the ISR master error bit if we don't clear
3991 * all the EIR bits. Otherwise the edge triggered
3992 * IIR on i965/g4x wouldn't notice that an interrupt
3993 * is still pending. Also some EIR bits can't be
3994 * cleared except by handling the underlying error
3995 * (or by a GPU reset) so we mask any bit that
3996 * remains set.
3997 */
3998 emr = I915_READ(EMR);
3999 I915_WRITE(EMR, 0xffffffff);
4000 I915_WRITE(EMR, emr | *eir_stuck);
4001}
4002
4003static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv,
4004 u32 eir, u32 eir_stuck)
4005{
4006 DRM_DEBUG("Master Error, EIR 0x%08x\n", eir);
4007
4008 if (eir_stuck)
4009 DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck);
4010}
4011
4012static irqreturn_t i8xx_irq_handler(int irq, void *arg)
4013{
4014 struct drm_i915_private *dev_priv = arg;
4015 irqreturn_t ret = IRQ_NONE;
4016
4017 if (!intel_irqs_enabled(dev_priv))
4018 return IRQ_NONE;
4019
4020 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4021 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4022
4023 do {
4024 u32 pipe_stats[I915_MAX_PIPES] = {};
4025 u16 eir = 0, eir_stuck = 0;
4026 u16 iir;
4027
4028 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
4029 if (iir == 0)
4030 break;
4031
4032 ret = IRQ_HANDLED;
4033
4034 /* Call regardless, as some status bits might not be
4035 * signalled in iir */
4036 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4037
4038 if (iir & I915_MASTER_ERROR_INTERRUPT)
4039 i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4040
4041 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
4042
4043 if (iir & I915_USER_INTERRUPT)
4044 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4045
4046 if (iir & I915_MASTER_ERROR_INTERRUPT)
4047 i8xx_error_irq_handler(dev_priv, eir, eir_stuck);
4048
4049 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4050 } while (0);
4051
4052 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4053
4054 return ret;
4055}
4056
4057static void i915_irq_reset(struct drm_i915_private *dev_priv)
4058{
4059 struct intel_uncore *uncore = &dev_priv->uncore;
4060
4061 if (I915_HAS_HOTPLUG(dev_priv)) {
4062 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4063 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4064 }
4065
4066 i9xx_pipestat_irq_reset(dev_priv);
4067
4068 GEN3_IRQ_RESET(uncore, GEN2_);
4069}
4070
4071static void i915_irq_postinstall(struct drm_i915_private *dev_priv)
4072{
4073 struct intel_uncore *uncore = &dev_priv->uncore;
4074 u32 enable_mask;
4075
4076 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE |
4077 I915_ERROR_MEMORY_REFRESH));
4078
4079 /* Unmask the interrupts that we always want on. */
4080 dev_priv->irq_mask =
4081 ~(I915_ASLE_INTERRUPT |
4082 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4083 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4084 I915_MASTER_ERROR_INTERRUPT);
4085
4086 enable_mask =
4087 I915_ASLE_INTERRUPT |
4088 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4089 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4090 I915_MASTER_ERROR_INTERRUPT |
4091 I915_USER_INTERRUPT;
4092
4093 if (I915_HAS_HOTPLUG(dev_priv)) {
4094 /* Enable in IER... */
4095 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
4096 /* and unmask in IMR */
4097 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
4098 }
4099
4100 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4101
4102 /* Interrupt setup is already guaranteed to be single-threaded, this is
4103 * just to make the assert_spin_locked check happy. */
4104 spin_lock_irq(&dev_priv->irq_lock);
4105 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4106 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4107 spin_unlock_irq(&dev_priv->irq_lock);
4108
4109 i915_enable_asle_pipestat(dev_priv);
4110}
4111
4112static irqreturn_t i915_irq_handler(int irq, void *arg)
4113{
4114 struct drm_i915_private *dev_priv = arg;
4115 irqreturn_t ret = IRQ_NONE;
4116
4117 if (!intel_irqs_enabled(dev_priv))
4118 return IRQ_NONE;
4119
4120 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4121 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4122
4123 do {
4124 u32 pipe_stats[I915_MAX_PIPES] = {};
4125 u32 eir = 0, eir_stuck = 0;
4126 u32 hotplug_status = 0;
4127 u32 iir;
4128
4129 iir = I915_READ(GEN2_IIR);
4130 if (iir == 0)
4131 break;
4132
4133 ret = IRQ_HANDLED;
4134
4135 if (I915_HAS_HOTPLUG(dev_priv) &&
4136 iir & I915_DISPLAY_PORT_INTERRUPT)
4137 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4138
4139 /* Call regardless, as some status bits might not be
4140 * signalled in iir */
4141 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4142
4143 if (iir & I915_MASTER_ERROR_INTERRUPT)
4144 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4145
4146 I915_WRITE(GEN2_IIR, iir);
4147
4148 if (iir & I915_USER_INTERRUPT)
4149 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4150
4151 if (iir & I915_MASTER_ERROR_INTERRUPT)
4152 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4153
4154 if (hotplug_status)
4155 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4156
4157 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4158 } while (0);
4159
4160 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4161
4162 return ret;
4163}
4164
4165static void i965_irq_reset(struct drm_i915_private *dev_priv)
4166{
4167 struct intel_uncore *uncore = &dev_priv->uncore;
4168
4169 i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0);
4170 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4171
4172 i9xx_pipestat_irq_reset(dev_priv);
4173
4174 GEN3_IRQ_RESET(uncore, GEN2_);
4175}
4176
4177static void i965_irq_postinstall(struct drm_i915_private *dev_priv)
4178{
4179 struct intel_uncore *uncore = &dev_priv->uncore;
4180 u32 enable_mask;
4181 u32 error_mask;
4182
4183 /*
4184 * Enable some error detection, note the instruction error mask
4185 * bit is reserved, so we leave it masked.
4186 */
4187 if (IS_G4X(dev_priv)) {
4188 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4189 GM45_ERROR_MEM_PRIV |
4190 GM45_ERROR_CP_PRIV |
4191 I915_ERROR_MEMORY_REFRESH);
4192 } else {
4193 error_mask = ~(I915_ERROR_PAGE_TABLE |
4194 I915_ERROR_MEMORY_REFRESH);
4195 }
4196 I915_WRITE(EMR, error_mask);
4197
4198 /* Unmask the interrupts that we always want on. */
4199 dev_priv->irq_mask =
4200 ~(I915_ASLE_INTERRUPT |
4201 I915_DISPLAY_PORT_INTERRUPT |
4202 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4203 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4204 I915_MASTER_ERROR_INTERRUPT);
4205
4206 enable_mask =
4207 I915_ASLE_INTERRUPT |
4208 I915_DISPLAY_PORT_INTERRUPT |
4209 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4210 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4211 I915_MASTER_ERROR_INTERRUPT |
4212 I915_USER_INTERRUPT;
4213
4214 if (IS_G4X(dev_priv))
4215 enable_mask |= I915_BSD_USER_INTERRUPT;
4216
4217 GEN3_IRQ_INIT(uncore, GEN2_, dev_priv->irq_mask, enable_mask);
4218
4219 /* Interrupt setup is already guaranteed to be single-threaded, this is
4220 * just to make the assert_spin_locked check happy. */
4221 spin_lock_irq(&dev_priv->irq_lock);
4222 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4223 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4224 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
4225 spin_unlock_irq(&dev_priv->irq_lock);
4226
4227 i915_enable_asle_pipestat(dev_priv);
4228}
4229
4230static void i915_hpd_irq_setup(struct drm_i915_private *dev_priv)
4231{
4232 u32 hotplug_en;
4233
4234 lockdep_assert_held(&dev_priv->irq_lock);
4235
4236 /* Note HDMI and DP share hotplug bits */
4237 /* enable bits are the same for all generations */
4238 hotplug_en = intel_hpd_enabled_irqs(dev_priv, hpd_mask_i915);
4239 /* Programming the CRT detection parameters tends
4240 to generate a spurious hotplug event about three
4241 seconds later. So just do it once.
4242 */
4243 if (IS_G4X(dev_priv))
4244 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4245 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
4246
4247 /* Ignore TV since it's buggy */
4248 i915_hotplug_interrupt_update_locked(dev_priv,
4249 HOTPLUG_INT_EN_MASK |
4250 CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |
4251 CRT_HOTPLUG_ACTIVATION_PERIOD_64,
4252 hotplug_en);
4253}
4254
4255static irqreturn_t i965_irq_handler(int irq, void *arg)
4256{
4257 struct drm_i915_private *dev_priv = arg;
4258 irqreturn_t ret = IRQ_NONE;
4259
4260 if (!intel_irqs_enabled(dev_priv))
4261 return IRQ_NONE;
4262
4263 /* IRQs are synced during runtime_suspend, we don't require a wakeref */
4264 disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4265
4266 do {
4267 u32 pipe_stats[I915_MAX_PIPES] = {};
4268 u32 eir = 0, eir_stuck = 0;
4269 u32 hotplug_status = 0;
4270 u32 iir;
4271
4272 iir = I915_READ(GEN2_IIR);
4273 if (iir == 0)
4274 break;
4275
4276 ret = IRQ_HANDLED;
4277
4278 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4279 hotplug_status = i9xx_hpd_irq_ack(dev_priv);
4280
4281 /* Call regardless, as some status bits might not be
4282 * signalled in iir */
4283 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
4284
4285 if (iir & I915_MASTER_ERROR_INTERRUPT)
4286 i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck);
4287
4288 I915_WRITE(GEN2_IIR, iir);
4289
4290 if (iir & I915_USER_INTERRUPT)
4291 intel_engine_breadcrumbs_irq(dev_priv->engine[RCS0]);
4292
4293 if (iir & I915_BSD_USER_INTERRUPT)
4294 intel_engine_breadcrumbs_irq(dev_priv->engine[VCS0]);
4295
4296 if (iir & I915_MASTER_ERROR_INTERRUPT)
4297 i9xx_error_irq_handler(dev_priv, eir, eir_stuck);
4298
4299 if (hotplug_status)
4300 i9xx_hpd_irq_handler(dev_priv, hotplug_status);
4301
4302 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);
4303 } while (0);
4304
4305 enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
4306
4307 return ret;
4308}
4309
4310/**
4311 * intel_irq_init - initializes irq support
4312 * @dev_priv: i915 device instance
4313 *
4314 * This function initializes all the irq support including work items, timers
4315 * and all the vtables. It does not setup the interrupt itself though.
4316 */
4317void intel_irq_init(struct drm_i915_private *dev_priv)
4318{
4319 struct drm_device *dev = &dev_priv->drm;
4320 struct intel_rps *rps = &dev_priv->gt_pm.rps;
4321 int i;
4322
4323 if (IS_I945GM(dev_priv))
4324 i945gm_vblank_work_init(dev_priv);
4325
4326 intel_hpd_init_work(dev_priv);
4327
4328 INIT_WORK(&rps->work, gen6_pm_rps_work);
4329
4330 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
4331 for (i = 0; i < MAX_L3_SLICES; ++i)
4332 dev_priv->l3_parity.remap_info[i] = NULL;
4333
4334 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */
4335 if (HAS_GT_UC(dev_priv) && INTEL_GEN(dev_priv) < 11)
4336 dev_priv->gt.pm_guc_events = GUC_INTR_GUC2HOST << 16;
4337
4338 /* Let's track the enabled rps events */
4339 if (IS_VALLEYVIEW(dev_priv))
4340 /* WaGsvRC0ResidencyMethod:vlv */
4341 dev_priv->pm_rps_events = GEN6_PM_RP_UP_EI_EXPIRED;
4342 else
4343 dev_priv->pm_rps_events = (GEN6_PM_RP_UP_THRESHOLD |
4344 GEN6_PM_RP_DOWN_THRESHOLD |
4345 GEN6_PM_RP_DOWN_TIMEOUT);
4346
4347 /* We share the register with other engine */
4348 if (INTEL_GEN(dev_priv) > 9)
4349 GEM_WARN_ON(dev_priv->pm_rps_events & 0xffff0000);
4350
4351 rps->pm_intrmsk_mbz = 0;
4352
4353 /*
4354 * SNB,IVB,HSW can while VLV,CHV may hard hang on looping batchbuffer
4355 * if GEN6_PM_UP_EI_EXPIRED is masked.
4356 *
4357 * TODO: verify if this can be reproduced on VLV,CHV.
4358 */
4359 if (INTEL_GEN(dev_priv) <= 7)
4360 rps->pm_intrmsk_mbz |= GEN6_PM_RP_UP_EI_EXPIRED;
4361
4362 if (INTEL_GEN(dev_priv) >= 8)
4363 rps->pm_intrmsk_mbz |= GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC;
4364
4365 dev->vblank_disable_immediate = true;
4366
4367 /* Most platforms treat the display irq block as an always-on
4368 * power domain. vlv/chv can disable it at runtime and need
4369 * special care to avoid writing any of the display block registers
4370 * outside of the power domain. We defer setting up the display irqs
4371 * in this case to the runtime pm.
4372 */
4373 dev_priv->display_irqs_enabled = true;
4374 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4375 dev_priv->display_irqs_enabled = false;
4376
4377 dev_priv->hotplug.hpd_storm_threshold = HPD_STORM_DEFAULT_THRESHOLD;
4378 /* If we have MST support, we want to avoid doing short HPD IRQ storm
4379 * detection, as short HPD storms will occur as a natural part of
4380 * sideband messaging with MST.
4381 * On older platforms however, IRQ storms can occur with both long and
4382 * short pulses, as seen on some G4x systems.
4383 */
4384 dev_priv->hotplug.hpd_short_storm_enabled = !HAS_DP_MST(dev_priv);
4385
4386 if (HAS_GMCH(dev_priv)) {
4387 if (I915_HAS_HOTPLUG(dev_priv))
4388 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
4389 } else {
4390 if (HAS_PCH_MCC(dev_priv))
4391 /* EHL doesn't need most of gen11_hpd_irq_setup */
4392 dev_priv->display.hpd_irq_setup = mcc_hpd_irq_setup;
4393 else if (INTEL_GEN(dev_priv) >= 11)
4394 dev_priv->display.hpd_irq_setup = gen11_hpd_irq_setup;
4395 else if (IS_GEN9_LP(dev_priv))
4396 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
4397 else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
4398 dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup;
4399 else
4400 dev_priv->display.hpd_irq_setup = ilk_hpd_irq_setup;
4401 }
4402}
4403
4404/**
4405 * intel_irq_fini - deinitializes IRQ support
4406 * @i915: i915 device instance
4407 *
4408 * This function deinitializes all the IRQ support.
4409 */
4410void intel_irq_fini(struct drm_i915_private *i915)
4411{
4412 int i;
4413
4414 if (IS_I945GM(i915))
4415 i945gm_vblank_work_fini(i915);
4416
4417 for (i = 0; i < MAX_L3_SLICES; ++i)
4418 kfree(i915->l3_parity.remap_info[i]);
4419}
4420
4421static irq_handler_t intel_irq_handler(struct drm_i915_private *dev_priv)
4422{
4423 if (HAS_GMCH(dev_priv)) {
4424 if (IS_CHERRYVIEW(dev_priv))
4425 return cherryview_irq_handler;
4426 else if (IS_VALLEYVIEW(dev_priv))
4427 return valleyview_irq_handler;
4428 else if (IS_GEN(dev_priv, 4))
4429 return i965_irq_handler;
4430 else if (IS_GEN(dev_priv, 3))
4431 return i915_irq_handler;
4432 else
4433 return i8xx_irq_handler;
4434 } else {
4435 if (INTEL_GEN(dev_priv) >= 11)
4436 return gen11_irq_handler;
4437 else if (INTEL_GEN(dev_priv) >= 8)
4438 return gen8_irq_handler;
4439 else
4440 return ironlake_irq_handler;
4441 }
4442}
4443
4444static void intel_irq_reset(struct drm_i915_private *dev_priv)
4445{
4446 if (HAS_GMCH(dev_priv)) {
4447 if (IS_CHERRYVIEW(dev_priv))
4448 cherryview_irq_reset(dev_priv);
4449 else if (IS_VALLEYVIEW(dev_priv))
4450 valleyview_irq_reset(dev_priv);
4451 else if (IS_GEN(dev_priv, 4))
4452 i965_irq_reset(dev_priv);
4453 else if (IS_GEN(dev_priv, 3))
4454 i915_irq_reset(dev_priv);
4455 else
4456 i8xx_irq_reset(dev_priv);
4457 } else {
4458 if (INTEL_GEN(dev_priv) >= 11)
4459 gen11_irq_reset(dev_priv);
4460 else if (INTEL_GEN(dev_priv) >= 8)
4461 gen8_irq_reset(dev_priv);
4462 else
4463 ironlake_irq_reset(dev_priv);
4464 }
4465}
4466
4467static void intel_irq_postinstall(struct drm_i915_private *dev_priv)
4468{
4469 if (HAS_GMCH(dev_priv)) {
4470 if (IS_CHERRYVIEW(dev_priv))
4471 cherryview_irq_postinstall(dev_priv);
4472 else if (IS_VALLEYVIEW(dev_priv))
4473 valleyview_irq_postinstall(dev_priv);
4474 else if (IS_GEN(dev_priv, 4))
4475 i965_irq_postinstall(dev_priv);
4476 else if (IS_GEN(dev_priv, 3))
4477 i915_irq_postinstall(dev_priv);
4478 else
4479 i8xx_irq_postinstall(dev_priv);
4480 } else {
4481 if (INTEL_GEN(dev_priv) >= 11)
4482 gen11_irq_postinstall(dev_priv);
4483 else if (INTEL_GEN(dev_priv) >= 8)
4484 gen8_irq_postinstall(dev_priv);
4485 else
4486 ironlake_irq_postinstall(dev_priv);
4487 }
4488}
4489
4490/**
4491 * intel_irq_install - enables the hardware interrupt
4492 * @dev_priv: i915 device instance
4493 *
4494 * This function enables the hardware interrupt handling, but leaves the hotplug
4495 * handling still disabled. It is called after intel_irq_init().
4496 *
4497 * In the driver load and resume code we need working interrupts in a few places
4498 * but don't want to deal with the hassle of concurrent probe and hotplug
4499 * workers. Hence the split into this two-stage approach.
4500 */
4501int intel_irq_install(struct drm_i915_private *dev_priv)
4502{
4503 int irq = dev_priv->drm.pdev->irq;
4504 int ret;
4505
4506 /*
4507 * We enable some interrupt sources in our postinstall hooks, so mark
4508 * interrupts as enabled _before_ actually enabling them to avoid
4509 * special cases in our ordering checks.
4510 */
4511 dev_priv->runtime_pm.irqs_enabled = true;
4512
4513 dev_priv->drm.irq_enabled = true;
4514
4515 intel_irq_reset(dev_priv);
4516
4517 ret = request_irq(irq, intel_irq_handler(dev_priv),
4518 IRQF_SHARED, DRIVER_NAME, dev_priv);
4519 if (ret < 0) {
4520 dev_priv->drm.irq_enabled = false;
4521 return ret;
4522 }
4523
4524 intel_irq_postinstall(dev_priv);
4525
4526 return ret;
4527}
4528
4529/**
4530 * intel_irq_uninstall - finilizes all irq handling
4531 * @dev_priv: i915 device instance
4532 *
4533 * This stops interrupt and hotplug handling and unregisters and frees all
4534 * resources acquired in the init functions.
4535 */
4536void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4537{
4538 int irq = dev_priv->drm.pdev->irq;
4539
4540 /*
4541 * FIXME we can get called twice during driver load
4542 * error handling due to intel_modeset_cleanup()
4543 * calling us out of sequence. Would be nice if
4544 * it didn't do that...
4545 */
4546 if (!dev_priv->drm.irq_enabled)
4547 return;
4548
4549 dev_priv->drm.irq_enabled = false;
4550
4551 intel_irq_reset(dev_priv);
4552
4553 free_irq(irq, dev_priv);
4554
4555 intel_hpd_cancel_work(dev_priv);
4556 dev_priv->runtime_pm.irqs_enabled = false;
4557}
4558
4559/**
4560 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4561 * @dev_priv: i915 device instance
4562 *
4563 * This function is used to disable interrupts at runtime, both in the runtime
4564 * pm and the system suspend/resume code.
4565 */
4566void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4567{
4568 intel_irq_reset(dev_priv);
4569 dev_priv->runtime_pm.irqs_enabled = false;
4570 intel_synchronize_irq(dev_priv);
4571}
4572
4573/**
4574 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4575 * @dev_priv: i915 device instance
4576 *
4577 * This function is used to enable interrupts at runtime, both in the runtime
4578 * pm and the system suspend/resume code.
4579 */
4580void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
4581{
4582 dev_priv->runtime_pm.irqs_enabled = true;
4583 intel_irq_reset(dev_priv);
4584 intel_irq_postinstall(dev_priv);
4585}
4586
4587bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
4588{
4589 /*
4590 * We only use drm_irq_uninstall() at unload and VT switch, so
4591 * this is the only thing we need to check.
4592 */
4593 return dev_priv->runtime_pm.irqs_enabled;
4594}
4595
4596void intel_synchronize_irq(struct drm_i915_private *i915)
4597{
4598 synchronize_irq(i915->drm.pdev->irq);
4599}