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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/spinlock.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/pm_runtime.h>
18#include <linux/of.h>
19
20#define DRIVER_NAME "zynq-gpio"
21
22/* Maximum banks */
23#define ZYNQ_GPIO_MAX_BANK 4
24#define ZYNQMP_GPIO_MAX_BANK 6
25#define VERSAL_GPIO_MAX_BANK 4
26#define PMC_GPIO_MAX_BANK 5
27#define VERSAL_UNUSED_BANKS 2
28
29#define ZYNQ_GPIO_BANK0_NGPIO 32
30#define ZYNQ_GPIO_BANK1_NGPIO 22
31#define ZYNQ_GPIO_BANK2_NGPIO 32
32#define ZYNQ_GPIO_BANK3_NGPIO 32
33
34#define ZYNQMP_GPIO_BANK0_NGPIO 26
35#define ZYNQMP_GPIO_BANK1_NGPIO 26
36#define ZYNQMP_GPIO_BANK2_NGPIO 26
37#define ZYNQMP_GPIO_BANK3_NGPIO 32
38#define ZYNQMP_GPIO_BANK4_NGPIO 32
39#define ZYNQMP_GPIO_BANK5_NGPIO 32
40
41#define ZYNQ_GPIO_NR_GPIOS 118
42#define ZYNQMP_GPIO_NR_GPIOS 174
43
44#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
45#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
48#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
51#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
54#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
57#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
59#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
60#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
61 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
62
63/* Register offsets for the GPIO device */
64/* LSW Mask & Data -WO */
65#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
66/* MSW Mask & Data -WO */
67#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
68/* Data Register-RW */
69#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
70#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
71/* Direction mode reg-RW */
72#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
73/* Output enable reg-RW */
74#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
75/* Interrupt mask reg-RO */
76#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
77/* Interrupt enable reg-WO */
78#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
79/* Interrupt disable reg-WO */
80#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
81/* Interrupt status reg-RO */
82#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
83/* Interrupt type reg-RW */
84#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
85/* Interrupt polarity reg-RW */
86#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
87/* Interrupt on any, reg-RW */
88#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
89
90/* Disable all interrupts mask */
91#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
92
93/* Mid pin number of a bank */
94#define ZYNQ_GPIO_MID_PIN_NUM 16
95
96/* GPIO upper 16 bit mask */
97#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
98
99/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
100#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
101#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
102#define GPIO_QUIRK_VERSAL BIT(2)
103
104struct gpio_regs {
105 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
106 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
107 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
108 u32 outen[ZYNQMP_GPIO_MAX_BANK];
109 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
110 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
111 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
112 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
113 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
114};
115
116/**
117 * struct zynq_gpio - gpio device private data structure
118 * @chip: instance of the gpio_chip
119 * @base_addr: base address of the GPIO device
120 * @clk: clock resource for this controller
121 * @irq: interrupt for the GPIO device
122 * @p_data: pointer to platform data
123 * @context: context registers
124 * @dirlock: lock used for direction in/out synchronization
125 */
126struct zynq_gpio {
127 struct gpio_chip chip;
128 void __iomem *base_addr;
129 struct clk *clk;
130 int irq;
131 const struct zynq_platform_data *p_data;
132 struct gpio_regs context;
133 spinlock_t dirlock; /* lock */
134};
135
136/**
137 * struct zynq_platform_data - zynq gpio platform data structure
138 * @label: string to store in gpio->label
139 * @quirks: Flags is used to identify the platform
140 * @ngpio: max number of gpio pins
141 * @max_bank: maximum number of gpio banks
142 * @bank_min: this array represents bank's min pin
143 * @bank_max: this array represents bank's max pin
144 */
145struct zynq_platform_data {
146 const char *label;
147 u32 quirks;
148 u16 ngpio;
149 int max_bank;
150 int bank_min[ZYNQMP_GPIO_MAX_BANK];
151 int bank_max[ZYNQMP_GPIO_MAX_BANK];
152};
153
154static struct irq_chip zynq_gpio_level_irqchip;
155static struct irq_chip zynq_gpio_edge_irqchip;
156
157/**
158 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
159 * @gpio: Pointer to driver data struct
160 *
161 * Return: 0 if zynqmp, 1 if zynq.
162 */
163static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
164{
165 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
166}
167
168/**
169 * gpio_data_ro_bug - test if HW bug exists or not
170 * @gpio: Pointer to driver data struct
171 *
172 * Return: 0 if bug doesnot exist, 1 if bug exists.
173 */
174static int gpio_data_ro_bug(struct zynq_gpio *gpio)
175{
176 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
177}
178
179/**
180 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
181 * for a given pin in the GPIO device
182 * @pin_num: gpio pin number within the device
183 * @bank_num: an output parameter used to return the bank number of the gpio
184 * pin
185 * @bank_pin_num: an output parameter used to return pin number within a bank
186 * for the given gpio pin
187 * @gpio: gpio device data structure
188 *
189 * Returns the bank number and pin offset within the bank.
190 */
191static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
192 unsigned int *bank_num,
193 unsigned int *bank_pin_num,
194 struct zynq_gpio *gpio)
195{
196 int bank;
197
198 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
199 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
200 (pin_num <= gpio->p_data->bank_max[bank])) {
201 *bank_num = bank;
202 *bank_pin_num = pin_num -
203 gpio->p_data->bank_min[bank];
204 return;
205 }
206 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
207 bank = bank + VERSAL_UNUSED_BANKS;
208 }
209
210 /* default */
211 WARN(true, "invalid GPIO pin number: %u", pin_num);
212 *bank_num = 0;
213 *bank_pin_num = 0;
214}
215
216/**
217 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
218 * @chip: gpio_chip instance to be worked on
219 * @pin: gpio pin number within the device
220 *
221 * This function reads the state of the specified pin of the GPIO device.
222 *
223 * Return: 0 if the pin is low, 1 if pin is high.
224 */
225static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
226{
227 u32 data;
228 unsigned int bank_num, bank_pin_num;
229 struct zynq_gpio *gpio = gpiochip_get_data(chip);
230
231 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
232
233 if (gpio_data_ro_bug(gpio)) {
234 if (zynq_gpio_is_zynq(gpio)) {
235 if (bank_num <= 1) {
236 data = readl_relaxed(gpio->base_addr +
237 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
238 } else {
239 data = readl_relaxed(gpio->base_addr +
240 ZYNQ_GPIO_DATA_OFFSET(bank_num));
241 }
242 } else {
243 if (bank_num <= 2) {
244 data = readl_relaxed(gpio->base_addr +
245 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
246 } else {
247 data = readl_relaxed(gpio->base_addr +
248 ZYNQ_GPIO_DATA_OFFSET(bank_num));
249 }
250 }
251 } else {
252 data = readl_relaxed(gpio->base_addr +
253 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
254 }
255 return (data >> bank_pin_num) & 1;
256}
257
258/**
259 * zynq_gpio_set_value - Modify the state of the pin with specified value
260 * @chip: gpio_chip instance to be worked on
261 * @pin: gpio pin number within the device
262 * @state: value used to modify the state of the specified pin
263 *
264 * This function calculates the register offset (i.e to lower 16 bits or
265 * upper 16 bits) based on the given pin number and sets the state of a
266 * gpio pin to the specified value. The state is either 0 or non-zero.
267 */
268static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
269 int state)
270{
271 unsigned int reg_offset, bank_num, bank_pin_num;
272 struct zynq_gpio *gpio = gpiochip_get_data(chip);
273
274 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
275
276 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
277 /* only 16 data bits in bit maskable reg */
278 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
279 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
280 } else {
281 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
282 }
283
284 /*
285 * get the 32 bit value to be written to the mask/data register where
286 * the upper 16 bits is the mask and lower 16 bits is the data
287 */
288 state = !!state;
289 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
290 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
291
292 writel_relaxed(state, gpio->base_addr + reg_offset);
293}
294
295/**
296 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
297 * @chip: gpio_chip instance to be worked on
298 * @pin: gpio pin number within the device
299 *
300 * This function uses the read-modify-write sequence to set the direction of
301 * the gpio pin as input.
302 *
303 * Return: 0 always
304 */
305static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
306{
307 u32 reg;
308 unsigned int bank_num, bank_pin_num;
309 unsigned long flags;
310 struct zynq_gpio *gpio = gpiochip_get_data(chip);
311
312 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
313
314 /*
315 * On zynq bank 0 pins 7 and 8 are special and cannot be used
316 * as inputs.
317 */
318 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
319 (bank_pin_num == 7 || bank_pin_num == 8))
320 return -EINVAL;
321
322 /* clear the bit in direction mode reg to set the pin as input */
323 spin_lock_irqsave(&gpio->dirlock, flags);
324 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
325 reg &= ~BIT(bank_pin_num);
326 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
327 spin_unlock_irqrestore(&gpio->dirlock, flags);
328
329 return 0;
330}
331
332/**
333 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
334 * @chip: gpio_chip instance to be worked on
335 * @pin: gpio pin number within the device
336 * @state: value to be written to specified pin
337 *
338 * This function sets the direction of specified GPIO pin as output, configures
339 * the Output Enable register for the pin and uses zynq_gpio_set to set
340 * the state of the pin to the value specified.
341 *
342 * Return: 0 always
343 */
344static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
345 int state)
346{
347 u32 reg;
348 unsigned int bank_num, bank_pin_num;
349 unsigned long flags;
350 struct zynq_gpio *gpio = gpiochip_get_data(chip);
351
352 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
353
354 /* set the GPIO pin as output */
355 spin_lock_irqsave(&gpio->dirlock, flags);
356 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
357 reg |= BIT(bank_pin_num);
358 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
359
360 /* configure the output enable reg for the pin */
361 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
362 reg |= BIT(bank_pin_num);
363 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
364 spin_unlock_irqrestore(&gpio->dirlock, flags);
365
366 /* set the state of the pin */
367 zynq_gpio_set_value(chip, pin, state);
368 return 0;
369}
370
371/**
372 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
373 * @chip: gpio_chip instance to be worked on
374 * @pin: gpio pin number within the device
375 *
376 * This function returns the direction of the specified GPIO.
377 *
378 * Return: GPIO_LINE_DIRECTION_OUT or GPIO_LINE_DIRECTION_IN
379 */
380static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
381{
382 u32 reg;
383 unsigned int bank_num, bank_pin_num;
384 struct zynq_gpio *gpio = gpiochip_get_data(chip);
385
386 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
387
388 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
389
390 if (reg & BIT(bank_pin_num))
391 return GPIO_LINE_DIRECTION_OUT;
392
393 return GPIO_LINE_DIRECTION_IN;
394}
395
396/**
397 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
398 * @irq_data: per irq and chip data passed down to chip functions
399 *
400 * This function calculates gpio pin number from irq number and sets the
401 * bit in the Interrupt Disable register of the corresponding bank to disable
402 * interrupts for that pin.
403 */
404static void zynq_gpio_irq_mask(struct irq_data *irq_data)
405{
406 unsigned int device_pin_num, bank_num, bank_pin_num;
407 struct zynq_gpio *gpio =
408 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
409
410 device_pin_num = irq_data->hwirq;
411 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
412 writel_relaxed(BIT(bank_pin_num),
413 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
414}
415
416/**
417 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
418 * @irq_data: irq data containing irq number of gpio pin for the interrupt
419 * to enable
420 *
421 * This function calculates the gpio pin number from irq number and sets the
422 * bit in the Interrupt Enable register of the corresponding bank to enable
423 * interrupts for that pin.
424 */
425static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
426{
427 unsigned int device_pin_num, bank_num, bank_pin_num;
428 struct zynq_gpio *gpio =
429 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
430
431 device_pin_num = irq_data->hwirq;
432 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
433 writel_relaxed(BIT(bank_pin_num),
434 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
435}
436
437/**
438 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
439 * @irq_data: irq data containing irq number of gpio pin for the interrupt
440 * to ack
441 *
442 * This function calculates gpio pin number from irq number and sets the bit
443 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
444 */
445static void zynq_gpio_irq_ack(struct irq_data *irq_data)
446{
447 unsigned int device_pin_num, bank_num, bank_pin_num;
448 struct zynq_gpio *gpio =
449 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
450
451 device_pin_num = irq_data->hwirq;
452 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
453 writel_relaxed(BIT(bank_pin_num),
454 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
455}
456
457/**
458 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
459 * @irq_data: irq data containing irq number of gpio pin for the interrupt
460 * to enable
461 *
462 * Clears the INTSTS bit and unmasks the given interrupt.
463 */
464static void zynq_gpio_irq_enable(struct irq_data *irq_data)
465{
466 /*
467 * The Zynq GPIO controller does not disable interrupt detection when
468 * the interrupt is masked and only disables the propagation of the
469 * interrupt. This means when the controller detects an interrupt
470 * condition while the interrupt is logically disabled it will propagate
471 * that interrupt event once the interrupt is enabled. This will cause
472 * the interrupt consumer to see spurious interrupts to prevent this
473 * first make sure that the interrupt is not asserted and then enable
474 * it.
475 */
476 zynq_gpio_irq_ack(irq_data);
477 zynq_gpio_irq_unmask(irq_data);
478}
479
480/**
481 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
482 * @irq_data: irq data containing irq number of gpio pin
483 * @type: interrupt type that is to be set for the gpio pin
484 *
485 * This function gets the gpio pin number and its bank from the gpio pin number
486 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
487 *
488 * Return: 0, negative error otherwise.
489 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
490 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
491 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
492 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
493 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
494 */
495static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
496{
497 u32 int_type, int_pol, int_any;
498 unsigned int device_pin_num, bank_num, bank_pin_num;
499 struct zynq_gpio *gpio =
500 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
501
502 device_pin_num = irq_data->hwirq;
503 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
504
505 int_type = readl_relaxed(gpio->base_addr +
506 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
507 int_pol = readl_relaxed(gpio->base_addr +
508 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
509 int_any = readl_relaxed(gpio->base_addr +
510 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
511
512 /*
513 * based on the type requested, configure the INT_TYPE, INT_POLARITY
514 * and INT_ANY registers
515 */
516 switch (type) {
517 case IRQ_TYPE_EDGE_RISING:
518 int_type |= BIT(bank_pin_num);
519 int_pol |= BIT(bank_pin_num);
520 int_any &= ~BIT(bank_pin_num);
521 break;
522 case IRQ_TYPE_EDGE_FALLING:
523 int_type |= BIT(bank_pin_num);
524 int_pol &= ~BIT(bank_pin_num);
525 int_any &= ~BIT(bank_pin_num);
526 break;
527 case IRQ_TYPE_EDGE_BOTH:
528 int_type |= BIT(bank_pin_num);
529 int_any |= BIT(bank_pin_num);
530 break;
531 case IRQ_TYPE_LEVEL_HIGH:
532 int_type &= ~BIT(bank_pin_num);
533 int_pol |= BIT(bank_pin_num);
534 break;
535 case IRQ_TYPE_LEVEL_LOW:
536 int_type &= ~BIT(bank_pin_num);
537 int_pol &= ~BIT(bank_pin_num);
538 break;
539 default:
540 return -EINVAL;
541 }
542
543 writel_relaxed(int_type,
544 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
545 writel_relaxed(int_pol,
546 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
547 writel_relaxed(int_any,
548 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
549
550 if (type & IRQ_TYPE_LEVEL_MASK)
551 irq_set_chip_handler_name_locked(irq_data,
552 &zynq_gpio_level_irqchip,
553 handle_fasteoi_irq, NULL);
554 else
555 irq_set_chip_handler_name_locked(irq_data,
556 &zynq_gpio_edge_irqchip,
557 handle_level_irq, NULL);
558
559 return 0;
560}
561
562static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
563{
564 struct zynq_gpio *gpio =
565 gpiochip_get_data(irq_data_get_irq_chip_data(data));
566
567 irq_set_irq_wake(gpio->irq, on);
568
569 return 0;
570}
571
572static int zynq_gpio_irq_reqres(struct irq_data *d)
573{
574 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
575 int ret;
576
577 ret = pm_runtime_get_sync(chip->parent);
578 if (ret < 0)
579 return ret;
580
581 return gpiochip_reqres_irq(chip, d->hwirq);
582}
583
584static void zynq_gpio_irq_relres(struct irq_data *d)
585{
586 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
587
588 gpiochip_relres_irq(chip, d->hwirq);
589 pm_runtime_put(chip->parent);
590}
591
592/* irq chip descriptor */
593static struct irq_chip zynq_gpio_level_irqchip = {
594 .name = DRIVER_NAME,
595 .irq_enable = zynq_gpio_irq_enable,
596 .irq_eoi = zynq_gpio_irq_ack,
597 .irq_mask = zynq_gpio_irq_mask,
598 .irq_unmask = zynq_gpio_irq_unmask,
599 .irq_set_type = zynq_gpio_set_irq_type,
600 .irq_set_wake = zynq_gpio_set_wake,
601 .irq_request_resources = zynq_gpio_irq_reqres,
602 .irq_release_resources = zynq_gpio_irq_relres,
603 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
604 IRQCHIP_MASK_ON_SUSPEND,
605};
606
607static struct irq_chip zynq_gpio_edge_irqchip = {
608 .name = DRIVER_NAME,
609 .irq_enable = zynq_gpio_irq_enable,
610 .irq_ack = zynq_gpio_irq_ack,
611 .irq_mask = zynq_gpio_irq_mask,
612 .irq_unmask = zynq_gpio_irq_unmask,
613 .irq_set_type = zynq_gpio_set_irq_type,
614 .irq_set_wake = zynq_gpio_set_wake,
615 .irq_request_resources = zynq_gpio_irq_reqres,
616 .irq_release_resources = zynq_gpio_irq_relres,
617 .flags = IRQCHIP_MASK_ON_SUSPEND,
618};
619
620static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
621 unsigned int bank_num,
622 unsigned long pending)
623{
624 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
625 struct irq_domain *irqdomain = gpio->chip.irq.domain;
626 int offset;
627
628 if (!pending)
629 return;
630
631 for_each_set_bit(offset, &pending, 32) {
632 unsigned int gpio_irq;
633
634 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
635 generic_handle_irq(gpio_irq);
636 }
637}
638
639/**
640 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
641 * @desc: irq descriptor instance of the 'irq'
642 *
643 * This function reads the Interrupt Status Register of each bank to get the
644 * gpio pin number which has triggered an interrupt. It then acks the triggered
645 * interrupt and calls the pin specific handler set by the higher layer
646 * application for that pin.
647 * Note: A bug is reported if no handler is set for the gpio pin.
648 */
649static void zynq_gpio_irqhandler(struct irq_desc *desc)
650{
651 u32 int_sts, int_enb;
652 unsigned int bank_num;
653 struct zynq_gpio *gpio =
654 gpiochip_get_data(irq_desc_get_handler_data(desc));
655 struct irq_chip *irqchip = irq_desc_get_chip(desc);
656
657 chained_irq_enter(irqchip, desc);
658
659 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
660 int_sts = readl_relaxed(gpio->base_addr +
661 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
662 int_enb = readl_relaxed(gpio->base_addr +
663 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
664 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
665 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
666 bank_num = bank_num + VERSAL_UNUSED_BANKS;
667 }
668
669 chained_irq_exit(irqchip, desc);
670}
671
672static void zynq_gpio_save_context(struct zynq_gpio *gpio)
673{
674 unsigned int bank_num;
675
676 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
677 gpio->context.datalsw[bank_num] =
678 readl_relaxed(gpio->base_addr +
679 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
680 gpio->context.datamsw[bank_num] =
681 readl_relaxed(gpio->base_addr +
682 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
683 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
684 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
685 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
686 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
687 gpio->context.int_type[bank_num] =
688 readl_relaxed(gpio->base_addr +
689 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
690 gpio->context.int_polarity[bank_num] =
691 readl_relaxed(gpio->base_addr +
692 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
693 gpio->context.int_any[bank_num] =
694 readl_relaxed(gpio->base_addr +
695 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
696 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
697 bank_num = bank_num + VERSAL_UNUSED_BANKS;
698 }
699}
700
701static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
702{
703 unsigned int bank_num;
704
705 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
706 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
707 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
708 writel_relaxed(gpio->context.datalsw[bank_num],
709 gpio->base_addr +
710 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
711 writel_relaxed(gpio->context.datamsw[bank_num],
712 gpio->base_addr +
713 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
714 writel_relaxed(gpio->context.dirm[bank_num],
715 gpio->base_addr +
716 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
717 writel_relaxed(gpio->context.int_type[bank_num],
718 gpio->base_addr +
719 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
720 writel_relaxed(gpio->context.int_polarity[bank_num],
721 gpio->base_addr +
722 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
723 writel_relaxed(gpio->context.int_any[bank_num],
724 gpio->base_addr +
725 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
726 writel_relaxed(~(gpio->context.int_en[bank_num]),
727 gpio->base_addr +
728 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
729 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
730 bank_num = bank_num + VERSAL_UNUSED_BANKS;
731 }
732}
733
734static int __maybe_unused zynq_gpio_suspend(struct device *dev)
735{
736 struct zynq_gpio *gpio = dev_get_drvdata(dev);
737 struct irq_data *data = irq_get_irq_data(gpio->irq);
738
739 if (!device_may_wakeup(dev))
740 disable_irq(gpio->irq);
741
742 if (!irqd_is_wakeup_set(data)) {
743 zynq_gpio_save_context(gpio);
744 return pm_runtime_force_suspend(dev);
745 }
746
747 return 0;
748}
749
750static int __maybe_unused zynq_gpio_resume(struct device *dev)
751{
752 struct zynq_gpio *gpio = dev_get_drvdata(dev);
753 struct irq_data *data = irq_get_irq_data(gpio->irq);
754 int ret;
755
756 if (!device_may_wakeup(dev))
757 enable_irq(gpio->irq);
758
759 if (!irqd_is_wakeup_set(data)) {
760 ret = pm_runtime_force_resume(dev);
761 zynq_gpio_restore_context(gpio);
762 return ret;
763 }
764
765 return 0;
766}
767
768static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
769{
770 struct zynq_gpio *gpio = dev_get_drvdata(dev);
771
772 clk_disable_unprepare(gpio->clk);
773
774 return 0;
775}
776
777static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
778{
779 struct zynq_gpio *gpio = dev_get_drvdata(dev);
780
781 return clk_prepare_enable(gpio->clk);
782}
783
784static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
785{
786 int ret;
787
788 ret = pm_runtime_get_sync(chip->parent);
789
790 /*
791 * If the device is already active pm_runtime_get() will return 1 on
792 * success, but gpio_request still needs to return 0.
793 */
794 return ret < 0 ? ret : 0;
795}
796
797static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
798{
799 pm_runtime_put(chip->parent);
800}
801
802static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
803 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
804 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
805 zynq_gpio_runtime_resume, NULL)
806};
807
808static const struct zynq_platform_data versal_gpio_def = {
809 .label = "versal_gpio",
810 .quirks = GPIO_QUIRK_VERSAL,
811 .ngpio = 58,
812 .max_bank = VERSAL_GPIO_MAX_BANK,
813 .bank_min[0] = 0,
814 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
815 .bank_min[3] = 26,
816 .bank_max[3] = 57, /* Bank 3 is connected to FMIOs (32 pins) */
817};
818
819static const struct zynq_platform_data pmc_gpio_def = {
820 .label = "pmc_gpio",
821 .ngpio = 116,
822 .max_bank = PMC_GPIO_MAX_BANK,
823 .bank_min[0] = 0,
824 .bank_max[0] = 25, /* 0 to 25 are connected to MIOs (26 pins) */
825 .bank_min[1] = 26,
826 .bank_max[1] = 51, /* Bank 1 are connected to MIOs (26 pins) */
827 .bank_min[3] = 52,
828 .bank_max[3] = 83, /* Bank 3 is connected to EMIOs (32 pins) */
829 .bank_min[4] = 84,
830 .bank_max[4] = 115, /* Bank 4 is connected to EMIOs (32 pins) */
831};
832
833static const struct zynq_platform_data zynqmp_gpio_def = {
834 .label = "zynqmp_gpio",
835 .quirks = GPIO_QUIRK_DATA_RO_BUG,
836 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
837 .max_bank = ZYNQMP_GPIO_MAX_BANK,
838 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
839 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
840 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
841 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
842 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
843 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
844 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
845 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
846 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
847 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
848 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
849 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
850};
851
852static const struct zynq_platform_data zynq_gpio_def = {
853 .label = "zynq_gpio",
854 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
855 .ngpio = ZYNQ_GPIO_NR_GPIOS,
856 .max_bank = ZYNQ_GPIO_MAX_BANK,
857 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
858 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
859 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
860 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
861 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
862 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
863 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
864 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
865};
866
867static const struct of_device_id zynq_gpio_of_match[] = {
868 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
869 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
870 { .compatible = "xlnx,versal-gpio-1.0", .data = &versal_gpio_def },
871 { .compatible = "xlnx,pmc-gpio-1.0", .data = &pmc_gpio_def },
872 { /* end of table */ }
873};
874MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
875
876/**
877 * zynq_gpio_probe - Initialization method for a zynq_gpio device
878 * @pdev: platform device instance
879 *
880 * This function allocates memory resources for the gpio device and registers
881 * all the banks of the device. It will also set up interrupts for the gpio
882 * pins.
883 * Note: Interrupts are disabled for all the banks during initialization.
884 *
885 * Return: 0 on success, negative error otherwise.
886 */
887static int zynq_gpio_probe(struct platform_device *pdev)
888{
889 int ret, bank_num;
890 struct zynq_gpio *gpio;
891 struct gpio_chip *chip;
892 struct gpio_irq_chip *girq;
893 const struct of_device_id *match;
894
895 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
896 if (!gpio)
897 return -ENOMEM;
898
899 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
900 if (!match) {
901 dev_err(&pdev->dev, "of_match_node() failed\n");
902 return -EINVAL;
903 }
904 gpio->p_data = match->data;
905 platform_set_drvdata(pdev, gpio);
906
907 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
908 if (IS_ERR(gpio->base_addr))
909 return PTR_ERR(gpio->base_addr);
910
911 gpio->irq = platform_get_irq(pdev, 0);
912 if (gpio->irq < 0)
913 return gpio->irq;
914
915 /* configure the gpio chip */
916 chip = &gpio->chip;
917 chip->label = gpio->p_data->label;
918 chip->owner = THIS_MODULE;
919 chip->parent = &pdev->dev;
920 chip->get = zynq_gpio_get_value;
921 chip->set = zynq_gpio_set_value;
922 chip->request = zynq_gpio_request;
923 chip->free = zynq_gpio_free;
924 chip->direction_input = zynq_gpio_dir_in;
925 chip->direction_output = zynq_gpio_dir_out;
926 chip->get_direction = zynq_gpio_get_direction;
927 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
928 chip->ngpio = gpio->p_data->ngpio;
929
930 /* Retrieve GPIO clock */
931 gpio->clk = devm_clk_get(&pdev->dev, NULL);
932 if (IS_ERR(gpio->clk)) {
933 if (PTR_ERR(gpio->clk) != -EPROBE_DEFER)
934 dev_err(&pdev->dev, "input clock not found.\n");
935 return PTR_ERR(gpio->clk);
936 }
937 ret = clk_prepare_enable(gpio->clk);
938 if (ret) {
939 dev_err(&pdev->dev, "Unable to enable clock.\n");
940 return ret;
941 }
942
943 spin_lock_init(&gpio->dirlock);
944
945 pm_runtime_set_active(&pdev->dev);
946 pm_runtime_enable(&pdev->dev);
947 ret = pm_runtime_get_sync(&pdev->dev);
948 if (ret < 0)
949 goto err_pm_dis;
950
951 /* disable interrupts for all banks */
952 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
953 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
954 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
955 if (gpio->p_data->quirks & GPIO_QUIRK_VERSAL)
956 bank_num = bank_num + VERSAL_UNUSED_BANKS;
957 }
958
959 /* Set up the GPIO irqchip */
960 girq = &chip->irq;
961 girq->chip = &zynq_gpio_edge_irqchip;
962 girq->parent_handler = zynq_gpio_irqhandler;
963 girq->num_parents = 1;
964 girq->parents = devm_kcalloc(&pdev->dev, 1,
965 sizeof(*girq->parents),
966 GFP_KERNEL);
967 if (!girq->parents) {
968 ret = -ENOMEM;
969 goto err_pm_put;
970 }
971 girq->parents[0] = gpio->irq;
972 girq->default_type = IRQ_TYPE_NONE;
973 girq->handler = handle_level_irq;
974
975 /* report a bug if gpio chip registration fails */
976 ret = gpiochip_add_data(chip, gpio);
977 if (ret) {
978 dev_err(&pdev->dev, "Failed to add gpio chip\n");
979 goto err_pm_put;
980 }
981
982 irq_set_status_flags(gpio->irq, IRQ_DISABLE_UNLAZY);
983 device_init_wakeup(&pdev->dev, 1);
984 pm_runtime_put(&pdev->dev);
985
986 return 0;
987
988err_pm_put:
989 pm_runtime_put(&pdev->dev);
990err_pm_dis:
991 pm_runtime_disable(&pdev->dev);
992 clk_disable_unprepare(gpio->clk);
993
994 return ret;
995}
996
997/**
998 * zynq_gpio_remove - Driver removal function
999 * @pdev: platform device instance
1000 *
1001 * Return: 0 always
1002 */
1003static int zynq_gpio_remove(struct platform_device *pdev)
1004{
1005 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
1006
1007 pm_runtime_get_sync(&pdev->dev);
1008 gpiochip_remove(&gpio->chip);
1009 clk_disable_unprepare(gpio->clk);
1010 device_set_wakeup_capable(&pdev->dev, 0);
1011 pm_runtime_disable(&pdev->dev);
1012 return 0;
1013}
1014
1015static struct platform_driver zynq_gpio_driver = {
1016 .driver = {
1017 .name = DRIVER_NAME,
1018 .pm = &zynq_gpio_dev_pm_ops,
1019 .of_match_table = zynq_gpio_of_match,
1020 },
1021 .probe = zynq_gpio_probe,
1022 .remove = zynq_gpio_remove,
1023};
1024
1025/**
1026 * zynq_gpio_init - Initial driver registration call
1027 *
1028 * Return: value from platform_driver_register
1029 */
1030static int __init zynq_gpio_init(void)
1031{
1032 return platform_driver_register(&zynq_gpio_driver);
1033}
1034postcore_initcall(zynq_gpio_init);
1035
1036static void __exit zynq_gpio_exit(void)
1037{
1038 platform_driver_unregister(&zynq_gpio_driver);
1039}
1040module_exit(zynq_gpio_exit);
1041
1042MODULE_AUTHOR("Xilinx Inc.");
1043MODULE_DESCRIPTION("Zynq GPIO driver");
1044MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Xilinx Zynq GPIO device driver
4 *
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/module.h>
15#include <linux/platform_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/of.h>
18
19#define DRIVER_NAME "zynq-gpio"
20
21/* Maximum banks */
22#define ZYNQ_GPIO_MAX_BANK 4
23#define ZYNQMP_GPIO_MAX_BANK 6
24
25#define ZYNQ_GPIO_BANK0_NGPIO 32
26#define ZYNQ_GPIO_BANK1_NGPIO 22
27#define ZYNQ_GPIO_BANK2_NGPIO 32
28#define ZYNQ_GPIO_BANK3_NGPIO 32
29
30#define ZYNQMP_GPIO_BANK0_NGPIO 26
31#define ZYNQMP_GPIO_BANK1_NGPIO 26
32#define ZYNQMP_GPIO_BANK2_NGPIO 26
33#define ZYNQMP_GPIO_BANK3_NGPIO 32
34#define ZYNQMP_GPIO_BANK4_NGPIO 32
35#define ZYNQMP_GPIO_BANK5_NGPIO 32
36
37#define ZYNQ_GPIO_NR_GPIOS 118
38#define ZYNQMP_GPIO_NR_GPIOS 174
39
40#define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
41#define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
42 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
43#define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
44#define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
45 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
46#define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
47#define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
48 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
49#define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
50#define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
51 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
52#define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
53#define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
54 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
55#define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
56#define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
57 ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
58
59/* Register offsets for the GPIO device */
60/* LSW Mask & Data -WO */
61#define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
62/* MSW Mask & Data -WO */
63#define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
64/* Data Register-RW */
65#define ZYNQ_GPIO_DATA_OFFSET(BANK) (0x040 + (4 * BANK))
66#define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
67/* Direction mode reg-RW */
68#define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
69/* Output enable reg-RW */
70#define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
71/* Interrupt mask reg-RO */
72#define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
73/* Interrupt enable reg-WO */
74#define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
75/* Interrupt disable reg-WO */
76#define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
77/* Interrupt status reg-RO */
78#define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
79/* Interrupt type reg-RW */
80#define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
81/* Interrupt polarity reg-RW */
82#define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
83/* Interrupt on any, reg-RW */
84#define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
85
86/* Disable all interrupts mask */
87#define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
88
89/* Mid pin number of a bank */
90#define ZYNQ_GPIO_MID_PIN_NUM 16
91
92/* GPIO upper 16 bit mask */
93#define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
94
95/* set to differentiate zynq from zynqmp, 0=zynqmp, 1=zynq */
96#define ZYNQ_GPIO_QUIRK_IS_ZYNQ BIT(0)
97#define GPIO_QUIRK_DATA_RO_BUG BIT(1)
98
99struct gpio_regs {
100 u32 datamsw[ZYNQMP_GPIO_MAX_BANK];
101 u32 datalsw[ZYNQMP_GPIO_MAX_BANK];
102 u32 dirm[ZYNQMP_GPIO_MAX_BANK];
103 u32 outen[ZYNQMP_GPIO_MAX_BANK];
104 u32 int_en[ZYNQMP_GPIO_MAX_BANK];
105 u32 int_dis[ZYNQMP_GPIO_MAX_BANK];
106 u32 int_type[ZYNQMP_GPIO_MAX_BANK];
107 u32 int_polarity[ZYNQMP_GPIO_MAX_BANK];
108 u32 int_any[ZYNQMP_GPIO_MAX_BANK];
109};
110
111/**
112 * struct zynq_gpio - gpio device private data structure
113 * @chip: instance of the gpio_chip
114 * @base_addr: base address of the GPIO device
115 * @clk: clock resource for this controller
116 * @irq: interrupt for the GPIO device
117 * @p_data: pointer to platform data
118 * @context: context registers
119 */
120struct zynq_gpio {
121 struct gpio_chip chip;
122 void __iomem *base_addr;
123 struct clk *clk;
124 int irq;
125 const struct zynq_platform_data *p_data;
126 struct gpio_regs context;
127};
128
129/**
130 * struct zynq_platform_data - zynq gpio platform data structure
131 * @label: string to store in gpio->label
132 * @quirks: Flags is used to identify the platform
133 * @ngpio: max number of gpio pins
134 * @max_bank: maximum number of gpio banks
135 * @bank_min: this array represents bank's min pin
136 * @bank_max: this array represents bank's max pin
137 */
138struct zynq_platform_data {
139 const char *label;
140 u32 quirks;
141 u16 ngpio;
142 int max_bank;
143 int bank_min[ZYNQMP_GPIO_MAX_BANK];
144 int bank_max[ZYNQMP_GPIO_MAX_BANK];
145};
146
147static struct irq_chip zynq_gpio_level_irqchip;
148static struct irq_chip zynq_gpio_edge_irqchip;
149
150/**
151 * zynq_gpio_is_zynq - test if HW is zynq or zynqmp
152 * @gpio: Pointer to driver data struct
153 *
154 * Return: 0 if zynqmp, 1 if zynq.
155 */
156static int zynq_gpio_is_zynq(struct zynq_gpio *gpio)
157{
158 return !!(gpio->p_data->quirks & ZYNQ_GPIO_QUIRK_IS_ZYNQ);
159}
160
161/**
162 * gpio_data_ro_bug - test if HW bug exists or not
163 * @gpio: Pointer to driver data struct
164 *
165 * Return: 0 if bug doesnot exist, 1 if bug exists.
166 */
167static int gpio_data_ro_bug(struct zynq_gpio *gpio)
168{
169 return !!(gpio->p_data->quirks & GPIO_QUIRK_DATA_RO_BUG);
170}
171
172/**
173 * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
174 * for a given pin in the GPIO device
175 * @pin_num: gpio pin number within the device
176 * @bank_num: an output parameter used to return the bank number of the gpio
177 * pin
178 * @bank_pin_num: an output parameter used to return pin number within a bank
179 * for the given gpio pin
180 * @gpio: gpio device data structure
181 *
182 * Returns the bank number and pin offset within the bank.
183 */
184static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
185 unsigned int *bank_num,
186 unsigned int *bank_pin_num,
187 struct zynq_gpio *gpio)
188{
189 int bank;
190
191 for (bank = 0; bank < gpio->p_data->max_bank; bank++) {
192 if ((pin_num >= gpio->p_data->bank_min[bank]) &&
193 (pin_num <= gpio->p_data->bank_max[bank])) {
194 *bank_num = bank;
195 *bank_pin_num = pin_num -
196 gpio->p_data->bank_min[bank];
197 return;
198 }
199 }
200
201 /* default */
202 WARN(true, "invalid GPIO pin number: %u", pin_num);
203 *bank_num = 0;
204 *bank_pin_num = 0;
205}
206
207/**
208 * zynq_gpio_get_value - Get the state of the specified pin of GPIO device
209 * @chip: gpio_chip instance to be worked on
210 * @pin: gpio pin number within the device
211 *
212 * This function reads the state of the specified pin of the GPIO device.
213 *
214 * Return: 0 if the pin is low, 1 if pin is high.
215 */
216static int zynq_gpio_get_value(struct gpio_chip *chip, unsigned int pin)
217{
218 u32 data;
219 unsigned int bank_num, bank_pin_num;
220 struct zynq_gpio *gpio = gpiochip_get_data(chip);
221
222 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
223
224 if (gpio_data_ro_bug(gpio)) {
225 if (zynq_gpio_is_zynq(gpio)) {
226 if (bank_num <= 1) {
227 data = readl_relaxed(gpio->base_addr +
228 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
229 } else {
230 data = readl_relaxed(gpio->base_addr +
231 ZYNQ_GPIO_DATA_OFFSET(bank_num));
232 }
233 } else {
234 if (bank_num <= 2) {
235 data = readl_relaxed(gpio->base_addr +
236 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
237 } else {
238 data = readl_relaxed(gpio->base_addr +
239 ZYNQ_GPIO_DATA_OFFSET(bank_num));
240 }
241 }
242 } else {
243 data = readl_relaxed(gpio->base_addr +
244 ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
245 }
246 return (data >> bank_pin_num) & 1;
247}
248
249/**
250 * zynq_gpio_set_value - Modify the state of the pin with specified value
251 * @chip: gpio_chip instance to be worked on
252 * @pin: gpio pin number within the device
253 * @state: value used to modify the state of the specified pin
254 *
255 * This function calculates the register offset (i.e to lower 16 bits or
256 * upper 16 bits) based on the given pin number and sets the state of a
257 * gpio pin to the specified value. The state is either 0 or non-zero.
258 */
259static void zynq_gpio_set_value(struct gpio_chip *chip, unsigned int pin,
260 int state)
261{
262 unsigned int reg_offset, bank_num, bank_pin_num;
263 struct zynq_gpio *gpio = gpiochip_get_data(chip);
264
265 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
266
267 if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
268 /* only 16 data bits in bit maskable reg */
269 bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
270 reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
271 } else {
272 reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
273 }
274
275 /*
276 * get the 32 bit value to be written to the mask/data register where
277 * the upper 16 bits is the mask and lower 16 bits is the data
278 */
279 state = !!state;
280 state = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
281 ((state << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
282
283 writel_relaxed(state, gpio->base_addr + reg_offset);
284}
285
286/**
287 * zynq_gpio_dir_in - Set the direction of the specified GPIO pin as input
288 * @chip: gpio_chip instance to be worked on
289 * @pin: gpio pin number within the device
290 *
291 * This function uses the read-modify-write sequence to set the direction of
292 * the gpio pin as input.
293 *
294 * Return: 0 always
295 */
296static int zynq_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
297{
298 u32 reg;
299 unsigned int bank_num, bank_pin_num;
300 struct zynq_gpio *gpio = gpiochip_get_data(chip);
301
302 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
303
304 /*
305 * On zynq bank 0 pins 7 and 8 are special and cannot be used
306 * as inputs.
307 */
308 if (zynq_gpio_is_zynq(gpio) && bank_num == 0 &&
309 (bank_pin_num == 7 || bank_pin_num == 8))
310 return -EINVAL;
311
312 /* clear the bit in direction mode reg to set the pin as input */
313 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
314 reg &= ~BIT(bank_pin_num);
315 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
316
317 return 0;
318}
319
320/**
321 * zynq_gpio_dir_out - Set the direction of the specified GPIO pin as output
322 * @chip: gpio_chip instance to be worked on
323 * @pin: gpio pin number within the device
324 * @state: value to be written to specified pin
325 *
326 * This function sets the direction of specified GPIO pin as output, configures
327 * the Output Enable register for the pin and uses zynq_gpio_set to set
328 * the state of the pin to the value specified.
329 *
330 * Return: 0 always
331 */
332static int zynq_gpio_dir_out(struct gpio_chip *chip, unsigned int pin,
333 int state)
334{
335 u32 reg;
336 unsigned int bank_num, bank_pin_num;
337 struct zynq_gpio *gpio = gpiochip_get_data(chip);
338
339 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
340
341 /* set the GPIO pin as output */
342 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
343 reg |= BIT(bank_pin_num);
344 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
345
346 /* configure the output enable reg for the pin */
347 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
348 reg |= BIT(bank_pin_num);
349 writel_relaxed(reg, gpio->base_addr + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
350
351 /* set the state of the pin */
352 zynq_gpio_set_value(chip, pin, state);
353 return 0;
354}
355
356/**
357 * zynq_gpio_get_direction - Read the direction of the specified GPIO pin
358 * @chip: gpio_chip instance to be worked on
359 * @pin: gpio pin number within the device
360 *
361 * This function returns the direction of the specified GPIO.
362 *
363 * Return: 0 for output, 1 for input
364 */
365static int zynq_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
366{
367 u32 reg;
368 unsigned int bank_num, bank_pin_num;
369 struct zynq_gpio *gpio = gpiochip_get_data(chip);
370
371 zynq_gpio_get_bank_pin(pin, &bank_num, &bank_pin_num, gpio);
372
373 reg = readl_relaxed(gpio->base_addr + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
374
375 return !(reg & BIT(bank_pin_num));
376}
377
378/**
379 * zynq_gpio_irq_mask - Disable the interrupts for a gpio pin
380 * @irq_data: per irq and chip data passed down to chip functions
381 *
382 * This function calculates gpio pin number from irq number and sets the
383 * bit in the Interrupt Disable register of the corresponding bank to disable
384 * interrupts for that pin.
385 */
386static void zynq_gpio_irq_mask(struct irq_data *irq_data)
387{
388 unsigned int device_pin_num, bank_num, bank_pin_num;
389 struct zynq_gpio *gpio =
390 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
391
392 device_pin_num = irq_data->hwirq;
393 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
394 writel_relaxed(BIT(bank_pin_num),
395 gpio->base_addr + ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
396}
397
398/**
399 * zynq_gpio_irq_unmask - Enable the interrupts for a gpio pin
400 * @irq_data: irq data containing irq number of gpio pin for the interrupt
401 * to enable
402 *
403 * This function calculates the gpio pin number from irq number and sets the
404 * bit in the Interrupt Enable register of the corresponding bank to enable
405 * interrupts for that pin.
406 */
407static void zynq_gpio_irq_unmask(struct irq_data *irq_data)
408{
409 unsigned int device_pin_num, bank_num, bank_pin_num;
410 struct zynq_gpio *gpio =
411 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
412
413 device_pin_num = irq_data->hwirq;
414 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
415 writel_relaxed(BIT(bank_pin_num),
416 gpio->base_addr + ZYNQ_GPIO_INTEN_OFFSET(bank_num));
417}
418
419/**
420 * zynq_gpio_irq_ack - Acknowledge the interrupt of a gpio pin
421 * @irq_data: irq data containing irq number of gpio pin for the interrupt
422 * to ack
423 *
424 * This function calculates gpio pin number from irq number and sets the bit
425 * in the Interrupt Status Register of the corresponding bank, to ACK the irq.
426 */
427static void zynq_gpio_irq_ack(struct irq_data *irq_data)
428{
429 unsigned int device_pin_num, bank_num, bank_pin_num;
430 struct zynq_gpio *gpio =
431 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
432
433 device_pin_num = irq_data->hwirq;
434 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
435 writel_relaxed(BIT(bank_pin_num),
436 gpio->base_addr + ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
437}
438
439/**
440 * zynq_gpio_irq_enable - Enable the interrupts for a gpio pin
441 * @irq_data: irq data containing irq number of gpio pin for the interrupt
442 * to enable
443 *
444 * Clears the INTSTS bit and unmasks the given interrupt.
445 */
446static void zynq_gpio_irq_enable(struct irq_data *irq_data)
447{
448 /*
449 * The Zynq GPIO controller does not disable interrupt detection when
450 * the interrupt is masked and only disables the propagation of the
451 * interrupt. This means when the controller detects an interrupt
452 * condition while the interrupt is logically disabled it will propagate
453 * that interrupt event once the interrupt is enabled. This will cause
454 * the interrupt consumer to see spurious interrupts to prevent this
455 * first make sure that the interrupt is not asserted and then enable
456 * it.
457 */
458 zynq_gpio_irq_ack(irq_data);
459 zynq_gpio_irq_unmask(irq_data);
460}
461
462/**
463 * zynq_gpio_set_irq_type - Set the irq type for a gpio pin
464 * @irq_data: irq data containing irq number of gpio pin
465 * @type: interrupt type that is to be set for the gpio pin
466 *
467 * This function gets the gpio pin number and its bank from the gpio pin number
468 * and configures the INT_TYPE, INT_POLARITY and INT_ANY registers.
469 *
470 * Return: 0, negative error otherwise.
471 * TYPE-EDGE_RISING, INT_TYPE - 1, INT_POLARITY - 1, INT_ANY - 0;
472 * TYPE-EDGE_FALLING, INT_TYPE - 1, INT_POLARITY - 0, INT_ANY - 0;
473 * TYPE-EDGE_BOTH, INT_TYPE - 1, INT_POLARITY - NA, INT_ANY - 1;
474 * TYPE-LEVEL_HIGH, INT_TYPE - 0, INT_POLARITY - 1, INT_ANY - NA;
475 * TYPE-LEVEL_LOW, INT_TYPE - 0, INT_POLARITY - 0, INT_ANY - NA
476 */
477static int zynq_gpio_set_irq_type(struct irq_data *irq_data, unsigned int type)
478{
479 u32 int_type, int_pol, int_any;
480 unsigned int device_pin_num, bank_num, bank_pin_num;
481 struct zynq_gpio *gpio =
482 gpiochip_get_data(irq_data_get_irq_chip_data(irq_data));
483
484 device_pin_num = irq_data->hwirq;
485 zynq_gpio_get_bank_pin(device_pin_num, &bank_num, &bank_pin_num, gpio);
486
487 int_type = readl_relaxed(gpio->base_addr +
488 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
489 int_pol = readl_relaxed(gpio->base_addr +
490 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
491 int_any = readl_relaxed(gpio->base_addr +
492 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
493
494 /*
495 * based on the type requested, configure the INT_TYPE, INT_POLARITY
496 * and INT_ANY registers
497 */
498 switch (type) {
499 case IRQ_TYPE_EDGE_RISING:
500 int_type |= BIT(bank_pin_num);
501 int_pol |= BIT(bank_pin_num);
502 int_any &= ~BIT(bank_pin_num);
503 break;
504 case IRQ_TYPE_EDGE_FALLING:
505 int_type |= BIT(bank_pin_num);
506 int_pol &= ~BIT(bank_pin_num);
507 int_any &= ~BIT(bank_pin_num);
508 break;
509 case IRQ_TYPE_EDGE_BOTH:
510 int_type |= BIT(bank_pin_num);
511 int_any |= BIT(bank_pin_num);
512 break;
513 case IRQ_TYPE_LEVEL_HIGH:
514 int_type &= ~BIT(bank_pin_num);
515 int_pol |= BIT(bank_pin_num);
516 break;
517 case IRQ_TYPE_LEVEL_LOW:
518 int_type &= ~BIT(bank_pin_num);
519 int_pol &= ~BIT(bank_pin_num);
520 break;
521 default:
522 return -EINVAL;
523 }
524
525 writel_relaxed(int_type,
526 gpio->base_addr + ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
527 writel_relaxed(int_pol,
528 gpio->base_addr + ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
529 writel_relaxed(int_any,
530 gpio->base_addr + ZYNQ_GPIO_INTANY_OFFSET(bank_num));
531
532 if (type & IRQ_TYPE_LEVEL_MASK)
533 irq_set_chip_handler_name_locked(irq_data,
534 &zynq_gpio_level_irqchip,
535 handle_fasteoi_irq, NULL);
536 else
537 irq_set_chip_handler_name_locked(irq_data,
538 &zynq_gpio_edge_irqchip,
539 handle_level_irq, NULL);
540
541 return 0;
542}
543
544static int zynq_gpio_set_wake(struct irq_data *data, unsigned int on)
545{
546 struct zynq_gpio *gpio =
547 gpiochip_get_data(irq_data_get_irq_chip_data(data));
548
549 irq_set_irq_wake(gpio->irq, on);
550
551 return 0;
552}
553
554static int zynq_gpio_irq_reqres(struct irq_data *d)
555{
556 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
557 int ret;
558
559 ret = pm_runtime_get_sync(chip->parent);
560 if (ret < 0)
561 return ret;
562
563 return gpiochip_reqres_irq(chip, d->hwirq);
564}
565
566static void zynq_gpio_irq_relres(struct irq_data *d)
567{
568 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
569
570 gpiochip_relres_irq(chip, d->hwirq);
571 pm_runtime_put(chip->parent);
572}
573
574/* irq chip descriptor */
575static struct irq_chip zynq_gpio_level_irqchip = {
576 .name = DRIVER_NAME,
577 .irq_enable = zynq_gpio_irq_enable,
578 .irq_eoi = zynq_gpio_irq_ack,
579 .irq_mask = zynq_gpio_irq_mask,
580 .irq_unmask = zynq_gpio_irq_unmask,
581 .irq_set_type = zynq_gpio_set_irq_type,
582 .irq_set_wake = zynq_gpio_set_wake,
583 .irq_request_resources = zynq_gpio_irq_reqres,
584 .irq_release_resources = zynq_gpio_irq_relres,
585 .flags = IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_HANDLED |
586 IRQCHIP_MASK_ON_SUSPEND,
587};
588
589static struct irq_chip zynq_gpio_edge_irqchip = {
590 .name = DRIVER_NAME,
591 .irq_enable = zynq_gpio_irq_enable,
592 .irq_ack = zynq_gpio_irq_ack,
593 .irq_mask = zynq_gpio_irq_mask,
594 .irq_unmask = zynq_gpio_irq_unmask,
595 .irq_set_type = zynq_gpio_set_irq_type,
596 .irq_set_wake = zynq_gpio_set_wake,
597 .irq_request_resources = zynq_gpio_irq_reqres,
598 .irq_release_resources = zynq_gpio_irq_relres,
599 .flags = IRQCHIP_MASK_ON_SUSPEND,
600};
601
602static void zynq_gpio_handle_bank_irq(struct zynq_gpio *gpio,
603 unsigned int bank_num,
604 unsigned long pending)
605{
606 unsigned int bank_offset = gpio->p_data->bank_min[bank_num];
607 struct irq_domain *irqdomain = gpio->chip.irq.domain;
608 int offset;
609
610 if (!pending)
611 return;
612
613 for_each_set_bit(offset, &pending, 32) {
614 unsigned int gpio_irq;
615
616 gpio_irq = irq_find_mapping(irqdomain, offset + bank_offset);
617 generic_handle_irq(gpio_irq);
618 }
619}
620
621/**
622 * zynq_gpio_irqhandler - IRQ handler for the gpio banks of a gpio device
623 * @desc: irq descriptor instance of the 'irq'
624 *
625 * This function reads the Interrupt Status Register of each bank to get the
626 * gpio pin number which has triggered an interrupt. It then acks the triggered
627 * interrupt and calls the pin specific handler set by the higher layer
628 * application for that pin.
629 * Note: A bug is reported if no handler is set for the gpio pin.
630 */
631static void zynq_gpio_irqhandler(struct irq_desc *desc)
632{
633 u32 int_sts, int_enb;
634 unsigned int bank_num;
635 struct zynq_gpio *gpio =
636 gpiochip_get_data(irq_desc_get_handler_data(desc));
637 struct irq_chip *irqchip = irq_desc_get_chip(desc);
638
639 chained_irq_enter(irqchip, desc);
640
641 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
642 int_sts = readl_relaxed(gpio->base_addr +
643 ZYNQ_GPIO_INTSTS_OFFSET(bank_num));
644 int_enb = readl_relaxed(gpio->base_addr +
645 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
646 zynq_gpio_handle_bank_irq(gpio, bank_num, int_sts & ~int_enb);
647 }
648
649 chained_irq_exit(irqchip, desc);
650}
651
652static void zynq_gpio_save_context(struct zynq_gpio *gpio)
653{
654 unsigned int bank_num;
655
656 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
657 gpio->context.datalsw[bank_num] =
658 readl_relaxed(gpio->base_addr +
659 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
660 gpio->context.datamsw[bank_num] =
661 readl_relaxed(gpio->base_addr +
662 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
663 gpio->context.dirm[bank_num] = readl_relaxed(gpio->base_addr +
664 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
665 gpio->context.int_en[bank_num] = readl_relaxed(gpio->base_addr +
666 ZYNQ_GPIO_INTMASK_OFFSET(bank_num));
667 gpio->context.int_type[bank_num] =
668 readl_relaxed(gpio->base_addr +
669 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
670 gpio->context.int_polarity[bank_num] =
671 readl_relaxed(gpio->base_addr +
672 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
673 gpio->context.int_any[bank_num] =
674 readl_relaxed(gpio->base_addr +
675 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
676 }
677}
678
679static void zynq_gpio_restore_context(struct zynq_gpio *gpio)
680{
681 unsigned int bank_num;
682
683 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++) {
684 writel_relaxed(gpio->context.datalsw[bank_num],
685 gpio->base_addr +
686 ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num));
687 writel_relaxed(gpio->context.datamsw[bank_num],
688 gpio->base_addr +
689 ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num));
690 writel_relaxed(gpio->context.dirm[bank_num],
691 gpio->base_addr +
692 ZYNQ_GPIO_DIRM_OFFSET(bank_num));
693 writel_relaxed(gpio->context.int_en[bank_num],
694 gpio->base_addr +
695 ZYNQ_GPIO_INTEN_OFFSET(bank_num));
696 writel_relaxed(gpio->context.int_type[bank_num],
697 gpio->base_addr +
698 ZYNQ_GPIO_INTTYPE_OFFSET(bank_num));
699 writel_relaxed(gpio->context.int_polarity[bank_num],
700 gpio->base_addr +
701 ZYNQ_GPIO_INTPOL_OFFSET(bank_num));
702 writel_relaxed(gpio->context.int_any[bank_num],
703 gpio->base_addr +
704 ZYNQ_GPIO_INTANY_OFFSET(bank_num));
705 }
706}
707
708static int __maybe_unused zynq_gpio_suspend(struct device *dev)
709{
710 struct zynq_gpio *gpio = dev_get_drvdata(dev);
711 struct irq_data *data = irq_get_irq_data(gpio->irq);
712
713 if (!irqd_is_wakeup_set(data)) {
714 zynq_gpio_save_context(gpio);
715 return pm_runtime_force_suspend(dev);
716 }
717
718 return 0;
719}
720
721static int __maybe_unused zynq_gpio_resume(struct device *dev)
722{
723 struct zynq_gpio *gpio = dev_get_drvdata(dev);
724 struct irq_data *data = irq_get_irq_data(gpio->irq);
725 int ret;
726
727 if (!irqd_is_wakeup_set(data)) {
728 ret = pm_runtime_force_resume(dev);
729 zynq_gpio_restore_context(gpio);
730 return ret;
731 }
732
733 return 0;
734}
735
736static int __maybe_unused zynq_gpio_runtime_suspend(struct device *dev)
737{
738 struct zynq_gpio *gpio = dev_get_drvdata(dev);
739
740 clk_disable_unprepare(gpio->clk);
741
742 return 0;
743}
744
745static int __maybe_unused zynq_gpio_runtime_resume(struct device *dev)
746{
747 struct zynq_gpio *gpio = dev_get_drvdata(dev);
748
749 return clk_prepare_enable(gpio->clk);
750}
751
752static int zynq_gpio_request(struct gpio_chip *chip, unsigned int offset)
753{
754 int ret;
755
756 ret = pm_runtime_get_sync(chip->parent);
757
758 /*
759 * If the device is already active pm_runtime_get() will return 1 on
760 * success, but gpio_request still needs to return 0.
761 */
762 return ret < 0 ? ret : 0;
763}
764
765static void zynq_gpio_free(struct gpio_chip *chip, unsigned int offset)
766{
767 pm_runtime_put(chip->parent);
768}
769
770static const struct dev_pm_ops zynq_gpio_dev_pm_ops = {
771 SET_SYSTEM_SLEEP_PM_OPS(zynq_gpio_suspend, zynq_gpio_resume)
772 SET_RUNTIME_PM_OPS(zynq_gpio_runtime_suspend,
773 zynq_gpio_runtime_resume, NULL)
774};
775
776static const struct zynq_platform_data zynqmp_gpio_def = {
777 .label = "zynqmp_gpio",
778 .quirks = GPIO_QUIRK_DATA_RO_BUG,
779 .ngpio = ZYNQMP_GPIO_NR_GPIOS,
780 .max_bank = ZYNQMP_GPIO_MAX_BANK,
781 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
782 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
783 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
784 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
785 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
786 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
787 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
788 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
789 .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
790 .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
791 .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
792 .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
793};
794
795static const struct zynq_platform_data zynq_gpio_def = {
796 .label = "zynq_gpio",
797 .quirks = ZYNQ_GPIO_QUIRK_IS_ZYNQ | GPIO_QUIRK_DATA_RO_BUG,
798 .ngpio = ZYNQ_GPIO_NR_GPIOS,
799 .max_bank = ZYNQ_GPIO_MAX_BANK,
800 .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
801 .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
802 .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
803 .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
804 .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
805 .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
806 .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
807 .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
808};
809
810static const struct of_device_id zynq_gpio_of_match[] = {
811 { .compatible = "xlnx,zynq-gpio-1.0", .data = &zynq_gpio_def },
812 { .compatible = "xlnx,zynqmp-gpio-1.0", .data = &zynqmp_gpio_def },
813 { /* end of table */ }
814};
815MODULE_DEVICE_TABLE(of, zynq_gpio_of_match);
816
817/**
818 * zynq_gpio_probe - Initialization method for a zynq_gpio device
819 * @pdev: platform device instance
820 *
821 * This function allocates memory resources for the gpio device and registers
822 * all the banks of the device. It will also set up interrupts for the gpio
823 * pins.
824 * Note: Interrupts are disabled for all the banks during initialization.
825 *
826 * Return: 0 on success, negative error otherwise.
827 */
828static int zynq_gpio_probe(struct platform_device *pdev)
829{
830 int ret, bank_num;
831 struct zynq_gpio *gpio;
832 struct gpio_chip *chip;
833 struct gpio_irq_chip *girq;
834 const struct of_device_id *match;
835
836 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
837 if (!gpio)
838 return -ENOMEM;
839
840 match = of_match_node(zynq_gpio_of_match, pdev->dev.of_node);
841 if (!match) {
842 dev_err(&pdev->dev, "of_match_node() failed\n");
843 return -EINVAL;
844 }
845 gpio->p_data = match->data;
846 platform_set_drvdata(pdev, gpio);
847
848 gpio->base_addr = devm_platform_ioremap_resource(pdev, 0);
849 if (IS_ERR(gpio->base_addr))
850 return PTR_ERR(gpio->base_addr);
851
852 gpio->irq = platform_get_irq(pdev, 0);
853 if (gpio->irq < 0)
854 return gpio->irq;
855
856 /* configure the gpio chip */
857 chip = &gpio->chip;
858 chip->label = gpio->p_data->label;
859 chip->owner = THIS_MODULE;
860 chip->parent = &pdev->dev;
861 chip->get = zynq_gpio_get_value;
862 chip->set = zynq_gpio_set_value;
863 chip->request = zynq_gpio_request;
864 chip->free = zynq_gpio_free;
865 chip->direction_input = zynq_gpio_dir_in;
866 chip->direction_output = zynq_gpio_dir_out;
867 chip->get_direction = zynq_gpio_get_direction;
868 chip->base = of_alias_get_id(pdev->dev.of_node, "gpio");
869 chip->ngpio = gpio->p_data->ngpio;
870
871 /* Retrieve GPIO clock */
872 gpio->clk = devm_clk_get(&pdev->dev, NULL);
873 if (IS_ERR(gpio->clk)) {
874 dev_err(&pdev->dev, "input clock not found.\n");
875 return PTR_ERR(gpio->clk);
876 }
877 ret = clk_prepare_enable(gpio->clk);
878 if (ret) {
879 dev_err(&pdev->dev, "Unable to enable clock.\n");
880 return ret;
881 }
882
883 pm_runtime_set_active(&pdev->dev);
884 pm_runtime_enable(&pdev->dev);
885 ret = pm_runtime_get_sync(&pdev->dev);
886 if (ret < 0)
887 goto err_pm_dis;
888
889 /* disable interrupts for all banks */
890 for (bank_num = 0; bank_num < gpio->p_data->max_bank; bank_num++)
891 writel_relaxed(ZYNQ_GPIO_IXR_DISABLE_ALL, gpio->base_addr +
892 ZYNQ_GPIO_INTDIS_OFFSET(bank_num));
893
894 /* Set up the GPIO irqchip */
895 girq = &chip->irq;
896 girq->chip = &zynq_gpio_edge_irqchip;
897 girq->parent_handler = zynq_gpio_irqhandler;
898 girq->num_parents = 1;
899 girq->parents = devm_kcalloc(&pdev->dev, 1,
900 sizeof(*girq->parents),
901 GFP_KERNEL);
902 if (!girq->parents) {
903 ret = -ENOMEM;
904 goto err_pm_put;
905 }
906 girq->parents[0] = gpio->irq;
907 girq->default_type = IRQ_TYPE_NONE;
908 girq->handler = handle_level_irq;
909
910 /* report a bug if gpio chip registration fails */
911 ret = gpiochip_add_data(chip, gpio);
912 if (ret) {
913 dev_err(&pdev->dev, "Failed to add gpio chip\n");
914 goto err_pm_put;
915 }
916
917 pm_runtime_put(&pdev->dev);
918
919 return 0;
920
921err_pm_put:
922 pm_runtime_put(&pdev->dev);
923err_pm_dis:
924 pm_runtime_disable(&pdev->dev);
925 clk_disable_unprepare(gpio->clk);
926
927 return ret;
928}
929
930/**
931 * zynq_gpio_remove - Driver removal function
932 * @pdev: platform device instance
933 *
934 * Return: 0 always
935 */
936static int zynq_gpio_remove(struct platform_device *pdev)
937{
938 struct zynq_gpio *gpio = platform_get_drvdata(pdev);
939
940 pm_runtime_get_sync(&pdev->dev);
941 gpiochip_remove(&gpio->chip);
942 clk_disable_unprepare(gpio->clk);
943 device_set_wakeup_capable(&pdev->dev, 0);
944 pm_runtime_disable(&pdev->dev);
945 return 0;
946}
947
948static struct platform_driver zynq_gpio_driver = {
949 .driver = {
950 .name = DRIVER_NAME,
951 .pm = &zynq_gpio_dev_pm_ops,
952 .of_match_table = zynq_gpio_of_match,
953 },
954 .probe = zynq_gpio_probe,
955 .remove = zynq_gpio_remove,
956};
957
958/**
959 * zynq_gpio_init - Initial driver registration call
960 *
961 * Return: value from platform_driver_register
962 */
963static int __init zynq_gpio_init(void)
964{
965 return platform_driver_register(&zynq_gpio_driver);
966}
967postcore_initcall(zynq_gpio_init);
968
969static void __exit zynq_gpio_exit(void)
970{
971 platform_driver_unregister(&zynq_gpio_driver);
972}
973module_exit(zynq_gpio_exit);
974
975MODULE_AUTHOR("Xilinx Inc.");
976MODULE_DESCRIPTION("Zynq GPIO driver");
977MODULE_LICENSE("GPL");