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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car GPIO Support
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 */
8
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/spinlock.h>
23#include <linux/slab.h>
24
25struct gpio_rcar_bank_info {
26 u32 iointsel;
27 u32 inoutsel;
28 u32 outdt;
29 u32 posneg;
30 u32 edglevel;
31 u32 bothedge;
32 u32 intmsk;
33};
34
35struct gpio_rcar_priv {
36 void __iomem *base;
37 spinlock_t lock;
38 struct device *dev;
39 struct gpio_chip gpio_chip;
40 struct irq_chip irq_chip;
41 unsigned int irq_parent;
42 atomic_t wakeup_path;
43 bool has_outdtsel;
44 bool has_both_edge_trigger;
45 struct gpio_rcar_bank_info bank_info;
46};
47
48#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
49#define INOUTSEL 0x04 /* General Input/Output Switching Register */
50#define OUTDT 0x08 /* General Output Register */
51#define INDT 0x0c /* General Input Register */
52#define INTDT 0x10 /* Interrupt Display Register */
53#define INTCLR 0x14 /* Interrupt Clear Register */
54#define INTMSK 0x18 /* Interrupt Mask Register */
55#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
56#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
57#define EDGLEVEL 0x24 /* Edge/level Select Register */
58#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
59#define OUTDTSEL 0x40 /* Output Data Select Register */
60#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
61
62#define RCAR_MAX_GPIO_PER_BANK 32
63
64static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
65{
66 return ioread32(p->base + offs);
67}
68
69static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
70 u32 value)
71{
72 iowrite32(value, p->base + offs);
73}
74
75static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
76 int bit, bool value)
77{
78 u32 tmp = gpio_rcar_read(p, offs);
79
80 if (value)
81 tmp |= BIT(bit);
82 else
83 tmp &= ~BIT(bit);
84
85 gpio_rcar_write(p, offs, tmp);
86}
87
88static void gpio_rcar_irq_disable(struct irq_data *d)
89{
90 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
91 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
92
93 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
94}
95
96static void gpio_rcar_irq_enable(struct irq_data *d)
97{
98 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
99 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
100
101 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
102}
103
104static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
105 unsigned int hwirq,
106 bool active_high_rising_edge,
107 bool level_trigger,
108 bool both)
109{
110 unsigned long flags;
111
112 /* follow steps in the GPIO documentation for
113 * "Setting Edge-Sensitive Interrupt Input Mode" and
114 * "Setting Level-Sensitive Interrupt Input Mode"
115 */
116
117 spin_lock_irqsave(&p->lock, flags);
118
119 /* Configure positive or negative logic in POSNEG */
120 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
121
122 /* Configure edge or level trigger in EDGLEVEL */
123 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
124
125 /* Select one edge or both edges in BOTHEDGE */
126 if (p->has_both_edge_trigger)
127 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
128
129 /* Select "Interrupt Input Mode" in IOINTSEL */
130 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
131
132 /* Write INTCLR in case of edge trigger */
133 if (!level_trigger)
134 gpio_rcar_write(p, INTCLR, BIT(hwirq));
135
136 spin_unlock_irqrestore(&p->lock, flags);
137}
138
139static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
140{
141 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
142 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
143 unsigned int hwirq = irqd_to_hwirq(d);
144
145 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
146
147 switch (type & IRQ_TYPE_SENSE_MASK) {
148 case IRQ_TYPE_LEVEL_HIGH:
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
150 false);
151 break;
152 case IRQ_TYPE_LEVEL_LOW:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
154 false);
155 break;
156 case IRQ_TYPE_EDGE_RISING:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
158 false);
159 break;
160 case IRQ_TYPE_EDGE_FALLING:
161 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
162 false);
163 break;
164 case IRQ_TYPE_EDGE_BOTH:
165 if (!p->has_both_edge_trigger)
166 return -EINVAL;
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
168 true);
169 break;
170 default:
171 return -EINVAL;
172 }
173 return 0;
174}
175
176static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
177{
178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
179 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
180 int error;
181
182 if (p->irq_parent) {
183 error = irq_set_irq_wake(p->irq_parent, on);
184 if (error) {
185 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
186 p->irq_parent);
187 p->irq_parent = 0;
188 }
189 }
190
191 if (on)
192 atomic_inc(&p->wakeup_path);
193 else
194 atomic_dec(&p->wakeup_path);
195
196 return 0;
197}
198
199static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200{
201 struct gpio_rcar_priv *p = dev_id;
202 u32 pending;
203 unsigned int offset, irqs_handled = 0;
204
205 while ((pending = gpio_rcar_read(p, INTDT) &
206 gpio_rcar_read(p, INTMSK))) {
207 offset = __ffs(pending);
208 gpio_rcar_write(p, INTCLR, BIT(offset));
209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
210 offset));
211 irqs_handled++;
212 }
213
214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215}
216
217static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 unsigned int gpio,
219 bool output)
220{
221 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 unsigned long flags;
223
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
227 */
228
229 spin_lock_irqsave(&p->lock, flags);
230
231 /* Configure positive logic in POSNEG */
232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239
240 /* Select General Output Register to output data in OUTDTSEL */
241 if (p->has_outdtsel && output)
242 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
243
244 spin_unlock_irqrestore(&p->lock, flags);
245}
246
247static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
248{
249 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
250 int error;
251
252 error = pm_runtime_get_sync(p->dev);
253 if (error < 0) {
254 pm_runtime_put(p->dev);
255 return error;
256 }
257
258 error = pinctrl_gpio_request(chip->base + offset);
259 if (error)
260 pm_runtime_put(p->dev);
261
262 return error;
263}
264
265static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
266{
267 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
268
269 pinctrl_gpio_free(chip->base + offset);
270
271 /*
272 * Set the GPIO as an input to ensure that the next GPIO request won't
273 * drive the GPIO pin as an output.
274 */
275 gpio_rcar_config_general_input_output_mode(chip, offset, false);
276
277 pm_runtime_put(p->dev);
278}
279
280static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
281{
282 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
283
284 if (gpio_rcar_read(p, INOUTSEL) & BIT(offset))
285 return GPIO_LINE_DIRECTION_OUT;
286
287 return GPIO_LINE_DIRECTION_IN;
288}
289
290static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
291{
292 gpio_rcar_config_general_input_output_mode(chip, offset, false);
293 return 0;
294}
295
296static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
297{
298 u32 bit = BIT(offset);
299
300 /* testing on r8a7790 shows that INDT does not show correct pin state
301 * when configured as output, so use OUTDT in case of output pins */
302 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
303 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
304 else
305 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
306}
307
308static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
309{
310 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
311 unsigned long flags;
312
313 spin_lock_irqsave(&p->lock, flags);
314 gpio_rcar_modify_bit(p, OUTDT, offset, value);
315 spin_unlock_irqrestore(&p->lock, flags);
316}
317
318static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
319 unsigned long *bits)
320{
321 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
322 unsigned long flags;
323 u32 val, bankmask;
324
325 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
326 if (chip->valid_mask)
327 bankmask &= chip->valid_mask[0];
328
329 if (!bankmask)
330 return;
331
332 spin_lock_irqsave(&p->lock, flags);
333 val = gpio_rcar_read(p, OUTDT);
334 val &= ~bankmask;
335 val |= (bankmask & bits[0]);
336 gpio_rcar_write(p, OUTDT, val);
337 spin_unlock_irqrestore(&p->lock, flags);
338}
339
340static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
341 int value)
342{
343 /* write GPIO value to output before selecting output mode of pin */
344 gpio_rcar_set(chip, offset, value);
345 gpio_rcar_config_general_input_output_mode(chip, offset, true);
346 return 0;
347}
348
349struct gpio_rcar_info {
350 bool has_outdtsel;
351 bool has_both_edge_trigger;
352};
353
354static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
355 .has_outdtsel = false,
356 .has_both_edge_trigger = false,
357};
358
359static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
360 .has_outdtsel = true,
361 .has_both_edge_trigger = true,
362};
363
364static const struct of_device_id gpio_rcar_of_table[] = {
365 {
366 .compatible = "renesas,gpio-r8a7743",
367 /* RZ/G1 GPIO is identical to R-Car Gen2. */
368 .data = &gpio_rcar_info_gen2,
369 }, {
370 .compatible = "renesas,gpio-r8a7790",
371 .data = &gpio_rcar_info_gen2,
372 }, {
373 .compatible = "renesas,gpio-r8a7791",
374 .data = &gpio_rcar_info_gen2,
375 }, {
376 .compatible = "renesas,gpio-r8a7792",
377 .data = &gpio_rcar_info_gen2,
378 }, {
379 .compatible = "renesas,gpio-r8a7793",
380 .data = &gpio_rcar_info_gen2,
381 }, {
382 .compatible = "renesas,gpio-r8a7794",
383 .data = &gpio_rcar_info_gen2,
384 }, {
385 .compatible = "renesas,gpio-r8a7795",
386 /* Gen3 GPIO is identical to Gen2. */
387 .data = &gpio_rcar_info_gen2,
388 }, {
389 .compatible = "renesas,gpio-r8a7796",
390 /* Gen3 GPIO is identical to Gen2. */
391 .data = &gpio_rcar_info_gen2,
392 }, {
393 .compatible = "renesas,rcar-gen1-gpio",
394 .data = &gpio_rcar_info_gen1,
395 }, {
396 .compatible = "renesas,rcar-gen2-gpio",
397 .data = &gpio_rcar_info_gen2,
398 }, {
399 .compatible = "renesas,rcar-gen3-gpio",
400 /* Gen3 GPIO is identical to Gen2. */
401 .data = &gpio_rcar_info_gen2,
402 }, {
403 .compatible = "renesas,gpio-rcar",
404 .data = &gpio_rcar_info_gen1,
405 }, {
406 /* Terminator */
407 },
408};
409
410MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
411
412static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
413{
414 struct device_node *np = p->dev->of_node;
415 const struct gpio_rcar_info *info;
416 struct of_phandle_args args;
417 int ret;
418
419 info = of_device_get_match_data(p->dev);
420 p->has_outdtsel = info->has_outdtsel;
421 p->has_both_edge_trigger = info->has_both_edge_trigger;
422
423 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
424 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
425
426 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
427 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
428 *npins, RCAR_MAX_GPIO_PER_BANK);
429 *npins = RCAR_MAX_GPIO_PER_BANK;
430 }
431
432 return 0;
433}
434
435static int gpio_rcar_probe(struct platform_device *pdev)
436{
437 struct gpio_rcar_priv *p;
438 struct resource *irq;
439 struct gpio_chip *gpio_chip;
440 struct irq_chip *irq_chip;
441 struct gpio_irq_chip *girq;
442 struct device *dev = &pdev->dev;
443 const char *name = dev_name(dev);
444 unsigned int npins;
445 int ret;
446
447 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
448 if (!p)
449 return -ENOMEM;
450
451 p->dev = dev;
452 spin_lock_init(&p->lock);
453
454 /* Get device configuration from DT node */
455 ret = gpio_rcar_parse_dt(p, &npins);
456 if (ret < 0)
457 return ret;
458
459 platform_set_drvdata(pdev, p);
460
461 pm_runtime_enable(dev);
462
463 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
464 if (!irq) {
465 dev_err(dev, "missing IRQ\n");
466 ret = -EINVAL;
467 goto err0;
468 }
469
470 p->base = devm_platform_ioremap_resource(pdev, 0);
471 if (IS_ERR(p->base)) {
472 ret = PTR_ERR(p->base);
473 goto err0;
474 }
475
476 gpio_chip = &p->gpio_chip;
477 gpio_chip->request = gpio_rcar_request;
478 gpio_chip->free = gpio_rcar_free;
479 gpio_chip->get_direction = gpio_rcar_get_direction;
480 gpio_chip->direction_input = gpio_rcar_direction_input;
481 gpio_chip->get = gpio_rcar_get;
482 gpio_chip->direction_output = gpio_rcar_direction_output;
483 gpio_chip->set = gpio_rcar_set;
484 gpio_chip->set_multiple = gpio_rcar_set_multiple;
485 gpio_chip->label = name;
486 gpio_chip->parent = dev;
487 gpio_chip->owner = THIS_MODULE;
488 gpio_chip->base = -1;
489 gpio_chip->ngpio = npins;
490
491 irq_chip = &p->irq_chip;
492 irq_chip->name = "gpio-rcar";
493 irq_chip->parent_device = dev;
494 irq_chip->irq_mask = gpio_rcar_irq_disable;
495 irq_chip->irq_unmask = gpio_rcar_irq_enable;
496 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
497 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
498 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
499
500 girq = &gpio_chip->irq;
501 girq->chip = irq_chip;
502 /* This will let us handle the parent IRQ in the driver */
503 girq->parent_handler = NULL;
504 girq->num_parents = 0;
505 girq->parents = NULL;
506 girq->default_type = IRQ_TYPE_NONE;
507 girq->handler = handle_level_irq;
508
509 ret = gpiochip_add_data(gpio_chip, p);
510 if (ret) {
511 dev_err(dev, "failed to add GPIO controller\n");
512 goto err0;
513 }
514
515 p->irq_parent = irq->start;
516 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
517 IRQF_SHARED, name, p)) {
518 dev_err(dev, "failed to request IRQ\n");
519 ret = -ENOENT;
520 goto err1;
521 }
522
523 dev_info(dev, "driving %d GPIOs\n", npins);
524
525 return 0;
526
527err1:
528 gpiochip_remove(gpio_chip);
529err0:
530 pm_runtime_disable(dev);
531 return ret;
532}
533
534static int gpio_rcar_remove(struct platform_device *pdev)
535{
536 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
537
538 gpiochip_remove(&p->gpio_chip);
539
540 pm_runtime_disable(&pdev->dev);
541 return 0;
542}
543
544#ifdef CONFIG_PM_SLEEP
545static int gpio_rcar_suspend(struct device *dev)
546{
547 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
548
549 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
550 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
551 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
552 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
553 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
554 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
555 if (p->has_both_edge_trigger)
556 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
557
558 if (atomic_read(&p->wakeup_path))
559 device_set_wakeup_path(dev);
560
561 return 0;
562}
563
564static int gpio_rcar_resume(struct device *dev)
565{
566 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
567 unsigned int offset;
568 u32 mask;
569
570 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
571 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
572 continue;
573
574 mask = BIT(offset);
575 /* I/O pin */
576 if (!(p->bank_info.iointsel & mask)) {
577 if (p->bank_info.inoutsel & mask)
578 gpio_rcar_direction_output(
579 &p->gpio_chip, offset,
580 !!(p->bank_info.outdt & mask));
581 else
582 gpio_rcar_direction_input(&p->gpio_chip,
583 offset);
584 } else {
585 /* Interrupt pin */
586 gpio_rcar_config_interrupt_input_mode(
587 p,
588 offset,
589 !(p->bank_info.posneg & mask),
590 !(p->bank_info.edglevel & mask),
591 !!(p->bank_info.bothedge & mask));
592
593 if (p->bank_info.intmsk & mask)
594 gpio_rcar_write(p, MSKCLR, mask);
595 }
596 }
597
598 return 0;
599}
600#endif /* CONFIG_PM_SLEEP*/
601
602static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
603
604static struct platform_driver gpio_rcar_device_driver = {
605 .probe = gpio_rcar_probe,
606 .remove = gpio_rcar_remove,
607 .driver = {
608 .name = "gpio_rcar",
609 .pm = &gpio_rcar_pm_ops,
610 .of_match_table = of_match_ptr(gpio_rcar_of_table),
611 }
612};
613
614module_platform_driver(gpio_rcar_device_driver);
615
616MODULE_AUTHOR("Magnus Damm");
617MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
618MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas R-Car GPIO Support
4 *
5 * Copyright (C) 2014 Renesas Electronics Corporation
6 * Copyright (C) 2013 Magnus Damm
7 */
8
9#include <linux/err.h>
10#include <linux/gpio/driver.h>
11#include <linux/init.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/ioport.h>
15#include <linux/irq.h>
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/consumer.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/spinlock.h>
23#include <linux/slab.h>
24
25struct gpio_rcar_bank_info {
26 u32 iointsel;
27 u32 inoutsel;
28 u32 outdt;
29 u32 posneg;
30 u32 edglevel;
31 u32 bothedge;
32 u32 intmsk;
33};
34
35struct gpio_rcar_priv {
36 void __iomem *base;
37 spinlock_t lock;
38 struct device *dev;
39 struct gpio_chip gpio_chip;
40 struct irq_chip irq_chip;
41 unsigned int irq_parent;
42 atomic_t wakeup_path;
43 bool has_outdtsel;
44 bool has_both_edge_trigger;
45 struct gpio_rcar_bank_info bank_info;
46};
47
48#define IOINTSEL 0x00 /* General IO/Interrupt Switching Register */
49#define INOUTSEL 0x04 /* General Input/Output Switching Register */
50#define OUTDT 0x08 /* General Output Register */
51#define INDT 0x0c /* General Input Register */
52#define INTDT 0x10 /* Interrupt Display Register */
53#define INTCLR 0x14 /* Interrupt Clear Register */
54#define INTMSK 0x18 /* Interrupt Mask Register */
55#define MSKCLR 0x1c /* Interrupt Mask Clear Register */
56#define POSNEG 0x20 /* Positive/Negative Logic Select Register */
57#define EDGLEVEL 0x24 /* Edge/level Select Register */
58#define FILONOFF 0x28 /* Chattering Prevention On/Off Register */
59#define OUTDTSEL 0x40 /* Output Data Select Register */
60#define BOTHEDGE 0x4c /* One Edge/Both Edge Select Register */
61
62#define RCAR_MAX_GPIO_PER_BANK 32
63
64static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
65{
66 return ioread32(p->base + offs);
67}
68
69static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
70 u32 value)
71{
72 iowrite32(value, p->base + offs);
73}
74
75static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
76 int bit, bool value)
77{
78 u32 tmp = gpio_rcar_read(p, offs);
79
80 if (value)
81 tmp |= BIT(bit);
82 else
83 tmp &= ~BIT(bit);
84
85 gpio_rcar_write(p, offs, tmp);
86}
87
88static void gpio_rcar_irq_disable(struct irq_data *d)
89{
90 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
91 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
92
93 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
94}
95
96static void gpio_rcar_irq_enable(struct irq_data *d)
97{
98 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
99 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
100
101 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
102}
103
104static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
105 unsigned int hwirq,
106 bool active_high_rising_edge,
107 bool level_trigger,
108 bool both)
109{
110 unsigned long flags;
111
112 /* follow steps in the GPIO documentation for
113 * "Setting Edge-Sensitive Interrupt Input Mode" and
114 * "Setting Level-Sensitive Interrupt Input Mode"
115 */
116
117 spin_lock_irqsave(&p->lock, flags);
118
119 /* Configure postive or negative logic in POSNEG */
120 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
121
122 /* Configure edge or level trigger in EDGLEVEL */
123 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
124
125 /* Select one edge or both edges in BOTHEDGE */
126 if (p->has_both_edge_trigger)
127 gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
128
129 /* Select "Interrupt Input Mode" in IOINTSEL */
130 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
131
132 /* Write INTCLR in case of edge trigger */
133 if (!level_trigger)
134 gpio_rcar_write(p, INTCLR, BIT(hwirq));
135
136 spin_unlock_irqrestore(&p->lock, flags);
137}
138
139static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
140{
141 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
142 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
143 unsigned int hwirq = irqd_to_hwirq(d);
144
145 dev_dbg(p->dev, "sense irq = %d, type = %d\n", hwirq, type);
146
147 switch (type & IRQ_TYPE_SENSE_MASK) {
148 case IRQ_TYPE_LEVEL_HIGH:
149 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
150 false);
151 break;
152 case IRQ_TYPE_LEVEL_LOW:
153 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
154 false);
155 break;
156 case IRQ_TYPE_EDGE_RISING:
157 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
158 false);
159 break;
160 case IRQ_TYPE_EDGE_FALLING:
161 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
162 false);
163 break;
164 case IRQ_TYPE_EDGE_BOTH:
165 if (!p->has_both_edge_trigger)
166 return -EINVAL;
167 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
168 true);
169 break;
170 default:
171 return -EINVAL;
172 }
173 return 0;
174}
175
176static int gpio_rcar_irq_set_wake(struct irq_data *d, unsigned int on)
177{
178 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
179 struct gpio_rcar_priv *p = gpiochip_get_data(gc);
180 int error;
181
182 if (p->irq_parent) {
183 error = irq_set_irq_wake(p->irq_parent, on);
184 if (error) {
185 dev_dbg(p->dev, "irq %u doesn't support irq_set_wake\n",
186 p->irq_parent);
187 p->irq_parent = 0;
188 }
189 }
190
191 if (on)
192 atomic_inc(&p->wakeup_path);
193 else
194 atomic_dec(&p->wakeup_path);
195
196 return 0;
197}
198
199static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
200{
201 struct gpio_rcar_priv *p = dev_id;
202 u32 pending;
203 unsigned int offset, irqs_handled = 0;
204
205 while ((pending = gpio_rcar_read(p, INTDT) &
206 gpio_rcar_read(p, INTMSK))) {
207 offset = __ffs(pending);
208 gpio_rcar_write(p, INTCLR, BIT(offset));
209 generic_handle_irq(irq_find_mapping(p->gpio_chip.irq.domain,
210 offset));
211 irqs_handled++;
212 }
213
214 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
215}
216
217static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
218 unsigned int gpio,
219 bool output)
220{
221 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
222 unsigned long flags;
223
224 /* follow steps in the GPIO documentation for
225 * "Setting General Output Mode" and
226 * "Setting General Input Mode"
227 */
228
229 spin_lock_irqsave(&p->lock, flags);
230
231 /* Configure postive logic in POSNEG */
232 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
233
234 /* Select "General Input/Output Mode" in IOINTSEL */
235 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
236
237 /* Select Input Mode or Output Mode in INOUTSEL */
238 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
239
240 /* Select General Output Register to output data in OUTDTSEL */
241 if (p->has_outdtsel && output)
242 gpio_rcar_modify_bit(p, OUTDTSEL, gpio, false);
243
244 spin_unlock_irqrestore(&p->lock, flags);
245}
246
247static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
248{
249 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
250 int error;
251
252 error = pm_runtime_get_sync(p->dev);
253 if (error < 0)
254 return error;
255
256 error = pinctrl_gpio_request(chip->base + offset);
257 if (error)
258 pm_runtime_put(p->dev);
259
260 return error;
261}
262
263static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
264{
265 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
266
267 pinctrl_gpio_free(chip->base + offset);
268
269 /*
270 * Set the GPIO as an input to ensure that the next GPIO request won't
271 * drive the GPIO pin as an output.
272 */
273 gpio_rcar_config_general_input_output_mode(chip, offset, false);
274
275 pm_runtime_put(p->dev);
276}
277
278static int gpio_rcar_get_direction(struct gpio_chip *chip, unsigned int offset)
279{
280 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
281
282 return !(gpio_rcar_read(p, INOUTSEL) & BIT(offset));
283}
284
285static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
286{
287 gpio_rcar_config_general_input_output_mode(chip, offset, false);
288 return 0;
289}
290
291static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
292{
293 u32 bit = BIT(offset);
294
295 /* testing on r8a7790 shows that INDT does not show correct pin state
296 * when configured as output, so use OUTDT in case of output pins */
297 if (gpio_rcar_read(gpiochip_get_data(chip), INOUTSEL) & bit)
298 return !!(gpio_rcar_read(gpiochip_get_data(chip), OUTDT) & bit);
299 else
300 return !!(gpio_rcar_read(gpiochip_get_data(chip), INDT) & bit);
301}
302
303static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
304{
305 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
306 unsigned long flags;
307
308 spin_lock_irqsave(&p->lock, flags);
309 gpio_rcar_modify_bit(p, OUTDT, offset, value);
310 spin_unlock_irqrestore(&p->lock, flags);
311}
312
313static void gpio_rcar_set_multiple(struct gpio_chip *chip, unsigned long *mask,
314 unsigned long *bits)
315{
316 struct gpio_rcar_priv *p = gpiochip_get_data(chip);
317 unsigned long flags;
318 u32 val, bankmask;
319
320 bankmask = mask[0] & GENMASK(chip->ngpio - 1, 0);
321 if (chip->valid_mask)
322 bankmask &= chip->valid_mask[0];
323
324 if (!bankmask)
325 return;
326
327 spin_lock_irqsave(&p->lock, flags);
328 val = gpio_rcar_read(p, OUTDT);
329 val &= ~bankmask;
330 val |= (bankmask & bits[0]);
331 gpio_rcar_write(p, OUTDT, val);
332 spin_unlock_irqrestore(&p->lock, flags);
333}
334
335static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
336 int value)
337{
338 /* write GPIO value to output before selecting output mode of pin */
339 gpio_rcar_set(chip, offset, value);
340 gpio_rcar_config_general_input_output_mode(chip, offset, true);
341 return 0;
342}
343
344struct gpio_rcar_info {
345 bool has_outdtsel;
346 bool has_both_edge_trigger;
347};
348
349static const struct gpio_rcar_info gpio_rcar_info_gen1 = {
350 .has_outdtsel = false,
351 .has_both_edge_trigger = false,
352};
353
354static const struct gpio_rcar_info gpio_rcar_info_gen2 = {
355 .has_outdtsel = true,
356 .has_both_edge_trigger = true,
357};
358
359static const struct of_device_id gpio_rcar_of_table[] = {
360 {
361 .compatible = "renesas,gpio-r8a7743",
362 /* RZ/G1 GPIO is identical to R-Car Gen2. */
363 .data = &gpio_rcar_info_gen2,
364 }, {
365 .compatible = "renesas,gpio-r8a7790",
366 .data = &gpio_rcar_info_gen2,
367 }, {
368 .compatible = "renesas,gpio-r8a7791",
369 .data = &gpio_rcar_info_gen2,
370 }, {
371 .compatible = "renesas,gpio-r8a7792",
372 .data = &gpio_rcar_info_gen2,
373 }, {
374 .compatible = "renesas,gpio-r8a7793",
375 .data = &gpio_rcar_info_gen2,
376 }, {
377 .compatible = "renesas,gpio-r8a7794",
378 .data = &gpio_rcar_info_gen2,
379 }, {
380 .compatible = "renesas,gpio-r8a7795",
381 /* Gen3 GPIO is identical to Gen2. */
382 .data = &gpio_rcar_info_gen2,
383 }, {
384 .compatible = "renesas,gpio-r8a7796",
385 /* Gen3 GPIO is identical to Gen2. */
386 .data = &gpio_rcar_info_gen2,
387 }, {
388 .compatible = "renesas,rcar-gen1-gpio",
389 .data = &gpio_rcar_info_gen1,
390 }, {
391 .compatible = "renesas,rcar-gen2-gpio",
392 .data = &gpio_rcar_info_gen2,
393 }, {
394 .compatible = "renesas,rcar-gen3-gpio",
395 /* Gen3 GPIO is identical to Gen2. */
396 .data = &gpio_rcar_info_gen2,
397 }, {
398 .compatible = "renesas,gpio-rcar",
399 .data = &gpio_rcar_info_gen1,
400 }, {
401 /* Terminator */
402 },
403};
404
405MODULE_DEVICE_TABLE(of, gpio_rcar_of_table);
406
407static int gpio_rcar_parse_dt(struct gpio_rcar_priv *p, unsigned int *npins)
408{
409 struct device_node *np = p->dev->of_node;
410 const struct gpio_rcar_info *info;
411 struct of_phandle_args args;
412 int ret;
413
414 info = of_device_get_match_data(p->dev);
415 p->has_outdtsel = info->has_outdtsel;
416 p->has_both_edge_trigger = info->has_both_edge_trigger;
417
418 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args);
419 *npins = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK;
420
421 if (*npins == 0 || *npins > RCAR_MAX_GPIO_PER_BANK) {
422 dev_warn(p->dev, "Invalid number of gpio lines %u, using %u\n",
423 *npins, RCAR_MAX_GPIO_PER_BANK);
424 *npins = RCAR_MAX_GPIO_PER_BANK;
425 }
426
427 return 0;
428}
429
430static int gpio_rcar_probe(struct platform_device *pdev)
431{
432 struct gpio_rcar_priv *p;
433 struct resource *irq;
434 struct gpio_chip *gpio_chip;
435 struct irq_chip *irq_chip;
436 struct device *dev = &pdev->dev;
437 const char *name = dev_name(dev);
438 unsigned int npins;
439 int ret;
440
441 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
442 if (!p)
443 return -ENOMEM;
444
445 p->dev = dev;
446 spin_lock_init(&p->lock);
447
448 /* Get device configuration from DT node */
449 ret = gpio_rcar_parse_dt(p, &npins);
450 if (ret < 0)
451 return ret;
452
453 platform_set_drvdata(pdev, p);
454
455 pm_runtime_enable(dev);
456
457 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
458 if (!irq) {
459 dev_err(dev, "missing IRQ\n");
460 ret = -EINVAL;
461 goto err0;
462 }
463
464 p->base = devm_platform_ioremap_resource(pdev, 0);
465 if (IS_ERR(p->base)) {
466 ret = PTR_ERR(p->base);
467 goto err0;
468 }
469
470 gpio_chip = &p->gpio_chip;
471 gpio_chip->request = gpio_rcar_request;
472 gpio_chip->free = gpio_rcar_free;
473 gpio_chip->get_direction = gpio_rcar_get_direction;
474 gpio_chip->direction_input = gpio_rcar_direction_input;
475 gpio_chip->get = gpio_rcar_get;
476 gpio_chip->direction_output = gpio_rcar_direction_output;
477 gpio_chip->set = gpio_rcar_set;
478 gpio_chip->set_multiple = gpio_rcar_set_multiple;
479 gpio_chip->label = name;
480 gpio_chip->parent = dev;
481 gpio_chip->owner = THIS_MODULE;
482 gpio_chip->base = -1;
483 gpio_chip->ngpio = npins;
484
485 irq_chip = &p->irq_chip;
486 irq_chip->name = name;
487 irq_chip->parent_device = dev;
488 irq_chip->irq_mask = gpio_rcar_irq_disable;
489 irq_chip->irq_unmask = gpio_rcar_irq_enable;
490 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
491 irq_chip->irq_set_wake = gpio_rcar_irq_set_wake;
492 irq_chip->flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_MASK_ON_SUSPEND;
493
494 ret = gpiochip_add_data(gpio_chip, p);
495 if (ret) {
496 dev_err(dev, "failed to add GPIO controller\n");
497 goto err0;
498 }
499
500 ret = gpiochip_irqchip_add(gpio_chip, irq_chip, 0, handle_level_irq,
501 IRQ_TYPE_NONE);
502 if (ret) {
503 dev_err(dev, "cannot add irqchip\n");
504 goto err1;
505 }
506
507 p->irq_parent = irq->start;
508 if (devm_request_irq(dev, irq->start, gpio_rcar_irq_handler,
509 IRQF_SHARED, name, p)) {
510 dev_err(dev, "failed to request IRQ\n");
511 ret = -ENOENT;
512 goto err1;
513 }
514
515 dev_info(dev, "driving %d GPIOs\n", npins);
516
517 return 0;
518
519err1:
520 gpiochip_remove(gpio_chip);
521err0:
522 pm_runtime_disable(dev);
523 return ret;
524}
525
526static int gpio_rcar_remove(struct platform_device *pdev)
527{
528 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
529
530 gpiochip_remove(&p->gpio_chip);
531
532 pm_runtime_disable(&pdev->dev);
533 return 0;
534}
535
536#ifdef CONFIG_PM_SLEEP
537static int gpio_rcar_suspend(struct device *dev)
538{
539 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
540
541 p->bank_info.iointsel = gpio_rcar_read(p, IOINTSEL);
542 p->bank_info.inoutsel = gpio_rcar_read(p, INOUTSEL);
543 p->bank_info.outdt = gpio_rcar_read(p, OUTDT);
544 p->bank_info.intmsk = gpio_rcar_read(p, INTMSK);
545 p->bank_info.posneg = gpio_rcar_read(p, POSNEG);
546 p->bank_info.edglevel = gpio_rcar_read(p, EDGLEVEL);
547 if (p->has_both_edge_trigger)
548 p->bank_info.bothedge = gpio_rcar_read(p, BOTHEDGE);
549
550 if (atomic_read(&p->wakeup_path))
551 device_set_wakeup_path(dev);
552
553 return 0;
554}
555
556static int gpio_rcar_resume(struct device *dev)
557{
558 struct gpio_rcar_priv *p = dev_get_drvdata(dev);
559 unsigned int offset;
560 u32 mask;
561
562 for (offset = 0; offset < p->gpio_chip.ngpio; offset++) {
563 if (!gpiochip_line_is_valid(&p->gpio_chip, offset))
564 continue;
565
566 mask = BIT(offset);
567 /* I/O pin */
568 if (!(p->bank_info.iointsel & mask)) {
569 if (p->bank_info.inoutsel & mask)
570 gpio_rcar_direction_output(
571 &p->gpio_chip, offset,
572 !!(p->bank_info.outdt & mask));
573 else
574 gpio_rcar_direction_input(&p->gpio_chip,
575 offset);
576 } else {
577 /* Interrupt pin */
578 gpio_rcar_config_interrupt_input_mode(
579 p,
580 offset,
581 !(p->bank_info.posneg & mask),
582 !(p->bank_info.edglevel & mask),
583 !!(p->bank_info.bothedge & mask));
584
585 if (p->bank_info.intmsk & mask)
586 gpio_rcar_write(p, MSKCLR, mask);
587 }
588 }
589
590 return 0;
591}
592#endif /* CONFIG_PM_SLEEP*/
593
594static SIMPLE_DEV_PM_OPS(gpio_rcar_pm_ops, gpio_rcar_suspend, gpio_rcar_resume);
595
596static struct platform_driver gpio_rcar_device_driver = {
597 .probe = gpio_rcar_probe,
598 .remove = gpio_rcar_remove,
599 .driver = {
600 .name = "gpio_rcar",
601 .pm = &gpio_rcar_pm_ops,
602 .of_match_table = of_match_ptr(gpio_rcar_of_table),
603 }
604};
605
606module_platform_driver(gpio_rcar_device_driver);
607
608MODULE_AUTHOR("Magnus Damm");
609MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
610MODULE_LICENSE("GPL v2");