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1// SPDX-License-Identifier: GPL-2.0-only
2/**
3 * Copyright (C) 2020 Microchip
4 *
5 * Author: Kamel Bouhara <kamel.bouhara@bootlin.com>
6 */
7#include <linux/clk.h>
8#include <linux/counter.h>
9#include <linux/mfd/syscon.h>
10#include <linux/module.h>
11#include <linux/mutex.h>
12#include <linux/of.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/regmap.h>
16#include <soc/at91/atmel_tcb.h>
17
18#define ATMEL_TC_CMR_MASK (ATMEL_TC_LDRA_RISING | ATMEL_TC_LDRB_FALLING | \
19 ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_LDBDIS | \
20 ATMEL_TC_LDBSTOP)
21
22#define ATMEL_TC_QDEN BIT(8)
23#define ATMEL_TC_POSEN BIT(9)
24
25struct mchp_tc_data {
26 const struct atmel_tcb_config *tc_cfg;
27 struct counter_device counter;
28 struct regmap *regmap;
29 int qdec_mode;
30 int num_channels;
31 int channel[2];
32 bool trig_inverted;
33};
34
35enum mchp_tc_count_function {
36 MCHP_TC_FUNCTION_INCREASE,
37 MCHP_TC_FUNCTION_QUADRATURE,
38};
39
40static enum counter_count_function mchp_tc_count_functions[] = {
41 [MCHP_TC_FUNCTION_INCREASE] = COUNTER_COUNT_FUNCTION_INCREASE,
42 [MCHP_TC_FUNCTION_QUADRATURE] = COUNTER_COUNT_FUNCTION_QUADRATURE_X4,
43};
44
45enum mchp_tc_synapse_action {
46 MCHP_TC_SYNAPSE_ACTION_NONE = 0,
47 MCHP_TC_SYNAPSE_ACTION_RISING_EDGE,
48 MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE,
49 MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE
50};
51
52static enum counter_synapse_action mchp_tc_synapse_actions[] = {
53 [MCHP_TC_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
54 [MCHP_TC_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
55 [MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
56 [MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
57};
58
59static struct counter_signal mchp_tc_count_signals[] = {
60 {
61 .id = 0,
62 .name = "Channel A",
63 },
64 {
65 .id = 1,
66 .name = "Channel B",
67 }
68};
69
70static struct counter_synapse mchp_tc_count_synapses[] = {
71 {
72 .actions_list = mchp_tc_synapse_actions,
73 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
74 .signal = &mchp_tc_count_signals[0]
75 },
76 {
77 .actions_list = mchp_tc_synapse_actions,
78 .num_actions = ARRAY_SIZE(mchp_tc_synapse_actions),
79 .signal = &mchp_tc_count_signals[1]
80 }
81};
82
83static int mchp_tc_count_function_get(struct counter_device *counter,
84 struct counter_count *count,
85 size_t *function)
86{
87 struct mchp_tc_data *const priv = counter->priv;
88
89 if (priv->qdec_mode)
90 *function = MCHP_TC_FUNCTION_QUADRATURE;
91 else
92 *function = MCHP_TC_FUNCTION_INCREASE;
93
94 return 0;
95}
96
97static int mchp_tc_count_function_set(struct counter_device *counter,
98 struct counter_count *count,
99 size_t function)
100{
101 struct mchp_tc_data *const priv = counter->priv;
102 u32 bmr, cmr;
103
104 regmap_read(priv->regmap, ATMEL_TC_BMR, &bmr);
105 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
106
107 /* Set capture mode */
108 cmr &= ~ATMEL_TC_WAVE;
109
110 switch (function) {
111 case MCHP_TC_FUNCTION_INCREASE:
112 priv->qdec_mode = 0;
113 /* Set highest rate based on whether soc has gclk or not */
114 bmr &= ~(ATMEL_TC_QDEN | ATMEL_TC_POSEN);
115 if (priv->tc_cfg->has_gclk)
116 cmr |= ATMEL_TC_TIMER_CLOCK2;
117 else
118 cmr |= ATMEL_TC_TIMER_CLOCK1;
119 /* Setup the period capture mode */
120 cmr |= ATMEL_TC_CMR_MASK;
121 cmr &= ~(ATMEL_TC_ABETRG | ATMEL_TC_XC0);
122 break;
123 case MCHP_TC_FUNCTION_QUADRATURE:
124 if (!priv->tc_cfg->has_qdec)
125 return -EINVAL;
126 /* In QDEC mode settings both channels 0 and 1 are required */
127 if (priv->num_channels < 2 || priv->channel[0] != 0 ||
128 priv->channel[1] != 1) {
129 pr_err("Invalid channels number or id for quadrature mode\n");
130 return -EINVAL;
131 }
132 priv->qdec_mode = 1;
133 bmr |= ATMEL_TC_QDEN | ATMEL_TC_POSEN;
134 cmr |= ATMEL_TC_ETRGEDG_RISING | ATMEL_TC_ABETRG | ATMEL_TC_XC0;
135 break;
136 }
137
138 regmap_write(priv->regmap, ATMEL_TC_BMR, bmr);
139 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), cmr);
140
141 /* Enable clock and trigger counter */
142 regmap_write(priv->regmap, ATMEL_TC_REG(priv->channel[0], CCR),
143 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
144
145 if (priv->qdec_mode) {
146 regmap_write(priv->regmap,
147 ATMEL_TC_REG(priv->channel[1], CMR), cmr);
148 regmap_write(priv->regmap,
149 ATMEL_TC_REG(priv->channel[1], CCR),
150 ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
151 }
152
153 return 0;
154}
155
156static int mchp_tc_count_signal_read(struct counter_device *counter,
157 struct counter_signal *signal,
158 enum counter_signal_value *val)
159{
160 struct mchp_tc_data *const priv = counter->priv;
161 bool sigstatus;
162 u32 sr;
163
164 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], SR), &sr);
165
166 if (priv->trig_inverted)
167 sigstatus = (sr & ATMEL_TC_MTIOB);
168 else
169 sigstatus = (sr & ATMEL_TC_MTIOA);
170
171 *val = sigstatus ? COUNTER_SIGNAL_HIGH : COUNTER_SIGNAL_LOW;
172
173 return 0;
174}
175
176static int mchp_tc_count_action_get(struct counter_device *counter,
177 struct counter_count *count,
178 struct counter_synapse *synapse,
179 size_t *action)
180{
181 struct mchp_tc_data *const priv = counter->priv;
182 u32 cmr;
183
184 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CMR), &cmr);
185
186 *action = MCHP_TC_SYNAPSE_ACTION_NONE;
187
188 if (cmr & ATMEL_TC_ETRGEDG_NONE)
189 *action = MCHP_TC_SYNAPSE_ACTION_NONE;
190 else if (cmr & ATMEL_TC_ETRGEDG_RISING)
191 *action = MCHP_TC_SYNAPSE_ACTION_RISING_EDGE;
192 else if (cmr & ATMEL_TC_ETRGEDG_FALLING)
193 *action = MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE;
194 else if (cmr & ATMEL_TC_ETRGEDG_BOTH)
195 *action = MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE;
196
197 return 0;
198}
199
200static int mchp_tc_count_action_set(struct counter_device *counter,
201 struct counter_count *count,
202 struct counter_synapse *synapse,
203 size_t action)
204{
205 struct mchp_tc_data *const priv = counter->priv;
206 u32 edge = ATMEL_TC_ETRGEDG_NONE;
207
208 /* QDEC mode is rising edge only */
209 if (priv->qdec_mode)
210 return -EINVAL;
211
212 switch (action) {
213 case MCHP_TC_SYNAPSE_ACTION_NONE:
214 edge = ATMEL_TC_ETRGEDG_NONE;
215 break;
216 case MCHP_TC_SYNAPSE_ACTION_RISING_EDGE:
217 edge = ATMEL_TC_ETRGEDG_RISING;
218 break;
219 case MCHP_TC_SYNAPSE_ACTION_FALLING_EDGE:
220 edge = ATMEL_TC_ETRGEDG_FALLING;
221 break;
222 case MCHP_TC_SYNAPSE_ACTION_BOTH_EDGE:
223 edge = ATMEL_TC_ETRGEDG_BOTH;
224 break;
225 }
226
227 return regmap_write_bits(priv->regmap,
228 ATMEL_TC_REG(priv->channel[0], CMR),
229 ATMEL_TC_ETRGEDG, edge);
230}
231
232static int mchp_tc_count_read(struct counter_device *counter,
233 struct counter_count *count,
234 unsigned long *val)
235{
236 struct mchp_tc_data *const priv = counter->priv;
237 u32 cnt;
238
239 regmap_read(priv->regmap, ATMEL_TC_REG(priv->channel[0], CV), &cnt);
240 *val = cnt;
241
242 return 0;
243}
244
245static struct counter_count mchp_tc_counts[] = {
246 {
247 .id = 0,
248 .name = "Timer Counter",
249 .functions_list = mchp_tc_count_functions,
250 .num_functions = ARRAY_SIZE(mchp_tc_count_functions),
251 .synapses = mchp_tc_count_synapses,
252 .num_synapses = ARRAY_SIZE(mchp_tc_count_synapses),
253 },
254};
255
256static struct counter_ops mchp_tc_ops = {
257 .signal_read = mchp_tc_count_signal_read,
258 .count_read = mchp_tc_count_read,
259 .function_get = mchp_tc_count_function_get,
260 .function_set = mchp_tc_count_function_set,
261 .action_get = mchp_tc_count_action_get,
262 .action_set = mchp_tc_count_action_set
263};
264
265static const struct atmel_tcb_config tcb_rm9200_config = {
266 .counter_width = 16,
267};
268
269static const struct atmel_tcb_config tcb_sam9x5_config = {
270 .counter_width = 32,
271};
272
273static const struct atmel_tcb_config tcb_sama5d2_config = {
274 .counter_width = 32,
275 .has_gclk = true,
276 .has_qdec = true,
277};
278
279static const struct atmel_tcb_config tcb_sama5d3_config = {
280 .counter_width = 32,
281 .has_qdec = true,
282};
283
284static const struct of_device_id atmel_tc_of_match[] = {
285 { .compatible = "atmel,at91rm9200-tcb", .data = &tcb_rm9200_config, },
286 { .compatible = "atmel,at91sam9x5-tcb", .data = &tcb_sam9x5_config, },
287 { .compatible = "atmel,sama5d2-tcb", .data = &tcb_sama5d2_config, },
288 { .compatible = "atmel,sama5d3-tcb", .data = &tcb_sama5d3_config, },
289 { /* sentinel */ }
290};
291
292static void mchp_tc_clk_remove(void *ptr)
293{
294 clk_disable_unprepare((struct clk *)ptr);
295}
296
297static int mchp_tc_probe(struct platform_device *pdev)
298{
299 struct device_node *np = pdev->dev.of_node;
300 const struct atmel_tcb_config *tcb_config;
301 const struct of_device_id *match;
302 struct mchp_tc_data *priv;
303 char clk_name[7];
304 struct regmap *regmap;
305 struct clk *clk[3];
306 int channel;
307 int ret, i;
308
309 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
310 if (!priv)
311 return -ENOMEM;
312
313 platform_set_drvdata(pdev, priv);
314
315 match = of_match_node(atmel_tc_of_match, np->parent);
316 tcb_config = match->data;
317 if (!tcb_config) {
318 dev_err(&pdev->dev, "No matching parent node found\n");
319 return -ENODEV;
320 }
321
322 regmap = syscon_node_to_regmap(np->parent);
323 if (IS_ERR(regmap))
324 return PTR_ERR(regmap);
325
326 /* max. channels number is 2 when in QDEC mode */
327 priv->num_channels = of_property_count_u32_elems(np, "reg");
328 if (priv->num_channels < 0) {
329 dev_err(&pdev->dev, "Invalid or missing channel\n");
330 return -EINVAL;
331 }
332
333 /* Register channels and initialize clocks */
334 for (i = 0; i < priv->num_channels; i++) {
335 ret = of_property_read_u32_index(np, "reg", i, &channel);
336 if (ret < 0 || channel > 2)
337 return -ENODEV;
338
339 priv->channel[i] = channel;
340
341 snprintf(clk_name, sizeof(clk_name), "t%d_clk", channel);
342
343 clk[i] = of_clk_get_by_name(np->parent, clk_name);
344 if (IS_ERR(clk[i])) {
345 /* Fallback to t0_clk */
346 clk[i] = of_clk_get_by_name(np->parent, "t0_clk");
347 if (IS_ERR(clk[i]))
348 return PTR_ERR(clk[i]);
349 }
350
351 ret = clk_prepare_enable(clk[i]);
352 if (ret)
353 return ret;
354
355 ret = devm_add_action_or_reset(&pdev->dev,
356 mchp_tc_clk_remove,
357 clk[i]);
358 if (ret)
359 return ret;
360
361 dev_dbg(&pdev->dev,
362 "Initialized capture mode on channel %d\n",
363 channel);
364 }
365
366 priv->tc_cfg = tcb_config;
367 priv->regmap = regmap;
368 priv->counter.name = dev_name(&pdev->dev);
369 priv->counter.parent = &pdev->dev;
370 priv->counter.ops = &mchp_tc_ops;
371 priv->counter.num_counts = ARRAY_SIZE(mchp_tc_counts);
372 priv->counter.counts = mchp_tc_counts;
373 priv->counter.num_signals = ARRAY_SIZE(mchp_tc_count_signals);
374 priv->counter.signals = mchp_tc_count_signals;
375 priv->counter.priv = priv;
376
377 return devm_counter_register(&pdev->dev, &priv->counter);
378}
379
380static const struct of_device_id mchp_tc_dt_ids[] = {
381 { .compatible = "microchip,tcb-capture", },
382 { /* sentinel */ },
383};
384MODULE_DEVICE_TABLE(of, mchp_tc_dt_ids);
385
386static struct platform_driver mchp_tc_driver = {
387 .probe = mchp_tc_probe,
388 .driver = {
389 .name = "microchip-tcb-capture",
390 .of_match_table = mchp_tc_dt_ids,
391 },
392};
393module_platform_driver(mchp_tc_driver);
394
395MODULE_AUTHOR("Kamel Bouhara <kamel.bouhara@bootlin.com>");
396MODULE_DESCRIPTION("Microchip TCB Capture driver");
397MODULE_LICENSE("GPL v2");