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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This program is used to generate definitions needed by
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach kernel code:
7 * generate asm statements containing #defines,
8 * compile this file to assembler, and then extract the
9 * #defines from the assembly-language output.
10 */
11
12#define GENERATING_ASM_OFFSETS /* asm/smp.h */
13
14#include <linux/compat.h>
15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/mman.h>
22#include <linux/mm.h>
23#include <linux/suspend.h>
24#include <linux/hrtimer.h>
25#ifdef CONFIG_PPC64
26#include <linux/time.h>
27#include <linux/hardirq.h>
28#endif
29#include <linux/kbuild.h>
30
31#include <asm/io.h>
32#include <asm/page.h>
33#include <asm/processor.h>
34#include <asm/cputable.h>
35#include <asm/thread_info.h>
36#include <asm/rtas.h>
37#include <asm/vdso_datapage.h>
38#include <asm/dbell.h>
39#ifdef CONFIG_PPC64
40#include <asm/paca.h>
41#include <asm/lppaca.h>
42#include <asm/cache.h>
43#include <asm/mmu.h>
44#include <asm/hvcall.h>
45#include <asm/xics.h>
46#endif
47#ifdef CONFIG_PPC_POWERNV
48#include <asm/opal.h>
49#endif
50#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
51#include <linux/kvm_host.h>
52#endif
53#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
54#include <asm/kvm_book3s.h>
55#include <asm/kvm_ppc.h>
56#endif
57
58#ifdef CONFIG_PPC32
59#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
60#include "head_booke.h"
61#endif
62#endif
63
64#if defined(CONFIG_PPC_FSL_BOOK3E)
65#include "../mm/mmu_decl.h"
66#endif
67
68#ifdef CONFIG_PPC_8xx
69#include <asm/fixmap.h>
70#endif
71
72#ifdef CONFIG_XMON
73#include "../xmon/xmon_bpts.h"
74#endif
75
76#define STACK_PT_REGS_OFFSET(sym, val) \
77 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
78
79int main(void)
80{
81 OFFSET(THREAD, task_struct, thread);
82 OFFSET(MM, task_struct, mm);
83#ifdef CONFIG_STACKPROTECTOR
84 OFFSET(TASK_CANARY, task_struct, stack_canary);
85#ifdef CONFIG_PPC64
86 OFFSET(PACA_CANARY, paca_struct, canary);
87#endif
88#endif
89 OFFSET(MMCONTEXTID, mm_struct, context.id);
90#ifdef CONFIG_PPC64
91 DEFINE(SIGSEGV, SIGSEGV);
92 DEFINE(NMI_MASK, NMI_MASK);
93#else
94 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
95#ifdef CONFIG_PPC_RTAS
96 OFFSET(RTAS_SP, thread_struct, rtas_sp);
97#endif
98#endif /* CONFIG_PPC64 */
99 OFFSET(TASK_STACK, task_struct, stack);
100#ifdef CONFIG_SMP
101 OFFSET(TASK_CPU, task_struct, cpu);
102#endif
103
104#ifdef CONFIG_LIVEPATCH
105 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
106#endif
107
108 OFFSET(KSP, thread_struct, ksp);
109 OFFSET(PT_REGS, thread_struct, regs);
110#ifdef CONFIG_BOOKE
111 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
112#endif
113 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
114 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
115 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
116 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
117 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
118#ifdef CONFIG_ALTIVEC
119 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
120 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
121 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
122 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
123 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
124 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
125#endif /* CONFIG_ALTIVEC */
126#ifdef CONFIG_VSX
127 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
128#endif /* CONFIG_VSX */
129#ifdef CONFIG_PPC64
130 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
131#else /* CONFIG_PPC64 */
132 OFFSET(PGDIR, thread_struct, pgdir);
133#ifdef CONFIG_VMAP_STACK
134 OFFSET(SRR0, thread_struct, srr0);
135 OFFSET(SRR1, thread_struct, srr1);
136 OFFSET(DAR, thread_struct, dar);
137 OFFSET(DSISR, thread_struct, dsisr);
138#ifdef CONFIG_PPC_BOOK3S_32
139 OFFSET(THR0, thread_struct, r0);
140 OFFSET(THR3, thread_struct, r3);
141 OFFSET(THR4, thread_struct, r4);
142 OFFSET(THR5, thread_struct, r5);
143 OFFSET(THR6, thread_struct, r6);
144 OFFSET(THR8, thread_struct, r8);
145 OFFSET(THR9, thread_struct, r9);
146 OFFSET(THR11, thread_struct, r11);
147 OFFSET(THLR, thread_struct, lr);
148 OFFSET(THCTR, thread_struct, ctr);
149#endif
150#endif
151#ifdef CONFIG_SPE
152 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
153 OFFSET(THREAD_ACC, thread_struct, acc);
154 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
155 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
156#endif /* CONFIG_SPE */
157#endif /* CONFIG_PPC64 */
158#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
159 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
160#endif
161#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
162 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
163#endif
164#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
165 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
166#endif
167#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
168 OFFSET(KUAP, thread_struct, kuap);
169#endif
170
171#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
172 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
173 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
174 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
175 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
176 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
177 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
178 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
179 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
180 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
181 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
182 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
183 /* Local pt_regs on stack for Transactional Memory funcs. */
184 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
185 sizeof(struct pt_regs) + 16);
186#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
187
188 OFFSET(TI_FLAGS, thread_info, flags);
189 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
190 OFFSET(TI_PREEMPT, thread_info, preempt_count);
191
192#ifdef CONFIG_PPC64
193 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
194 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
195 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
196 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
197 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
198 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
199 /* paca */
200 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
201 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
202 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
203 OFFSET(PACAKSAVE, paca_struct, kstack);
204 OFFSET(PACACURRENT, paca_struct, __current);
205 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
206 offsetof(struct task_struct, thread_info));
207 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
208 OFFSET(PACAR1, paca_struct, saved_r1);
209 OFFSET(PACATOC, paca_struct, kernel_toc);
210 OFFSET(PACAKBASE, paca_struct, kernelbase);
211 OFFSET(PACAKMSR, paca_struct, kernel_msr);
212 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
213 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
214 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
215#ifdef CONFIG_PPC_BOOK3S
216 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
217#ifdef CONFIG_PPC_MM_SLICES
218 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
219 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
220 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
221 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
222#endif /* CONFIG_PPC_MM_SLICES */
223#endif
224
225#ifdef CONFIG_PPC_BOOK3E
226 OFFSET(PACAPGD, paca_struct, pgd);
227 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
228 OFFSET(PACA_EXGEN, paca_struct, exgen);
229 OFFSET(PACA_EXTLB, paca_struct, extlb);
230 OFFSET(PACA_EXMC, paca_struct, exmc);
231 OFFSET(PACA_EXCRIT, paca_struct, excrit);
232 OFFSET(PACA_EXDBG, paca_struct, exdbg);
233 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
234 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
235 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
236 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
237
238 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
239 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
240 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
241#endif /* CONFIG_PPC_BOOK3E */
242
243#ifdef CONFIG_PPC_BOOK3S_64
244 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
245 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
246 OFFSET(PACASTABRR, paca_struct, stab_rr);
247 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
248#ifdef CONFIG_PPC_MM_SLICES
249 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
250#else
251 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
252#endif /* CONFIG_PPC_MM_SLICES */
253 OFFSET(PACA_EXGEN, paca_struct, exgen);
254 OFFSET(PACA_EXMC, paca_struct, exmc);
255 OFFSET(PACA_EXSLB, paca_struct, exslb);
256 OFFSET(PACA_EXNMI, paca_struct, exnmi);
257#ifdef CONFIG_PPC_PSERIES
258 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
259#endif
260 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
261 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
262 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
263 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
264 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
265#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
266 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
267#endif
268 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
269 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
270 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
271#endif /* CONFIG_PPC_BOOK3S_64 */
272 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
273#ifdef CONFIG_PPC_BOOK3S_64
274 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
275 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
276 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
277 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
278 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
279 OFFSET(PACA_EXRFI, paca_struct, exrfi);
280 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
281
282#endif
283 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
284 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
285 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
286 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
287 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
288 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
289 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
290#ifdef CONFIG_PPC_BOOK3E
291 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
292#endif
293 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
294#else /* CONFIG_PPC64 */
295#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
296 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
297 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
298 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
299 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
300#endif
301#endif /* CONFIG_PPC64 */
302
303 /* RTAS */
304 OFFSET(RTASBASE, rtas_t, base);
305 OFFSET(RTASENTRY, rtas_t, entry);
306
307 /* Interrupt register frame */
308 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
309 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
310 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
311 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
312 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
313 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
314 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
315 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
316 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
317 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
318 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
319 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
320 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
321 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
322 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
323 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
324#ifndef CONFIG_PPC64
325 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
326#endif /* CONFIG_PPC64 */
327 /*
328 * Note: these symbols include _ because they overlap with special
329 * register names
330 */
331 STACK_PT_REGS_OFFSET(_NIP, nip);
332 STACK_PT_REGS_OFFSET(_MSR, msr);
333 STACK_PT_REGS_OFFSET(_CTR, ctr);
334 STACK_PT_REGS_OFFSET(_LINK, link);
335 STACK_PT_REGS_OFFSET(_CCR, ccr);
336 STACK_PT_REGS_OFFSET(_XER, xer);
337 STACK_PT_REGS_OFFSET(_DAR, dar);
338 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
339 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
340 STACK_PT_REGS_OFFSET(RESULT, result);
341 STACK_PT_REGS_OFFSET(_TRAP, trap);
342#ifndef CONFIG_PPC64
343 /*
344 * The PowerPC 400-class & Book-E processors have neither the DAR
345 * nor the DSISR SPRs. Hence, we overload them to hold the similar
346 * DEAR and ESR SPRs for such processors. For critical interrupts
347 * we use them to hold SRR0 and SRR1.
348 */
349 STACK_PT_REGS_OFFSET(_DEAR, dar);
350 STACK_PT_REGS_OFFSET(_ESR, dsisr);
351#else /* CONFIG_PPC64 */
352 STACK_PT_REGS_OFFSET(SOFTE, softe);
353 STACK_PT_REGS_OFFSET(_PPR, ppr);
354#endif /* CONFIG_PPC64 */
355
356#ifdef CONFIG_PPC_KUAP
357 STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap);
358#endif
359
360#if defined(CONFIG_PPC32)
361#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
362 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
363 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
364 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
365 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
366 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
367 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
368 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
369 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
370 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
371 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
372 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
373 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
374 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
375 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
376 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
377 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
378#endif
379#endif
380
381#ifndef CONFIG_PPC64
382 OFFSET(MM_PGD, mm_struct, pgd);
383#endif /* ! CONFIG_PPC64 */
384
385 /* About the CPU features table */
386 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
387 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
388 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
389
390 OFFSET(pbe_address, pbe, address);
391 OFFSET(pbe_orig_address, pbe, orig_address);
392 OFFSET(pbe_next, pbe, next);
393
394#ifndef CONFIG_PPC64
395 DEFINE(TASK_SIZE, TASK_SIZE);
396 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
397#endif /* ! CONFIG_PPC64 */
398
399 /* datapage offsets for use by vdso */
400 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
401 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
402 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
403 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
404 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
405 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
406 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
407 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
408 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
409 OFFSET(STAMP_XTIME_SEC, vdso_data, stamp_xtime_sec);
410 OFFSET(STAMP_XTIME_NSEC, vdso_data, stamp_xtime_nsec);
411 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
412 OFFSET(CLOCK_HRTIMER_RES, vdso_data, hrtimer_res);
413#ifdef CONFIG_PPC64
414 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
415 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
416 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
417 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
418 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
419 OFFSET(TVAL64_TV_SEC, __kernel_old_timeval, tv_sec);
420 OFFSET(TVAL64_TV_USEC, __kernel_old_timeval, tv_usec);
421#endif
422 OFFSET(TSPC64_TV_SEC, __kernel_timespec, tv_sec);
423 OFFSET(TSPC64_TV_NSEC, __kernel_timespec, tv_nsec);
424 OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec);
425 OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec);
426 OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec);
427 OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec);
428 /* timeval/timezone offsets for use by vdso */
429 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
430 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
431
432 /* Other bits used by the vdso */
433 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
434 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
435 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
436 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
437 DEFINE(CLOCK_MAX, CLOCK_TAI);
438 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
439 DEFINE(EINVAL, EINVAL);
440 DEFINE(KTIME_LOW_RES, KTIME_LOW_RES);
441
442#ifdef CONFIG_BUG
443 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
444#endif
445
446#ifdef CONFIG_PPC_BOOK3S_64
447 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
448#else
449 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
450#endif
451 DEFINE(PTE_SIZE, sizeof(pte_t));
452
453#ifdef CONFIG_KVM
454 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
455 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
456 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
457 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
458 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
459 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
460#ifdef CONFIG_ALTIVEC
461 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
462#endif
463 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
464 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
465 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
466#ifdef CONFIG_PPC_BOOK3S
467 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
468#endif
469 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
470 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
471#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
472 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
473 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
474 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
475 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
476 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
477 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
478 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
479#endif
480#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
481 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
482 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
483 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
484 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
485 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
486 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
487 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
488 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
489 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
490 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
491 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
492#endif
493 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
494 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
495 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
496 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
497 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
498 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
499 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
500 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
501 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
502 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
503#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
504 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
505#endif
506
507 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
508 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
509 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
510 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
511 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
512 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
513
514 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
515 OFFSET(KVM_LPID, kvm, arch.lpid);
516
517 /* book3s */
518#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
519 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
520 OFFSET(KVM_SDR1, kvm, arch.sdr1);
521 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
522 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
523 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
524 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
525 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
526 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
527 OFFSET(KVM_RADIX, kvm, arch.radix);
528 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
529 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
530 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
531 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
532 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
533 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
534 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
535 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
536 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
537 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
538#endif
539#ifdef CONFIG_PPC_BOOK3S
540 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
541 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
542 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
543 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
544 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
545 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
546 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
547 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
548 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
549 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
550 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
551 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
552 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
553 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
554 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
555 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
556 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
557 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
558 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
559 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
560 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
561 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
562 OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
563 OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
564 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
565 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
566 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
567 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
568 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
569 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
570 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
571 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
572 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
573 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
574 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
575 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
576 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
577 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
578 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
579 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
580 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
581 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
582 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
583 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
584 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
585 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
586 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
587 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
588 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
589 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
590 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
591 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
592 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
593 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
594 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
595 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
596 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
597 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
598 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
599 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
600 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
601 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
602 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
603 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
604 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
605 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
606#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
607 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
608 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
609 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
610 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
611 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
612 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
613 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
614 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
615 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
616 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
617 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
618 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
619 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
620 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
621 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
622 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
623#endif
624
625#ifdef CONFIG_PPC_BOOK3S_64
626#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
627 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
628# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
629#else
630# define SVCPU_FIELD(x, f)
631#endif
632# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
633#else /* 32-bit */
634# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
635# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
636#endif
637
638 SVCPU_FIELD(SVCPU_CR, cr);
639 SVCPU_FIELD(SVCPU_XER, xer);
640 SVCPU_FIELD(SVCPU_CTR, ctr);
641 SVCPU_FIELD(SVCPU_LR, lr);
642 SVCPU_FIELD(SVCPU_PC, pc);
643 SVCPU_FIELD(SVCPU_R0, gpr[0]);
644 SVCPU_FIELD(SVCPU_R1, gpr[1]);
645 SVCPU_FIELD(SVCPU_R2, gpr[2]);
646 SVCPU_FIELD(SVCPU_R3, gpr[3]);
647 SVCPU_FIELD(SVCPU_R4, gpr[4]);
648 SVCPU_FIELD(SVCPU_R5, gpr[5]);
649 SVCPU_FIELD(SVCPU_R6, gpr[6]);
650 SVCPU_FIELD(SVCPU_R7, gpr[7]);
651 SVCPU_FIELD(SVCPU_R8, gpr[8]);
652 SVCPU_FIELD(SVCPU_R9, gpr[9]);
653 SVCPU_FIELD(SVCPU_R10, gpr[10]);
654 SVCPU_FIELD(SVCPU_R11, gpr[11]);
655 SVCPU_FIELD(SVCPU_R12, gpr[12]);
656 SVCPU_FIELD(SVCPU_R13, gpr[13]);
657 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
658 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
659 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
660 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
661#ifdef CONFIG_PPC_BOOK3S_32
662 SVCPU_FIELD(SVCPU_SR, sr);
663#endif
664#ifdef CONFIG_PPC64
665 SVCPU_FIELD(SVCPU_SLB, slb);
666 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
667 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
668#endif
669
670 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
671 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
672 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
673 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
674 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
675 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
676 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
677 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
678 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
679 HSTATE_FIELD(HSTATE_NAPPING, napping);
680
681#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
682 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
683 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
684 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
685 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
686 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
687 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
688 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
689 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
690 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
691 HSTATE_FIELD(HSTATE_PTID, ptid);
692 HSTATE_FIELD(HSTATE_TID, tid);
693 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
694 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
695 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
696 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
697 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
698 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
699 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
700 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
701 HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]);
702 HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]);
703 HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]);
704 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
705 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
706 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
707 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
708 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
709 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
710 HSTATE_FIELD(HSTATE_PURR, host_purr);
711 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
712 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
713 HSTATE_FIELD(HSTATE_DABR, dabr);
714 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
715 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
716 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
717 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
718 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
719 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
720 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
721 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
722 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
723 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
724#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
725
726#ifdef CONFIG_PPC_BOOK3S_64
727 HSTATE_FIELD(HSTATE_CFAR, cfar);
728 HSTATE_FIELD(HSTATE_PPR, ppr);
729 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
730#endif /* CONFIG_PPC_BOOK3S_64 */
731
732#else /* CONFIG_PPC_BOOK3S */
733 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
734 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
735 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
736 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
737 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
738 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
739 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
740 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
741 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
742 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
743#endif /* CONFIG_PPC_BOOK3S */
744#endif /* CONFIG_KVM */
745
746#ifdef CONFIG_KVM_GUEST
747 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
748 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
749 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
750 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
751 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
752 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
753 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
754#endif
755
756#ifdef CONFIG_44x
757 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
758 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
759#endif
760#ifdef CONFIG_PPC_FSL_BOOK3E
761 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
762 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
763 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
764 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
765 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
766 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
767#endif
768
769#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
770 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
771 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
772 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
773 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
774#endif
775
776#ifdef CONFIG_KVM_BOOKE_HV
777 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
778 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
779#endif
780
781#ifdef CONFIG_KVM_XICS
782 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
783 arch.xive_saved_state));
784 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
785 arch.xive_cam_word));
786 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
787 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
788 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
789 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
790#endif
791
792#ifdef CONFIG_KVM_EXIT_TIMING
793 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
794 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
795 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
796 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
797#endif
798
799 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
800 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
801
802#ifdef CONFIG_PPC_8xx
803 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
804#endif
805
806#ifdef CONFIG_XMON
807 DEFINE(BPT_SIZE, BPT_SIZE);
808#endif
809
810 return 0;
811}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * This program is used to generate definitions needed by
4 * assembly language modules.
5 *
6 * We use the technique used in the OSF Mach kernel code:
7 * generate asm statements containing #defines,
8 * compile this file to assembler, and then extract the
9 * #defines from the assembly-language output.
10 */
11
12#define GENERATING_ASM_OFFSETS /* asm/smp.h */
13
14#include <linux/compat.h>
15#include <linux/signal.h>
16#include <linux/sched.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/string.h>
20#include <linux/types.h>
21#include <linux/mman.h>
22#include <linux/mm.h>
23#include <linux/suspend.h>
24#include <linux/hrtimer.h>
25#ifdef CONFIG_PPC64
26#include <linux/time.h>
27#include <linux/hardirq.h>
28#endif
29#include <linux/kbuild.h>
30
31#include <asm/io.h>
32#include <asm/page.h>
33#include <asm/pgtable.h>
34#include <asm/processor.h>
35#include <asm/cputable.h>
36#include <asm/thread_info.h>
37#include <asm/rtas.h>
38#include <asm/vdso_datapage.h>
39#include <asm/dbell.h>
40#ifdef CONFIG_PPC64
41#include <asm/paca.h>
42#include <asm/lppaca.h>
43#include <asm/cache.h>
44#include <asm/mmu.h>
45#include <asm/hvcall.h>
46#include <asm/xics.h>
47#endif
48#ifdef CONFIG_PPC_POWERNV
49#include <asm/opal.h>
50#endif
51#if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
52#include <linux/kvm_host.h>
53#endif
54#if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
55#include <asm/kvm_book3s.h>
56#include <asm/kvm_ppc.h>
57#endif
58
59#ifdef CONFIG_PPC32
60#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
61#include "head_booke.h"
62#endif
63#endif
64
65#if defined(CONFIG_PPC_FSL_BOOK3E)
66#include "../mm/mmu_decl.h"
67#endif
68
69#ifdef CONFIG_PPC_8xx
70#include <asm/fixmap.h>
71#endif
72
73#define STACK_PT_REGS_OFFSET(sym, val) \
74 DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
75
76int main(void)
77{
78 OFFSET(THREAD, task_struct, thread);
79 OFFSET(MM, task_struct, mm);
80#ifdef CONFIG_STACKPROTECTOR
81 OFFSET(TASK_CANARY, task_struct, stack_canary);
82#ifdef CONFIG_PPC64
83 OFFSET(PACA_CANARY, paca_struct, canary);
84#endif
85#endif
86 OFFSET(MMCONTEXTID, mm_struct, context.id);
87#ifdef CONFIG_PPC64
88 DEFINE(SIGSEGV, SIGSEGV);
89 DEFINE(NMI_MASK, NMI_MASK);
90#else
91 OFFSET(KSP_LIMIT, thread_struct, ksp_limit);
92#ifdef CONFIG_PPC_RTAS
93 OFFSET(RTAS_SP, thread_struct, rtas_sp);
94#endif
95#endif /* CONFIG_PPC64 */
96 OFFSET(TASK_STACK, task_struct, stack);
97#ifdef CONFIG_SMP
98 OFFSET(TASK_CPU, task_struct, cpu);
99#endif
100
101#ifdef CONFIG_LIVEPATCH
102 OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
103#endif
104
105 OFFSET(KSP, thread_struct, ksp);
106 OFFSET(PT_REGS, thread_struct, regs);
107#ifdef CONFIG_BOOKE
108 OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
109#endif
110 OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
111 OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
112 OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
113 OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
114 OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
115#ifdef CONFIG_ALTIVEC
116 OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
117 OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
118 OFFSET(THREAD_VRSAVE, thread_struct, vrsave);
119 OFFSET(THREAD_USED_VR, thread_struct, used_vr);
120 OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
121 OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
122#endif /* CONFIG_ALTIVEC */
123#ifdef CONFIG_VSX
124 OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
125#endif /* CONFIG_VSX */
126#ifdef CONFIG_PPC64
127 OFFSET(KSP_VSID, thread_struct, ksp_vsid);
128#else /* CONFIG_PPC64 */
129 OFFSET(PGDIR, thread_struct, pgdir);
130#ifdef CONFIG_SPE
131 OFFSET(THREAD_EVR0, thread_struct, evr[0]);
132 OFFSET(THREAD_ACC, thread_struct, acc);
133 OFFSET(THREAD_SPEFSCR, thread_struct, spefscr);
134 OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
135#endif /* CONFIG_SPE */
136#endif /* CONFIG_PPC64 */
137#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
138 OFFSET(THREAD_DBCR0, thread_struct, debug.dbcr0);
139#endif
140#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
141 OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
142#endif
143#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
144 OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
145#endif
146#if defined(CONFIG_PPC_BOOK3S_32) && defined(CONFIG_PPC_KUAP)
147 OFFSET(KUAP, thread_struct, kuap);
148#endif
149
150#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
151 OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
152 OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
153 OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
154 OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
155 OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
156 OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
157 OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
158 OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
159 OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
160 OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
161 OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
162 /* Local pt_regs on stack for Transactional Memory funcs. */
163 DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
164 sizeof(struct pt_regs) + 16);
165#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
166
167 OFFSET(TI_FLAGS, thread_info, flags);
168 OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
169 OFFSET(TI_PREEMPT, thread_info, preempt_count);
170
171#ifdef CONFIG_PPC64
172 OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
173 OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
174 OFFSET(DCACHEL1BLOCKSPERPAGE, ppc64_caches, l1d.blocks_per_page);
175 OFFSET(ICACHEL1BLOCKSIZE, ppc64_caches, l1i.block_size);
176 OFFSET(ICACHEL1LOGBLOCKSIZE, ppc64_caches, l1i.log_block_size);
177 OFFSET(ICACHEL1BLOCKSPERPAGE, ppc64_caches, l1i.blocks_per_page);
178 /* paca */
179 DEFINE(PACA_SIZE, sizeof(struct paca_struct));
180 OFFSET(PACAPACAINDEX, paca_struct, paca_index);
181 OFFSET(PACAPROCSTART, paca_struct, cpu_start);
182 OFFSET(PACAKSAVE, paca_struct, kstack);
183 OFFSET(PACACURRENT, paca_struct, __current);
184 DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
185 offsetof(struct task_struct, thread_info));
186 OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
187 OFFSET(PACAR1, paca_struct, saved_r1);
188 OFFSET(PACATOC, paca_struct, kernel_toc);
189 OFFSET(PACAKBASE, paca_struct, kernelbase);
190 OFFSET(PACAKMSR, paca_struct, kernel_msr);
191 OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
192 OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
193 OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
194#ifdef CONFIG_PPC_BOOK3S
195 OFFSET(PACACONTEXTID, paca_struct, mm_ctx_id);
196#ifdef CONFIG_PPC_MM_SLICES
197 OFFSET(PACALOWSLICESPSIZE, paca_struct, mm_ctx_low_slices_psize);
198 OFFSET(PACAHIGHSLICEPSIZE, paca_struct, mm_ctx_high_slices_psize);
199 OFFSET(PACA_SLB_ADDR_LIMIT, paca_struct, mm_ctx_slb_addr_limit);
200 DEFINE(MMUPSIZEDEFSIZE, sizeof(struct mmu_psize_def));
201#endif /* CONFIG_PPC_MM_SLICES */
202#endif
203
204#ifdef CONFIG_PPC_BOOK3E
205 OFFSET(PACAPGD, paca_struct, pgd);
206 OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
207 OFFSET(PACA_EXGEN, paca_struct, exgen);
208 OFFSET(PACA_EXTLB, paca_struct, extlb);
209 OFFSET(PACA_EXMC, paca_struct, exmc);
210 OFFSET(PACA_EXCRIT, paca_struct, excrit);
211 OFFSET(PACA_EXDBG, paca_struct, exdbg);
212 OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
213 OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
214 OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
215 OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
216
217 OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
218 OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
219 OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
220#endif /* CONFIG_PPC_BOOK3E */
221
222#ifdef CONFIG_PPC_BOOK3S_64
223 OFFSET(PACASLBCACHE, paca_struct, slb_cache);
224 OFFSET(PACASLBCACHEPTR, paca_struct, slb_cache_ptr);
225 OFFSET(PACASTABRR, paca_struct, stab_rr);
226 OFFSET(PACAVMALLOCSLLP, paca_struct, vmalloc_sllp);
227#ifdef CONFIG_PPC_MM_SLICES
228 OFFSET(MMUPSIZESLLP, mmu_psize_def, sllp);
229#else
230 OFFSET(PACACONTEXTSLLP, paca_struct, mm_ctx_sllp);
231#endif /* CONFIG_PPC_MM_SLICES */
232 OFFSET(PACA_EXGEN, paca_struct, exgen);
233 OFFSET(PACA_EXMC, paca_struct, exmc);
234 OFFSET(PACA_EXSLB, paca_struct, exslb);
235 OFFSET(PACA_EXNMI, paca_struct, exnmi);
236#ifdef CONFIG_PPC_PSERIES
237 OFFSET(PACALPPACAPTR, paca_struct, lppaca_ptr);
238#endif
239 OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
240 OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
241 OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
242 OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
243 OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
244#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
245 OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
246#endif
247 OFFSET(LPPACA_DTLIDX, lppaca, dtl_idx);
248 OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
249 OFFSET(PACA_DTL_RIDX, paca_struct, dtl_ridx);
250#endif /* CONFIG_PPC_BOOK3S_64 */
251 OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
252#ifdef CONFIG_PPC_BOOK3S_64
253 OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
254 OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
255 OFFSET(PACA_IN_MCE, paca_struct, in_mce);
256 OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
257 OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
258 OFFSET(PACA_EXRFI, paca_struct, exrfi);
259 OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
260
261#endif
262 OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
263 OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
264 OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
265 OFFSET(ACCOUNT_STARTTIME, paca_struct, accounting.starttime);
266 OFFSET(ACCOUNT_STARTTIME_USER, paca_struct, accounting.starttime_user);
267 OFFSET(ACCOUNT_USER_TIME, paca_struct, accounting.utime);
268 OFFSET(ACCOUNT_SYSTEM_TIME, paca_struct, accounting.stime);
269#ifdef CONFIG_PPC_BOOK3E
270 OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
271#endif
272 OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
273#else /* CONFIG_PPC64 */
274#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
275 OFFSET(ACCOUNT_STARTTIME, thread_info, accounting.starttime);
276 OFFSET(ACCOUNT_STARTTIME_USER, thread_info, accounting.starttime_user);
277 OFFSET(ACCOUNT_USER_TIME, thread_info, accounting.utime);
278 OFFSET(ACCOUNT_SYSTEM_TIME, thread_info, accounting.stime);
279#endif
280#endif /* CONFIG_PPC64 */
281
282 /* RTAS */
283 OFFSET(RTASBASE, rtas_t, base);
284 OFFSET(RTASENTRY, rtas_t, entry);
285
286 /* Interrupt register frame */
287 DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
288 DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_OVERHEAD + sizeof(struct pt_regs));
289 STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
290 STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
291 STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
292 STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
293 STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
294 STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
295 STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
296 STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
297 STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
298 STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
299 STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
300 STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
301 STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
302 STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
303#ifndef CONFIG_PPC64
304 STACK_PT_REGS_OFFSET(GPR14, gpr[14]);
305#endif /* CONFIG_PPC64 */
306 /*
307 * Note: these symbols include _ because they overlap with special
308 * register names
309 */
310 STACK_PT_REGS_OFFSET(_NIP, nip);
311 STACK_PT_REGS_OFFSET(_MSR, msr);
312 STACK_PT_REGS_OFFSET(_CTR, ctr);
313 STACK_PT_REGS_OFFSET(_LINK, link);
314 STACK_PT_REGS_OFFSET(_CCR, ccr);
315 STACK_PT_REGS_OFFSET(_XER, xer);
316 STACK_PT_REGS_OFFSET(_DAR, dar);
317 STACK_PT_REGS_OFFSET(_DSISR, dsisr);
318 STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
319 STACK_PT_REGS_OFFSET(RESULT, result);
320 STACK_PT_REGS_OFFSET(_TRAP, trap);
321#ifndef CONFIG_PPC64
322 /*
323 * The PowerPC 400-class & Book-E processors have neither the DAR
324 * nor the DSISR SPRs. Hence, we overload them to hold the similar
325 * DEAR and ESR SPRs for such processors. For critical interrupts
326 * we use them to hold SRR0 and SRR1.
327 */
328 STACK_PT_REGS_OFFSET(_DEAR, dar);
329 STACK_PT_REGS_OFFSET(_ESR, dsisr);
330#else /* CONFIG_PPC64 */
331 STACK_PT_REGS_OFFSET(SOFTE, softe);
332 STACK_PT_REGS_OFFSET(_PPR, ppr);
333#endif /* CONFIG_PPC64 */
334
335#ifdef CONFIG_PPC_KUAP
336 STACK_PT_REGS_OFFSET(STACK_REGS_KUAP, kuap);
337#endif
338
339#if defined(CONFIG_PPC32)
340#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
341 DEFINE(EXC_LVL_SIZE, STACK_EXC_LVL_FRAME_SIZE);
342 DEFINE(MAS0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
343 /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
344 DEFINE(MMUCR, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas0));
345 DEFINE(MAS1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas1));
346 DEFINE(MAS2, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas2));
347 DEFINE(MAS3, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas3));
348 DEFINE(MAS6, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas6));
349 DEFINE(MAS7, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, mas7));
350 DEFINE(_SRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr0));
351 DEFINE(_SRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, srr1));
352 DEFINE(_CSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr0));
353 DEFINE(_CSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, csrr1));
354 DEFINE(_DSRR0, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr0));
355 DEFINE(_DSRR1, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, dsrr1));
356 DEFINE(SAVED_KSP_LIMIT, STACK_INT_FRAME_SIZE+offsetof(struct exception_regs, saved_ksp_limit));
357#endif
358#endif
359
360#ifndef CONFIG_PPC64
361 OFFSET(MM_PGD, mm_struct, pgd);
362#endif /* ! CONFIG_PPC64 */
363
364 /* About the CPU features table */
365 OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
366 OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
367 OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
368
369 OFFSET(pbe_address, pbe, address);
370 OFFSET(pbe_orig_address, pbe, orig_address);
371 OFFSET(pbe_next, pbe, next);
372
373#ifndef CONFIG_PPC64
374 DEFINE(TASK_SIZE, TASK_SIZE);
375 DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
376#endif /* ! CONFIG_PPC64 */
377
378 /* datapage offsets for use by vdso */
379 OFFSET(CFG_TB_ORIG_STAMP, vdso_data, tb_orig_stamp);
380 OFFSET(CFG_TB_TICKS_PER_SEC, vdso_data, tb_ticks_per_sec);
381 OFFSET(CFG_TB_TO_XS, vdso_data, tb_to_xs);
382 OFFSET(CFG_TB_UPDATE_COUNT, vdso_data, tb_update_count);
383 OFFSET(CFG_TZ_MINUTEWEST, vdso_data, tz_minuteswest);
384 OFFSET(CFG_TZ_DSTTIME, vdso_data, tz_dsttime);
385 OFFSET(CFG_SYSCALL_MAP32, vdso_data, syscall_map_32);
386 OFFSET(WTOM_CLOCK_SEC, vdso_data, wtom_clock_sec);
387 OFFSET(WTOM_CLOCK_NSEC, vdso_data, wtom_clock_nsec);
388 OFFSET(STAMP_XTIME, vdso_data, stamp_xtime);
389 OFFSET(STAMP_SEC_FRAC, vdso_data, stamp_sec_fraction);
390 OFFSET(CFG_ICACHE_BLOCKSZ, vdso_data, icache_block_size);
391 OFFSET(CFG_DCACHE_BLOCKSZ, vdso_data, dcache_block_size);
392 OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_data, icache_log_block_size);
393 OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_data, dcache_log_block_size);
394#ifdef CONFIG_PPC64
395 OFFSET(CFG_SYSCALL_MAP64, vdso_data, syscall_map_64);
396 OFFSET(TVAL64_TV_SEC, timeval, tv_sec);
397 OFFSET(TVAL64_TV_USEC, timeval, tv_usec);
398 OFFSET(TVAL32_TV_SEC, old_timeval32, tv_sec);
399 OFFSET(TVAL32_TV_USEC, old_timeval32, tv_usec);
400 OFFSET(TSPC64_TV_SEC, timespec, tv_sec);
401 OFFSET(TSPC64_TV_NSEC, timespec, tv_nsec);
402 OFFSET(TSPC32_TV_SEC, old_timespec32, tv_sec);
403 OFFSET(TSPC32_TV_NSEC, old_timespec32, tv_nsec);
404#else
405 OFFSET(TVAL32_TV_SEC, timeval, tv_sec);
406 OFFSET(TVAL32_TV_USEC, timeval, tv_usec);
407 OFFSET(TSPC32_TV_SEC, timespec, tv_sec);
408 OFFSET(TSPC32_TV_NSEC, timespec, tv_nsec);
409#endif
410 /* timeval/timezone offsets for use by vdso */
411 OFFSET(TZONE_TZ_MINWEST, timezone, tz_minuteswest);
412 OFFSET(TZONE_TZ_DSTTIME, timezone, tz_dsttime);
413
414 /* Other bits used by the vdso */
415 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
416 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
417 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
418 DEFINE(CLOCK_MONOTONIC_COARSE, CLOCK_MONOTONIC_COARSE);
419 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
420 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
421
422#ifdef CONFIG_BUG
423 DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
424#endif
425
426#ifdef CONFIG_PPC_BOOK3S_64
427 DEFINE(PGD_TABLE_SIZE, (sizeof(pgd_t) << max(RADIX_PGD_INDEX_SIZE, H_PGD_INDEX_SIZE)));
428#else
429 DEFINE(PGD_TABLE_SIZE, PGD_TABLE_SIZE);
430#endif
431 DEFINE(PTE_SIZE, sizeof(pte_t));
432
433#ifdef CONFIG_KVM
434 OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
435 OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
436 OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
437 OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
438 OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
439 OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
440#ifdef CONFIG_ALTIVEC
441 OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
442#endif
443 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
444 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
445 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
446#ifdef CONFIG_PPC_BOOK3S
447 OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
448#endif
449 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
450 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
451#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
452 OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
453 OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
454 OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
455 OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
456 OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
457 OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
458 OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
459#endif
460#ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
461 OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
462 OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
463 OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
464 OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
465 OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
466 OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
467 OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
468 OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
469 OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
470 OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
471 OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
472#endif
473 OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
474 OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
475 OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
476 OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
477 OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
478 OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
479 OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
480 OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
481 OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
482 OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
483#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
484 OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
485#endif
486
487 OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
488 OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
489 OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
490 OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
491 OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
492 OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
493
494 OFFSET(VCPU_KVM, kvm_vcpu, kvm);
495 OFFSET(KVM_LPID, kvm, arch.lpid);
496
497 /* book3s */
498#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
499 OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
500 OFFSET(KVM_SDR1, kvm, arch.sdr1);
501 OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
502 OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
503 OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
504 OFFSET(KVM_NEED_FLUSH, kvm, arch.need_tlb_flush.bits);
505 OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
506 OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
507 OFFSET(KVM_RADIX, kvm, arch.radix);
508 OFFSET(KVM_FWNMI, kvm, arch.fwnmi_enabled);
509 OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
510 OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
511 OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
512 OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
513 OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
514 OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
515 OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
516 OFFSET(VCPU_CPU, kvm_vcpu, cpu);
517 OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
518#endif
519#ifdef CONFIG_PPC_BOOK3S
520 OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
521 OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
522 OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
523 OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
524 OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
525 OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
526 OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
527 OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
528 OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
529 OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
530 OFFSET(VCPU_DAWR, kvm_vcpu, arch.dawr);
531 OFFSET(VCPU_DAWRX, kvm_vcpu, arch.dawrx);
532 OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
533 OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
534 OFFSET(VCPU_DEC, kvm_vcpu, arch.dec);
535 OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
536 OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
537 OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
538 OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
539 OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
540 OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
541 OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
542 OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
543 OFFSET(VCPU_SPMC, kvm_vcpu, arch.spmc);
544 OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
545 OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
546 OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
547 OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
548 OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
549 OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
550 OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
551 OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
552 OFFSET(VCPU_FAULT_GPA, kvm_vcpu, arch.fault_gpa);
553 OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
554 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
555 OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
556 OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
557 OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
558 OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
559 OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
560 OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
561 OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
562 OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
563 OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
564 OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
565 OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
566 OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
567 OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
568 OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
569 OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
570 OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
571 OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
572 OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
573 OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
574 OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
575 OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
576 OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
577 OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
578 OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
579 OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
580 OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
581 OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
582 OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
583 DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
584#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
585 OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
586 OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
587 OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
588 OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
589 OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
590 OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
591 OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
592 OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
593 OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
594 OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
595 OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
596 OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
597 OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
598 OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
599 OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
600 OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
601#endif
602
603#ifdef CONFIG_PPC_BOOK3S_64
604#ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
605 OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
606# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
607#else
608# define SVCPU_FIELD(x, f)
609#endif
610# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
611#else /* 32-bit */
612# define SVCPU_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
613# define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
614#endif
615
616 SVCPU_FIELD(SVCPU_CR, cr);
617 SVCPU_FIELD(SVCPU_XER, xer);
618 SVCPU_FIELD(SVCPU_CTR, ctr);
619 SVCPU_FIELD(SVCPU_LR, lr);
620 SVCPU_FIELD(SVCPU_PC, pc);
621 SVCPU_FIELD(SVCPU_R0, gpr[0]);
622 SVCPU_FIELD(SVCPU_R1, gpr[1]);
623 SVCPU_FIELD(SVCPU_R2, gpr[2]);
624 SVCPU_FIELD(SVCPU_R3, gpr[3]);
625 SVCPU_FIELD(SVCPU_R4, gpr[4]);
626 SVCPU_FIELD(SVCPU_R5, gpr[5]);
627 SVCPU_FIELD(SVCPU_R6, gpr[6]);
628 SVCPU_FIELD(SVCPU_R7, gpr[7]);
629 SVCPU_FIELD(SVCPU_R8, gpr[8]);
630 SVCPU_FIELD(SVCPU_R9, gpr[9]);
631 SVCPU_FIELD(SVCPU_R10, gpr[10]);
632 SVCPU_FIELD(SVCPU_R11, gpr[11]);
633 SVCPU_FIELD(SVCPU_R12, gpr[12]);
634 SVCPU_FIELD(SVCPU_R13, gpr[13]);
635 SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
636 SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
637 SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
638 SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
639#ifdef CONFIG_PPC_BOOK3S_32
640 SVCPU_FIELD(SVCPU_SR, sr);
641#endif
642#ifdef CONFIG_PPC64
643 SVCPU_FIELD(SVCPU_SLB, slb);
644 SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
645 SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
646#endif
647
648 HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
649 HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
650 HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
651 HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
652 HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
653 HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
654 HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
655 HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
656 HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
657 HSTATE_FIELD(HSTATE_NAPPING, napping);
658
659#ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
660 HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
661 HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
662 HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
663 HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
664 HSTATE_FIELD(HSTATE_XICS_PHYS, xics_phys);
665 HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
666 HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
667 HSTATE_FIELD(HSTATE_SAVED_XIRR, saved_xirr);
668 HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
669 HSTATE_FIELD(HSTATE_PTID, ptid);
670 HSTATE_FIELD(HSTATE_TID, tid);
671 HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
672 HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
673 HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
674 HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
675 HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
676 HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
677 HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
678 HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
679 HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
680 HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
681 HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
682 HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
683 HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
684 HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
685 HSTATE_FIELD(HSTATE_PURR, host_purr);
686 HSTATE_FIELD(HSTATE_SPURR, host_spurr);
687 HSTATE_FIELD(HSTATE_DSCR, host_dscr);
688 HSTATE_FIELD(HSTATE_DABR, dabr);
689 HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
690 HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
691 DEFINE(IPI_PRIORITY, IPI_PRIORITY);
692 OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
693 OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
694 OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
695 OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
696 OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
697 OFFSET(KVM_SPLIT_DO_SET, kvm_split_mode, do_set);
698 OFFSET(KVM_SPLIT_DO_RESTORE, kvm_split_mode, do_restore);
699#endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
700
701#ifdef CONFIG_PPC_BOOK3S_64
702 HSTATE_FIELD(HSTATE_CFAR, cfar);
703 HSTATE_FIELD(HSTATE_PPR, ppr);
704 HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
705#endif /* CONFIG_PPC_BOOK3S_64 */
706
707#else /* CONFIG_PPC_BOOK3S */
708 OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
709 OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
710 OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
711 OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
712 OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
713 OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
714 OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
715 OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
716 OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
717 OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
718#endif /* CONFIG_PPC_BOOK3S */
719#endif /* CONFIG_KVM */
720
721#ifdef CONFIG_KVM_GUEST
722 OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
723 OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
724 OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
725 OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
726 OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
727 OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
728 OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
729#endif
730
731#ifdef CONFIG_44x
732 DEFINE(PGD_T_LOG2, PGD_T_LOG2);
733 DEFINE(PTE_T_LOG2, PTE_T_LOG2);
734#endif
735#ifdef CONFIG_PPC_FSL_BOOK3E
736 DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
737 OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
738 OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
739 OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
740 OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
741 OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
742#endif
743
744#if defined(CONFIG_KVM) && defined(CONFIG_SPE)
745 OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
746 OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
747 OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
748 OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
749#endif
750
751#ifdef CONFIG_KVM_BOOKE_HV
752 OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
753 OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
754#endif
755
756#ifdef CONFIG_KVM_XICS
757 DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
758 arch.xive_saved_state));
759 DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
760 arch.xive_cam_word));
761 DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
762 DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
763 DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
764 DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
765#endif
766
767#ifdef CONFIG_KVM_EXIT_TIMING
768 OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
769 OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
770 OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
771 OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
772#endif
773
774 DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
775 DEFINE(PPC_DBELL_MSGTYPE, PPC_DBELL_MSGTYPE);
776
777#ifdef CONFIG_PPC_8xx
778 DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
779#endif
780
781 return 0;
782}