1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (C) 2013 NVIDIA Corporation
   4 */
   5
   6#include <linux/clk.h>
   7#include <linux/clk-provider.h>
   8#include <linux/debugfs.h>
 
   9#include <linux/io.h>
  10#include <linux/module.h>
  11#include <linux/of_device.h>
  12#include <linux/platform_device.h>
  13#include <linux/pm_runtime.h>
  14#include <linux/regulator/consumer.h>
  15#include <linux/reset.h>
  16
  17#include <soc/tegra/pmc.h>
  18
  19#include <drm/drm_atomic_helper.h>
  20#include <drm/drm_debugfs.h>
  21#include <drm/drm_dp_helper.h>
  22#include <drm/drm_file.h>
  23#include <drm/drm_panel.h>
  24#include <drm/drm_scdc_helper.h>
  25#include <drm/drm_simple_kms_helper.h>
  26
  27#include "dc.h"
  28#include "dp.h"
  29#include "drm.h"
  30#include "hda.h"
  31#include "sor.h"
  32#include "trace.h"
  33
  34#define SOR_REKEY 0x38
  35
  36struct tegra_sor_hdmi_settings {
  37	unsigned long frequency;
  38
  39	u8 vcocap;
  40	u8 filter;
  41	u8 ichpmp;
  42	u8 loadadj;
  43	u8 tmds_termadj;
  44	u8 tx_pu_value;
  45	u8 bg_temp_coef;
  46	u8 bg_vref_level;
  47	u8 avdd10_level;
  48	u8 avdd14_level;
  49	u8 sparepll;
  50
  51	u8 drive_current[4];
  52	u8 preemphasis[4];
  53};
  54
  55#if 1
  56static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
  57	{
  58		.frequency = 54000000,
  59		.vcocap = 0x0,
  60		.filter = 0x0,
  61		.ichpmp = 0x1,
  62		.loadadj = 0x3,
  63		.tmds_termadj = 0x9,
  64		.tx_pu_value = 0x10,
  65		.bg_temp_coef = 0x3,
  66		.bg_vref_level = 0x8,
  67		.avdd10_level = 0x4,
  68		.avdd14_level = 0x4,
  69		.sparepll = 0x0,
  70		.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  71		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  72	}, {
  73		.frequency = 75000000,
  74		.vcocap = 0x3,
  75		.filter = 0x0,
  76		.ichpmp = 0x1,
  77		.loadadj = 0x3,
  78		.tmds_termadj = 0x9,
  79		.tx_pu_value = 0x40,
  80		.bg_temp_coef = 0x3,
  81		.bg_vref_level = 0x8,
  82		.avdd10_level = 0x4,
  83		.avdd14_level = 0x4,
  84		.sparepll = 0x0,
  85		.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
  86		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
  87	}, {
  88		.frequency = 150000000,
  89		.vcocap = 0x3,
  90		.filter = 0x0,
  91		.ichpmp = 0x1,
  92		.loadadj = 0x3,
  93		.tmds_termadj = 0x9,
  94		.tx_pu_value = 0x66,
  95		.bg_temp_coef = 0x3,
  96		.bg_vref_level = 0x8,
  97		.avdd10_level = 0x4,
  98		.avdd14_level = 0x4,
  99		.sparepll = 0x0,
 100		.drive_current = { 0x33, 0x3a, 0x3a, 0x3a },
 101		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 102	}, {
 103		.frequency = 300000000,
 104		.vcocap = 0x3,
 105		.filter = 0x0,
 106		.ichpmp = 0x1,
 107		.loadadj = 0x3,
 108		.tmds_termadj = 0x9,
 109		.tx_pu_value = 0x66,
 110		.bg_temp_coef = 0x3,
 111		.bg_vref_level = 0xa,
 112		.avdd10_level = 0x4,
 113		.avdd14_level = 0x4,
 114		.sparepll = 0x0,
 115		.drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 116		.preemphasis = { 0x00, 0x17, 0x17, 0x17 },
 117	}, {
 118		.frequency = 600000000,
 119		.vcocap = 0x3,
 120		.filter = 0x0,
 121		.ichpmp = 0x1,
 122		.loadadj = 0x3,
 123		.tmds_termadj = 0x9,
 124		.tx_pu_value = 0x66,
 125		.bg_temp_coef = 0x3,
 126		.bg_vref_level = 0x8,
 127		.avdd10_level = 0x4,
 128		.avdd14_level = 0x4,
 129		.sparepll = 0x0,
 130		.drive_current = { 0x33, 0x3f, 0x3f, 0x3f },
 131		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 132	},
 133};
 134#else
 135static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = {
 136	{
 137		.frequency = 75000000,
 138		.vcocap = 0x3,
 139		.filter = 0x0,
 140		.ichpmp = 0x1,
 141		.loadadj = 0x3,
 142		.tmds_termadj = 0x9,
 143		.tx_pu_value = 0x40,
 144		.bg_temp_coef = 0x3,
 145		.bg_vref_level = 0x8,
 146		.avdd10_level = 0x4,
 147		.avdd14_level = 0x4,
 148		.sparepll = 0x0,
 149		.drive_current = { 0x29, 0x29, 0x29, 0x29 },
 150		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 151	}, {
 152		.frequency = 150000000,
 153		.vcocap = 0x3,
 154		.filter = 0x0,
 155		.ichpmp = 0x1,
 156		.loadadj = 0x3,
 157		.tmds_termadj = 0x9,
 158		.tx_pu_value = 0x66,
 159		.bg_temp_coef = 0x3,
 160		.bg_vref_level = 0x8,
 161		.avdd10_level = 0x4,
 162		.avdd14_level = 0x4,
 163		.sparepll = 0x0,
 164		.drive_current = { 0x30, 0x37, 0x37, 0x37 },
 165		.preemphasis = { 0x01, 0x02, 0x02, 0x02 },
 166	}, {
 167		.frequency = 300000000,
 168		.vcocap = 0x3,
 169		.filter = 0x0,
 170		.ichpmp = 0x6,
 171		.loadadj = 0x3,
 172		.tmds_termadj = 0x9,
 173		.tx_pu_value = 0x66,
 174		.bg_temp_coef = 0x3,
 175		.bg_vref_level = 0xf,
 176		.avdd10_level = 0x4,
 177		.avdd14_level = 0x4,
 178		.sparepll = 0x0,
 179		.drive_current = { 0x30, 0x37, 0x37, 0x37 },
 180		.preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
 181	}, {
 182		.frequency = 600000000,
 183		.vcocap = 0x3,
 184		.filter = 0x0,
 185		.ichpmp = 0xa,
 186		.loadadj = 0x3,
 187		.tmds_termadj = 0xb,
 188		.tx_pu_value = 0x66,
 189		.bg_temp_coef = 0x3,
 190		.bg_vref_level = 0xe,
 191		.avdd10_level = 0x4,
 192		.avdd14_level = 0x4,
 193		.sparepll = 0x0,
 194		.drive_current = { 0x35, 0x3e, 0x3e, 0x3e },
 195		.preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
 196	},
 197};
 198#endif
 199
 200static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
 201	{
 202		.frequency = 54000000,
 203		.vcocap = 0,
 204		.filter = 5,
 205		.ichpmp = 5,
 206		.loadadj = 3,
 207		.tmds_termadj = 0xf,
 208		.tx_pu_value = 0,
 209		.bg_temp_coef = 3,
 210		.bg_vref_level = 8,
 211		.avdd10_level = 4,
 212		.avdd14_level = 4,
 213		.sparepll = 0x54,
 214		.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 215		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 216	}, {
 217		.frequency = 75000000,
 218		.vcocap = 1,
 219		.filter = 5,
 220		.ichpmp = 5,
 221		.loadadj = 3,
 222		.tmds_termadj = 0xf,
 223		.tx_pu_value = 0,
 224		.bg_temp_coef = 3,
 225		.bg_vref_level = 8,
 226		.avdd10_level = 4,
 227		.avdd14_level = 4,
 228		.sparepll = 0x44,
 229		.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 230		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 231	}, {
 232		.frequency = 150000000,
 233		.vcocap = 3,
 234		.filter = 5,
 235		.ichpmp = 5,
 236		.loadadj = 3,
 237		.tmds_termadj = 15,
 238		.tx_pu_value = 0x66 /* 0 */,
 239		.bg_temp_coef = 3,
 240		.bg_vref_level = 8,
 241		.avdd10_level = 4,
 242		.avdd14_level = 4,
 243		.sparepll = 0x00, /* 0x34 */
 244		.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 245		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 246	}, {
 247		.frequency = 300000000,
 248		.vcocap = 3,
 249		.filter = 5,
 250		.ichpmp = 5,
 251		.loadadj = 3,
 252		.tmds_termadj = 15,
 253		.tx_pu_value = 64,
 254		.bg_temp_coef = 3,
 255		.bg_vref_level = 8,
 256		.avdd10_level = 4,
 257		.avdd14_level = 4,
 258		.sparepll = 0x34,
 259		.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 260		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 261	}, {
 262		.frequency = 600000000,
 263		.vcocap = 3,
 264		.filter = 5,
 265		.ichpmp = 5,
 266		.loadadj = 3,
 267		.tmds_termadj = 12,
 268		.tx_pu_value = 96,
 269		.bg_temp_coef = 3,
 270		.bg_vref_level = 8,
 271		.avdd10_level = 4,
 272		.avdd14_level = 4,
 273		.sparepll = 0x34,
 274		.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 275		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 276	}
 277};
 278
 279static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
 280	{
 281		.frequency = 54000000,
 282		.vcocap = 0,
 283		.filter = 5,
 284		.ichpmp = 5,
 285		.loadadj = 3,
 286		.tmds_termadj = 0xf,
 287		.tx_pu_value = 0,
 288		.bg_temp_coef = 3,
 289		.bg_vref_level = 8,
 290		.avdd10_level = 4,
 291		.avdd14_level = 4,
 292		.sparepll = 0x54,
 293		.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 294		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 295	}, {
 296		.frequency = 75000000,
 297		.vcocap = 1,
 298		.filter = 5,
 299		.ichpmp = 5,
 300		.loadadj = 3,
 301		.tmds_termadj = 0xf,
 302		.tx_pu_value = 0,
 303		.bg_temp_coef = 3,
 304		.bg_vref_level = 8,
 305		.avdd10_level = 4,
 306		.avdd14_level = 4,
 307		.sparepll = 0x44,
 308		.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
 309		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 310	}, {
 311		.frequency = 150000000,
 312		.vcocap = 3,
 313		.filter = 5,
 314		.ichpmp = 5,
 315		.loadadj = 3,
 316		.tmds_termadj = 15,
 317		.tx_pu_value = 0x66 /* 0 */,
 318		.bg_temp_coef = 3,
 319		.bg_vref_level = 8,
 320		.avdd10_level = 4,
 321		.avdd14_level = 4,
 322		.sparepll = 0x00, /* 0x34 */
 323		.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
 324		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 325	}, {
 326		.frequency = 300000000,
 327		.vcocap = 3,
 328		.filter = 5,
 329		.ichpmp = 5,
 330		.loadadj = 3,
 331		.tmds_termadj = 15,
 332		.tx_pu_value = 64,
 333		.bg_temp_coef = 3,
 334		.bg_vref_level = 8,
 335		.avdd10_level = 4,
 336		.avdd14_level = 4,
 337		.sparepll = 0x34,
 338		.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 339		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 340	}, {
 341		.frequency = 600000000,
 342		.vcocap = 3,
 343		.filter = 5,
 344		.ichpmp = 5,
 345		.loadadj = 3,
 346		.tmds_termadj = 12,
 347		.tx_pu_value = 96,
 348		.bg_temp_coef = 3,
 349		.bg_vref_level = 8,
 350		.avdd10_level = 4,
 351		.avdd14_level = 4,
 352		.sparepll = 0x34,
 353		.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
 354		.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
 355	}
 356};
 357
 358struct tegra_sor_regs {
 359	unsigned int head_state0;
 360	unsigned int head_state1;
 361	unsigned int head_state2;
 362	unsigned int head_state3;
 363	unsigned int head_state4;
 364	unsigned int head_state5;
 365	unsigned int pll0;
 366	unsigned int pll1;
 367	unsigned int pll2;
 368	unsigned int pll3;
 369	unsigned int dp_padctl0;
 370	unsigned int dp_padctl2;
 371};
 372
 373struct tegra_sor_soc {
 
 374	bool supports_lvds;
 375	bool supports_hdmi;
 376	bool supports_dp;
 377	bool supports_audio;
 378	bool supports_hdcp;
 379
 380	const struct tegra_sor_regs *regs;
 381	bool has_nvdisplay;
 382
 383	const struct tegra_sor_hdmi_settings *settings;
 384	unsigned int num_settings;
 385
 386	const u8 *xbar_cfg;
 387	const u8 *lane_map;
 388
 389	const u8 (*voltage_swing)[4][4];
 390	const u8 (*pre_emphasis)[4][4];
 391	const u8 (*post_cursor)[4][4];
 392	const u8 (*tx_pu)[4][4];
 393};
 394
 395struct tegra_sor;
 396
 397struct tegra_sor_ops {
 398	const char *name;
 399	int (*probe)(struct tegra_sor *sor);
 400	int (*remove)(struct tegra_sor *sor);
 401	void (*audio_enable)(struct tegra_sor *sor);
 402	void (*audio_disable)(struct tegra_sor *sor);
 403};
 404
 405struct tegra_sor {
 406	struct host1x_client client;
 407	struct tegra_output output;
 408	struct device *dev;
 409
 410	const struct tegra_sor_soc *soc;
 411	void __iomem *regs;
 412	unsigned int index;
 413	unsigned int irq;
 414
 415	struct reset_control *rst;
 416	struct clk *clk_parent;
 417	struct clk *clk_safe;
 418	struct clk *clk_out;
 419	struct clk *clk_pad;
 420	struct clk *clk_dp;
 421	struct clk *clk;
 422
 423	u8 xbar_cfg[5];
 424
 425	struct drm_dp_link link;
 426	struct drm_dp_aux *aux;
 427
 428	struct drm_info_list *debugfs_files;
 429
 430	const struct tegra_sor_ops *ops;
 431	enum tegra_io_pad pad;
 432
 433	/* for HDMI 2.0 */
 434	struct tegra_sor_hdmi_settings *settings;
 435	unsigned int num_settings;
 436
 437	struct regulator *avdd_io_supply;
 438	struct regulator *vdd_pll_supply;
 439	struct regulator *hdmi_supply;
 440
 441	struct delayed_work scdc;
 442	bool scdc_enabled;
 443
 444	struct tegra_hda_format format;
 445};
 446
 447struct tegra_sor_state {
 448	struct drm_connector_state base;
 449
 450	unsigned int link_speed;
 451	unsigned long pclk;
 452	unsigned int bpc;
 453};
 454
 455static inline struct tegra_sor_state *
 456to_sor_state(struct drm_connector_state *state)
 457{
 458	return container_of(state, struct tegra_sor_state, base);
 459}
 460
 461struct tegra_sor_config {
 462	u32 bits_per_pixel;
 463
 464	u32 active_polarity;
 465	u32 active_count;
 466	u32 tu_size;
 467	u32 active_frac;
 468	u32 watermark;
 469
 470	u32 hblank_symbols;
 471	u32 vblank_symbols;
 472};
 473
 474static inline struct tegra_sor *
 475host1x_client_to_sor(struct host1x_client *client)
 476{
 477	return container_of(client, struct tegra_sor, client);
 478}
 479
 480static inline struct tegra_sor *to_sor(struct tegra_output *output)
 481{
 482	return container_of(output, struct tegra_sor, output);
 483}
 484
 485static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset)
 486{
 487	u32 value = readl(sor->regs + (offset << 2));
 488
 489	trace_sor_readl(sor->dev, offset, value);
 490
 491	return value;
 492}
 493
 494static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value,
 495				    unsigned int offset)
 496{
 497	trace_sor_writel(sor->dev, offset, value);
 498	writel(value, sor->regs + (offset << 2));
 499}
 500
 501static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent)
 502{
 503	int err;
 504
 505	clk_disable_unprepare(sor->clk);
 506
 507	err = clk_set_parent(sor->clk_out, parent);
 508	if (err < 0)
 509		return err;
 510
 511	err = clk_prepare_enable(sor->clk);
 512	if (err < 0)
 513		return err;
 514
 515	return 0;
 516}
 517
 518struct tegra_clk_sor_pad {
 519	struct clk_hw hw;
 520	struct tegra_sor *sor;
 521};
 522
 523static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw)
 524{
 525	return container_of(hw, struct tegra_clk_sor_pad, hw);
 526}
 527
 528static const char * const tegra_clk_sor_pad_parents[2][2] = {
 529	{ "pll_d_out0", "pll_dp" },
 530	{ "pll_d2_out0", "pll_dp" },
 531};
 532
 533/*
 534 * Implementing ->set_parent() here isn't really required because the parent
 535 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in
 536 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the
 537 * Tegra186 and later SoC generations where the BPMP implements this clock
 538 * and doesn't expose the mux via the common clock framework.
 539 */
 540
 541static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index)
 542{
 543	struct tegra_clk_sor_pad *pad = to_pad(hw);
 544	struct tegra_sor *sor = pad->sor;
 545	u32 value;
 546
 547	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 548	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 549
 550	switch (index) {
 551	case 0:
 552		value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
 553		break;
 554
 555	case 1:
 556		value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 557		break;
 558	}
 559
 560	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 561
 562	return 0;
 563}
 564
 565static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw)
 566{
 567	struct tegra_clk_sor_pad *pad = to_pad(hw);
 568	struct tegra_sor *sor = pad->sor;
 569	u8 parent = U8_MAX;
 570	u32 value;
 571
 572	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 573
 574	switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) {
 575	case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK:
 576	case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK:
 577		parent = 0;
 578		break;
 579
 580	case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK:
 581	case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK:
 582		parent = 1;
 583		break;
 584	}
 585
 586	return parent;
 587}
 588
 589static const struct clk_ops tegra_clk_sor_pad_ops = {
 590	.set_parent = tegra_clk_sor_pad_set_parent,
 591	.get_parent = tegra_clk_sor_pad_get_parent,
 592};
 593
 594static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor,
 595					      const char *name)
 596{
 597	struct tegra_clk_sor_pad *pad;
 598	struct clk_init_data init;
 599	struct clk *clk;
 600
 601	pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL);
 602	if (!pad)
 603		return ERR_PTR(-ENOMEM);
 604
 605	pad->sor = sor;
 606
 607	init.name = name;
 608	init.flags = 0;
 609	init.parent_names = tegra_clk_sor_pad_parents[sor->index];
 610	init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]);
 611	init.ops = &tegra_clk_sor_pad_ops;
 612
 613	pad->hw.init = &init;
 614
 615	clk = devm_clk_register(sor->dev, &pad->hw);
 616
 617	return clk;
 618}
 619
 620static void tegra_sor_filter_rates(struct tegra_sor *sor)
 
 621{
 622	struct drm_dp_link *link = &sor->link;
 623	unsigned int i;
 624
 625	/* Tegra only supports RBR, HBR and HBR2 */
 626	for (i = 0; i < link->num_rates; i++) {
 627		switch (link->rates[i]) {
 628		case 1620000:
 629		case 2700000:
 630		case 5400000:
 631			break;
 632
 633		default:
 634			DRM_DEBUG_KMS("link rate %lu kHz not supported\n",
 635				      link->rates[i]);
 636			link->rates[i] = 0;
 637			break;
 638		}
 639	}
 640
 641	drm_dp_link_update_rates(link);
 642}
 643
 644static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes)
 645{
 646	unsigned long timeout;
 647	u32 value;
 
 648
 649	/*
 650	 * Clear or set the PD_TXD bit corresponding to each lane, depending
 651	 * on whether it is used or not.
 652	 */
 653	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 654
 655	if (lanes <= 2)
 656		value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 657			   SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]));
 658	else
 659		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) |
 660			 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]);
 661
 662	if (lanes <= 1)
 663		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 664	else
 665		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]);
 666
 667	if (lanes == 0)
 668		value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 669	else
 670		value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]);
 671
 672	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 673
 674	/* start lane sequencer */
 675	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 676		SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 677	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 678
 679	timeout = jiffies + msecs_to_jiffies(250);
 680
 681	while (time_before(jiffies, timeout)) {
 682		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 683		if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 684			break;
 685
 686		usleep_range(250, 1000);
 687	}
 688
 689	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 690		return -ETIMEDOUT;
 
 
 
 691
 692	return 0;
 693}
 
 
 
 694
 695static int tegra_sor_power_down_lanes(struct tegra_sor *sor)
 696{
 697	unsigned long timeout;
 698	u32 value;
 699
 700	/* power down all lanes */
 701	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 702	value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 703		   SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 
 704	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 705
 706	/* start lane sequencer */
 707	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 708		SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 709	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 710
 711	timeout = jiffies + msecs_to_jiffies(250);
 712
 713	while (time_before(jiffies, timeout)) {
 714		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 715		if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 716			break;
 717
 718		usleep_range(25, 100);
 719	}
 720
 721	if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 722		return -ETIMEDOUT;
 723
 724	return 0;
 725}
 726
 727static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes)
 728{
 729	u32 value;
 730
 731	/* pre-charge all used lanes */
 732	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 733
 734	if (lanes <= 2)
 735		value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 736			   SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]));
 737	else
 738		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) |
 739			 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]);
 740
 741	if (lanes <= 1)
 742		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 743	else
 744		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]);
 745
 746	if (lanes == 0)
 747		value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 748	else
 749		value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]);
 750
 751	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 752
 753	usleep_range(15, 100);
 754
 755	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 756	value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 757		   SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 758	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 759}
 760
 761static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor)
 762{
 763	u32 mask = 0x08, adj = 0, value;
 764
 765	/* enable pad calibration logic */
 766	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 767	value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 768	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 769
 770	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 771	value |= SOR_PLL1_TMDS_TERM;
 772	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 773
 774	while (mask) {
 775		adj |= mask;
 776
 777		value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 778		value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 779		value |= SOR_PLL1_TMDS_TERMADJ(adj);
 780		tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 781
 782		usleep_range(100, 200);
 783
 784		value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 785		if (value & SOR_PLL1_TERM_COMPOUT)
 786			adj &= ~mask;
 787
 788		mask >>= 1;
 
 
 
 
 789	}
 790
 791	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 792	value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
 793	value |= SOR_PLL1_TMDS_TERMADJ(adj);
 794	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 795
 796	/* disable pad calibration logic */
 797	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 798	value |= SOR_DP_PADCTL_PAD_CAL_PD;
 799	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 800}
 801
 802static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link)
 803{
 804	struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 805	u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0;
 806	const struct tegra_sor_soc *soc = sor->soc;
 807	u32 pattern = 0, tx_pu = 0, value;
 808	unsigned int i;
 809
 810	for (value = 0, i = 0; i < link->lanes; i++) {
 811		u8 vs = link->train.request.voltage_swing[i];
 812		u8 pe = link->train.request.pre_emphasis[i];
 813		u8 pc = link->train.request.post_cursor[i];
 814		u8 shift = sor->soc->lane_map[i] << 3;
 815
 816		voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift;
 817		pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift;
 818		post_cursor |= soc->post_cursor[pc][vs][pe] << shift;
 819
 820		if (sor->soc->tx_pu[pc][vs][pe] > tx_pu)
 821			tx_pu = sor->soc->tx_pu[pc][vs][pe];
 822
 823		switch (link->train.pattern) {
 824		case DP_TRAINING_PATTERN_DISABLE:
 825			value = SOR_DP_TPG_SCRAMBLER_GALIOS |
 826				SOR_DP_TPG_PATTERN_NONE;
 827			break;
 828
 829		case DP_TRAINING_PATTERN_1:
 830			value = SOR_DP_TPG_SCRAMBLER_NONE |
 831				SOR_DP_TPG_PATTERN_TRAIN1;
 832			break;
 833
 834		case DP_TRAINING_PATTERN_2:
 835			value = SOR_DP_TPG_SCRAMBLER_NONE |
 836				SOR_DP_TPG_PATTERN_TRAIN2;
 837			break;
 838
 839		case DP_TRAINING_PATTERN_3:
 840			value = SOR_DP_TPG_SCRAMBLER_NONE |
 841				SOR_DP_TPG_PATTERN_TRAIN3;
 842			break;
 843
 844		default:
 845			return -EINVAL;
 846		}
 847
 848		if (link->caps.channel_coding)
 849			value |= SOR_DP_TPG_CHANNEL_CODING;
 
 
 
 850
 851		pattern = pattern << 8 | value;
 
 
 
 
 852	}
 853
 854	tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0);
 855	tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0);
 856
 857	if (link->caps.tps3_supported)
 858		tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0);
 859
 860	tegra_sor_writel(sor, pattern, SOR_DP_TPG);
 861
 862	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
 863	value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 864	value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 865	value |= SOR_DP_PADCTL_TX_PU(tx_pu);
 866	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
 867
 868	usleep_range(20, 100);
 869
 870	return 0;
 871}
 872
 873static int tegra_sor_dp_link_configure(struct drm_dp_link *link)
 874{
 875	struct tegra_sor *sor = container_of(link, struct tegra_sor, link);
 876	unsigned int rate, lanes;
 877	u32 value;
 878	int err;
 879
 880	rate = drm_dp_link_rate_to_bw_code(link->rate);
 881	lanes = link->lanes;
 882
 883	/* configure link speed and lane count */
 884	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 885	value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 886	value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 887	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 888
 889	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
 890	value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 891	value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 892
 893	if (link->caps.enhanced_framing)
 894		value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 895
 896	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
 897
 898	usleep_range(400, 1000);
 899
 900	/* configure load pulse position adjustment */
 901	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
 902	value &= ~SOR_PLL1_LOADADJ_MASK;
 903
 904	switch (rate) {
 905	case DP_LINK_BW_1_62:
 906		value |= SOR_PLL1_LOADADJ(0x3);
 907		break;
 908
 909	case DP_LINK_BW_2_7:
 910		value |= SOR_PLL1_LOADADJ(0x4);
 911		break;
 912
 913	case DP_LINK_BW_5_4:
 914		value |= SOR_PLL1_LOADADJ(0x6);
 915		break;
 
 
 916	}
 917
 918	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
 919
 920	/* use alternate scrambler reset for eDP */
 921	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
 922
 923	if (link->edp == 0)
 924		value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 925	else
 926		value |= SOR_DP_SPARE_PANEL_INTERNAL;
 927
 928	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
 929
 930	err = tegra_sor_power_down_lanes(sor);
 931	if (err < 0) {
 932		dev_err(sor->dev, "failed to power down lanes: %d\n", err);
 933		return err;
 934	}
 935
 936	/* power up and pre-charge lanes */
 937	err = tegra_sor_power_up_lanes(sor, lanes);
 938	if (err < 0) {
 939		dev_err(sor->dev, "failed to power up %u lane%s: %d\n",
 940			lanes, (lanes != 1) ? "s" : "", err);
 941		return err;
 942	}
 943
 944	tegra_sor_dp_precharge(sor, lanes);
 945
 946	return 0;
 947}
 948
 949static const struct drm_dp_link_ops tegra_sor_dp_link_ops = {
 950	.apply_training = tegra_sor_dp_link_apply_training,
 951	.configure = tegra_sor_dp_link_configure,
 952};
 953
 954static void tegra_sor_super_update(struct tegra_sor *sor)
 955{
 956	tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 957	tegra_sor_writel(sor, 1, SOR_SUPER_STATE0);
 958	tegra_sor_writel(sor, 0, SOR_SUPER_STATE0);
 959}
 960
 961static void tegra_sor_update(struct tegra_sor *sor)
 962{
 963	tegra_sor_writel(sor, 0, SOR_STATE0);
 964	tegra_sor_writel(sor, 1, SOR_STATE0);
 965	tegra_sor_writel(sor, 0, SOR_STATE0);
 966}
 967
 968static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 969{
 970	u32 value;
 971
 972	value = tegra_sor_readl(sor, SOR_PWM_DIV);
 973	value &= ~SOR_PWM_DIV_MASK;
 974	value |= 0x400; /* period */
 975	tegra_sor_writel(sor, value, SOR_PWM_DIV);
 976
 977	value = tegra_sor_readl(sor, SOR_PWM_CTL);
 978	value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 979	value |= 0x400; /* duty cycle */
 980	value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 981	value |= SOR_PWM_CTL_TRIGGER;
 982	tegra_sor_writel(sor, value, SOR_PWM_CTL);
 983
 984	timeout = jiffies + msecs_to_jiffies(timeout);
 985
 986	while (time_before(jiffies, timeout)) {
 987		value = tegra_sor_readl(sor, SOR_PWM_CTL);
 988		if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 989			return 0;
 990
 991		usleep_range(25, 100);
 992	}
 993
 994	return -ETIMEDOUT;
 995}
 996
 997static int tegra_sor_attach(struct tegra_sor *sor)
 998{
 999	unsigned long value, timeout;
1000
1001	/* wake up in normal mode */
1002	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1003	value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
1004	value |= SOR_SUPER_STATE_MODE_NORMAL;
1005	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1006	tegra_sor_super_update(sor);
1007
1008	/* attach */
1009	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1010	value |= SOR_SUPER_STATE_ATTACHED;
1011	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1012	tegra_sor_super_update(sor);
1013
1014	timeout = jiffies + msecs_to_jiffies(250);
1015
1016	while (time_before(jiffies, timeout)) {
1017		value = tegra_sor_readl(sor, SOR_TEST);
1018		if ((value & SOR_TEST_ATTACHED) != 0)
1019			return 0;
1020
1021		usleep_range(25, 100);
1022	}
1023
1024	return -ETIMEDOUT;
1025}
1026
1027static int tegra_sor_wakeup(struct tegra_sor *sor)
1028{
1029	unsigned long value, timeout;
1030
1031	timeout = jiffies + msecs_to_jiffies(250);
1032
1033	/* wait for head to wake up */
1034	while (time_before(jiffies, timeout)) {
1035		value = tegra_sor_readl(sor, SOR_TEST);
1036		value &= SOR_TEST_HEAD_MODE_MASK;
1037
1038		if (value == SOR_TEST_HEAD_MODE_AWAKE)
1039			return 0;
1040
1041		usleep_range(25, 100);
1042	}
1043
1044	return -ETIMEDOUT;
1045}
1046
1047static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
1048{
1049	u32 value;
1050
1051	value = tegra_sor_readl(sor, SOR_PWR);
1052	value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
1053	tegra_sor_writel(sor, value, SOR_PWR);
1054
1055	timeout = jiffies + msecs_to_jiffies(timeout);
1056
1057	while (time_before(jiffies, timeout)) {
1058		value = tegra_sor_readl(sor, SOR_PWR);
1059		if ((value & SOR_PWR_TRIGGER) == 0)
1060			return 0;
1061
1062		usleep_range(25, 100);
1063	}
1064
1065	return -ETIMEDOUT;
1066}
1067
1068struct tegra_sor_params {
1069	/* number of link clocks per line */
1070	unsigned int num_clocks;
1071	/* ratio between input and output */
1072	u64 ratio;
1073	/* precision factor */
1074	u64 precision;
1075
1076	unsigned int active_polarity;
1077	unsigned int active_count;
1078	unsigned int active_frac;
1079	unsigned int tu_size;
1080	unsigned int error;
1081};
1082
1083static int tegra_sor_compute_params(struct tegra_sor *sor,
1084				    struct tegra_sor_params *params,
1085				    unsigned int tu_size)
1086{
1087	u64 active_sym, active_count, frac, approx;
1088	u32 active_polarity, active_frac = 0;
1089	const u64 f = params->precision;
1090	s64 error;
1091
1092	active_sym = params->ratio * tu_size;
1093	active_count = div_u64(active_sym, f) * f;
1094	frac = active_sym - active_count;
1095
1096	/* fraction < 0.5 */
1097	if (frac >= (f / 2)) {
1098		active_polarity = 1;
1099		frac = f - frac;
1100	} else {
1101		active_polarity = 0;
1102	}
1103
1104	if (frac != 0) {
1105		frac = div_u64(f * f,  frac); /* 1/fraction */
1106		if (frac <= (15 * f)) {
1107			active_frac = div_u64(frac, f);
1108
1109			/* round up */
1110			if (active_polarity)
1111				active_frac++;
1112		} else {
1113			active_frac = active_polarity ? 1 : 15;
1114		}
1115	}
1116
1117	if (active_frac == 1)
1118		active_polarity = 0;
1119
1120	if (active_polarity == 1) {
1121		if (active_frac) {
1122			approx = active_count + (active_frac * (f - 1)) * f;
1123			approx = div_u64(approx, active_frac * f);
1124		} else {
1125			approx = active_count + f;
1126		}
1127	} else {
1128		if (active_frac)
1129			approx = active_count + div_u64(f, active_frac);
1130		else
1131			approx = active_count;
1132	}
1133
1134	error = div_s64(active_sym - approx, tu_size);
1135	error *= params->num_clocks;
1136
1137	if (error <= 0 && abs(error) < params->error) {
1138		params->active_count = div_u64(active_count, f);
1139		params->active_polarity = active_polarity;
1140		params->active_frac = active_frac;
1141		params->error = abs(error);
1142		params->tu_size = tu_size;
1143
1144		if (error == 0)
1145			return true;
1146	}
1147
1148	return false;
1149}
1150
1151static int tegra_sor_compute_config(struct tegra_sor *sor,
1152				    const struct drm_display_mode *mode,
1153				    struct tegra_sor_config *config,
1154				    struct drm_dp_link *link)
1155{
1156	const u64 f = 100000, link_rate = link->rate * 1000;
1157	const u64 pclk = mode->clock * 1000;
1158	u64 input, output, watermark, num;
1159	struct tegra_sor_params params;
1160	u32 num_syms_per_line;
1161	unsigned int i;
1162
1163	if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel)
1164		return -EINVAL;
1165
 
1166	input = pclk * config->bits_per_pixel;
1167	output = link_rate * 8 * link->lanes;
1168
1169	if (input >= output)
1170		return -ERANGE;
1171
1172	memset(&params, 0, sizeof(params));
1173	params.ratio = div64_u64(input * f, output);
1174	params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
1175	params.precision = f;
1176	params.error = 64 * f;
1177	params.tu_size = 64;
1178
1179	for (i = params.tu_size; i >= 32; i--)
1180		if (tegra_sor_compute_params(sor, &params, i))
1181			break;
1182
1183	if (params.active_frac == 0) {
1184		config->active_polarity = 0;
1185		config->active_count = params.active_count;
1186
1187		if (!params.active_polarity)
1188			config->active_count--;
1189
1190		config->tu_size = params.tu_size;
1191		config->active_frac = 1;
1192	} else {
1193		config->active_polarity = params.active_polarity;
1194		config->active_count = params.active_count;
1195		config->active_frac = params.active_frac;
1196		config->tu_size = params.tu_size;
1197	}
1198
1199	dev_dbg(sor->dev,
1200		"polarity: %d active count: %d tu size: %d active frac: %d\n",
1201		config->active_polarity, config->active_count,
1202		config->tu_size, config->active_frac);
1203
1204	watermark = params.ratio * config->tu_size * (f - params.ratio);
1205	watermark = div_u64(watermark, f);
1206
1207	watermark = div_u64(watermark + params.error, f);
1208	config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
1209	num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
1210			    (link->lanes * 8);
1211
1212	if (config->watermark > 30) {
1213		config->watermark = 30;
1214		dev_err(sor->dev,
1215			"unable to compute TU size, forcing watermark to %u\n",
1216			config->watermark);
1217	} else if (config->watermark > num_syms_per_line) {
1218		config->watermark = num_syms_per_line;
1219		dev_err(sor->dev, "watermark too high, forcing to %u\n",
1220			config->watermark);
1221	}
1222
1223	/* compute the number of symbols per horizontal blanking interval */
1224	num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
1225	config->hblank_symbols = div_u64(num, pclk);
1226
1227	if (link->caps.enhanced_framing)
1228		config->hblank_symbols -= 3;
1229
1230	config->hblank_symbols -= 12 / link->lanes;
1231
1232	/* compute the number of symbols per vertical blanking interval */
1233	num = (mode->hdisplay - 25) * link_rate;
1234	config->vblank_symbols = div_u64(num, pclk);
1235	config->vblank_symbols -= 36 / link->lanes + 4;
1236
1237	dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
1238		config->vblank_symbols);
1239
1240	return 0;
1241}
1242
1243static void tegra_sor_apply_config(struct tegra_sor *sor,
1244				   const struct tegra_sor_config *config)
1245{
1246	u32 value;
1247
1248	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
1249	value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1250	value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size);
1251	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
1252
1253	value = tegra_sor_readl(sor, SOR_DP_CONFIG0);
1254	value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1255	value |= SOR_DP_CONFIG_WATERMARK(config->watermark);
1256
1257	value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1258	value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count);
1259
1260	value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1261	value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac);
1262
1263	if (config->active_polarity)
1264		value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1265	else
1266		value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1267
1268	value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1269	value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1270	tegra_sor_writel(sor, value, SOR_DP_CONFIG0);
1271
1272	value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1273	value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1274	value |= config->hblank_symbols & 0xffff;
1275	tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1276
1277	value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1278	value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1279	value |= config->vblank_symbols & 0xffff;
1280	tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1281}
1282
1283static void tegra_sor_mode_set(struct tegra_sor *sor,
1284			       const struct drm_display_mode *mode,
1285			       struct tegra_sor_state *state)
1286{
1287	struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
1288	unsigned int vbe, vse, hbe, hse, vbs, hbs;
1289	u32 value;
1290
1291	value = tegra_sor_readl(sor, SOR_STATE1);
1292	value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK;
1293	value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1294	value &= ~SOR_STATE_ASY_OWNER_MASK;
1295
1296	value |= SOR_STATE_ASY_CRC_MODE_COMPLETE |
1297		 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1298
1299	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1300		value &= ~SOR_STATE_ASY_HSYNCPOL;
1301
1302	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1303		value |= SOR_STATE_ASY_HSYNCPOL;
1304
1305	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1306		value &= ~SOR_STATE_ASY_VSYNCPOL;
1307
1308	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1309		value |= SOR_STATE_ASY_VSYNCPOL;
1310
1311	switch (state->bpc) {
1312	case 16:
1313		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444;
1314		break;
1315
1316	case 12:
1317		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444;
1318		break;
1319
1320	case 10:
1321		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444;
1322		break;
1323
1324	case 8:
1325		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1326		break;
1327
1328	case 6:
1329		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1330		break;
1331
1332	default:
1333		value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1334		break;
1335	}
1336
1337	tegra_sor_writel(sor, value, SOR_STATE1);
1338
1339	/*
1340	 * TODO: The video timing programming below doesn't seem to match the
1341	 * register definitions.
1342	 */
1343
1344	value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1345	tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe);
1346
1347	/* sync end = sync width - 1 */
1348	vse = mode->vsync_end - mode->vsync_start - 1;
1349	hse = mode->hsync_end - mode->hsync_start - 1;
1350
1351	value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1352	tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe);
1353
1354	/* blank end = sync end + back porch */
1355	vbe = vse + (mode->vtotal - mode->vsync_end);
1356	hbe = hse + (mode->htotal - mode->hsync_end);
1357
1358	value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1359	tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe);
1360
1361	/* blank start = blank end + active */
1362	vbs = vbe + mode->vdisplay;
1363	hbs = hbe + mode->hdisplay;
1364
1365	value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1366	tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe);
1367
1368	/* XXX interlacing support */
1369	tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe);
1370}
1371
1372static int tegra_sor_detach(struct tegra_sor *sor)
1373{
1374	unsigned long value, timeout;
1375
1376	/* switch to safe mode */
1377	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1378	value &= ~SOR_SUPER_STATE_MODE_NORMAL;
1379	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1380	tegra_sor_super_update(sor);
1381
1382	timeout = jiffies + msecs_to_jiffies(250);
1383
1384	while (time_before(jiffies, timeout)) {
1385		value = tegra_sor_readl(sor, SOR_PWR);
1386		if (value & SOR_PWR_MODE_SAFE)
1387			break;
1388	}
1389
1390	if ((value & SOR_PWR_MODE_SAFE) == 0)
1391		return -ETIMEDOUT;
1392
1393	/* go to sleep */
1394	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1395	value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
1396	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1397	tegra_sor_super_update(sor);
1398
1399	/* detach */
1400	value = tegra_sor_readl(sor, SOR_SUPER_STATE1);
1401	value &= ~SOR_SUPER_STATE_ATTACHED;
1402	tegra_sor_writel(sor, value, SOR_SUPER_STATE1);
1403	tegra_sor_super_update(sor);
1404
1405	timeout = jiffies + msecs_to_jiffies(250);
1406
1407	while (time_before(jiffies, timeout)) {
1408		value = tegra_sor_readl(sor, SOR_TEST);
1409		if ((value & SOR_TEST_ATTACHED) == 0)
1410			break;
1411
1412		usleep_range(25, 100);
1413	}
1414
1415	if ((value & SOR_TEST_ATTACHED) != 0)
1416		return -ETIMEDOUT;
1417
1418	return 0;
1419}
1420
1421static int tegra_sor_power_down(struct tegra_sor *sor)
1422{
1423	unsigned long value, timeout;
1424	int err;
1425
1426	value = tegra_sor_readl(sor, SOR_PWR);
1427	value &= ~SOR_PWR_NORMAL_STATE_PU;
1428	value |= SOR_PWR_TRIGGER;
1429	tegra_sor_writel(sor, value, SOR_PWR);
1430
1431	timeout = jiffies + msecs_to_jiffies(250);
1432
1433	while (time_before(jiffies, timeout)) {
1434		value = tegra_sor_readl(sor, SOR_PWR);
1435		if ((value & SOR_PWR_TRIGGER) == 0)
1436			return 0;
1437
1438		usleep_range(25, 100);
1439	}
1440
1441	if ((value & SOR_PWR_TRIGGER) != 0)
1442		return -ETIMEDOUT;
1443
1444	/* switch to safe parent clock */
1445	err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
1446	if (err < 0) {
1447		dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
1448		return err;
1449	}
1450
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1451	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1452	value |= SOR_PLL2_PORT_POWERDOWN;
1453	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1454
1455	usleep_range(20, 100);
1456
1457	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
1458	value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR;
1459	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
1460
1461	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
1462	value |= SOR_PLL2_SEQ_PLLCAPPD;
1463	value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
1464	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
1465
1466	usleep_range(20, 100);
1467
1468	return 0;
1469}
1470
1471static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1472{
1473	u32 value;
1474
1475	timeout = jiffies + msecs_to_jiffies(timeout);
1476
1477	while (time_before(jiffies, timeout)) {
1478		value = tegra_sor_readl(sor, SOR_CRCA);
1479		if (value & SOR_CRCA_VALID)
1480			return 0;
1481
1482		usleep_range(100, 200);
1483	}
1484
1485	return -ETIMEDOUT;
1486}
1487
1488static int tegra_sor_show_crc(struct seq_file *s, void *data)
1489{
1490	struct drm_info_node *node = s->private;
1491	struct tegra_sor *sor = node->info_ent->data;
1492	struct drm_crtc *crtc = sor->output.encoder.crtc;
1493	struct drm_device *drm = node->minor->dev;
1494	int err = 0;
1495	u32 value;
1496
1497	drm_modeset_lock_all(drm);
1498
1499	if (!crtc || !crtc->state->active) {
1500		err = -EBUSY;
1501		goto unlock;
1502	}
1503
1504	value = tegra_sor_readl(sor, SOR_STATE1);
1505	value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1506	tegra_sor_writel(sor, value, SOR_STATE1);
1507
1508	value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1509	value |= SOR_CRC_CNTRL_ENABLE;
1510	tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1511
1512	value = tegra_sor_readl(sor, SOR_TEST);
1513	value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1514	tegra_sor_writel(sor, value, SOR_TEST);
1515
1516	err = tegra_sor_crc_wait(sor, 100);
1517	if (err < 0)
1518		goto unlock;
1519
1520	tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA);
1521	value = tegra_sor_readl(sor, SOR_CRCB);
1522
1523	seq_printf(s, "%08x\n", value);
1524
1525unlock:
1526	drm_modeset_unlock_all(drm);
1527	return err;
1528}
1529
1530#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
1531
1532static const struct debugfs_reg32 tegra_sor_regs[] = {
1533	DEBUGFS_REG32(SOR_CTXSW),
1534	DEBUGFS_REG32(SOR_SUPER_STATE0),
1535	DEBUGFS_REG32(SOR_SUPER_STATE1),
1536	DEBUGFS_REG32(SOR_STATE0),
1537	DEBUGFS_REG32(SOR_STATE1),
1538	DEBUGFS_REG32(SOR_HEAD_STATE0(0)),
1539	DEBUGFS_REG32(SOR_HEAD_STATE0(1)),
1540	DEBUGFS_REG32(SOR_HEAD_STATE1(0)),
1541	DEBUGFS_REG32(SOR_HEAD_STATE1(1)),
1542	DEBUGFS_REG32(SOR_HEAD_STATE2(0)),
1543	DEBUGFS_REG32(SOR_HEAD_STATE2(1)),
1544	DEBUGFS_REG32(SOR_HEAD_STATE3(0)),
1545	DEBUGFS_REG32(SOR_HEAD_STATE3(1)),
1546	DEBUGFS_REG32(SOR_HEAD_STATE4(0)),
1547	DEBUGFS_REG32(SOR_HEAD_STATE4(1)),
1548	DEBUGFS_REG32(SOR_HEAD_STATE5(0)),
1549	DEBUGFS_REG32(SOR_HEAD_STATE5(1)),
1550	DEBUGFS_REG32(SOR_CRC_CNTRL),
1551	DEBUGFS_REG32(SOR_DP_DEBUG_MVID),
1552	DEBUGFS_REG32(SOR_CLK_CNTRL),
1553	DEBUGFS_REG32(SOR_CAP),
1554	DEBUGFS_REG32(SOR_PWR),
1555	DEBUGFS_REG32(SOR_TEST),
1556	DEBUGFS_REG32(SOR_PLL0),
1557	DEBUGFS_REG32(SOR_PLL1),
1558	DEBUGFS_REG32(SOR_PLL2),
1559	DEBUGFS_REG32(SOR_PLL3),
1560	DEBUGFS_REG32(SOR_CSTM),
1561	DEBUGFS_REG32(SOR_LVDS),
1562	DEBUGFS_REG32(SOR_CRCA),
1563	DEBUGFS_REG32(SOR_CRCB),
1564	DEBUGFS_REG32(SOR_BLANK),
1565	DEBUGFS_REG32(SOR_SEQ_CTL),
1566	DEBUGFS_REG32(SOR_LANE_SEQ_CTL),
1567	DEBUGFS_REG32(SOR_SEQ_INST(0)),
1568	DEBUGFS_REG32(SOR_SEQ_INST(1)),
1569	DEBUGFS_REG32(SOR_SEQ_INST(2)),
1570	DEBUGFS_REG32(SOR_SEQ_INST(3)),
1571	DEBUGFS_REG32(SOR_SEQ_INST(4)),
1572	DEBUGFS_REG32(SOR_SEQ_INST(5)),
1573	DEBUGFS_REG32(SOR_SEQ_INST(6)),
1574	DEBUGFS_REG32(SOR_SEQ_INST(7)),
1575	DEBUGFS_REG32(SOR_SEQ_INST(8)),
1576	DEBUGFS_REG32(SOR_SEQ_INST(9)),
1577	DEBUGFS_REG32(SOR_SEQ_INST(10)),
1578	DEBUGFS_REG32(SOR_SEQ_INST(11)),
1579	DEBUGFS_REG32(SOR_SEQ_INST(12)),
1580	DEBUGFS_REG32(SOR_SEQ_INST(13)),
1581	DEBUGFS_REG32(SOR_SEQ_INST(14)),
1582	DEBUGFS_REG32(SOR_SEQ_INST(15)),
1583	DEBUGFS_REG32(SOR_PWM_DIV),
1584	DEBUGFS_REG32(SOR_PWM_CTL),
1585	DEBUGFS_REG32(SOR_VCRC_A0),
1586	DEBUGFS_REG32(SOR_VCRC_A1),
1587	DEBUGFS_REG32(SOR_VCRC_B0),
1588	DEBUGFS_REG32(SOR_VCRC_B1),
1589	DEBUGFS_REG32(SOR_CCRC_A0),
1590	DEBUGFS_REG32(SOR_CCRC_A1),
1591	DEBUGFS_REG32(SOR_CCRC_B0),
1592	DEBUGFS_REG32(SOR_CCRC_B1),
1593	DEBUGFS_REG32(SOR_EDATA_A0),
1594	DEBUGFS_REG32(SOR_EDATA_A1),
1595	DEBUGFS_REG32(SOR_EDATA_B0),
1596	DEBUGFS_REG32(SOR_EDATA_B1),
1597	DEBUGFS_REG32(SOR_COUNT_A0),
1598	DEBUGFS_REG32(SOR_COUNT_A1),
1599	DEBUGFS_REG32(SOR_COUNT_B0),
1600	DEBUGFS_REG32(SOR_COUNT_B1),
1601	DEBUGFS_REG32(SOR_DEBUG_A0),
1602	DEBUGFS_REG32(SOR_DEBUG_A1),
1603	DEBUGFS_REG32(SOR_DEBUG_B0),
1604	DEBUGFS_REG32(SOR_DEBUG_B1),
1605	DEBUGFS_REG32(SOR_TRIG),
1606	DEBUGFS_REG32(SOR_MSCHECK),
1607	DEBUGFS_REG32(SOR_XBAR_CTRL),
1608	DEBUGFS_REG32(SOR_XBAR_POL),
1609	DEBUGFS_REG32(SOR_DP_LINKCTL0),
1610	DEBUGFS_REG32(SOR_DP_LINKCTL1),
1611	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0),
1612	DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1),
1613	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0),
1614	DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1),
1615	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0),
1616	DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1),
1617	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0),
1618	DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1),
1619	DEBUGFS_REG32(SOR_LANE_POSTCURSOR0),
1620	DEBUGFS_REG32(SOR_LANE_POSTCURSOR1),
1621	DEBUGFS_REG32(SOR_DP_CONFIG0),
1622	DEBUGFS_REG32(SOR_DP_CONFIG1),
1623	DEBUGFS_REG32(SOR_DP_MN0),
1624	DEBUGFS_REG32(SOR_DP_MN1),
1625	DEBUGFS_REG32(SOR_DP_PADCTL0),
1626	DEBUGFS_REG32(SOR_DP_PADCTL1),
1627	DEBUGFS_REG32(SOR_DP_PADCTL2),
1628	DEBUGFS_REG32(SOR_DP_DEBUG0),
1629	DEBUGFS_REG32(SOR_DP_DEBUG1),
1630	DEBUGFS_REG32(SOR_DP_SPARE0),
1631	DEBUGFS_REG32(SOR_DP_SPARE1),
1632	DEBUGFS_REG32(SOR_DP_AUDIO_CTRL),
1633	DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS),
1634	DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS),
1635	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER),
1636	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0),
1637	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1),
1638	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2),
1639	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3),
1640	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4),
1641	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5),
1642	DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6),
1643	DEBUGFS_REG32(SOR_DP_TPG),
1644	DEBUGFS_REG32(SOR_DP_TPG_CONFIG),
1645	DEBUGFS_REG32(SOR_DP_LQ_CSTM0),
1646	DEBUGFS_REG32(SOR_DP_LQ_CSTM1),
1647	DEBUGFS_REG32(SOR_DP_LQ_CSTM2),
1648};
1649
1650static int tegra_sor_show_regs(struct seq_file *s, void *data)
1651{
1652	struct drm_info_node *node = s->private;
1653	struct tegra_sor *sor = node->info_ent->data;
1654	struct drm_crtc *crtc = sor->output.encoder.crtc;
1655	struct drm_device *drm = node->minor->dev;
1656	unsigned int i;
1657	int err = 0;
1658
1659	drm_modeset_lock_all(drm);
1660
1661	if (!crtc || !crtc->state->active) {
1662		err = -EBUSY;
1663		goto unlock;
1664	}
1665
1666	for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) {
1667		unsigned int offset = tegra_sor_regs[i].offset;
1668
1669		seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name,
1670			   offset, tegra_sor_readl(sor, offset));
1671	}
1672
1673unlock:
1674	drm_modeset_unlock_all(drm);
1675	return err;
1676}
1677
1678static const struct drm_info_list debugfs_files[] = {
1679	{ "crc", tegra_sor_show_crc, 0, NULL },
1680	{ "regs", tegra_sor_show_regs, 0, NULL },
1681};
1682
1683static int tegra_sor_late_register(struct drm_connector *connector)
1684{
1685	struct tegra_output *output = connector_to_output(connector);
1686	unsigned int i, count = ARRAY_SIZE(debugfs_files);
1687	struct drm_minor *minor = connector->dev->primary;
1688	struct dentry *root = connector->debugfs_entry;
1689	struct tegra_sor *sor = to_sor(output);
 
1690
1691	sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1692				     GFP_KERNEL);
1693	if (!sor->debugfs_files)
1694		return -ENOMEM;
1695
1696	for (i = 0; i < count; i++)
1697		sor->debugfs_files[i].data = sor;
1698
1699	drm_debugfs_create_files(sor->debugfs_files, count, root, minor);
 
 
1700
1701	return 0;
 
 
 
 
 
 
1702}
1703
1704static void tegra_sor_early_unregister(struct drm_connector *connector)
1705{
1706	struct tegra_output *output = connector_to_output(connector);
1707	unsigned int count = ARRAY_SIZE(debugfs_files);
1708	struct tegra_sor *sor = to_sor(output);
1709
1710	drm_debugfs_remove_files(sor->debugfs_files, count,
1711				 connector->dev->primary);
1712	kfree(sor->debugfs_files);
1713	sor->debugfs_files = NULL;
1714}
1715
1716static void tegra_sor_connector_reset(struct drm_connector *connector)
1717{
1718	struct tegra_sor_state *state;
1719
1720	state = kzalloc(sizeof(*state), GFP_KERNEL);
1721	if (!state)
1722		return;
1723
1724	if (connector->state) {
1725		__drm_atomic_helper_connector_destroy_state(connector->state);
1726		kfree(connector->state);
1727	}
1728
1729	__drm_atomic_helper_connector_reset(connector, &state->base);
1730}
1731
1732static enum drm_connector_status
1733tegra_sor_connector_detect(struct drm_connector *connector, bool force)
1734{
1735	struct tegra_output *output = connector_to_output(connector);
1736	struct tegra_sor *sor = to_sor(output);
1737
1738	if (sor->aux)
1739		return drm_dp_aux_detect(sor->aux);
1740
1741	return tegra_output_connector_detect(connector, force);
1742}
1743
1744static struct drm_connector_state *
1745tegra_sor_connector_duplicate_state(struct drm_connector *connector)
1746{
1747	struct tegra_sor_state *state = to_sor_state(connector->state);
1748	struct tegra_sor_state *copy;
1749
1750	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
1751	if (!copy)
1752		return NULL;
1753
1754	__drm_atomic_helper_connector_duplicate_state(connector, &copy->base);
1755
1756	return &copy->base;
1757}
1758
1759static const struct drm_connector_funcs tegra_sor_connector_funcs = {
1760	.reset = tegra_sor_connector_reset,
1761	.detect = tegra_sor_connector_detect,
1762	.fill_modes = drm_helper_probe_single_connector_modes,
1763	.destroy = tegra_output_connector_destroy,
1764	.atomic_duplicate_state = tegra_sor_connector_duplicate_state,
1765	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1766	.late_register = tegra_sor_late_register,
1767	.early_unregister = tegra_sor_early_unregister,
1768};
1769
1770static int tegra_sor_connector_get_modes(struct drm_connector *connector)
1771{
1772	struct tegra_output *output = connector_to_output(connector);
1773	struct tegra_sor *sor = to_sor(output);
1774	int err;
1775
1776	if (sor->aux)
1777		drm_dp_aux_enable(sor->aux);
1778
1779	err = tegra_output_connector_get_modes(connector);
1780
1781	if (sor->aux)
1782		drm_dp_aux_disable(sor->aux);
1783
1784	return err;
1785}
1786
1787static enum drm_mode_status
1788tegra_sor_connector_mode_valid(struct drm_connector *connector,
1789			       struct drm_display_mode *mode)
1790{
1791	return MODE_OK;
1792}
1793
1794static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
1795	.get_modes = tegra_sor_connector_get_modes,
1796	.mode_valid = tegra_sor_connector_mode_valid,
1797};
1798
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1799static int
1800tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1801			       struct drm_crtc_state *crtc_state,
1802			       struct drm_connector_state *conn_state)
1803{
1804	struct tegra_output *output = encoder_to_output(encoder);
1805	struct tegra_sor_state *state = to_sor_state(conn_state);
1806	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1807	unsigned long pclk = crtc_state->mode.clock * 1000;
1808	struct tegra_sor *sor = to_sor(output);
1809	struct drm_display_info *info;
1810	int err;
1811
1812	info = &output->connector.display_info;
1813
1814	/*
1815	 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so
1816	 * the pixel clock must be corrected accordingly.
1817	 */
1818	if (pclk >= 340000000) {
1819		state->link_speed = 20;
1820		state->pclk = pclk / 2;
1821	} else {
1822		state->link_speed = 10;
1823		state->pclk = pclk;
1824	}
1825
1826	err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1827					 pclk, 0);
1828	if (err < 0) {
1829		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1830		return err;
1831	}
1832
1833	switch (info->bpc) {
1834	case 8:
1835	case 6:
1836		state->bpc = info->bpc;
1837		break;
1838
1839	default:
1840		DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc);
1841		state->bpc = 8;
1842		break;
1843	}
1844
1845	return 0;
1846}
1847
 
 
 
 
 
 
1848static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size)
1849{
1850	u32 value = 0;
1851	size_t i;
1852
1853	for (i = size; i > 0; i--)
1854		value = (value << 8) | ptr[i - 1];
1855
1856	return value;
1857}
1858
1859static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor,
1860					  const void *data, size_t size)
1861{
1862	const u8 *ptr = data;
1863	unsigned long offset;
1864	size_t i, j;
1865	u32 value;
1866
1867	switch (ptr[0]) {
1868	case HDMI_INFOFRAME_TYPE_AVI:
1869		offset = SOR_HDMI_AVI_INFOFRAME_HEADER;
1870		break;
1871
1872	case HDMI_INFOFRAME_TYPE_AUDIO:
1873		offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER;
1874		break;
1875
1876	case HDMI_INFOFRAME_TYPE_VENDOR:
1877		offset = SOR_HDMI_VSI_INFOFRAME_HEADER;
1878		break;
1879
1880	default:
1881		dev_err(sor->dev, "unsupported infoframe type: %02x\n",
1882			ptr[0]);
1883		return;
1884	}
1885
1886	value = INFOFRAME_HEADER_TYPE(ptr[0]) |
1887		INFOFRAME_HEADER_VERSION(ptr[1]) |
1888		INFOFRAME_HEADER_LEN(ptr[2]);
1889	tegra_sor_writel(sor, value, offset);
1890	offset++;
1891
1892	/*
1893	 * Each subpack contains 7 bytes, divided into:
1894	 * - subpack_low: bytes 0 - 3
1895	 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
1896	 */
1897	for (i = 3, j = 0; i < size; i += 7, j += 8) {
1898		size_t rem = size - i, num = min_t(size_t, rem, 4);
1899
1900		value = tegra_sor_hdmi_subpack(&ptr[i], num);
1901		tegra_sor_writel(sor, value, offset++);
1902
1903		num = min_t(size_t, rem - num, 3);
1904
1905		value = tegra_sor_hdmi_subpack(&ptr[i + 4], num);
1906		tegra_sor_writel(sor, value, offset++);
1907	}
1908}
1909
1910static int
1911tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor,
1912				   const struct drm_display_mode *mode)
1913{
1914	u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
1915	struct hdmi_avi_infoframe frame;
1916	u32 value;
1917	int err;
1918
1919	/* disable AVI infoframe */
1920	value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1921	value &= ~INFOFRAME_CTRL_SINGLE;
1922	value &= ~INFOFRAME_CTRL_OTHER;
1923	value &= ~INFOFRAME_CTRL_ENABLE;
1924	tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1925
1926	err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
1927						       &sor->output.connector, mode);
1928	if (err < 0) {
1929		dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
1930		return err;
1931	}
1932
1933	err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1934	if (err < 0) {
1935		dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err);
1936		return err;
1937	}
1938
1939	tegra_sor_hdmi_write_infopack(sor, buffer, err);
1940
1941	/* enable AVI infoframe */
1942	value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL);
1943	value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
1944	value |= INFOFRAME_CTRL_ENABLE;
1945	tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL);
1946
1947	return 0;
1948}
1949
1950static void tegra_sor_write_eld(struct tegra_sor *sor)
1951{
1952	size_t length = drm_eld_size(sor->output.connector.eld), i;
1953
1954	for (i = 0; i < length; i++)
1955		tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i],
1956				 SOR_AUDIO_HDA_ELD_BUFWR);
1957
1958	/*
1959	 * The HDA codec will always report an ELD buffer size of 96 bytes and
1960	 * the HDA codec driver will check that each byte read from the buffer
1961	 * is valid. Therefore every byte must be written, even if no 96 bytes
1962	 * were parsed from EDID.
1963	 */
1964	for (i = length; i < 96; i++)
1965		tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR);
1966}
1967
1968static void tegra_sor_audio_prepare(struct tegra_sor *sor)
1969{
1970	u32 value;
1971
1972	/*
1973	 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1974	 * is used for interoperability between the HDA codec driver and the
1975	 * HDMI/DP driver.
1976	 */
1977	value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0;
1978	tegra_sor_writel(sor, value, SOR_INT_ENABLE);
1979	tegra_sor_writel(sor, value, SOR_INT_MASK);
1980
1981	tegra_sor_write_eld(sor);
1982
1983	value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD;
1984	tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE);
1985}
1986
1987static void tegra_sor_audio_unprepare(struct tegra_sor *sor)
1988{
1989	tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE);
1990	tegra_sor_writel(sor, 0, SOR_INT_MASK);
1991	tegra_sor_writel(sor, 0, SOR_INT_ENABLE);
1992}
1993
1994static void tegra_sor_audio_enable(struct tegra_sor *sor)
1995{
1996	u32 value;
1997
1998	value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL);
1999
2000	/* select HDA audio input */
2001	value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK);
2002	value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA);
2003
2004	/* inject null samples */
2005	if (sor->format.channels != 2)
2006		value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2007	else
2008		value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL;
2009
2010	value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH;
2011
2012	tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL);
2013
2014	/* enable advertising HBR capability */
2015	tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE);
2016}
2017
2018static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor)
2019{
2020	u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
2021	struct hdmi_audio_infoframe frame;
2022	u32 value;
2023	int err;
2024
2025	err = hdmi_audio_infoframe_init(&frame);
2026	if (err < 0) {
2027		dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err);
2028		return err;
2029	}
2030
2031	frame.channels = sor->format.channels;
2032
2033	err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
2034	if (err < 0) {
2035		dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err);
2036		return err;
2037	}
2038
2039	tegra_sor_hdmi_write_infopack(sor, buffer, err);
2040
2041	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2042	value |= INFOFRAME_CTRL_CHECKSUM_ENABLE;
2043	value |= INFOFRAME_CTRL_ENABLE;
2044	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2045
2046	return 0;
2047}
2048
2049static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor)
2050{
2051	u32 value;
2052
2053	tegra_sor_audio_enable(sor);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2054
2055	tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL);
2056
2057	value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH |
2058		SOR_HDMI_SPARE_CTS_RESET(1) |
2059		SOR_HDMI_SPARE_HW_CTS_ENABLE;
2060	tegra_sor_writel(sor, value, SOR_HDMI_SPARE);
2061
2062	/* enable HW CTS */
2063	value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0);
2064	tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW);
2065
2066	/* allow packet to be sent */
2067	value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE;
2068	tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH);
2069
2070	/* reset N counter and enable lookup */
2071	value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP;
2072	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2073
2074	value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000);
2075	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320);
2076	tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320);
2077
2078	tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441);
2079	tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441);
2080
2081	tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882);
2082	tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882);
2083
2084	tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764);
2085	tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764);
2086
2087	value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000);
2088	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480);
2089	tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480);
2090
2091	value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000);
2092	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960);
2093	tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960);
2094
2095	value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000);
2096	tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920);
2097	tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920);
2098
2099	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N);
2100	value &= ~SOR_HDMI_AUDIO_N_RESET;
2101	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N);
2102
2103	tegra_sor_hdmi_enable_audio_infoframe(sor);
2104}
2105
2106static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor)
2107{
2108	u32 value;
2109
2110	value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2111	value &= ~INFOFRAME_CTRL_ENABLE;
2112	tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL);
2113}
2114
2115static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor)
2116{
2117	tegra_sor_hdmi_disable_audio_infoframe(sor);
2118}
2119
2120static struct tegra_sor_hdmi_settings *
2121tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency)
2122{
2123	unsigned int i;
2124
2125	for (i = 0; i < sor->num_settings; i++)
2126		if (frequency <= sor->settings[i].frequency)
2127			return &sor->settings[i];
2128
2129	return NULL;
2130}
2131
2132static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor)
2133{
2134	u32 value;
2135
2136	value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2137	value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2138	value &= ~SOR_HDMI2_CTRL_SCRAMBLE;
2139	tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2140}
2141
2142static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor)
2143{
2144	struct i2c_adapter *ddc = sor->output.ddc;
2145
2146	drm_scdc_set_high_tmds_clock_ratio(ddc, false);
2147	drm_scdc_set_scrambling(ddc, false);
2148
2149	tegra_sor_hdmi_disable_scrambling(sor);
2150}
2151
2152static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor)
2153{
2154	if (sor->scdc_enabled) {
2155		cancel_delayed_work_sync(&sor->scdc);
2156		tegra_sor_hdmi_scdc_disable(sor);
2157	}
2158}
2159
2160static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor)
2161{
2162	u32 value;
2163
2164	value = tegra_sor_readl(sor, SOR_HDMI2_CTRL);
2165	value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4;
2166	value |= SOR_HDMI2_CTRL_SCRAMBLE;
2167	tegra_sor_writel(sor, value, SOR_HDMI2_CTRL);
2168}
2169
2170static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor)
2171{
2172	struct i2c_adapter *ddc = sor->output.ddc;
2173
2174	drm_scdc_set_high_tmds_clock_ratio(ddc, true);
2175	drm_scdc_set_scrambling(ddc, true);
2176
2177	tegra_sor_hdmi_enable_scrambling(sor);
2178}
2179
2180static void tegra_sor_hdmi_scdc_work(struct work_struct *work)
2181{
2182	struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work);
2183	struct i2c_adapter *ddc = sor->output.ddc;
2184
2185	if (!drm_scdc_get_scrambling_status(ddc)) {
2186		DRM_DEBUG_KMS("SCDC not scrambled\n");
2187		tegra_sor_hdmi_scdc_enable(sor);
2188	}
2189
2190	schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2191}
2192
2193static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor)
2194{
2195	struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc;
2196	struct drm_display_mode *mode;
2197
2198	mode = &sor->output.encoder.crtc->state->adjusted_mode;
2199
2200	if (mode->clock >= 340000 && scdc->supported) {
2201		schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000));
2202		tegra_sor_hdmi_scdc_enable(sor);
2203		sor->scdc_enabled = true;
2204	}
2205}
2206
2207static void tegra_sor_hdmi_disable(struct drm_encoder *encoder)
2208{
2209	struct tegra_output *output = encoder_to_output(encoder);
2210	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2211	struct tegra_sor *sor = to_sor(output);
2212	u32 value;
2213	int err;
2214
2215	tegra_sor_audio_unprepare(sor);
2216	tegra_sor_hdmi_scdc_stop(sor);
2217
2218	err = tegra_sor_detach(sor);
2219	if (err < 0)
2220		dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2221
2222	tegra_sor_writel(sor, 0, SOR_STATE1);
2223	tegra_sor_update(sor);
2224
2225	/* disable display to SOR clock */
2226	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2227
2228	if (!sor->soc->has_nvdisplay)
2229		value &= ~SOR1_TIMING_CYA;
2230
2231	value &= ~SOR_ENABLE(sor->index);
2232
2233	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2234
2235	tegra_dc_commit(dc);
2236
2237	err = tegra_sor_power_down(sor);
2238	if (err < 0)
2239		dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2240
2241	err = tegra_io_pad_power_disable(sor->pad);
2242	if (err < 0)
2243		dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2244
2245	host1x_client_suspend(&sor->client);
2246}
2247
2248static void tegra_sor_hdmi_enable(struct drm_encoder *encoder)
2249{
2250	struct tegra_output *output = encoder_to_output(encoder);
2251	unsigned int h_ref_to_sync = 1, pulse_start, max_ac;
2252	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2253	struct tegra_sor_hdmi_settings *settings;
2254	struct tegra_sor *sor = to_sor(output);
2255	struct tegra_sor_state *state;
2256	struct drm_display_mode *mode;
2257	unsigned long rate, pclk;
2258	unsigned int div, i;
2259	u32 value;
2260	int err;
2261
2262	state = to_sor_state(output->connector.state);
2263	mode = &encoder->crtc->state->adjusted_mode;
2264	pclk = mode->clock * 1000;
2265
2266	err = host1x_client_resume(&sor->client);
2267	if (err < 0) {
2268		dev_err(sor->dev, "failed to resume: %d\n", err);
2269		return;
2270	}
2271
2272	/* switch to safe parent clock */
2273	err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2274	if (err < 0) {
2275		dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2276		return;
2277	}
2278
2279	div = clk_get_rate(sor->clk) / 1000000 * 4;
2280
2281	err = tegra_io_pad_power_enable(sor->pad);
2282	if (err < 0)
2283		dev_err(sor->dev, "failed to power on I/O pad: %d\n", err);
2284
2285	usleep_range(20, 100);
2286
2287	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2288	value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2289	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2290
2291	usleep_range(20, 100);
2292
2293	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2294	value &= ~SOR_PLL3_PLL_VDD_MODE_3V3;
2295	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2296
2297	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2298	value &= ~SOR_PLL0_VCOPD;
2299	value &= ~SOR_PLL0_PWR;
2300	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2301
2302	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2303	value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2304	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2305
2306	usleep_range(200, 400);
2307
2308	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2309	value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2310	value &= ~SOR_PLL2_PORT_POWERDOWN;
2311	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2312
2313	usleep_range(20, 100);
2314
2315	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2316	value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
2317		 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
2318	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2319
2320	while (true) {
2321		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2322		if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0)
2323			break;
2324
2325		usleep_range(250, 1000);
2326	}
2327
2328	value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
2329		SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5);
2330	tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
2331
2332	while (true) {
2333		value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
2334		if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
2335			break;
2336
2337		usleep_range(250, 1000);
2338	}
2339
2340	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2341	value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
2342	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2343
2344	if (mode->clock < 340000) {
2345		DRM_DEBUG_KMS("setting 2.7 GHz link speed\n");
2346		value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
2347	} else {
2348		DRM_DEBUG_KMS("setting 5.4 GHz link speed\n");
2349		value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40;
2350	}
2351
2352	value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
2353	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2354
2355	/* SOR pad PLL stabilization time */
2356	usleep_range(250, 1000);
2357
2358	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2359	value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
2360	value |= SOR_DP_LINKCTL_LANE_COUNT(4);
2361	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2362
2363	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2364	value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2365	value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2366	value &= ~SOR_DP_SPARE_SEQ_ENABLE;
2367	value &= ~SOR_DP_SPARE_MACRO_SOR_CLK;
2368	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2369
2370	value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) |
2371		SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8);
2372	tegra_sor_writel(sor, value, SOR_SEQ_CTL);
2373
2374	value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT |
2375		SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1);
2376	tegra_sor_writel(sor, value, SOR_SEQ_INST(0));
2377	tegra_sor_writel(sor, value, SOR_SEQ_INST(8));
2378
2379	if (!sor->soc->has_nvdisplay) {
2380		/* program the reference clock */
2381		value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div);
2382		tegra_sor_writel(sor, value, SOR_REFCLK);
2383	}
2384
2385	/* XXX not in TRM */
2386	for (value = 0, i = 0; i < 5; i++)
2387		value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) |
2388			 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2389
2390	tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2391	tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2392
2393	/*
2394	 * Switch the pad clock to the DP clock. Note that we cannot actually
2395	 * do this because Tegra186 and later don't support clk_set_parent()
2396	 * on the sorX_pad_clkout clocks. We already do the equivalent above
2397	 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2398	 */
2399#if 0
2400	err = clk_set_parent(sor->clk_pad, sor->clk_dp);
2401	if (err < 0) {
2402		dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2403			err);
2404		return;
2405	}
2406#endif
2407
2408	/* switch the SOR clock to the pad clock */
2409	err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2410	if (err < 0) {
2411		dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2412			err);
2413		return;
2414	}
2415
2416	/* switch the output clock to the parent pixel clock */
2417	err = clk_set_parent(sor->clk, sor->clk_parent);
2418	if (err < 0) {
2419		dev_err(sor->dev, "failed to select output parent clock: %d\n",
2420			err);
2421		return;
2422	}
2423
2424	/* adjust clock rate for HDMI 2.0 modes */
2425	rate = clk_get_rate(sor->clk_parent);
2426
2427	if (mode->clock >= 340000)
2428		rate /= 2;
2429
2430	DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk);
2431
2432	clk_set_rate(sor->clk, rate);
2433
2434	if (!sor->soc->has_nvdisplay) {
2435		value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe);
2436
2437		/* XXX is this the proper check? */
2438		if (mode->clock < 75000)
2439			value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED;
2440
2441		tegra_sor_writel(sor, value, SOR_INPUT_CONTROL);
2442	}
2443
2444	max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32;
2445
2446	value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) |
2447		SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY);
2448	tegra_sor_writel(sor, value, SOR_HDMI_CTRL);
2449
2450	if (!dc->soc->has_nvdisplay) {
2451		/* H_PULSE2 setup */
2452		pulse_start = h_ref_to_sync +
2453			      (mode->hsync_end - mode->hsync_start) +
2454			      (mode->htotal - mode->hsync_end) - 10;
2455
2456		value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE |
2457			PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL;
2458		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
2459
2460		value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start);
2461		tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
2462
2463		value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
2464		value |= H_PULSE2_ENABLE;
2465		tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0);
2466	}
2467
2468	/* infoframe setup */
2469	err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode);
2470	if (err < 0)
2471		dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err);
2472
2473	/* XXX HDMI audio support not implemented yet */
2474	tegra_sor_hdmi_disable_audio_infoframe(sor);
2475
2476	/* use single TMDS protocol */
2477	value = tegra_sor_readl(sor, SOR_STATE1);
2478	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2479	value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A;
2480	tegra_sor_writel(sor, value, SOR_STATE1);
2481
2482	/* power up pad calibration */
2483	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2484	value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
2485	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2486
2487	/* production settings */
2488	settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000);
2489	if (!settings) {
2490		dev_err(sor->dev, "no settings for pixel clock %d Hz\n",
2491			mode->clock * 1000);
2492		return;
2493	}
2494
2495	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2496	value &= ~SOR_PLL0_ICHPMP_MASK;
2497	value &= ~SOR_PLL0_FILTER_MASK;
2498	value &= ~SOR_PLL0_VCOCAP_MASK;
2499	value |= SOR_PLL0_ICHPMP(settings->ichpmp);
2500	value |= SOR_PLL0_FILTER(settings->filter);
2501	value |= SOR_PLL0_VCOCAP(settings->vcocap);
2502	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2503
2504	/* XXX not in TRM */
2505	value = tegra_sor_readl(sor, sor->soc->regs->pll1);
2506	value &= ~SOR_PLL1_LOADADJ_MASK;
2507	value &= ~SOR_PLL1_TMDS_TERMADJ_MASK;
2508	value |= SOR_PLL1_LOADADJ(settings->loadadj);
2509	value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj);
2510	value |= SOR_PLL1_TMDS_TERM;
2511	tegra_sor_writel(sor, value, sor->soc->regs->pll1);
2512
2513	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2514	value &= ~SOR_PLL3_BG_TEMP_COEF_MASK;
2515	value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK;
2516	value &= ~SOR_PLL3_AVDD10_LEVEL_MASK;
2517	value &= ~SOR_PLL3_AVDD14_LEVEL_MASK;
2518	value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef);
2519	value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level);
2520	value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level);
2521	value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level);
2522	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2523
2524	value = settings->drive_current[3] << 24 |
2525		settings->drive_current[2] << 16 |
2526		settings->drive_current[1] <<  8 |
2527		settings->drive_current[0] <<  0;
2528	tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0);
2529
2530	value = settings->preemphasis[3] << 24 |
2531		settings->preemphasis[2] << 16 |
2532		settings->preemphasis[1] <<  8 |
2533		settings->preemphasis[0] <<  0;
2534	tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0);
2535
2536	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2537	value &= ~SOR_DP_PADCTL_TX_PU_MASK;
2538	value |= SOR_DP_PADCTL_TX_PU_ENABLE;
2539	value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value);
2540	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2541
2542	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2);
2543	value &= ~SOR_DP_PADCTL_SPAREPLL_MASK;
2544	value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll);
2545	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2);
2546
2547	/* power down pad calibration */
2548	value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0);
2549	value |= SOR_DP_PADCTL_PAD_CAL_PD;
2550	tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0);
2551
2552	if (!dc->soc->has_nvdisplay) {
2553		/* miscellaneous display controller settings */
2554		value = VSYNC_H_POSITION(1);
2555		tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS);
2556	}
2557
2558	value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2559	value &= ~DITHER_CONTROL_MASK;
2560	value &= ~BASE_COLOR_SIZE_MASK;
2561
2562	switch (state->bpc) {
2563	case 6:
2564		value |= BASE_COLOR_SIZE_666;
2565		break;
2566
2567	case 8:
2568		value |= BASE_COLOR_SIZE_888;
2569		break;
2570
2571	case 10:
2572		value |= BASE_COLOR_SIZE_101010;
2573		break;
2574
2575	case 12:
2576		value |= BASE_COLOR_SIZE_121212;
2577		break;
2578
2579	default:
2580		WARN(1, "%u bits-per-color not supported\n", state->bpc);
2581		value |= BASE_COLOR_SIZE_888;
2582		break;
2583	}
2584
2585	tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL);
2586
2587	/* XXX set display head owner */
2588	value = tegra_sor_readl(sor, SOR_STATE1);
2589	value &= ~SOR_STATE_ASY_OWNER_MASK;
2590	value |= SOR_STATE_ASY_OWNER(1 + dc->pipe);
2591	tegra_sor_writel(sor, value, SOR_STATE1);
2592
2593	err = tegra_sor_power_up(sor, 250);
2594	if (err < 0)
2595		dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2596
2597	/* configure dynamic range of output */
2598	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2599	value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK;
2600	value &= ~SOR_HEAD_STATE_DYNRANGE_MASK;
2601	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2602
2603	/* configure colorspace */
2604	value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe);
2605	value &= ~SOR_HEAD_STATE_COLORSPACE_MASK;
2606	value |= SOR_HEAD_STATE_COLORSPACE_RGB;
2607	tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe);
2608
2609	tegra_sor_mode_set(sor, mode, state);
2610
2611	tegra_sor_update(sor);
2612
2613	/* program preamble timing in SOR (XXX) */
2614	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2615	value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE;
2616	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2617
2618	err = tegra_sor_attach(sor);
2619	if (err < 0)
2620		dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2621
2622	/* enable display to SOR clock and generate HDMI preamble */
2623	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2624
2625	if (!sor->soc->has_nvdisplay)
2626		value |= SOR1_TIMING_CYA;
2627
2628	value |= SOR_ENABLE(sor->index);
2629
2630	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2631
2632	if (dc->soc->has_nvdisplay) {
2633		value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2634		value &= ~PROTOCOL_MASK;
2635		value |= PROTOCOL_SINGLE_TMDS_A;
2636		tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index));
2637	}
2638
2639	tegra_dc_commit(dc);
2640
2641	err = tegra_sor_wakeup(sor);
2642	if (err < 0)
2643		dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2644
2645	tegra_sor_hdmi_scdc_start(sor);
2646	tegra_sor_audio_prepare(sor);
2647}
2648
2649static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = {
2650	.disable = tegra_sor_hdmi_disable,
2651	.enable = tegra_sor_hdmi_enable,
2652	.atomic_check = tegra_sor_encoder_atomic_check,
2653};
2654
2655static void tegra_sor_dp_disable(struct drm_encoder *encoder)
2656{
2657	struct tegra_output *output = encoder_to_output(encoder);
2658	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2659	struct tegra_sor *sor = to_sor(output);
2660	u32 value;
2661	int err;
2662
2663	if (output->panel)
2664		drm_panel_disable(output->panel);
2665
2666	/*
2667	 * Do not attempt to power down a DP link if we're not connected since
2668	 * the AUX transactions would just be timing out.
2669	 */
2670	if (output->connector.status != connector_status_disconnected) {
2671		err = drm_dp_link_power_down(sor->aux, &sor->link);
2672		if (err < 0)
2673			dev_err(sor->dev, "failed to power down link: %d\n",
2674				err);
2675	}
2676
2677	err = tegra_sor_detach(sor);
2678	if (err < 0)
2679		dev_err(sor->dev, "failed to detach SOR: %d\n", err);
2680
2681	tegra_sor_writel(sor, 0, SOR_STATE1);
2682	tegra_sor_update(sor);
2683
2684	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2685	value &= ~SOR_ENABLE(sor->index);
2686	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2687	tegra_dc_commit(dc);
2688
2689	value = tegra_sor_readl(sor, SOR_STATE1);
2690	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2691	value &= ~SOR_STATE_ASY_SUBOWNER_MASK;
2692	value &= ~SOR_STATE_ASY_OWNER_MASK;
2693	tegra_sor_writel(sor, value, SOR_STATE1);
2694	tegra_sor_update(sor);
2695
2696	/* switch to safe parent clock */
2697	err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2698	if (err < 0)
2699		dev_err(sor->dev, "failed to set safe clock: %d\n", err);
2700
2701	err = tegra_sor_power_down(sor);
2702	if (err < 0)
2703		dev_err(sor->dev, "failed to power down SOR: %d\n", err);
2704
2705	err = tegra_io_pad_power_disable(sor->pad);
2706	if (err < 0)
2707		dev_err(sor->dev, "failed to power off I/O pad: %d\n", err);
2708
2709	err = drm_dp_aux_disable(sor->aux);
2710	if (err < 0)
2711		dev_err(sor->dev, "failed disable DPAUX: %d\n", err);
2712
2713	if (output->panel)
2714		drm_panel_unprepare(output->panel);
2715
2716	host1x_client_suspend(&sor->client);
2717}
2718
2719static void tegra_sor_dp_enable(struct drm_encoder *encoder)
2720{
2721	struct tegra_output *output = encoder_to_output(encoder);
2722	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
2723	struct tegra_sor *sor = to_sor(output);
2724	struct tegra_sor_config config;
2725	struct tegra_sor_state *state;
2726	struct drm_display_mode *mode;
2727	struct drm_display_info *info;
2728	unsigned int i;
2729	u32 value;
2730	int err;
2731
2732	state = to_sor_state(output->connector.state);
2733	mode = &encoder->crtc->state->adjusted_mode;
2734	info = &output->connector.display_info;
2735
2736	err = host1x_client_resume(&sor->client);
2737	if (err < 0) {
2738		dev_err(sor->dev, "failed to resume: %d\n", err);
2739		return;
2740	}
2741
2742	/* switch to safe parent clock */
2743	err = tegra_sor_set_parent_clock(sor, sor->clk_safe);
2744	if (err < 0)
2745		dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
2746
2747	err = tegra_io_pad_power_enable(sor->pad);
2748	if (err < 0)
2749		dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err);
2750
2751	usleep_range(20, 100);
2752
2753	err = drm_dp_aux_enable(sor->aux);
2754	if (err < 0)
2755		dev_err(sor->dev, "failed to enable DPAUX: %d\n", err);
2756
2757	err = drm_dp_link_probe(sor->aux, &sor->link);
2758	if (err < 0)
2759		dev_err(sor->dev, "failed to probe DP link: %d\n", err);
2760
2761	tegra_sor_filter_rates(sor);
2762
2763	err = drm_dp_link_choose(&sor->link, mode, info);
2764	if (err < 0)
2765		dev_err(sor->dev, "failed to choose link: %d\n", err);
2766
2767	if (output->panel)
2768		drm_panel_prepare(output->panel);
2769
2770	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2771	value &= ~SOR_PLL2_BANDGAP_POWERDOWN;
2772	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2773
2774	usleep_range(20, 40);
2775
2776	value = tegra_sor_readl(sor, sor->soc->regs->pll3);
2777	value |= SOR_PLL3_PLL_VDD_MODE_3V3;
2778	tegra_sor_writel(sor, value, sor->soc->regs->pll3);
2779
2780	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2781	value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR);
2782	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2783
2784	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2785	value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE;
2786	value |= SOR_PLL2_SEQ_PLLCAPPD;
2787	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2788
2789	usleep_range(200, 400);
2790
2791	value = tegra_sor_readl(sor, sor->soc->regs->pll2);
2792	value &= ~SOR_PLL2_POWERDOWN_OVERRIDE;
2793	value &= ~SOR_PLL2_PORT_POWERDOWN;
2794	tegra_sor_writel(sor, value, sor->soc->regs->pll2);
2795
2796	value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
2797	value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
2798
2799	if (output->panel)
2800		value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
2801	else
2802		value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK;
2803
2804	tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
2805
2806	usleep_range(200, 400);
2807
2808	value = tegra_sor_readl(sor, SOR_DP_SPARE0);
2809	/* XXX not in TRM */
2810	if (output->panel)
2811		value |= SOR_DP_SPARE_PANEL_INTERNAL;
2812	else
2813		value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
2814
2815	value |= SOR_DP_SPARE_SEQ_ENABLE;
2816	tegra_sor_writel(sor, value, SOR_DP_SPARE0);
2817
2818	/* XXX not in TRM */
2819	tegra_sor_writel(sor, 0, SOR_LVDS);
2820
2821	value = tegra_sor_readl(sor, sor->soc->regs->pll0);
2822	value &= ~SOR_PLL0_ICHPMP_MASK;
2823	value &= ~SOR_PLL0_VCOCAP_MASK;
2824	value |= SOR_PLL0_ICHPMP(0x1);
2825	value |= SOR_PLL0_VCOCAP(0x3);
2826	value |= SOR_PLL0_RESISTOR_EXT;
2827	tegra_sor_writel(sor, value, sor->soc->regs->pll0);
2828
2829	/* XXX not in TRM */
2830	for (value = 0, i = 0; i < 5; i++)
2831		value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) |
2832			 SOR_XBAR_CTRL_LINK1_XSEL(i, i);
2833
2834	tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL);
2835	tegra_sor_writel(sor, value, SOR_XBAR_CTRL);
2836
2837	/*
2838	 * Switch the pad clock to the DP clock. Note that we cannot actually
2839	 * do this because Tegra186 and later don't support clk_set_parent()
2840	 * on the sorX_pad_clkout clocks. We already do the equivalent above
2841	 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register.
2842	 */
2843#if 0
2844	err = clk_set_parent(sor->clk_pad, sor->clk_parent);
2845	if (err < 0) {
2846		dev_err(sor->dev, "failed to select pad parent clock: %d\n",
2847			err);
2848		return;
2849	}
2850#endif
2851
2852	/* switch the SOR clock to the pad clock */
2853	err = tegra_sor_set_parent_clock(sor, sor->clk_pad);
2854	if (err < 0) {
2855		dev_err(sor->dev, "failed to select SOR parent clock: %d\n",
2856			err);
2857		return;
2858	}
2859
2860	/* switch the output clock to the parent pixel clock */
2861	err = clk_set_parent(sor->clk, sor->clk_parent);
2862	if (err < 0) {
2863		dev_err(sor->dev, "failed to select output parent clock: %d\n",
2864			err);
2865		return;
2866	}
2867
2868	/* use DP-A protocol */
2869	value = tegra_sor_readl(sor, SOR_STATE1);
2870	value &= ~SOR_STATE_ASY_PROTOCOL_MASK;
2871	value |= SOR_STATE_ASY_PROTOCOL_DP_A;
2872	tegra_sor_writel(sor, value, SOR_STATE1);
2873
2874	/* enable port */
2875	value = tegra_sor_readl(sor, SOR_DP_LINKCTL0);
2876	value |= SOR_DP_LINKCTL_ENABLE;
2877	tegra_sor_writel(sor, value, SOR_DP_LINKCTL0);
2878
2879	tegra_sor_dp_term_calibrate(sor);
2880
2881	err = drm_dp_link_train(&sor->link);
2882	if (err < 0)
2883		dev_err(sor->dev, "link training failed: %d\n", err);
2884	else
2885		dev_dbg(sor->dev, "link training succeeded\n");
2886
2887	err = drm_dp_link_power_up(sor->aux, &sor->link);
2888	if (err < 0)
2889		dev_err(sor->dev, "failed to power up DP link: %d\n", err);
2890
2891	/* compute configuration */
2892	memset(&config, 0, sizeof(config));
2893	config.bits_per_pixel = state->bpc * 3;
2894
2895	err = tegra_sor_compute_config(sor, mode, &config, &sor->link);
2896	if (err < 0)
2897		dev_err(sor->dev, "failed to compute configuration: %d\n", err);
2898
2899	tegra_sor_apply_config(sor, &config);
2900	tegra_sor_mode_set(sor, mode, state);
2901
2902	if (output->panel) {
2903		/* CSTM (LVDS, link A/B, upper) */
2904		value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
2905			SOR_CSTM_UPPER;
2906		tegra_sor_writel(sor, value, SOR_CSTM);
2907
2908		/* PWM setup */
2909		err = tegra_sor_setup_pwm(sor, 250);
2910		if (err < 0)
2911			dev_err(sor->dev, "failed to setup PWM: %d\n", err);
2912	}
2913
2914	tegra_sor_update(sor);
2915
2916	err = tegra_sor_power_up(sor, 250);
2917	if (err < 0)
2918		dev_err(sor->dev, "failed to power up SOR: %d\n", err);
2919
2920	/* attach and wake up */
2921	err = tegra_sor_attach(sor);
2922	if (err < 0)
2923		dev_err(sor->dev, "failed to attach SOR: %d\n", err);
2924
2925	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
2926	value |= SOR_ENABLE(sor->index);
2927	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
2928
2929	tegra_dc_commit(dc);
2930
2931	err = tegra_sor_wakeup(sor);
2932	if (err < 0)
2933		dev_err(sor->dev, "failed to wakeup SOR: %d\n", err);
2934
2935	if (output->panel)
2936		drm_panel_enable(output->panel);
2937}
2938
2939static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = {
2940	.disable = tegra_sor_dp_disable,
2941	.enable = tegra_sor_dp_enable,
2942	.atomic_check = tegra_sor_encoder_atomic_check,
2943};
2944
2945static int tegra_sor_hdmi_probe(struct tegra_sor *sor)
2946{
2947	int err;
2948
2949	sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
2950	if (IS_ERR(sor->avdd_io_supply)) {
2951		dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n",
2952			PTR_ERR(sor->avdd_io_supply));
2953		return PTR_ERR(sor->avdd_io_supply);
2954	}
2955
2956	err = regulator_enable(sor->avdd_io_supply);
2957	if (err < 0) {
2958		dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n",
2959			err);
2960		return err;
2961	}
2962
2963	sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
2964	if (IS_ERR(sor->vdd_pll_supply)) {
2965		dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n",
2966			PTR_ERR(sor->vdd_pll_supply));
2967		return PTR_ERR(sor->vdd_pll_supply);
2968	}
2969
2970	err = regulator_enable(sor->vdd_pll_supply);
2971	if (err < 0) {
2972		dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n",
2973			err);
2974		return err;
2975	}
2976
2977	sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi");
2978	if (IS_ERR(sor->hdmi_supply)) {
2979		dev_err(sor->dev, "cannot get HDMI supply: %ld\n",
2980			PTR_ERR(sor->hdmi_supply));
2981		return PTR_ERR(sor->hdmi_supply);
2982	}
2983
2984	err = regulator_enable(sor->hdmi_supply);
2985	if (err < 0) {
2986		dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err);
2987		return err;
2988	}
2989
2990	INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work);
2991
2992	return 0;
2993}
2994
2995static int tegra_sor_hdmi_remove(struct tegra_sor *sor)
2996{
2997	regulator_disable(sor->hdmi_supply);
2998	regulator_disable(sor->vdd_pll_supply);
2999	regulator_disable(sor->avdd_io_supply);
3000
3001	return 0;
3002}
3003
3004static const struct tegra_sor_ops tegra_sor_hdmi_ops = {
3005	.name = "HDMI",
3006	.probe = tegra_sor_hdmi_probe,
3007	.remove = tegra_sor_hdmi_remove,
3008	.audio_enable = tegra_sor_hdmi_audio_enable,
3009	.audio_disable = tegra_sor_hdmi_audio_disable,
3010};
3011
3012static int tegra_sor_dp_probe(struct tegra_sor *sor)
3013{
3014	int err;
3015
3016	sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp");
3017	if (IS_ERR(sor->avdd_io_supply))
3018		return PTR_ERR(sor->avdd_io_supply);
3019
3020	err = regulator_enable(sor->avdd_io_supply);
3021	if (err < 0)
3022		return err;
3023
3024	sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll");
3025	if (IS_ERR(sor->vdd_pll_supply))
3026		return PTR_ERR(sor->vdd_pll_supply);
3027
3028	err = regulator_enable(sor->vdd_pll_supply);
3029	if (err < 0)
3030		return err;
3031
3032	return 0;
3033}
3034
3035static int tegra_sor_dp_remove(struct tegra_sor *sor)
3036{
3037	regulator_disable(sor->vdd_pll_supply);
3038	regulator_disable(sor->avdd_io_supply);
3039
3040	return 0;
3041}
3042
3043static const struct tegra_sor_ops tegra_sor_dp_ops = {
3044	.name = "DP",
3045	.probe = tegra_sor_dp_probe,
3046	.remove = tegra_sor_dp_remove,
3047};
3048
3049static int tegra_sor_init(struct host1x_client *client)
3050{
3051	struct drm_device *drm = dev_get_drvdata(client->host);
3052	const struct drm_encoder_helper_funcs *helpers = NULL;
3053	struct tegra_sor *sor = host1x_client_to_sor(client);
3054	int connector = DRM_MODE_CONNECTOR_Unknown;
3055	int encoder = DRM_MODE_ENCODER_NONE;
 
3056	int err;
3057
3058	if (!sor->aux) {
3059		if (sor->ops == &tegra_sor_hdmi_ops) {
3060			connector = DRM_MODE_CONNECTOR_HDMIA;
3061			encoder = DRM_MODE_ENCODER_TMDS;
3062			helpers = &tegra_sor_hdmi_helpers;
3063		} else if (sor->soc->supports_lvds) {
3064			connector = DRM_MODE_CONNECTOR_LVDS;
3065			encoder = DRM_MODE_ENCODER_LVDS;
3066		}
3067	} else {
3068		if (sor->output.panel) {
3069			connector = DRM_MODE_CONNECTOR_eDP;
3070			encoder = DRM_MODE_ENCODER_TMDS;
3071			helpers = &tegra_sor_dp_helpers;
3072		} else {
3073			connector = DRM_MODE_CONNECTOR_DisplayPort;
3074			encoder = DRM_MODE_ENCODER_TMDS;
3075			helpers = &tegra_sor_dp_helpers;
3076		}
3077
3078		sor->link.ops = &tegra_sor_dp_link_ops;
3079		sor->link.aux = sor->aux;
3080	}
3081
3082	sor->output.dev = sor->dev;
3083
3084	drm_connector_init_with_ddc(drm, &sor->output.connector,
3085				    &tegra_sor_connector_funcs,
3086				    connector,
3087				    sor->output.ddc);
3088	drm_connector_helper_add(&sor->output.connector,
3089				 &tegra_sor_connector_helper_funcs);
3090	sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
3091
3092	drm_simple_encoder_init(drm, &sor->output.encoder, encoder);
 
3093	drm_encoder_helper_add(&sor->output.encoder, helpers);
3094
3095	drm_connector_attach_encoder(&sor->output.connector,
3096					  &sor->output.encoder);
3097	drm_connector_register(&sor->output.connector);
3098
3099	err = tegra_output_init(drm, &sor->output);
3100	if (err < 0) {
3101		dev_err(client->dev, "failed to initialize output: %d\n", err);
3102		return err;
3103	}
3104
3105	tegra_output_find_possible_crtcs(&sor->output, drm);
3106
3107	if (sor->aux) {
3108		err = drm_dp_aux_attach(sor->aux, &sor->output);
3109		if (err < 0) {
3110			dev_err(sor->dev, "failed to attach DP: %d\n", err);
3111			return err;
3112		}
3113	}
3114
3115	/*
3116	 * XXX: Remove this reset once proper hand-over from firmware to
3117	 * kernel is possible.
3118	 */
3119	if (sor->rst) {
3120		err = reset_control_acquire(sor->rst);
3121		if (err < 0) {
3122			dev_err(sor->dev, "failed to acquire SOR reset: %d\n",
3123				err);
3124			return err;
3125		}
3126
3127		err = reset_control_assert(sor->rst);
3128		if (err < 0) {
3129			dev_err(sor->dev, "failed to assert SOR reset: %d\n",
3130				err);
3131			return err;
3132		}
3133	}
3134
3135	err = clk_prepare_enable(sor->clk);
3136	if (err < 0) {
3137		dev_err(sor->dev, "failed to enable clock: %d\n", err);
3138		return err;
3139	}
3140
3141	usleep_range(1000, 3000);
3142
3143	if (sor->rst) {
3144		err = reset_control_deassert(sor->rst);
3145		if (err < 0) {
3146			dev_err(sor->dev, "failed to deassert SOR reset: %d\n",
3147				err);
3148			return err;
3149		}
3150
3151		reset_control_release(sor->rst);
3152	}
3153
3154	err = clk_prepare_enable(sor->clk_safe);
3155	if (err < 0)
3156		return err;
3157
3158	err = clk_prepare_enable(sor->clk_dp);
3159	if (err < 0)
3160		return err;
3161
 
 
 
 
 
 
 
 
 
3162	return 0;
3163}
3164
3165static int tegra_sor_exit(struct host1x_client *client)
3166{
3167	struct tegra_sor *sor = host1x_client_to_sor(client);
3168	int err;
3169
 
 
 
3170	tegra_output_exit(&sor->output);
3171
3172	if (sor->aux) {
3173		err = drm_dp_aux_detach(sor->aux);
3174		if (err < 0) {
3175			dev_err(sor->dev, "failed to detach DP: %d\n", err);
3176			return err;
3177		}
3178	}
3179
3180	clk_disable_unprepare(sor->clk_safe);
3181	clk_disable_unprepare(sor->clk_dp);
3182	clk_disable_unprepare(sor->clk);
3183
3184	return 0;
3185}
3186
3187static int tegra_sor_runtime_suspend(struct host1x_client *client)
 
 
 
 
 
 
 
 
 
3188{
3189	struct tegra_sor *sor = host1x_client_to_sor(client);
3190	struct device *dev = client->dev;
3191	int err;
3192
3193	if (sor->rst) {
3194		err = reset_control_assert(sor->rst);
3195		if (err < 0) {
3196			dev_err(dev, "failed to assert reset: %d\n", err);
3197			return err;
3198		}
3199
3200		reset_control_release(sor->rst);
3201	}
3202
3203	usleep_range(1000, 2000);
3204
3205	clk_disable_unprepare(sor->clk);
3206	pm_runtime_put_sync(dev);
3207
3208	return 0;
3209}
3210
3211static int tegra_sor_runtime_resume(struct host1x_client *client)
3212{
3213	struct tegra_sor *sor = host1x_client_to_sor(client);
3214	struct device *dev = client->dev;
3215	int err;
 
3216
3217	err = pm_runtime_get_sync(dev);
3218	if (err < 0) {
3219		dev_err(dev, "failed to get runtime PM: %d\n", err);
 
3220		return err;
3221	}
3222
3223	err = clk_prepare_enable(sor->clk);
 
 
 
 
 
 
 
3224	if (err < 0) {
3225		dev_err(dev, "failed to enable clock: %d\n", err);
3226		goto put_rpm;
3227	}
3228
3229	usleep_range(1000, 2000);
3230
3231	if (sor->rst) {
3232		err = reset_control_acquire(sor->rst);
3233		if (err < 0) {
3234			dev_err(dev, "failed to acquire reset: %d\n", err);
3235			goto disable_clk;
3236		}
3237
3238		err = reset_control_deassert(sor->rst);
3239		if (err < 0) {
3240			dev_err(dev, "failed to deassert reset: %d\n", err);
3241			goto release_reset;
3242		}
3243	}
3244
3245	return 0;
3246
3247release_reset:
3248	reset_control_release(sor->rst);
3249disable_clk:
3250	clk_disable_unprepare(sor->clk);
3251put_rpm:
3252	pm_runtime_put_sync(dev);
3253	return err;
3254}
3255
3256static const struct host1x_client_ops sor_client_ops = {
3257	.init = tegra_sor_init,
3258	.exit = tegra_sor_exit,
3259	.suspend = tegra_sor_runtime_suspend,
3260	.resume = tegra_sor_runtime_resume,
3261};
3262
3263static const u8 tegra124_sor_xbar_cfg[5] = {
3264	0, 1, 2, 3, 4
3265};
3266
3267static const struct tegra_sor_regs tegra124_sor_regs = {
3268	.head_state0 = 0x05,
3269	.head_state1 = 0x07,
3270	.head_state2 = 0x09,
3271	.head_state3 = 0x0b,
3272	.head_state4 = 0x0d,
3273	.head_state5 = 0x0f,
3274	.pll0 = 0x17,
3275	.pll1 = 0x18,
3276	.pll2 = 0x19,
3277	.pll3 = 0x1a,
3278	.dp_padctl0 = 0x5c,
3279	.dp_padctl2 = 0x73,
3280};
3281
3282/* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */
3283static const u8 tegra124_sor_lane_map[4] = {
3284	2, 1, 0, 3,
3285};
3286
3287static const u8 tegra124_sor_voltage_swing[4][4][4] = {
3288	{
3289		{ 0x13, 0x19, 0x1e, 0x28 },
3290		{ 0x1e, 0x25, 0x2d, },
3291		{ 0x28, 0x32, },
3292		{ 0x3c, },
3293	}, {
3294		{ 0x12, 0x17, 0x1b, 0x25 },
3295		{ 0x1c, 0x23, 0x2a, },
3296		{ 0x25, 0x2f, },
3297		{ 0x39, }
3298	}, {
3299		{ 0x12, 0x16, 0x1a, 0x22 },
3300		{ 0x1b, 0x20, 0x27, },
3301		{ 0x24, 0x2d, },
3302		{ 0x36, },
3303	}, {
3304		{ 0x11, 0x14, 0x17, 0x1f },
3305		{ 0x19, 0x1e, 0x24, },
3306		{ 0x22, 0x2a, },
3307		{ 0x32, },
3308	},
3309};
3310
3311static const u8 tegra124_sor_pre_emphasis[4][4][4] = {
3312	{
3313		{ 0x00, 0x09, 0x13, 0x25 },
3314		{ 0x00, 0x0f, 0x1e, },
3315		{ 0x00, 0x14, },
3316		{ 0x00, },
3317	}, {
3318		{ 0x00, 0x0a, 0x14, 0x28 },
3319		{ 0x00, 0x0f, 0x1e, },
3320		{ 0x00, 0x14, },
3321		{ 0x00 },
3322	}, {
3323		{ 0x00, 0x0a, 0x14, 0x28 },
3324		{ 0x00, 0x0f, 0x1e, },
3325		{ 0x00, 0x14, },
3326		{ 0x00, },
3327	}, {
3328		{ 0x00, 0x0a, 0x14, 0x28 },
3329		{ 0x00, 0x0f, 0x1e, },
3330		{ 0x00, 0x14, },
3331		{ 0x00, },
3332	},
3333};
3334
3335static const u8 tegra124_sor_post_cursor[4][4][4] = {
3336	{
3337		{ 0x00, 0x00, 0x00, 0x00 },
3338		{ 0x00, 0x00, 0x00, },
3339		{ 0x00, 0x00, },
3340		{ 0x00, },
3341	}, {
3342		{ 0x02, 0x02, 0x04, 0x05 },
3343		{ 0x02, 0x04, 0x05, },
3344		{ 0x04, 0x05, },
3345		{ 0x05, },
3346	}, {
3347		{ 0x04, 0x05, 0x08, 0x0b },
3348		{ 0x05, 0x09, 0x0b, },
3349		{ 0x08, 0x0a, },
3350		{ 0x0b, },
3351	}, {
3352		{ 0x05, 0x09, 0x0b, 0x12 },
3353		{ 0x09, 0x0d, 0x12, },
3354		{ 0x0b, 0x0f, },
3355		{ 0x12, },
3356	},
3357};
3358
3359static const u8 tegra124_sor_tx_pu[4][4][4] = {
3360	{
3361		{ 0x20, 0x30, 0x40, 0x60 },
3362		{ 0x30, 0x40, 0x60, },
3363		{ 0x40, 0x60, },
3364		{ 0x60, },
3365	}, {
3366		{ 0x20, 0x20, 0x30, 0x50 },
3367		{ 0x30, 0x40, 0x50, },
3368		{ 0x40, 0x50, },
3369		{ 0x60, },
3370	}, {
3371		{ 0x20, 0x20, 0x30, 0x40, },
3372		{ 0x30, 0x30, 0x40, },
3373		{ 0x40, 0x50, },
3374		{ 0x60, },
3375	}, {
3376		{ 0x20, 0x20, 0x20, 0x40, },
3377		{ 0x30, 0x30, 0x40, },
3378		{ 0x40, 0x40, },
3379		{ 0x60, },
3380	},
3381};
3382
3383static const struct tegra_sor_soc tegra124_sor = {
 
3384	.supports_lvds = true,
3385	.supports_hdmi = false,
3386	.supports_dp = true,
3387	.supports_audio = false,
3388	.supports_hdcp = false,
3389	.regs = &tegra124_sor_regs,
3390	.has_nvdisplay = false,
3391	.xbar_cfg = tegra124_sor_xbar_cfg,
3392	.lane_map = tegra124_sor_lane_map,
3393	.voltage_swing = tegra124_sor_voltage_swing,
3394	.pre_emphasis = tegra124_sor_pre_emphasis,
3395	.post_cursor = tegra124_sor_post_cursor,
3396	.tx_pu = tegra124_sor_tx_pu,
3397};
3398
3399static const u8 tegra132_sor_pre_emphasis[4][4][4] = {
3400	{
3401		{ 0x00, 0x08, 0x12, 0x24 },
3402		{ 0x01, 0x0e, 0x1d, },
3403		{ 0x01, 0x13, },
3404		{ 0x00, },
3405	}, {
3406		{ 0x00, 0x08, 0x12, 0x24 },
3407		{ 0x00, 0x0e, 0x1d, },
3408		{ 0x00, 0x13, },
3409		{ 0x00 },
3410	}, {
3411		{ 0x00, 0x08, 0x12, 0x24 },
3412		{ 0x00, 0x0e, 0x1d, },
3413		{ 0x00, 0x13, },
3414		{ 0x00, },
3415	}, {
3416		{ 0x00, 0x08, 0x12, 0x24 },
3417		{ 0x00, 0x0e, 0x1d, },
3418		{ 0x00, 0x13, },
3419		{ 0x00, },
3420	},
3421};
3422
3423static const struct tegra_sor_soc tegra132_sor = {
3424	.supports_lvds = true,
3425	.supports_hdmi = false,
3426	.supports_dp = true,
3427	.supports_audio = false,
3428	.supports_hdcp = false,
3429	.regs = &tegra124_sor_regs,
3430	.has_nvdisplay = false,
3431	.xbar_cfg = tegra124_sor_xbar_cfg,
3432	.lane_map = tegra124_sor_lane_map,
3433	.voltage_swing = tegra124_sor_voltage_swing,
3434	.pre_emphasis = tegra132_sor_pre_emphasis,
3435	.post_cursor = tegra124_sor_post_cursor,
3436	.tx_pu = tegra124_sor_tx_pu,
3437};
3438
3439static const struct tegra_sor_regs tegra210_sor_regs = {
3440	.head_state0 = 0x05,
3441	.head_state1 = 0x07,
3442	.head_state2 = 0x09,
3443	.head_state3 = 0x0b,
3444	.head_state4 = 0x0d,
3445	.head_state5 = 0x0f,
3446	.pll0 = 0x17,
3447	.pll1 = 0x18,
3448	.pll2 = 0x19,
3449	.pll3 = 0x1a,
3450	.dp_padctl0 = 0x5c,
3451	.dp_padctl2 = 0x73,
3452};
3453
3454static const u8 tegra210_sor_xbar_cfg[5] = {
3455	2, 1, 0, 3, 4
3456};
3457
3458static const u8 tegra210_sor_lane_map[4] = {
3459	0, 1, 2, 3,
3460};
3461
3462static const struct tegra_sor_soc tegra210_sor = {
 
3463	.supports_lvds = false,
3464	.supports_hdmi = false,
3465	.supports_dp = true,
3466	.supports_audio = false,
3467	.supports_hdcp = false,
3468
3469	.regs = &tegra210_sor_regs,
3470	.has_nvdisplay = false,
 
 
3471
3472	.xbar_cfg = tegra210_sor_xbar_cfg,
3473	.lane_map = tegra210_sor_lane_map,
3474	.voltage_swing = tegra124_sor_voltage_swing,
3475	.pre_emphasis = tegra124_sor_pre_emphasis,
3476	.post_cursor = tegra124_sor_post_cursor,
3477	.tx_pu = tegra124_sor_tx_pu,
3478};
3479
3480static const struct tegra_sor_soc tegra210_sor1 = {
 
3481	.supports_lvds = false,
3482	.supports_hdmi = true,
3483	.supports_dp = true,
3484	.supports_audio = true,
3485	.supports_hdcp = true,
3486
3487	.regs = &tegra210_sor_regs,
3488	.has_nvdisplay = false,
3489
3490	.num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults),
3491	.settings = tegra210_sor_hdmi_defaults,
 
3492	.xbar_cfg = tegra210_sor_xbar_cfg,
3493	.lane_map = tegra210_sor_lane_map,
3494	.voltage_swing = tegra124_sor_voltage_swing,
3495	.pre_emphasis = tegra124_sor_pre_emphasis,
3496	.post_cursor = tegra124_sor_post_cursor,
3497	.tx_pu = tegra124_sor_tx_pu,
3498};
3499
3500static const struct tegra_sor_regs tegra186_sor_regs = {
3501	.head_state0 = 0x151,
3502	.head_state1 = 0x154,
3503	.head_state2 = 0x157,
3504	.head_state3 = 0x15a,
3505	.head_state4 = 0x15d,
3506	.head_state5 = 0x160,
3507	.pll0 = 0x163,
3508	.pll1 = 0x164,
3509	.pll2 = 0x165,
3510	.pll3 = 0x166,
3511	.dp_padctl0 = 0x168,
3512	.dp_padctl2 = 0x16a,
3513};
3514
3515static const u8 tegra186_sor_voltage_swing[4][4][4] = {
3516	{
3517		{ 0x13, 0x19, 0x1e, 0x28 },
3518		{ 0x1e, 0x25, 0x2d, },
3519		{ 0x28, 0x32, },
3520		{ 0x39, },
3521	}, {
3522		{ 0x12, 0x16, 0x1b, 0x25 },
3523		{ 0x1c, 0x23, 0x2a, },
3524		{ 0x25, 0x2f, },
3525		{ 0x37, }
3526	}, {
3527		{ 0x12, 0x16, 0x1a, 0x22 },
3528		{ 0x1b, 0x20, 0x27, },
3529		{ 0x24, 0x2d, },
3530		{ 0x35, },
3531	}, {
3532		{ 0x11, 0x14, 0x17, 0x1f },
3533		{ 0x19, 0x1e, 0x24, },
3534		{ 0x22, 0x2a, },
3535		{ 0x32, },
3536	},
3537};
3538
3539static const u8 tegra186_sor_pre_emphasis[4][4][4] = {
3540	{
3541		{ 0x00, 0x08, 0x12, 0x24 },
3542		{ 0x01, 0x0e, 0x1d, },
3543		{ 0x01, 0x13, },
3544		{ 0x00, },
3545	}, {
3546		{ 0x00, 0x08, 0x12, 0x24 },
3547		{ 0x00, 0x0e, 0x1d, },
3548		{ 0x00, 0x13, },
3549		{ 0x00 },
3550	}, {
3551		{ 0x00, 0x08, 0x14, 0x24 },
3552		{ 0x00, 0x0e, 0x1d, },
3553		{ 0x00, 0x13, },
3554		{ 0x00, },
3555	}, {
3556		{ 0x00, 0x08, 0x12, 0x24 },
3557		{ 0x00, 0x0e, 0x1d, },
3558		{ 0x00, 0x13, },
3559		{ 0x00, },
3560	},
3561};
3562
3563static const struct tegra_sor_soc tegra186_sor = {
 
3564	.supports_lvds = false,
3565	.supports_hdmi = true,
3566	.supports_dp = true,
3567	.supports_audio = true,
3568	.supports_hdcp = true,
3569
3570	.regs = &tegra186_sor_regs,
3571	.has_nvdisplay = true,
3572
3573	.num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults),
3574	.settings = tegra186_sor_hdmi_defaults,
 
3575	.xbar_cfg = tegra124_sor_xbar_cfg,
3576	.lane_map = tegra124_sor_lane_map,
3577	.voltage_swing = tegra186_sor_voltage_swing,
3578	.pre_emphasis = tegra186_sor_pre_emphasis,
3579	.post_cursor = tegra124_sor_post_cursor,
3580	.tx_pu = tegra124_sor_tx_pu,
3581};
3582
3583static const struct tegra_sor_regs tegra194_sor_regs = {
3584	.head_state0 = 0x151,
3585	.head_state1 = 0x155,
3586	.head_state2 = 0x159,
3587	.head_state3 = 0x15d,
3588	.head_state4 = 0x161,
3589	.head_state5 = 0x165,
3590	.pll0 = 0x169,
3591	.pll1 = 0x16a,
3592	.pll2 = 0x16b,
3593	.pll3 = 0x16c,
3594	.dp_padctl0 = 0x16e,
3595	.dp_padctl2 = 0x16f,
3596};
3597
3598static const struct tegra_sor_soc tegra194_sor = {
 
3599	.supports_lvds = false,
3600	.supports_hdmi = true,
3601	.supports_dp = true,
3602	.supports_audio = true,
3603	.supports_hdcp = true,
3604
3605	.regs = &tegra194_sor_regs,
3606	.has_nvdisplay = true,
3607
3608	.num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
3609	.settings = tegra194_sor_hdmi_defaults,
3610
3611	.xbar_cfg = tegra210_sor_xbar_cfg,
3612	.lane_map = tegra124_sor_lane_map,
3613	.voltage_swing = tegra186_sor_voltage_swing,
3614	.pre_emphasis = tegra186_sor_pre_emphasis,
3615	.post_cursor = tegra124_sor_post_cursor,
3616	.tx_pu = tegra124_sor_tx_pu,
3617};
3618
3619static const struct of_device_id tegra_sor_of_match[] = {
3620	{ .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
 
3621	{ .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3622	{ .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3623	{ .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3624	{ .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3625	{ .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3626	{ },
3627};
3628MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
3629
3630static int tegra_sor_parse_dt(struct tegra_sor *sor)
3631{
3632	struct device_node *np = sor->dev->of_node;
3633	u32 xbar_cfg[5];
3634	unsigned int i;
3635	u32 value;
3636	int err;
3637
3638	if (sor->soc->has_nvdisplay) {
3639		err = of_property_read_u32(np, "nvidia,interface", &value);
3640		if (err < 0)
3641			return err;
3642
3643		sor->index = value;
3644
3645		/*
3646		 * override the default that we already set for Tegra210 and
3647		 * earlier
3648		 */
3649		sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index;
3650	} else {
3651		if (!sor->soc->supports_audio)
3652			sor->index = 0;
3653		else
3654			sor->index = 1;
3655	}
3656
3657	err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5);
3658	if (err < 0) {
3659		/* fall back to default per-SoC XBAR configuration */
3660		for (i = 0; i < 5; i++)
3661			sor->xbar_cfg[i] = sor->soc->xbar_cfg[i];
3662	} else {
3663		/* copy cells to SOR XBAR configuration */
3664		for (i = 0; i < 5; i++)
3665			sor->xbar_cfg[i] = xbar_cfg[i];
3666	}
3667
3668	return 0;
3669}
3670
3671static irqreturn_t tegra_sor_irq(int irq, void *data)
3672{
3673	struct tegra_sor *sor = data;
3674	u32 value;
3675
3676	value = tegra_sor_readl(sor, SOR_INT_STATUS);
3677	tegra_sor_writel(sor, value, SOR_INT_STATUS);
3678
3679	if (value & SOR_INT_CODEC_SCRATCH0) {
3680		value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0);
3681
3682		if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
3683			unsigned int format;
3684
3685			format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
3686
3687			tegra_hda_parse_format(format, &sor->format);
3688
3689			if (sor->ops->audio_enable)
3690				sor->ops->audio_enable(sor);
3691		} else {
3692			if (sor->ops->audio_disable)
3693				sor->ops->audio_disable(sor);
3694		}
3695	}
3696
3697	return IRQ_HANDLED;
3698}
3699
3700static int tegra_sor_probe(struct platform_device *pdev)
3701{
3702	struct device_node *np;
3703	struct tegra_sor *sor;
3704	struct resource *regs;
3705	int err;
3706
3707	sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
3708	if (!sor)
3709		return -ENOMEM;
3710
3711	sor->soc = of_device_get_match_data(&pdev->dev);
3712	sor->output.dev = sor->dev = &pdev->dev;
3713
3714	sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings,
3715				     sor->soc->num_settings *
3716					sizeof(*sor->settings),
3717				     GFP_KERNEL);
3718	if (!sor->settings)
3719		return -ENOMEM;
3720
3721	sor->num_settings = sor->soc->num_settings;
3722
3723	np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
3724	if (np) {
3725		sor->aux = drm_dp_aux_find_by_of_node(np);
3726		of_node_put(np);
3727
3728		if (!sor->aux)
3729			return -EPROBE_DEFER;
3730
3731		sor->output.ddc = &sor->aux->ddc;
3732	}
3733
3734	if (!sor->aux) {
3735		if (sor->soc->supports_hdmi) {
3736			sor->ops = &tegra_sor_hdmi_ops;
3737			sor->pad = TEGRA_IO_PAD_HDMI;
3738		} else if (sor->soc->supports_lvds) {
3739			dev_err(&pdev->dev, "LVDS not supported yet\n");
3740			return -ENODEV;
3741		} else {
3742			dev_err(&pdev->dev, "unknown (non-DP) support\n");
3743			return -ENODEV;
3744		}
3745	} else {
3746		np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0);
3747		/*
3748		 * No need to keep this around since we only use it as a check
3749		 * to see if a panel is connected (eDP) or not (DP).
3750		 */
3751		of_node_put(np);
3752
3753		sor->ops = &tegra_sor_dp_ops;
3754		sor->pad = TEGRA_IO_PAD_LVDS;
 
3755	}
3756
3757	err = tegra_sor_parse_dt(sor);
3758	if (err < 0)
3759		return err;
3760
3761	err = tegra_output_probe(&sor->output);
3762	if (err < 0) {
3763		dev_err(&pdev->dev, "failed to probe output: %d\n", err);
3764		return err;
3765	}
3766
3767	if (sor->ops && sor->ops->probe) {
3768		err = sor->ops->probe(sor);
3769		if (err < 0) {
3770			dev_err(&pdev->dev, "failed to probe %s: %d\n",
3771				sor->ops->name, err);
3772			goto output;
3773		}
3774	}
3775
3776	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3777	sor->regs = devm_ioremap_resource(&pdev->dev, regs);
3778	if (IS_ERR(sor->regs)) {
3779		err = PTR_ERR(sor->regs);
3780		goto remove;
3781	}
3782
3783	err = platform_get_irq(pdev, 0);
3784	if (err < 0) {
3785		dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
3786		goto remove;
3787	}
3788
3789	sor->irq = err;
3790
3791	err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0,
3792			       dev_name(sor->dev), sor);
3793	if (err < 0) {
3794		dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
3795		goto remove;
3796	}
3797
3798	sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor");
3799	if (IS_ERR(sor->rst)) {
3800		err = PTR_ERR(sor->rst);
3801
3802		if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) {
3803			dev_err(&pdev->dev, "failed to get reset control: %d\n",
3804				err);
3805			goto remove;
3806		}
3807
3808		/*
3809		 * At this point, the reset control is most likely being used
3810		 * by the generic power domain implementation. With any luck
3811		 * the power domain will have taken care of resetting the SOR
3812		 * and we don't have to do anything.
3813		 */
3814		sor->rst = NULL;
3815	}
3816
3817	sor->clk = devm_clk_get(&pdev->dev, NULL);
3818	if (IS_ERR(sor->clk)) {
3819		err = PTR_ERR(sor->clk);
3820		dev_err(&pdev->dev, "failed to get module clock: %d\n", err);
3821		goto remove;
3822	}
3823
3824	if (sor->soc->supports_hdmi || sor->soc->supports_dp) {
3825		struct device_node *np = pdev->dev.of_node;
3826		const char *name;
3827
3828		/*
3829		 * For backwards compatibility with Tegra210 device trees,
3830		 * fall back to the old clock name "source" if the new "out"
3831		 * clock is not available.
3832		 */
3833		if (of_property_match_string(np, "clock-names", "out") < 0)
3834			name = "source";
3835		else
3836			name = "out";
3837
3838		sor->clk_out = devm_clk_get(&pdev->dev, name);
3839		if (IS_ERR(sor->clk_out)) {
3840			err = PTR_ERR(sor->clk_out);
3841			dev_err(sor->dev, "failed to get %s clock: %d\n",
3842				name, err);
3843			goto remove;
3844		}
3845	} else {
3846		/* fall back to the module clock on SOR0 (eDP/LVDS only) */
3847		sor->clk_out = sor->clk;
3848	}
3849
3850	sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
3851	if (IS_ERR(sor->clk_parent)) {
3852		err = PTR_ERR(sor->clk_parent);
3853		dev_err(&pdev->dev, "failed to get parent clock: %d\n", err);
3854		goto remove;
3855	}
3856
3857	sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
3858	if (IS_ERR(sor->clk_safe)) {
3859		err = PTR_ERR(sor->clk_safe);
3860		dev_err(&pdev->dev, "failed to get safe clock: %d\n", err);
3861		goto remove;
3862	}
3863
3864	sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
3865	if (IS_ERR(sor->clk_dp)) {
3866		err = PTR_ERR(sor->clk_dp);
3867		dev_err(&pdev->dev, "failed to get DP clock: %d\n", err);
3868		goto remove;
3869	}
3870
3871	/*
3872	 * Starting with Tegra186, the BPMP provides an implementation for
3873	 * the pad output clock, so we have to look it up from device tree.
3874	 */
3875	sor->clk_pad = devm_clk_get(&pdev->dev, "pad");
3876	if (IS_ERR(sor->clk_pad)) {
3877		if (sor->clk_pad != ERR_PTR(-ENOENT)) {
3878			err = PTR_ERR(sor->clk_pad);
3879			goto remove;
3880		}
3881
3882		/*
3883		 * If the pad output clock is not available, then we assume
3884		 * we're on Tegra210 or earlier and have to provide our own
3885		 * implementation.
3886		 */
3887		sor->clk_pad = NULL;
3888	}
3889
3890	/*
3891	 * The bootloader may have set up the SOR such that it's module clock
3892	 * is sourced by one of the display PLLs. However, that doesn't work
3893	 * without properly having set up other bits of the SOR.
3894	 */
3895	err = clk_set_parent(sor->clk_out, sor->clk_safe);
3896	if (err < 0) {
3897		dev_err(&pdev->dev, "failed to use safe clock: %d\n", err);
3898		goto remove;
3899	}
3900
3901	platform_set_drvdata(pdev, sor);
3902	pm_runtime_enable(&pdev->dev);
3903
3904	INIT_LIST_HEAD(&sor->client.list);
3905	sor->client.ops = &sor_client_ops;
3906	sor->client.dev = &pdev->dev;
3907
3908	err = host1x_client_register(&sor->client);
3909	if (err < 0) {
3910		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
3911			err);
3912		goto rpm_disable;
3913	}
3914
3915	/*
3916	 * On Tegra210 and earlier, provide our own implementation for the
3917	 * pad output clock.
3918	 */
3919	if (!sor->clk_pad) {
3920		char *name;
3921
3922		name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout",
3923				      sor->index);
3924		if (!name) {
3925			err = -ENOMEM;
3926			goto unregister;
3927		}
3928
3929		err = host1x_client_resume(&sor->client);
3930		if (err < 0) {
3931			dev_err(sor->dev, "failed to resume: %d\n", err);
3932			goto unregister;
 
3933		}
3934
3935		sor->clk_pad = tegra_clk_sor_pad_register(sor, name);
3936		host1x_client_suspend(&sor->client);
 
3937	}
3938
3939	if (IS_ERR(sor->clk_pad)) {
3940		err = PTR_ERR(sor->clk_pad);
3941		dev_err(sor->dev, "failed to register SOR pad clock: %d\n",
 
 
 
 
 
 
 
 
 
 
 
3942			err);
3943		goto unregister;
3944	}
3945
3946	return 0;
3947
3948unregister:
3949	host1x_client_unregister(&sor->client);
3950rpm_disable:
3951	pm_runtime_disable(&pdev->dev);
3952remove:
3953	if (sor->ops && sor->ops->remove)
3954		sor->ops->remove(sor);
3955output:
3956	tegra_output_remove(&sor->output);
3957	return err;
3958}
3959
3960static int tegra_sor_remove(struct platform_device *pdev)
3961{
3962	struct tegra_sor *sor = platform_get_drvdata(pdev);
3963	int err;
3964
 
 
3965	err = host1x_client_unregister(&sor->client);
3966	if (err < 0) {
3967		dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
3968			err);
3969		return err;
3970	}
3971
3972	pm_runtime_disable(&pdev->dev);
3973
3974	if (sor->ops && sor->ops->remove) {
3975		err = sor->ops->remove(sor);
3976		if (err < 0)
3977			dev_err(&pdev->dev, "failed to remove SOR: %d\n", err);
3978	}
3979
3980	tegra_output_remove(&sor->output);
3981
3982	return 0;
3983}
3984
3985static int __maybe_unused tegra_sor_suspend(struct device *dev)
 
3986{
3987	struct tegra_sor *sor = dev_get_drvdata(dev);
3988	int err;
3989
3990	err = tegra_output_suspend(&sor->output);
3991	if (err < 0) {
3992		dev_err(dev, "failed to suspend output: %d\n", err);
3993		return err;
3994	}
3995
3996	if (sor->hdmi_supply) {
3997		err = regulator_disable(sor->hdmi_supply);
3998		if (err < 0) {
3999			tegra_output_resume(&sor->output);
4000			return err;
4001		}
 
 
4002	}
4003
 
 
 
 
4004	return 0;
4005}
4006
4007static int __maybe_unused tegra_sor_resume(struct device *dev)
4008{
4009	struct tegra_sor *sor = dev_get_drvdata(dev);
4010	int err;
4011
4012	if (sor->hdmi_supply) {
4013		err = regulator_enable(sor->hdmi_supply);
4014		if (err < 0)
4015			return err;
4016	}
4017
4018	err = tegra_output_resume(&sor->output);
4019	if (err < 0) {
4020		dev_err(dev, "failed to resume output: %d\n", err);
4021
4022		if (sor->hdmi_supply)
4023			regulator_disable(sor->hdmi_supply);
 
 
 
 
 
4024
4025		return err;
 
 
 
 
 
 
4026	}
4027
4028	return 0;
4029}
 
4030
4031static const struct dev_pm_ops tegra_sor_pm_ops = {
4032	SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume)
4033};
4034
4035struct platform_driver tegra_sor_driver = {
4036	.driver = {
4037		.name = "tegra-sor",
4038		.of_match_table = tegra_sor_of_match,
4039		.pm = &tegra_sor_pm_ops,
4040	},
4041	.probe = tegra_sor_probe,
4042	.remove = tegra_sor_remove,
4043};