Loading...
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27/**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34#include "amdgpu.h"
35#include "amdgpu_display.h"
36#include "amdgpu_gem.h"
37#include "amdgpu_dma_buf.h"
38#include <drm/amdgpu_drm.h>
39#include <linux/dma-buf.h>
40#include <linux/dma-fence-array.h>
41#include <linux/pci-p2pdma.h>
42
43/**
44 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
45 * @obj: GEM BO
46 *
47 * Sets up an in-kernel virtual mapping of the BO's memory.
48 *
49 * Returns:
50 * The virtual address of the mapping or an error pointer.
51 */
52void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
53{
54 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
55 int ret;
56
57 ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
58 &bo->dma_buf_vmap);
59 if (ret)
60 return ERR_PTR(ret);
61
62 return bo->dma_buf_vmap.virtual;
63}
64
65/**
66 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
67 * @obj: GEM BO
68 * @vaddr: Virtual address (unused)
69 *
70 * Tears down the in-kernel virtual mapping of the BO's memory.
71 */
72void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
73{
74 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
75
76 ttm_bo_kunmap(&bo->dma_buf_vmap);
77}
78
79/**
80 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
81 * @obj: GEM BO
82 * @vma: Virtual memory area
83 *
84 * Sets up a userspace mapping of the BO's memory in the given
85 * virtual memory area.
86 *
87 * Returns:
88 * 0 on success or a negative error code on failure.
89 */
90int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
91 struct vm_area_struct *vma)
92{
93 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
94 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
95 unsigned asize = amdgpu_bo_size(bo);
96 int ret;
97
98 if (!vma->vm_file)
99 return -ENODEV;
100
101 if (adev == NULL)
102 return -ENODEV;
103
104 /* Check for valid size. */
105 if (asize < vma->vm_end - vma->vm_start)
106 return -EINVAL;
107
108 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
109 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
110 return -EPERM;
111 }
112 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
113
114 /* prime mmap does not need to check access, so allow here */
115 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
116 if (ret)
117 return ret;
118
119 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
120 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
121
122 return ret;
123}
124
125static int
126__dma_resv_make_exclusive(struct dma_resv *obj)
127{
128 struct dma_fence **fences;
129 unsigned int count;
130 int r;
131
132 if (!dma_resv_get_list(obj)) /* no shared fences to convert */
133 return 0;
134
135 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
136 if (r)
137 return r;
138
139 if (count == 0) {
140 /* Now that was unexpected. */
141 } else if (count == 1) {
142 dma_resv_add_excl_fence(obj, fences[0]);
143 dma_fence_put(fences[0]);
144 kfree(fences);
145 } else {
146 struct dma_fence_array *array;
147
148 array = dma_fence_array_create(count, fences,
149 dma_fence_context_alloc(1), 0,
150 false);
151 if (!array)
152 goto err_fences_put;
153
154 dma_resv_add_excl_fence(obj, &array->base);
155 dma_fence_put(&array->base);
156 }
157
158 return 0;
159
160err_fences_put:
161 while (count--)
162 dma_fence_put(fences[count]);
163 kfree(fences);
164 return -ENOMEM;
165}
166
167/**
168 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
169 *
170 * @dmabuf: DMA-buf where we attach to
171 * @attach: attachment to add
172 *
173 * Add the attachment as user to the exported DMA-buf.
174 */
175static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
176 struct dma_buf_attachment *attach)
177{
178 struct drm_gem_object *obj = dmabuf->priv;
179 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
180 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
181 int r;
182
183 if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
184 attach->peer2peer = false;
185
186 if (attach->dev->driver == adev->dev->driver)
187 return 0;
188
189 r = amdgpu_bo_reserve(bo, false);
190 if (unlikely(r != 0))
191 return r;
192
193 /*
194 * We only create shared fences for internal use, but importers
195 * of the dmabuf rely on exclusive fences for implicitly
196 * tracking write hazards. As any of the current fences may
197 * correspond to a write, we need to convert all existing
198 * fences on the reservation object into a single exclusive
199 * fence.
200 */
201 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
202 if (r)
203 return r;
204
205 bo->prime_shared_count++;
206 amdgpu_bo_unreserve(bo);
207 return 0;
208}
209
210/**
211 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
212 *
213 * @dmabuf: DMA-buf where we remove the attachment from
214 * @attach: the attachment to remove
215 *
216 * Called when an attachment is removed from the DMA-buf.
217 */
218static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
219 struct dma_buf_attachment *attach)
220{
221 struct drm_gem_object *obj = dmabuf->priv;
222 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
223 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
224
225 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
226 bo->prime_shared_count--;
227}
228
229/**
230 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
231 *
232 * @attach: attachment to pin down
233 *
234 * Pin the BO which is backing the DMA-buf so that it can't move any more.
235 */
236static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
237{
238 struct drm_gem_object *obj = attach->dmabuf->priv;
239 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
240
241 /* pin buffer into GTT */
242 return amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
243}
244
245/**
246 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
247 *
248 * @attach: attachment to unpin
249 *
250 * Unpin a previously pinned BO to make it movable again.
251 */
252static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
253{
254 struct drm_gem_object *obj = attach->dmabuf->priv;
255 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
256
257 amdgpu_bo_unpin(bo);
258}
259
260/**
261 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
262 * @attach: DMA-buf attachment
263 * @dir: DMA direction
264 *
265 * Makes sure that the shared DMA buffer can be accessed by the target device.
266 * For now, simply pins it to the GTT domain, where it should be accessible by
267 * all DMA devices.
268 *
269 * Returns:
270 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
271 * code.
272 */
273static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
274 enum dma_data_direction dir)
275{
276 struct dma_buf *dma_buf = attach->dmabuf;
277 struct drm_gem_object *obj = dma_buf->priv;
278 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
279 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
280 struct sg_table *sgt;
281 long r;
282
283 if (!bo->pin_count) {
284 /* move buffer into GTT or VRAM */
285 struct ttm_operation_ctx ctx = { false, false };
286 unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
287
288 if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
289 attach->peer2peer) {
290 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
291 domains |= AMDGPU_GEM_DOMAIN_VRAM;
292 }
293 amdgpu_bo_placement_from_domain(bo, domains);
294 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
295 if (r)
296 return ERR_PTR(r);
297
298 } else if (!(amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type) &
299 AMDGPU_GEM_DOMAIN_GTT)) {
300 return ERR_PTR(-EBUSY);
301 }
302
303 switch (bo->tbo.mem.mem_type) {
304 case TTM_PL_TT:
305 sgt = drm_prime_pages_to_sg(bo->tbo.ttm->pages,
306 bo->tbo.num_pages);
307 if (IS_ERR(sgt))
308 return sgt;
309
310 if (dma_map_sgtable(attach->dev, sgt, dir,
311 DMA_ATTR_SKIP_CPU_SYNC))
312 goto error_free;
313 break;
314
315 case TTM_PL_VRAM:
316 r = amdgpu_vram_mgr_alloc_sgt(adev, &bo->tbo.mem, attach->dev,
317 dir, &sgt);
318 if (r)
319 return ERR_PTR(r);
320 break;
321 default:
322 return ERR_PTR(-EINVAL);
323 }
324
325 return sgt;
326
327error_free:
328 sg_free_table(sgt);
329 kfree(sgt);
330 return ERR_PTR(-EBUSY);
331}
332
333/**
334 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
335 * @attach: DMA-buf attachment
336 * @sgt: sg_table to unmap
337 * @dir: DMA direction
338 *
339 * This is called when a shared DMA buffer no longer needs to be accessible by
340 * another device. For now, simply unpins the buffer from GTT.
341 */
342static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
343 struct sg_table *sgt,
344 enum dma_data_direction dir)
345{
346 struct dma_buf *dma_buf = attach->dmabuf;
347 struct drm_gem_object *obj = dma_buf->priv;
348 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
349 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
350
351 if (sgt->sgl->page_link) {
352 dma_unmap_sgtable(attach->dev, sgt, dir, 0);
353 sg_free_table(sgt);
354 kfree(sgt);
355 } else {
356 amdgpu_vram_mgr_free_sgt(adev, attach->dev, dir, sgt);
357 }
358}
359
360/**
361 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
362 * @dma_buf: Shared DMA buffer
363 * @direction: Direction of DMA transfer
364 *
365 * This is called before CPU access to the shared DMA buffer's memory. If it's
366 * a read access, the buffer is moved to the GTT domain if possible, for optimal
367 * CPU read performance.
368 *
369 * Returns:
370 * 0 on success or a negative error code on failure.
371 */
372static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
373 enum dma_data_direction direction)
374{
375 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
376 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
377 struct ttm_operation_ctx ctx = { true, false };
378 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
379 int ret;
380 bool reads = (direction == DMA_BIDIRECTIONAL ||
381 direction == DMA_FROM_DEVICE);
382
383 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
384 return 0;
385
386 /* move to gtt */
387 ret = amdgpu_bo_reserve(bo, false);
388 if (unlikely(ret != 0))
389 return ret;
390
391 if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
392 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
393 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
394 }
395
396 amdgpu_bo_unreserve(bo);
397 return ret;
398}
399
400const struct dma_buf_ops amdgpu_dmabuf_ops = {
401 .attach = amdgpu_dma_buf_attach,
402 .detach = amdgpu_dma_buf_detach,
403 .pin = amdgpu_dma_buf_pin,
404 .unpin = amdgpu_dma_buf_unpin,
405 .map_dma_buf = amdgpu_dma_buf_map,
406 .unmap_dma_buf = amdgpu_dma_buf_unmap,
407 .release = drm_gem_dmabuf_release,
408 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
409 .mmap = drm_gem_dmabuf_mmap,
410 .vmap = drm_gem_dmabuf_vmap,
411 .vunmap = drm_gem_dmabuf_vunmap,
412};
413
414/**
415 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
416 * @gobj: GEM BO
417 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
418 *
419 * The main work is done by the &drm_gem_prime_export helper.
420 *
421 * Returns:
422 * Shared DMA buffer representing the GEM BO from the given device.
423 */
424struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
425 int flags)
426{
427 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
428 struct dma_buf *buf;
429
430 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
431 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
432 return ERR_PTR(-EPERM);
433
434 buf = drm_gem_prime_export(gobj, flags);
435 if (!IS_ERR(buf))
436 buf->ops = &amdgpu_dmabuf_ops;
437
438 return buf;
439}
440
441/**
442 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
443 *
444 * @dev: DRM device
445 * @dma_buf: DMA-buf
446 *
447 * Creates an empty SG BO for DMA-buf import.
448 *
449 * Returns:
450 * A new GEM BO of the given DRM device, representing the memory
451 * described by the given DMA-buf attachment and scatter/gather table.
452 */
453static struct drm_gem_object *
454amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
455{
456 struct dma_resv *resv = dma_buf->resv;
457 struct amdgpu_device *adev = dev->dev_private;
458 struct amdgpu_bo *bo;
459 struct amdgpu_bo_param bp;
460 int ret;
461
462 memset(&bp, 0, sizeof(bp));
463 bp.size = dma_buf->size;
464 bp.byte_align = PAGE_SIZE;
465 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
466 bp.flags = 0;
467 bp.type = ttm_bo_type_sg;
468 bp.resv = resv;
469 dma_resv_lock(resv, NULL);
470 ret = amdgpu_bo_create(adev, &bp, &bo);
471 if (ret)
472 goto error;
473
474 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
475 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
476 if (dma_buf->ops != &amdgpu_dmabuf_ops)
477 bo->prime_shared_count = 1;
478
479 dma_resv_unlock(resv);
480 return &bo->tbo.base;
481
482error:
483 dma_resv_unlock(resv);
484 return ERR_PTR(ret);
485}
486
487/**
488 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
489 *
490 * @attach: the DMA-buf attachment
491 *
492 * Invalidate the DMA-buf attachment, making sure that the we re-create the
493 * mapping before the next use.
494 */
495static void
496amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
497{
498 struct drm_gem_object *obj = attach->importer_priv;
499 struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
500 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
501 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
502 struct ttm_operation_ctx ctx = { false, false };
503 struct ttm_placement placement = {};
504 struct amdgpu_vm_bo_base *bo_base;
505 int r;
506
507 if (bo->tbo.mem.mem_type == TTM_PL_SYSTEM)
508 return;
509
510 r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
511 if (r) {
512 DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
513 return;
514 }
515
516 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
517 struct amdgpu_vm *vm = bo_base->vm;
518 struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
519
520 if (ticket) {
521 /* When we get an error here it means that somebody
522 * else is holding the VM lock and updating page tables
523 * So we can just continue here.
524 */
525 r = dma_resv_lock(resv, ticket);
526 if (r)
527 continue;
528
529 } else {
530 /* TODO: This is more problematic and we actually need
531 * to allow page tables updates without holding the
532 * lock.
533 */
534 if (!dma_resv_trylock(resv))
535 continue;
536 }
537
538 r = amdgpu_vm_clear_freed(adev, vm, NULL);
539 if (!r)
540 r = amdgpu_vm_handle_moved(adev, vm);
541
542 if (r && r != -EBUSY)
543 DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
544 r);
545
546 dma_resv_unlock(resv);
547 }
548}
549
550static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
551 .allow_peer2peer = true,
552 .move_notify = amdgpu_dma_buf_move_notify
553};
554
555/**
556 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
557 * @dev: DRM device
558 * @dma_buf: Shared DMA buffer
559 *
560 * Import a dma_buf into a the driver and potentially create a new GEM object.
561 *
562 * Returns:
563 * GEM BO representing the shared DMA buffer for the given device.
564 */
565struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
566 struct dma_buf *dma_buf)
567{
568 struct dma_buf_attachment *attach;
569 struct drm_gem_object *obj;
570
571 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
572 obj = dma_buf->priv;
573 if (obj->dev == dev) {
574 /*
575 * Importing dmabuf exported from out own gem increases
576 * refcount on gem itself instead of f_count of dmabuf.
577 */
578 drm_gem_object_get(obj);
579 return obj;
580 }
581 }
582
583 obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
584 if (IS_ERR(obj))
585 return obj;
586
587 attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
588 &amdgpu_dma_buf_attach_ops, obj);
589 if (IS_ERR(attach)) {
590 drm_gem_object_put(obj);
591 return ERR_CAST(attach);
592 }
593
594 get_dma_buf(dma_buf);
595 obj->import_attach = attach;
596 return obj;
597}
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * based on nouveau_prime.c
23 *
24 * Authors: Alex Deucher
25 */
26
27/**
28 * DOC: PRIME Buffer Sharing
29 *
30 * The following callback implementations are used for :ref:`sharing GEM buffer
31 * objects between different devices via PRIME <prime_buffer_sharing>`.
32 */
33
34#include "amdgpu.h"
35#include "amdgpu_display.h"
36#include "amdgpu_gem.h"
37#include <drm/amdgpu_drm.h>
38#include <linux/dma-buf.h>
39#include <linux/dma-fence-array.h>
40
41/**
42 * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
43 * implementation
44 * @obj: GEM buffer object (BO)
45 *
46 * Returns:
47 * A scatter/gather table for the pinned pages of the BO's memory.
48 */
49struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
50{
51 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
52 int npages = bo->tbo.num_pages;
53
54 return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
55}
56
57/**
58 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
59 * @obj: GEM BO
60 *
61 * Sets up an in-kernel virtual mapping of the BO's memory.
62 *
63 * Returns:
64 * The virtual address of the mapping or an error pointer.
65 */
66void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
67{
68 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
69 int ret;
70
71 ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
72 &bo->dma_buf_vmap);
73 if (ret)
74 return ERR_PTR(ret);
75
76 return bo->dma_buf_vmap.virtual;
77}
78
79/**
80 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
81 * @obj: GEM BO
82 * @vaddr: Virtual address (unused)
83 *
84 * Tears down the in-kernel virtual mapping of the BO's memory.
85 */
86void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
87{
88 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
89
90 ttm_bo_kunmap(&bo->dma_buf_vmap);
91}
92
93/**
94 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
95 * @obj: GEM BO
96 * @vma: Virtual memory area
97 *
98 * Sets up a userspace mapping of the BO's memory in the given
99 * virtual memory area.
100 *
101 * Returns:
102 * 0 on success or a negative error code on failure.
103 */
104int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
105 struct vm_area_struct *vma)
106{
107 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
108 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
109 unsigned asize = amdgpu_bo_size(bo);
110 int ret;
111
112 if (!vma->vm_file)
113 return -ENODEV;
114
115 if (adev == NULL)
116 return -ENODEV;
117
118 /* Check for valid size. */
119 if (asize < vma->vm_end - vma->vm_start)
120 return -EINVAL;
121
122 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
123 (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
124 return -EPERM;
125 }
126 vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
127
128 /* prime mmap does not need to check access, so allow here */
129 ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
130 if (ret)
131 return ret;
132
133 ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
134 drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
135
136 return ret;
137}
138
139static int
140__dma_resv_make_exclusive(struct dma_resv *obj)
141{
142 struct dma_fence **fences;
143 unsigned int count;
144 int r;
145
146 if (!dma_resv_get_list(obj)) /* no shared fences to convert */
147 return 0;
148
149 r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
150 if (r)
151 return r;
152
153 if (count == 0) {
154 /* Now that was unexpected. */
155 } else if (count == 1) {
156 dma_resv_add_excl_fence(obj, fences[0]);
157 dma_fence_put(fences[0]);
158 kfree(fences);
159 } else {
160 struct dma_fence_array *array;
161
162 array = dma_fence_array_create(count, fences,
163 dma_fence_context_alloc(1), 0,
164 false);
165 if (!array)
166 goto err_fences_put;
167
168 dma_resv_add_excl_fence(obj, &array->base);
169 dma_fence_put(&array->base);
170 }
171
172 return 0;
173
174err_fences_put:
175 while (count--)
176 dma_fence_put(fences[count]);
177 kfree(fences);
178 return -ENOMEM;
179}
180
181/**
182 * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation
183 * @dma_buf: Shared DMA buffer
184 * @attach: DMA-buf attachment
185 *
186 * Makes sure that the shared DMA buffer can be accessed by the target device.
187 * For now, simply pins it to the GTT domain, where it should be accessible by
188 * all DMA devices.
189 *
190 * Returns:
191 * 0 on success or a negative error code on failure.
192 */
193static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf,
194 struct dma_buf_attachment *attach)
195{
196 struct drm_gem_object *obj = dma_buf->priv;
197 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
198 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
199 long r;
200
201 r = drm_gem_map_attach(dma_buf, attach);
202 if (r)
203 return r;
204
205 r = amdgpu_bo_reserve(bo, false);
206 if (unlikely(r != 0))
207 goto error_detach;
208
209
210 if (attach->dev->driver != adev->dev->driver) {
211 /*
212 * We only create shared fences for internal use, but importers
213 * of the dmabuf rely on exclusive fences for implicitly
214 * tracking write hazards. As any of the current fences may
215 * correspond to a write, we need to convert all existing
216 * fences on the reservation object into a single exclusive
217 * fence.
218 */
219 r = __dma_resv_make_exclusive(bo->tbo.base.resv);
220 if (r)
221 goto error_unreserve;
222 }
223
224 /* pin buffer into GTT */
225 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
226 if (r)
227 goto error_unreserve;
228
229 if (attach->dev->driver != adev->dev->driver)
230 bo->prime_shared_count++;
231
232error_unreserve:
233 amdgpu_bo_unreserve(bo);
234
235error_detach:
236 if (r)
237 drm_gem_map_detach(dma_buf, attach);
238 return r;
239}
240
241/**
242 * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation
243 * @dma_buf: Shared DMA buffer
244 * @attach: DMA-buf attachment
245 *
246 * This is called when a shared DMA buffer no longer needs to be accessible by
247 * another device. For now, simply unpins the buffer from GTT.
248 */
249static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf,
250 struct dma_buf_attachment *attach)
251{
252 struct drm_gem_object *obj = dma_buf->priv;
253 struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
254 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
255 int ret = 0;
256
257 ret = amdgpu_bo_reserve(bo, true);
258 if (unlikely(ret != 0))
259 goto error;
260
261 amdgpu_bo_unpin(bo);
262 if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
263 bo->prime_shared_count--;
264 amdgpu_bo_unreserve(bo);
265
266error:
267 drm_gem_map_detach(dma_buf, attach);
268}
269
270/**
271 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
272 * @dma_buf: Shared DMA buffer
273 * @direction: Direction of DMA transfer
274 *
275 * This is called before CPU access to the shared DMA buffer's memory. If it's
276 * a read access, the buffer is moved to the GTT domain if possible, for optimal
277 * CPU read performance.
278 *
279 * Returns:
280 * 0 on success or a negative error code on failure.
281 */
282static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
283 enum dma_data_direction direction)
284{
285 struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
286 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
287 struct ttm_operation_ctx ctx = { true, false };
288 u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
289 int ret;
290 bool reads = (direction == DMA_BIDIRECTIONAL ||
291 direction == DMA_FROM_DEVICE);
292
293 if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
294 return 0;
295
296 /* move to gtt */
297 ret = amdgpu_bo_reserve(bo, false);
298 if (unlikely(ret != 0))
299 return ret;
300
301 if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
302 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
303 ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
304 }
305
306 amdgpu_bo_unreserve(bo);
307 return ret;
308}
309
310const struct dma_buf_ops amdgpu_dmabuf_ops = {
311 .attach = amdgpu_dma_buf_map_attach,
312 .detach = amdgpu_dma_buf_map_detach,
313 .map_dma_buf = drm_gem_map_dma_buf,
314 .unmap_dma_buf = drm_gem_unmap_dma_buf,
315 .release = drm_gem_dmabuf_release,
316 .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
317 .mmap = drm_gem_dmabuf_mmap,
318 .vmap = drm_gem_dmabuf_vmap,
319 .vunmap = drm_gem_dmabuf_vunmap,
320};
321
322/**
323 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
324 * @dev: DRM device
325 * @gobj: GEM BO
326 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
327 *
328 * The main work is done by the &drm_gem_prime_export helper.
329 *
330 * Returns:
331 * Shared DMA buffer representing the GEM BO from the given device.
332 */
333struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
334 int flags)
335{
336 struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
337 struct dma_buf *buf;
338
339 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
340 bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
341 return ERR_PTR(-EPERM);
342
343 buf = drm_gem_prime_export(gobj, flags);
344 if (!IS_ERR(buf)) {
345 buf->file->f_mapping = gobj->dev->anon_inode->i_mapping;
346 buf->ops = &amdgpu_dmabuf_ops;
347 }
348
349 return buf;
350}
351
352/**
353 * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
354 * implementation
355 * @dev: DRM device
356 * @attach: DMA-buf attachment
357 * @sg: Scatter/gather table
358 *
359 * Imports shared DMA buffer memory exported by another device.
360 *
361 * Returns:
362 * A new GEM BO of the given DRM device, representing the memory
363 * described by the given DMA-buf attachment and scatter/gather table.
364 */
365struct drm_gem_object *
366amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
367 struct dma_buf_attachment *attach,
368 struct sg_table *sg)
369{
370 struct dma_resv *resv = attach->dmabuf->resv;
371 struct amdgpu_device *adev = dev->dev_private;
372 struct amdgpu_bo *bo;
373 struct amdgpu_bo_param bp;
374 int ret;
375
376 memset(&bp, 0, sizeof(bp));
377 bp.size = attach->dmabuf->size;
378 bp.byte_align = PAGE_SIZE;
379 bp.domain = AMDGPU_GEM_DOMAIN_CPU;
380 bp.flags = 0;
381 bp.type = ttm_bo_type_sg;
382 bp.resv = resv;
383 dma_resv_lock(resv, NULL);
384 ret = amdgpu_bo_create(adev, &bp, &bo);
385 if (ret)
386 goto error;
387
388 bo->tbo.sg = sg;
389 bo->tbo.ttm->sg = sg;
390 bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
391 bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
392 if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
393 bo->prime_shared_count = 1;
394
395 dma_resv_unlock(resv);
396 return &bo->tbo.base;
397
398error:
399 dma_resv_unlock(resv);
400 return ERR_PTR(ret);
401}
402
403/**
404 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
405 * @dev: DRM device
406 * @dma_buf: Shared DMA buffer
407 *
408 * The main work is done by the &drm_gem_prime_import helper, which in turn
409 * uses &amdgpu_gem_prime_import_sg_table.
410 *
411 * Returns:
412 * GEM BO representing the shared DMA buffer for the given device.
413 */
414struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
415 struct dma_buf *dma_buf)
416{
417 struct drm_gem_object *obj;
418
419 if (dma_buf->ops == &amdgpu_dmabuf_ops) {
420 obj = dma_buf->priv;
421 if (obj->dev == dev) {
422 /*
423 * Importing dmabuf exported from out own gem increases
424 * refcount on gem itself instead of f_count of dmabuf.
425 */
426 drm_gem_object_get(obj);
427 return obj;
428 }
429 }
430
431 return drm_gem_prime_import(dev, dma_buf);
432}