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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* drivers/atm/firestream.h - FireStream 155 (MB86697) and
3 * FireStream 50 (MB86695) device driver
4 */
5
6/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
9 */
10
11/*
12*/
13
14
15/***********************************************************************
16 * first the defines for the chip. *
17 ***********************************************************************/
18
19
20/********************* General chip parameters. ************************/
21
22#define FS_NR_FREE_POOLS 8
23#define FS_NR_RX_QUEUES 4
24
25
26/********************* queues and queue access macros ******************/
27
28
29/* A queue entry. */
30struct FS_QENTRY {
31 u32 cmd;
32 u32 p0, p1, p2;
33};
34
35
36/* A freepool entry. */
37struct FS_BPENTRY {
38 u32 flags;
39 u32 next;
40 u32 bsa;
41 u32 aal_bufsize;
42
43 /* The hardware doesn't look at this, but we need the SKB somewhere... */
44 struct sk_buff *skb;
45 struct freepool *fp;
46 struct fs_dev *dev;
47};
48
49
50#define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f)
51
52
53/* OFFSETS against the base of a QUEUE... */
54#define QSA 0x00
55#define QEA 0x04
56#define QRP 0x08
57#define QWP 0x0c
58#define QCNF 0x10 /* Only for Release queues! */
59/* Not for the transmit pending queue. */
60
61
62/* OFFSETS against the base of a FREE POOL... */
63#define FPCNF 0x00
64#define FPSA 0x04
65#define FPEA 0x08
66#define FPCNT 0x0c
67#define FPCTU 0x10
68
69#define Q_SA(b) (b + QSA )
70#define Q_EA(b) (b + QEA )
71#define Q_RP(b) (b + QRP )
72#define Q_WP(b) (b + QWP )
73#define Q_CNF(b) (b + QCNF)
74
75#define FP_CNF(b) (b + FPCNF)
76#define FP_SA(b) (b + FPSA)
77#define FP_EA(b) (b + FPEA)
78#define FP_CNT(b) (b + FPCNT)
79#define FP_CTU(b) (b + FPCTU)
80
81/* bits in a queue register. */
82#define Q_FULL 0x1
83#define Q_EMPTY 0x2
84#define Q_INCWRAP 0x4
85#define Q_ADDR_MASK 0xfffffff0
86
87/* bits in a FreePool config register */
88#define RBFP_RBS (0x1 << 16)
89#define RBFP_RBSVAL (0x1 << 15)
90#define RBFP_CME (0x1 << 12)
91#define RBFP_DLP (0x1 << 11)
92#define RBFP_BFPWT (0x1 << 0)
93
94
95
96
97/* FireStream commands. */
98#define QE_CMD_NULL (0x00 << 22)
99#define QE_CMD_REG_RD (0x01 << 22)
100#define QE_CMD_REG_RDM (0x02 << 22)
101#define QE_CMD_REG_WR (0x03 << 22)
102#define QE_CMD_REG_WRM (0x04 << 22)
103#define QE_CMD_CONFIG_TX (0x05 << 22)
104#define QE_CMD_CONFIG_RX (0x06 << 22)
105#define QE_CMD_PRP_RD (0x07 << 22)
106#define QE_CMD_PRP_RDM (0x2a << 22)
107#define QE_CMD_PRP_WR (0x09 << 22)
108#define QE_CMD_PRP_WRM (0x2b << 22)
109#define QE_CMD_RX_EN (0x0a << 22)
110#define QE_CMD_RX_PURGE (0x0b << 22)
111#define QE_CMD_RX_PURGE_INH (0x0c << 22)
112#define QE_CMD_TX_EN (0x0d << 22)
113#define QE_CMD_TX_PURGE (0x0e << 22)
114#define QE_CMD_TX_PURGE_INH (0x0f << 22)
115#define QE_CMD_RST_CG (0x10 << 22)
116#define QE_CMD_SET_CG (0x11 << 22)
117#define QE_CMD_RST_CLP (0x12 << 22)
118#define QE_CMD_SET_CLP (0x13 << 22)
119#define QE_CMD_OVERRIDE (0x14 << 22)
120#define QE_CMD_ADD_BFP (0x15 << 22)
121#define QE_CMD_DUMP_TX (0x16 << 22)
122#define QE_CMD_DUMP_RX (0x17 << 22)
123#define QE_CMD_LRAM_RD (0x18 << 22)
124#define QE_CMD_LRAM_RDM (0x28 << 22)
125#define QE_CMD_LRAM_WR (0x19 << 22)
126#define QE_CMD_LRAM_WRM (0x29 << 22)
127#define QE_CMD_LRAM_BSET (0x1a << 22)
128#define QE_CMD_LRAM_BCLR (0x1b << 22)
129#define QE_CMD_CONFIG_SEGM (0x1c << 22)
130#define QE_CMD_READ_SEGM (0x1d << 22)
131#define QE_CMD_CONFIG_ROUT (0x1e << 22)
132#define QE_CMD_READ_ROUT (0x1f << 22)
133#define QE_CMD_CONFIG_TM (0x20 << 22)
134#define QE_CMD_READ_TM (0x21 << 22)
135#define QE_CMD_CONFIG_TXBM (0x22 << 22)
136#define QE_CMD_READ_TXBM (0x23 << 22)
137#define QE_CMD_CONFIG_RXBM (0x24 << 22)
138#define QE_CMD_READ_RXBM (0x25 << 22)
139#define QE_CMD_CONFIG_REAS (0x26 << 22)
140#define QE_CMD_READ_REAS (0x27 << 22)
141
142#define QE_TRANSMIT_DE (0x0 << 30)
143#define QE_CMD_LINKED (0x1 << 30)
144#define QE_CMD_IMM (0x2 << 30)
145#define QE_CMD_IMM_INQ (0x3 << 30)
146
147#define TD_EPI (0x1 << 27)
148#define TD_COMMAND (0x1 << 28)
149
150#define TD_DATA (0x0 << 29)
151#define TD_RM_CELL (0x1 << 29)
152#define TD_OAM_CELL (0x2 << 29)
153#define TD_OAM_CELL_SEGMENT (0x3 << 29)
154
155#define TD_BPI (0x1 << 20)
156
157#define FP_FLAGS_EPI (0x1 << 27)
158
159
160#define TX_PQ(i) (0x00 + (i) * 0x10)
161#define TXB_RQ (0x20)
162#define ST_Q (0x48)
163#define RXB_FP(i) (0x90 + (i) * 0x14)
164#define RXB_RQ(i) (0x134 + (i) * 0x14)
165
166
167#define TXQ_HP 0
168#define TXQ_LP 1
169
170/* Phew. You don't want to know how many revisions these simple queue
171 * address macros went through before I got them nice and compact as
172 * they are now. -- REW
173 */
174
175
176/* And now for something completely different:
177 * The rest of the registers... */
178
179
180#define CMDR0 0x34
181#define CMDR1 0x38
182#define CMDR2 0x3c
183#define CMDR3 0x40
184
185
186#define SARMODE0 0x5c
187
188#define SARMODE0_TXVCS_0 (0x0 << 0)
189#define SARMODE0_TXVCS_1k (0x1 << 0)
190#define SARMODE0_TXVCS_2k (0x2 << 0)
191#define SARMODE0_TXVCS_4k (0x3 << 0)
192#define SARMODE0_TXVCS_8k (0x4 << 0)
193#define SARMODE0_TXVCS_16k (0x5 << 0)
194#define SARMODE0_TXVCS_32k (0x6 << 0)
195#define SARMODE0_TXVCS_64k (0x7 << 0)
196#define SARMODE0_TXVCS_32 (0x8 << 0)
197
198#define SARMODE0_ABRVCS_0 (0x0 << 4)
199#define SARMODE0_ABRVCS_512 (0x1 << 4)
200#define SARMODE0_ABRVCS_1k (0x2 << 4)
201#define SARMODE0_ABRVCS_2k (0x3 << 4)
202#define SARMODE0_ABRVCS_4k (0x4 << 4)
203#define SARMODE0_ABRVCS_8k (0x5 << 4)
204#define SARMODE0_ABRVCS_16k (0x6 << 4)
205#define SARMODE0_ABRVCS_32k (0x7 << 4)
206#define SARMODE0_ABRVCS_32 (0x9 << 4) /* The others are "8", this one really has to
207 be 9. Tell me you don't believe me. -- REW */
208
209#define SARMODE0_RXVCS_0 (0x0 << 8)
210#define SARMODE0_RXVCS_1k (0x1 << 8)
211#define SARMODE0_RXVCS_2k (0x2 << 8)
212#define SARMODE0_RXVCS_4k (0x3 << 8)
213#define SARMODE0_RXVCS_8k (0x4 << 8)
214#define SARMODE0_RXVCS_16k (0x5 << 8)
215#define SARMODE0_RXVCS_32k (0x6 << 8)
216#define SARMODE0_RXVCS_64k (0x7 << 8)
217#define SARMODE0_RXVCS_32 (0x8 << 8)
218
219#define SARMODE0_CALSUP_1 (0x0 << 12)
220#define SARMODE0_CALSUP_2 (0x1 << 12)
221#define SARMODE0_CALSUP_3 (0x2 << 12)
222#define SARMODE0_CALSUP_4 (0x3 << 12)
223
224#define SARMODE0_PRPWT_FS50_0 (0x0 << 14)
225#define SARMODE0_PRPWT_FS50_2 (0x1 << 14)
226#define SARMODE0_PRPWT_FS50_5 (0x2 << 14)
227#define SARMODE0_PRPWT_FS50_11 (0x3 << 14)
228
229#define SARMODE0_PRPWT_FS155_0 (0x0 << 14)
230#define SARMODE0_PRPWT_FS155_1 (0x1 << 14)
231#define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
232#define SARMODE0_PRPWT_FS155_3 (0x3 << 14)
233
234#define SARMODE0_SRTS0 (0x1 << 23)
235#define SARMODE0_SRTS1 (0x1 << 24)
236
237#define SARMODE0_RUN (0x1 << 25)
238
239#define SARMODE0_UNLOCK (0x1 << 26)
240#define SARMODE0_CWRE (0x1 << 27)
241
242
243#define SARMODE0_INTMODE_READCLEAR (0x0 << 28)
244#define SARMODE0_INTMODE_READNOCLEAR (0x1 << 28)
245#define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
246#define SARMODE0_INTMODE_READCLEARINHIBIT (0x3 << 28) /* Tell me you don't believe me. */
247
248#define SARMODE0_GINT (0x1 << 30)
249#define SARMODE0_SHADEN (0x1 << 31)
250
251
252#define SARMODE1 0x60
253
254
255#define SARMODE1_TRTL_SHIFT 0 /* Program to 0 */
256#define SARMODE1_RRTL_SHIFT 4 /* Program to 0 */
257
258#define SARMODE1_TAGM (0x1 << 8) /* Program to 0 */
259
260#define SARMODE1_HECM0 (0x1 << 9)
261#define SARMODE1_HECM1 (0x1 << 10)
262#define SARMODE1_HECM2 (0x1 << 11)
263
264#define SARMODE1_GFCE (0x1 << 14)
265#define SARMODE1_GFCR (0x1 << 15)
266#define SARMODE1_PMS (0x1 << 18)
267#define SARMODE1_GPRI (0x1 << 19)
268#define SARMODE1_GPAS (0x1 << 20)
269#define SARMODE1_GVAS (0x1 << 21)
270#define SARMODE1_GNAM (0x1 << 22)
271#define SARMODE1_GPLEN (0x1 << 23)
272#define SARMODE1_DUMPE (0x1 << 24)
273#define SARMODE1_OAMCRC (0x1 << 25)
274#define SARMODE1_DCOAM (0x1 << 26)
275#define SARMODE1_DCRM (0x1 << 27)
276#define SARMODE1_TSTLP (0x1 << 28)
277#define SARMODE1_DEFHEC (0x1 << 29)
278
279
280#define ISR 0x64
281#define IUSR 0x68
282#define IMR 0x6c
283
284#define ISR_LPCO (0x1 << 0)
285#define ISR_DPCO (0x1 << 1)
286#define ISR_RBRQ0_W (0x1 << 2)
287#define ISR_RBRQ1_W (0x1 << 3)
288#define ISR_RBRQ2_W (0x1 << 4)
289#define ISR_RBRQ3_W (0x1 << 5)
290#define ISR_RBRQ0_NF (0x1 << 6)
291#define ISR_RBRQ1_NF (0x1 << 7)
292#define ISR_RBRQ2_NF (0x1 << 8)
293#define ISR_RBRQ3_NF (0x1 << 9)
294#define ISR_BFP_SC (0x1 << 10)
295#define ISR_INIT (0x1 << 11)
296#define ISR_INIT_ERR (0x1 << 12) /* Documented as "reserved" */
297#define ISR_USCEO (0x1 << 13)
298#define ISR_UPEC0 (0x1 << 14)
299#define ISR_VPFCO (0x1 << 15)
300#define ISR_CRCCO (0x1 << 16)
301#define ISR_HECO (0x1 << 17)
302#define ISR_TBRQ_W (0x1 << 18)
303#define ISR_TBRQ_NF (0x1 << 19)
304#define ISR_CTPQ_E (0x1 << 20)
305#define ISR_GFC_C0 (0x1 << 21)
306#define ISR_PCI_FTL (0x1 << 22)
307#define ISR_CSQ_W (0x1 << 23)
308#define ISR_CSQ_NF (0x1 << 24)
309#define ISR_EXT_INT (0x1 << 25)
310#define ISR_RXDMA_S (0x1 << 26)
311
312
313#define TMCONF 0x78
314/* Bits? */
315
316
317#define CALPRESCALE 0x7c
318/* Bits? */
319
320#define CELLOSCONF 0x84
321#define CELLOSCONF_COTS (0x1 << 28)
322#define CELLOSCONF_CEN (0x1 << 27)
323#define CELLOSCONF_SC8 (0x3 << 24)
324#define CELLOSCONF_SC4 (0x2 << 24)
325#define CELLOSCONF_SC2 (0x1 << 24)
326#define CELLOSCONF_SC1 (0x0 << 24)
327
328#define CELLOSCONF_COBS (0x1 << 16)
329#define CELLOSCONF_COPK (0x1 << 8)
330#define CELLOSCONF_COST (0x1 << 0)
331/* Bits? */
332
333#define RAS0 0x1bc
334#define RAS0_DCD_XHLT (0x1 << 31)
335
336#define RAS0_VPSEL (0x1 << 16)
337#define RAS0_VCSEL (0x1 << 0)
338
339#define RAS1 0x1c0
340#define RAS1_UTREG (0x1 << 5)
341
342
343#define DMAMR 0x1cc
344#define DMAMR_TX_MODE_FULL (0x0 << 0)
345#define DMAMR_TX_MODE_PART (0x1 << 0)
346#define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
347
348
349
350#define RAS2 0x280
351
352#define RAS2_NNI (0x1 << 0)
353#define RAS2_USEL (0x1 << 1)
354#define RAS2_UBS (0x1 << 2)
355
356
357
358struct fs_transmit_config {
359 u32 flags;
360 u32 atm_hdr;
361 u32 TMC[4];
362 u32 spec;
363 u32 rtag[3];
364};
365
366#define TC_FLAGS_AAL5 (0x0 << 29)
367#define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29)
368#define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29)
369#define TC_FLAGS_STREAMING (0x1 << 28)
370#define TC_FLAGS_PACKET (0x0)
371#define TC_FLAGS_TYPE_ABR (0x0 << 22)
372#define TC_FLAGS_TYPE_CBR (0x1 << 22)
373#define TC_FLAGS_TYPE_VBR (0x2 << 22)
374#define TC_FLAGS_TYPE_UBR (0x3 << 22)
375#define TC_FLAGS_CAL0 (0x0 << 20)
376#define TC_FLAGS_CAL1 (0x1 << 20)
377#define TC_FLAGS_CAL2 (0x2 << 20)
378#define TC_FLAGS_CAL3 (0x3 << 20)
379
380
381#define RC_FLAGS_NAM (0x1 << 13)
382#define RC_FLAGS_RXBM_PSB (0x0 << 14)
383#define RC_FLAGS_RXBM_CIF (0x1 << 14)
384#define RC_FLAGS_RXBM_PMB (0x2 << 14)
385#define RC_FLAGS_RXBM_STR (0x4 << 14)
386#define RC_FLAGS_RXBM_SAF (0x6 << 14)
387#define RC_FLAGS_RXBM_POS (0x6 << 14)
388#define RC_FLAGS_BFPS (0x1 << 17)
389
390#define RC_FLAGS_BFPS_BFP (0x1 << 17)
391
392#define RC_FLAGS_BFPS_BFP0 (0x0 << 17)
393#define RC_FLAGS_BFPS_BFP1 (0x1 << 17)
394#define RC_FLAGS_BFPS_BFP2 (0x2 << 17)
395#define RC_FLAGS_BFPS_BFP3 (0x3 << 17)
396#define RC_FLAGS_BFPS_BFP4 (0x4 << 17)
397#define RC_FLAGS_BFPS_BFP5 (0x5 << 17)
398#define RC_FLAGS_BFPS_BFP6 (0x6 << 17)
399#define RC_FLAGS_BFPS_BFP7 (0x7 << 17)
400#define RC_FLAGS_BFPS_BFP01 (0x8 << 17)
401#define RC_FLAGS_BFPS_BFP23 (0x9 << 17)
402#define RC_FLAGS_BFPS_BFP45 (0xa << 17)
403#define RC_FLAGS_BFPS_BFP67 (0xb << 17)
404#define RC_FLAGS_BFPS_BFP07 (0xc << 17)
405#define RC_FLAGS_BFPS_BFP27 (0xd << 17)
406#define RC_FLAGS_BFPS_BFP47 (0xe << 17)
407
408#define RC_FLAGS_BFPP (0x1 << 21)
409#define RC_FLAGS_TEVC (0x1 << 22)
410#define RC_FLAGS_TEP (0x1 << 23)
411#define RC_FLAGS_AAL5 (0x0 << 24)
412#define RC_FLAGS_TRANSP (0x1 << 24)
413#define RC_FLAGS_TRANSC (0x2 << 24)
414#define RC_FLAGS_ML (0x1 << 27)
415#define RC_FLAGS_TRBRM (0x1 << 28)
416#define RC_FLAGS_PRI (0x1 << 29)
417#define RC_FLAGS_HOAM (0x1 << 30)
418#define RC_FLAGS_CRC10 (0x1 << 31)
419
420
421#define RAC 0x1c8
422#define RAM 0x1c4
423
424
425
426/************************************************************************
427 * Then the datastructures that the DRIVER uses. *
428 ************************************************************************/
429
430#define TXQ_NENTRIES 32
431#define RXRQ_NENTRIES 1024
432
433
434struct fs_vcc {
435 int channo;
436 wait_queue_head_t close_wait;
437 struct sk_buff *last_skb;
438};
439
440
441struct queue {
442 struct FS_QENTRY *sa, *ea;
443 int offset;
444};
445
446struct freepool {
447 int offset;
448 int bufsize;
449 int nr_buffers;
450 int n;
451};
452
453
454struct fs_dev {
455 struct fs_dev *next; /* other FS devices */
456 int flags;
457
458 unsigned char irq; /* IRQ */
459 struct pci_dev *pci_dev; /* PCI stuff */
460 struct atm_dev *atm_dev;
461 struct timer_list timer;
462
463 unsigned long hw_base; /* mem base address */
464 void __iomem *base; /* Mapping of base address */
465 int channo;
466 unsigned long channel_mask;
467
468 struct queue hp_txq, lp_txq, tx_relq, st_q;
469 struct freepool rx_fp[FS_NR_FREE_POOLS];
470 struct queue rx_rq[FS_NR_RX_QUEUES];
471
472 int nchannels;
473 struct atm_vcc **atm_vccs;
474 void *tx_inuse;
475 int ntxpckts;
476};
477
478
479
480
481/* Number of channesl that the FS50 supports. */
482#define FS50_CHANNEL_BITS 5
483#define FS50_NR_CHANNELS (1 << FS50_CHANNEL_BITS)
484
485
486#define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
487#define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
488
489
490#define FS_IS50 0x1
491#define FS_IS155 0x2
492
493#define IS_FS50(dev) (dev->flags & FS_IS50)
494#define IS_FS155(dev) (dev->flags & FS_IS155)
495
496/* Within limits this is user-configurable. */
497/* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */
498#define FS155_VPI_BITS 4
499#define FS155_VCI_BITS 6
500
501#define FS155_CHANNEL_BITS (FS155_VPI_BITS + FS155_VCI_BITS)
502#define FS155_NR_CHANNELS (1 << FS155_CHANNEL_BITS)
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/* drivers/atm/firestream.h - FireStream 155 (MB86697) and
3 * FireStream 50 (MB86695) device driver
4 */
5
6/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
7 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
8 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
9 */
10
11/*
12*/
13
14
15/***********************************************************************
16 * first the defines for the chip. *
17 ***********************************************************************/
18
19
20/********************* General chip parameters. ************************/
21
22#define FS_NR_FREE_POOLS 8
23#define FS_NR_RX_QUEUES 4
24
25
26/********************* queues and queue access macros ******************/
27
28
29/* A queue entry. */
30struct FS_QENTRY {
31 u32 cmd;
32 u32 p0, p1, p2;
33};
34
35
36/* A freepool entry. */
37struct FS_BPENTRY {
38 u32 flags;
39 u32 next;
40 u32 bsa;
41 u32 aal_bufsize;
42
43 /* The hardware doesn't look at this, but we need the SKB somewhere... */
44 struct sk_buff *skb;
45 struct freepool *fp;
46 struct fs_dev *dev;
47};
48
49
50#define STATUS_CODE(qe) ((qe->cmd >> 22) & 0x3f)
51
52
53/* OFFSETS against the base of a QUEUE... */
54#define QSA 0x00
55#define QEA 0x04
56#define QRP 0x08
57#define QWP 0x0c
58#define QCNF 0x10 /* Only for Release queues! */
59/* Not for the transmit pending queue. */
60
61
62/* OFFSETS against the base of a FREE POOL... */
63#define FPCNF 0x00
64#define FPSA 0x04
65#define FPEA 0x08
66#define FPCNT 0x0c
67#define FPCTU 0x10
68
69#define Q_SA(b) (b + QSA )
70#define Q_EA(b) (b + QEA )
71#define Q_RP(b) (b + QRP )
72#define Q_WP(b) (b + QWP )
73#define Q_CNF(b) (b + QCNF)
74
75#define FP_CNF(b) (b + FPCNF)
76#define FP_SA(b) (b + FPSA)
77#define FP_EA(b) (b + FPEA)
78#define FP_CNT(b) (b + FPCNT)
79#define FP_CTU(b) (b + FPCTU)
80
81/* bits in a queue register. */
82#define Q_FULL 0x1
83#define Q_EMPTY 0x2
84#define Q_INCWRAP 0x4
85#define Q_ADDR_MASK 0xfffffff0
86
87/* bits in a FreePool config register */
88#define RBFP_RBS (0x1 << 16)
89#define RBFP_RBSVAL (0x1 << 15)
90#define RBFP_CME (0x1 << 12)
91#define RBFP_DLP (0x1 << 11)
92#define RBFP_BFPWT (0x1 << 0)
93
94
95
96
97/* FireStream commands. */
98#define QE_CMD_NULL (0x00 << 22)
99#define QE_CMD_REG_RD (0x01 << 22)
100#define QE_CMD_REG_RDM (0x02 << 22)
101#define QE_CMD_REG_WR (0x03 << 22)
102#define QE_CMD_REG_WRM (0x04 << 22)
103#define QE_CMD_CONFIG_TX (0x05 << 22)
104#define QE_CMD_CONFIG_RX (0x06 << 22)
105#define QE_CMD_PRP_RD (0x07 << 22)
106#define QE_CMD_PRP_RDM (0x2a << 22)
107#define QE_CMD_PRP_WR (0x09 << 22)
108#define QE_CMD_PRP_WRM (0x2b << 22)
109#define QE_CMD_RX_EN (0x0a << 22)
110#define QE_CMD_RX_PURGE (0x0b << 22)
111#define QE_CMD_RX_PURGE_INH (0x0c << 22)
112#define QE_CMD_TX_EN (0x0d << 22)
113#define QE_CMD_TX_PURGE (0x0e << 22)
114#define QE_CMD_TX_PURGE_INH (0x0f << 22)
115#define QE_CMD_RST_CG (0x10 << 22)
116#define QE_CMD_SET_CG (0x11 << 22)
117#define QE_CMD_RST_CLP (0x12 << 22)
118#define QE_CMD_SET_CLP (0x13 << 22)
119#define QE_CMD_OVERRIDE (0x14 << 22)
120#define QE_CMD_ADD_BFP (0x15 << 22)
121#define QE_CMD_DUMP_TX (0x16 << 22)
122#define QE_CMD_DUMP_RX (0x17 << 22)
123#define QE_CMD_LRAM_RD (0x18 << 22)
124#define QE_CMD_LRAM_RDM (0x28 << 22)
125#define QE_CMD_LRAM_WR (0x19 << 22)
126#define QE_CMD_LRAM_WRM (0x29 << 22)
127#define QE_CMD_LRAM_BSET (0x1a << 22)
128#define QE_CMD_LRAM_BCLR (0x1b << 22)
129#define QE_CMD_CONFIG_SEGM (0x1c << 22)
130#define QE_CMD_READ_SEGM (0x1d << 22)
131#define QE_CMD_CONFIG_ROUT (0x1e << 22)
132#define QE_CMD_READ_ROUT (0x1f << 22)
133#define QE_CMD_CONFIG_TM (0x20 << 22)
134#define QE_CMD_READ_TM (0x21 << 22)
135#define QE_CMD_CONFIG_TXBM (0x22 << 22)
136#define QE_CMD_READ_TXBM (0x23 << 22)
137#define QE_CMD_CONFIG_RXBM (0x24 << 22)
138#define QE_CMD_READ_RXBM (0x25 << 22)
139#define QE_CMD_CONFIG_REAS (0x26 << 22)
140#define QE_CMD_READ_REAS (0x27 << 22)
141
142#define QE_TRANSMIT_DE (0x0 << 30)
143#define QE_CMD_LINKED (0x1 << 30)
144#define QE_CMD_IMM (0x2 << 30)
145#define QE_CMD_IMM_INQ (0x3 << 30)
146
147#define TD_EPI (0x1 << 27)
148#define TD_COMMAND (0x1 << 28)
149
150#define TD_DATA (0x0 << 29)
151#define TD_RM_CELL (0x1 << 29)
152#define TD_OAM_CELL (0x2 << 29)
153#define TD_OAM_CELL_SEGMENT (0x3 << 29)
154
155#define TD_BPI (0x1 << 20)
156
157#define FP_FLAGS_EPI (0x1 << 27)
158
159
160#define TX_PQ(i) (0x00 + (i) * 0x10)
161#define TXB_RQ (0x20)
162#define ST_Q (0x48)
163#define RXB_FP(i) (0x90 + (i) * 0x14)
164#define RXB_RQ(i) (0x134 + (i) * 0x14)
165
166
167#define TXQ_HP 0
168#define TXQ_LP 1
169
170/* Phew. You don't want to know how many revisions these simple queue
171 * address macros went through before I got them nice and compact as
172 * they are now. -- REW
173 */
174
175
176/* And now for something completely different:
177 * The rest of the registers... */
178
179
180#define CMDR0 0x34
181#define CMDR1 0x38
182#define CMDR2 0x3c
183#define CMDR3 0x40
184
185
186#define SARMODE0 0x5c
187
188#define SARMODE0_TXVCS_0 (0x0 << 0)
189#define SARMODE0_TXVCS_1k (0x1 << 0)
190#define SARMODE0_TXVCS_2k (0x2 << 0)
191#define SARMODE0_TXVCS_4k (0x3 << 0)
192#define SARMODE0_TXVCS_8k (0x4 << 0)
193#define SARMODE0_TXVCS_16k (0x5 << 0)
194#define SARMODE0_TXVCS_32k (0x6 << 0)
195#define SARMODE0_TXVCS_64k (0x7 << 0)
196#define SARMODE0_TXVCS_32 (0x8 << 0)
197
198#define SARMODE0_ABRVCS_0 (0x0 << 4)
199#define SARMODE0_ABRVCS_512 (0x1 << 4)
200#define SARMODE0_ABRVCS_1k (0x2 << 4)
201#define SARMODE0_ABRVCS_2k (0x3 << 4)
202#define SARMODE0_ABRVCS_4k (0x4 << 4)
203#define SARMODE0_ABRVCS_8k (0x5 << 4)
204#define SARMODE0_ABRVCS_16k (0x6 << 4)
205#define SARMODE0_ABRVCS_32k (0x7 << 4)
206#define SARMODE0_ABRVCS_32 (0x9 << 4) /* The others are "8", this one really has to
207 be 9. Tell me you don't believe me. -- REW */
208
209#define SARMODE0_RXVCS_0 (0x0 << 8)
210#define SARMODE0_RXVCS_1k (0x1 << 8)
211#define SARMODE0_RXVCS_2k (0x2 << 8)
212#define SARMODE0_RXVCS_4k (0x3 << 8)
213#define SARMODE0_RXVCS_8k (0x4 << 8)
214#define SARMODE0_RXVCS_16k (0x5 << 8)
215#define SARMODE0_RXVCS_32k (0x6 << 8)
216#define SARMODE0_RXVCS_64k (0x7 << 8)
217#define SARMODE0_RXVCS_32 (0x8 << 8)
218
219#define SARMODE0_CALSUP_1 (0x0 << 12)
220#define SARMODE0_CALSUP_2 (0x1 << 12)
221#define SARMODE0_CALSUP_3 (0x2 << 12)
222#define SARMODE0_CALSUP_4 (0x3 << 12)
223
224#define SARMODE0_PRPWT_FS50_0 (0x0 << 14)
225#define SARMODE0_PRPWT_FS50_2 (0x1 << 14)
226#define SARMODE0_PRPWT_FS50_5 (0x2 << 14)
227#define SARMODE0_PRPWT_FS50_11 (0x3 << 14)
228
229#define SARMODE0_PRPWT_FS155_0 (0x0 << 14)
230#define SARMODE0_PRPWT_FS155_1 (0x1 << 14)
231#define SARMODE0_PRPWT_FS155_2 (0x2 << 14)
232#define SARMODE0_PRPWT_FS155_3 (0x3 << 14)
233
234#define SARMODE0_SRTS0 (0x1 << 23)
235#define SARMODE0_SRTS1 (0x1 << 24)
236
237#define SARMODE0_RUN (0x1 << 25)
238
239#define SARMODE0_UNLOCK (0x1 << 26)
240#define SARMODE0_CWRE (0x1 << 27)
241
242
243#define SARMODE0_INTMODE_READCLEAR (0x0 << 28)
244#define SARMODE0_INTMODE_READNOCLEAR (0x1 << 28)
245#define SARMODE0_INTMODE_READNOCLEARINHIBIT (0x2 << 28)
246#define SARMODE0_INTMODE_READCLEARINHIBIT (0x3 << 28) /* Tell me you don't believe me. */
247
248#define SARMODE0_GINT (0x1 << 30)
249#define SARMODE0_SHADEN (0x1 << 31)
250
251
252#define SARMODE1 0x60
253
254
255#define SARMODE1_TRTL_SHIFT 0 /* Program to 0 */
256#define SARMODE1_RRTL_SHIFT 4 /* Program to 0 */
257
258#define SARMODE1_TAGM (0x1 << 8) /* Program to 0 */
259
260#define SARMODE1_HECM0 (0x1 << 9)
261#define SARMODE1_HECM1 (0x1 << 10)
262#define SARMODE1_HECM2 (0x1 << 11)
263
264#define SARMODE1_GFCE (0x1 << 14)
265#define SARMODE1_GFCR (0x1 << 15)
266#define SARMODE1_PMS (0x1 << 18)
267#define SARMODE1_GPRI (0x1 << 19)
268#define SARMODE1_GPAS (0x1 << 20)
269#define SARMODE1_GVAS (0x1 << 21)
270#define SARMODE1_GNAM (0x1 << 22)
271#define SARMODE1_GPLEN (0x1 << 23)
272#define SARMODE1_DUMPE (0x1 << 24)
273#define SARMODE1_OAMCRC (0x1 << 25)
274#define SARMODE1_DCOAM (0x1 << 26)
275#define SARMODE1_DCRM (0x1 << 27)
276#define SARMODE1_TSTLP (0x1 << 28)
277#define SARMODE1_DEFHEC (0x1 << 29)
278
279
280#define ISR 0x64
281#define IUSR 0x68
282#define IMR 0x6c
283
284#define ISR_LPCO (0x1 << 0)
285#define ISR_DPCO (0x1 << 1)
286#define ISR_RBRQ0_W (0x1 << 2)
287#define ISR_RBRQ1_W (0x1 << 3)
288#define ISR_RBRQ2_W (0x1 << 4)
289#define ISR_RBRQ3_W (0x1 << 5)
290#define ISR_RBRQ0_NF (0x1 << 6)
291#define ISR_RBRQ1_NF (0x1 << 7)
292#define ISR_RBRQ2_NF (0x1 << 8)
293#define ISR_RBRQ3_NF (0x1 << 9)
294#define ISR_BFP_SC (0x1 << 10)
295#define ISR_INIT (0x1 << 11)
296#define ISR_INIT_ERR (0x1 << 12) /* Documented as "reserved" */
297#define ISR_USCEO (0x1 << 13)
298#define ISR_UPEC0 (0x1 << 14)
299#define ISR_VPFCO (0x1 << 15)
300#define ISR_CRCCO (0x1 << 16)
301#define ISR_HECO (0x1 << 17)
302#define ISR_TBRQ_W (0x1 << 18)
303#define ISR_TBRQ_NF (0x1 << 19)
304#define ISR_CTPQ_E (0x1 << 20)
305#define ISR_GFC_C0 (0x1 << 21)
306#define ISR_PCI_FTL (0x1 << 22)
307#define ISR_CSQ_W (0x1 << 23)
308#define ISR_CSQ_NF (0x1 << 24)
309#define ISR_EXT_INT (0x1 << 25)
310#define ISR_RXDMA_S (0x1 << 26)
311
312
313#define TMCONF 0x78
314/* Bits? */
315
316
317#define CALPRESCALE 0x7c
318/* Bits? */
319
320#define CELLOSCONF 0x84
321#define CELLOSCONF_COTS (0x1 << 28)
322#define CELLOSCONF_CEN (0x1 << 27)
323#define CELLOSCONF_SC8 (0x3 << 24)
324#define CELLOSCONF_SC4 (0x2 << 24)
325#define CELLOSCONF_SC2 (0x1 << 24)
326#define CELLOSCONF_SC1 (0x0 << 24)
327
328#define CELLOSCONF_COBS (0x1 << 16)
329#define CELLOSCONF_COPK (0x1 << 8)
330#define CELLOSCONF_COST (0x1 << 0)
331/* Bits? */
332
333#define RAS0 0x1bc
334#define RAS0_DCD_XHLT (0x1 << 31)
335
336#define RAS0_VPSEL (0x1 << 16)
337#define RAS0_VCSEL (0x1 << 0)
338
339#define RAS1 0x1c0
340#define RAS1_UTREG (0x1 << 5)
341
342
343#define DMAMR 0x1cc
344#define DMAMR_TX_MODE_FULL (0x0 << 0)
345#define DMAMR_TX_MODE_PART (0x1 << 0)
346#define DMAMR_TX_MODE_NONE (0x2 << 0) /* And 3 */
347
348
349
350#define RAS2 0x280
351
352#define RAS2_NNI (0x1 << 0)
353#define RAS2_USEL (0x1 << 1)
354#define RAS2_UBS (0x1 << 2)
355
356
357
358struct fs_transmit_config {
359 u32 flags;
360 u32 atm_hdr;
361 u32 TMC[4];
362 u32 spec;
363 u32 rtag[3];
364};
365
366#define TC_FLAGS_AAL5 (0x0 << 29)
367#define TC_FLAGS_TRANSPARENT_PAYLOAD (0x1 << 29)
368#define TC_FLAGS_TRANSPARENT_CELL (0x2 << 29)
369#define TC_FLAGS_STREAMING (0x1 << 28)
370#define TC_FLAGS_PACKET (0x0)
371#define TC_FLAGS_TYPE_ABR (0x0 << 22)
372#define TC_FLAGS_TYPE_CBR (0x1 << 22)
373#define TC_FLAGS_TYPE_VBR (0x2 << 22)
374#define TC_FLAGS_TYPE_UBR (0x3 << 22)
375#define TC_FLAGS_CAL0 (0x0 << 20)
376#define TC_FLAGS_CAL1 (0x1 << 20)
377#define TC_FLAGS_CAL2 (0x2 << 20)
378#define TC_FLAGS_CAL3 (0x3 << 20)
379
380
381#define RC_FLAGS_NAM (0x1 << 13)
382#define RC_FLAGS_RXBM_PSB (0x0 << 14)
383#define RC_FLAGS_RXBM_CIF (0x1 << 14)
384#define RC_FLAGS_RXBM_PMB (0x2 << 14)
385#define RC_FLAGS_RXBM_STR (0x4 << 14)
386#define RC_FLAGS_RXBM_SAF (0x6 << 14)
387#define RC_FLAGS_RXBM_POS (0x6 << 14)
388#define RC_FLAGS_BFPS (0x1 << 17)
389
390#define RC_FLAGS_BFPS_BFP (0x1 << 17)
391
392#define RC_FLAGS_BFPS_BFP0 (0x0 << 17)
393#define RC_FLAGS_BFPS_BFP1 (0x1 << 17)
394#define RC_FLAGS_BFPS_BFP2 (0x2 << 17)
395#define RC_FLAGS_BFPS_BFP3 (0x3 << 17)
396#define RC_FLAGS_BFPS_BFP4 (0x4 << 17)
397#define RC_FLAGS_BFPS_BFP5 (0x5 << 17)
398#define RC_FLAGS_BFPS_BFP6 (0x6 << 17)
399#define RC_FLAGS_BFPS_BFP7 (0x7 << 17)
400#define RC_FLAGS_BFPS_BFP01 (0x8 << 17)
401#define RC_FLAGS_BFPS_BFP23 (0x9 << 17)
402#define RC_FLAGS_BFPS_BFP45 (0xa << 17)
403#define RC_FLAGS_BFPS_BFP67 (0xb << 17)
404#define RC_FLAGS_BFPS_BFP07 (0xc << 17)
405#define RC_FLAGS_BFPS_BFP27 (0xd << 17)
406#define RC_FLAGS_BFPS_BFP47 (0xe << 17)
407
408#define RC_FLAGS_BFPP (0x1 << 21)
409#define RC_FLAGS_TEVC (0x1 << 22)
410#define RC_FLAGS_TEP (0x1 << 23)
411#define RC_FLAGS_AAL5 (0x0 << 24)
412#define RC_FLAGS_TRANSP (0x1 << 24)
413#define RC_FLAGS_TRANSC (0x2 << 24)
414#define RC_FLAGS_ML (0x1 << 27)
415#define RC_FLAGS_TRBRM (0x1 << 28)
416#define RC_FLAGS_PRI (0x1 << 29)
417#define RC_FLAGS_HOAM (0x1 << 30)
418#define RC_FLAGS_CRC10 (0x1 << 31)
419
420
421#define RAC 0x1c8
422#define RAM 0x1c4
423
424
425
426/************************************************************************
427 * Then the datastructures that the DRIVER uses. *
428 ************************************************************************/
429
430#define TXQ_NENTRIES 32
431#define RXRQ_NENTRIES 1024
432
433
434struct fs_vcc {
435 int channo;
436 wait_queue_head_t close_wait;
437 struct sk_buff *last_skb;
438};
439
440
441struct queue {
442 struct FS_QENTRY *sa, *ea;
443 int offset;
444};
445
446struct freepool {
447 int offset;
448 int bufsize;
449 int nr_buffers;
450 int n;
451};
452
453
454struct fs_dev {
455 struct fs_dev *next; /* other FS devices */
456 int flags;
457
458 unsigned char irq; /* IRQ */
459 struct pci_dev *pci_dev; /* PCI stuff */
460 struct atm_dev *atm_dev;
461 struct timer_list timer;
462
463 unsigned long hw_base; /* mem base address */
464 void __iomem *base; /* Mapping of base address */
465 int channo;
466 unsigned long channel_mask;
467
468 struct queue hp_txq, lp_txq, tx_relq, st_q;
469 struct freepool rx_fp[FS_NR_FREE_POOLS];
470 struct queue rx_rq[FS_NR_RX_QUEUES];
471
472 int nchannels;
473 struct atm_vcc **atm_vccs;
474 void *tx_inuse;
475 int ntxpckts;
476};
477
478
479
480
481/* Number of channesl that the FS50 supports. */
482#define FS50_CHANNEL_BITS 5
483#define FS50_NR_CHANNELS (1 << FS50_CHANNEL_BITS)
484
485
486#define FS_DEV(atm_dev) ((struct fs_dev *) (atm_dev)->dev_data)
487#define FS_VCC(atm_vcc) ((struct fs_vcc *) (atm_vcc)->dev_data)
488
489
490#define FS_IS50 0x1
491#define FS_IS155 0x2
492
493#define IS_FS50(dev) (dev->flags & FS_IS50)
494#define IS_FS155(dev) (dev->flags & FS_IS155)
495
496/* Within limits this is user-configurable. */
497/* Note: Currently the sum (10 -> 1k channels) is hardcoded in the driver. */
498#define FS155_VPI_BITS 4
499#define FS155_VCI_BITS 6
500
501#define FS155_CHANNEL_BITS (FS155_VPI_BITS + FS155_VCI_BITS)
502#define FS155_NR_CHANNELS (1 << FS155_CHANNEL_BITS)