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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
4 *
5 * Description: CoreSight Program Flow Trace driver
6 */
7
8#include <linux/kernel.h>
9#include <linux/moduleparam.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/fs.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/smp.h>
19#include <linux/sysfs.h>
20#include <linux/stat.h>
21#include <linux/pm_runtime.h>
22#include <linux/cpu.h>
23#include <linux/of.h>
24#include <linux/coresight.h>
25#include <linux/coresight-pmu.h>
26#include <linux/amba/bus.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29#include <linux/clk.h>
30#include <linux/perf_event.h>
31#include <asm/sections.h>
32
33#include "coresight-etm.h"
34#include "coresight-etm-perf.h"
35
36/*
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
39 */
40static int boot_enable;
41module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42
43static struct etm_drvdata *etmdrvdata[NR_CPUS];
44
45static enum cpuhp_state hp_online;
46
47/*
48 * Memory mapped writes to clear os lock are not supported on some processors
49 * and OS lock must be unlocked before any memory mapped access on such
50 * processors, otherwise memory mapped reads/writes will be invalid.
51 */
52static void etm_os_unlock(struct etm_drvdata *drvdata)
53{
54 /* Writing any value to ETMOSLAR unlocks the trace registers */
55 etm_writel(drvdata, 0x0, ETMOSLAR);
56 drvdata->os_unlock = true;
57 isb();
58}
59
60static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
61{
62 u32 etmcr;
63
64 /* Ensure pending cp14 accesses complete before setting pwrdwn */
65 mb();
66 isb();
67 etmcr = etm_readl(drvdata, ETMCR);
68 etmcr |= ETMCR_PWD_DWN;
69 etm_writel(drvdata, etmcr, ETMCR);
70}
71
72static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
73{
74 u32 etmcr;
75
76 etmcr = etm_readl(drvdata, ETMCR);
77 etmcr &= ~ETMCR_PWD_DWN;
78 etm_writel(drvdata, etmcr, ETMCR);
79 /* Ensure pwrup completes before subsequent cp14 accesses */
80 mb();
81 isb();
82}
83
84static void etm_set_pwrup(struct etm_drvdata *drvdata)
85{
86 u32 etmpdcr;
87
88 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
89 etmpdcr |= ETMPDCR_PWD_UP;
90 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
91 /* Ensure pwrup completes before subsequent cp14 accesses */
92 mb();
93 isb();
94}
95
96static void etm_clr_pwrup(struct etm_drvdata *drvdata)
97{
98 u32 etmpdcr;
99
100 /* Ensure pending cp14 accesses complete before clearing pwrup */
101 mb();
102 isb();
103 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
104 etmpdcr &= ~ETMPDCR_PWD_UP;
105 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
106}
107
108/**
109 * coresight_timeout_etm - loop until a bit has changed to a specific state.
110 * @drvdata: etm's private data structure.
111 * @offset: address of a register, starting from @addr.
112 * @position: the position of the bit of interest.
113 * @value: the value the bit should have.
114 *
115 * Basically the same as @coresight_timeout except for the register access
116 * method where we have to account for CP14 configurations.
117
118 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
119 * TIMEOUT_US has elapsed, which ever happens first.
120 */
121
122static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
123 int position, int value)
124{
125 int i;
126 u32 val;
127
128 for (i = TIMEOUT_US; i > 0; i--) {
129 val = etm_readl(drvdata, offset);
130 /* Waiting on the bit to go from 0 to 1 */
131 if (value) {
132 if (val & BIT(position))
133 return 0;
134 /* Waiting on the bit to go from 1 to 0 */
135 } else {
136 if (!(val & BIT(position)))
137 return 0;
138 }
139
140 /*
141 * Delay is arbitrary - the specification doesn't say how long
142 * we are expected to wait. Extra check required to make sure
143 * we don't wait needlessly on the last iteration.
144 */
145 if (i - 1)
146 udelay(1);
147 }
148
149 return -EAGAIN;
150}
151
152
153static void etm_set_prog(struct etm_drvdata *drvdata)
154{
155 u32 etmcr;
156
157 etmcr = etm_readl(drvdata, ETMCR);
158 etmcr |= ETMCR_ETM_PRG;
159 etm_writel(drvdata, etmcr, ETMCR);
160 /*
161 * Recommended by spec for cp14 accesses to ensure etmcr write is
162 * complete before polling etmsr
163 */
164 isb();
165 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
166 dev_err(&drvdata->csdev->dev,
167 "%s: timeout observed when probing at offset %#x\n",
168 __func__, ETMSR);
169 }
170}
171
172static void etm_clr_prog(struct etm_drvdata *drvdata)
173{
174 u32 etmcr;
175
176 etmcr = etm_readl(drvdata, ETMCR);
177 etmcr &= ~ETMCR_ETM_PRG;
178 etm_writel(drvdata, etmcr, ETMCR);
179 /*
180 * Recommended by spec for cp14 accesses to ensure etmcr write is
181 * complete before polling etmsr
182 */
183 isb();
184 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
185 dev_err(&drvdata->csdev->dev,
186 "%s: timeout observed when probing at offset %#x\n",
187 __func__, ETMSR);
188 }
189}
190
191void etm_set_default(struct etm_config *config)
192{
193 int i;
194
195 if (WARN_ON_ONCE(!config))
196 return;
197
198 /*
199 * Taken verbatim from the TRM:
200 *
201 * To trace all memory:
202 * set bit [24] in register 0x009, the ETMTECR1, to 1
203 * set all other bits in register 0x009, the ETMTECR1, to 0
204 * set all bits in register 0x007, the ETMTECR2, to 0
205 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
206 */
207 config->enable_ctrl1 = BIT(24);
208 config->enable_ctrl2 = 0x0;
209 config->enable_event = ETM_HARD_WIRE_RES_A;
210
211 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
212 config->enable_event = ETM_HARD_WIRE_RES_A;
213
214 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
215 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
220 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
221
222 for (i = 0; i < ETM_MAX_CNTR; i++) {
223 config->cntr_rld_val[i] = 0x0;
224 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
225 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
226 config->cntr_val[i] = 0x0;
227 }
228
229 config->seq_curr_state = 0x0;
230 config->ctxid_idx = 0x0;
231 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
232 config->ctxid_pid[i] = 0x0;
233
234 config->ctxid_mask = 0x0;
235 /* Setting default to 1024 as per TRM recommendation */
236 config->sync_freq = 0x400;
237}
238
239void etm_config_trace_mode(struct etm_config *config)
240{
241 u32 flags, mode;
242
243 mode = config->mode;
244
245 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
246
247 /* excluding kernel AND user space doesn't make sense */
248 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
249 return;
250
251 /* nothing to do if neither flags are set */
252 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
253 return;
254
255 flags = (1 << 0 | /* instruction execute */
256 3 << 3 | /* ARM instruction */
257 0 << 5 | /* No data value comparison */
258 0 << 7 | /* No exact mach */
259 0 << 8); /* Ignore context ID */
260
261 /* No need to worry about single address comparators. */
262 config->enable_ctrl2 = 0x0;
263
264 /* Bit 0 is address range comparator 1 */
265 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
266
267 /*
268 * On ETMv3.5:
269 * ETMACTRn[13,11] == Non-secure state comparison control
270 * ETMACTRn[12,10] == Secure state comparison control
271 *
272 * b00 == Match in all modes in this state
273 * b01 == Do not match in any more in this state
274 * b10 == Match in all modes excepts user mode in this state
275 * b11 == Match only in user mode in this state
276 */
277
278 /* Tracing in secure mode is not supported at this time */
279 flags |= (0 << 12 | 1 << 10);
280
281 if (mode & ETM_MODE_EXCL_USER) {
282 /* exclude user, match all modes except user mode */
283 flags |= (1 << 13 | 0 << 11);
284 } else {
285 /* exclude kernel, match only in user mode */
286 flags |= (1 << 13 | 1 << 11);
287 }
288
289 /*
290 * The ETMEEVR register is already set to "hard wire A". As such
291 * all there is to do is setup an address comparator that spans
292 * the entire address range and configure the state and mode bits.
293 */
294 config->addr_val[0] = (u32) 0x0;
295 config->addr_val[1] = (u32) ~0x0;
296 config->addr_acctype[0] = flags;
297 config->addr_acctype[1] = flags;
298 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
299 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
300}
301
302#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
303 ETMCR_TIMESTAMP_EN | \
304 ETMCR_RETURN_STACK)
305
306static int etm_parse_event_config(struct etm_drvdata *drvdata,
307 struct perf_event *event)
308{
309 struct etm_config *config = &drvdata->config;
310 struct perf_event_attr *attr = &event->attr;
311
312 if (!attr)
313 return -EINVAL;
314
315 /* Clear configuration from previous run */
316 memset(config, 0, sizeof(struct etm_config));
317
318 if (attr->exclude_kernel)
319 config->mode = ETM_MODE_EXCL_KERN;
320
321 if (attr->exclude_user)
322 config->mode = ETM_MODE_EXCL_USER;
323
324 /* Always start from the default config */
325 etm_set_default(config);
326
327 /*
328 * By default the tracers are configured to trace the whole address
329 * range. Narrow the field only if requested by user space.
330 */
331 if (config->mode)
332 etm_config_trace_mode(config);
333
334 /*
335 * At this time only cycle accurate, return stack and timestamp
336 * options are available.
337 */
338 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
339 return -EINVAL;
340
341 config->ctrl = attr->config;
342
343 /*
344 * Possible to have cores with PTM (supports ret stack) and ETM
345 * (never has ret stack) on the same SoC. So if we have a request
346 * for return stack that can't be honoured on this core then
347 * clear the bit - trace will still continue normally
348 */
349 if ((config->ctrl & ETMCR_RETURN_STACK) &&
350 !(drvdata->etmccer & ETMCCER_RETSTACK))
351 config->ctrl &= ~ETMCR_RETURN_STACK;
352
353 return 0;
354}
355
356static int etm_enable_hw(struct etm_drvdata *drvdata)
357{
358 int i, rc;
359 u32 etmcr;
360 struct etm_config *config = &drvdata->config;
361 struct coresight_device *csdev = drvdata->csdev;
362
363 CS_UNLOCK(drvdata->base);
364
365 rc = coresight_claim_device_unlocked(csdev);
366 if (rc)
367 goto done;
368
369 /* Turn engine on */
370 etm_clr_pwrdwn(drvdata);
371 /* Apply power to trace registers */
372 etm_set_pwrup(drvdata);
373 /* Make sure all registers are accessible */
374 etm_os_unlock(drvdata);
375
376 etm_set_prog(drvdata);
377
378 etmcr = etm_readl(drvdata, ETMCR);
379 /* Clear setting from a previous run if need be */
380 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
381 etmcr |= drvdata->port_size;
382 etmcr |= ETMCR_ETM_EN;
383 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
384 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
385 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
386 etm_writel(drvdata, config->enable_event, ETMTEEVR);
387 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
388 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
389 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
390 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
391 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
392 }
393 for (i = 0; i < drvdata->nr_cntr; i++) {
394 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
395 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
396 etm_writel(drvdata, config->cntr_rld_event[i],
397 ETMCNTRLDEVRn(i));
398 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
399 }
400 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
401 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
402 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
403 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
404 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
405 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
406 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
407 for (i = 0; i < drvdata->nr_ext_out; i++)
408 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
409 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
410 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
411 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
412 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
413 /* No external input selected */
414 etm_writel(drvdata, 0x0, ETMEXTINSELR);
415 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
416 /* No auxiliary control selected */
417 etm_writel(drvdata, 0x0, ETMAUXCR);
418 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
419 /* No VMID comparator value selected */
420 etm_writel(drvdata, 0x0, ETMVMIDCVR);
421
422 etm_clr_prog(drvdata);
423
424done:
425 CS_LOCK(drvdata->base);
426
427 dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
428 drvdata->cpu, rc);
429 return rc;
430}
431
432struct etm_enable_arg {
433 struct etm_drvdata *drvdata;
434 int rc;
435};
436
437static void etm_enable_hw_smp_call(void *info)
438{
439 struct etm_enable_arg *arg = info;
440
441 if (WARN_ON(!arg))
442 return;
443 arg->rc = etm_enable_hw(arg->drvdata);
444}
445
446static int etm_cpu_id(struct coresight_device *csdev)
447{
448 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
449
450 return drvdata->cpu;
451}
452
453int etm_get_trace_id(struct etm_drvdata *drvdata)
454{
455 unsigned long flags;
456 int trace_id = -1;
457 struct device *etm_dev;
458
459 if (!drvdata)
460 goto out;
461
462 etm_dev = drvdata->csdev->dev.parent;
463 if (!local_read(&drvdata->mode))
464 return drvdata->traceid;
465
466 pm_runtime_get_sync(etm_dev);
467
468 spin_lock_irqsave(&drvdata->spinlock, flags);
469
470 CS_UNLOCK(drvdata->base);
471 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
472 CS_LOCK(drvdata->base);
473
474 spin_unlock_irqrestore(&drvdata->spinlock, flags);
475 pm_runtime_put(etm_dev);
476
477out:
478 return trace_id;
479
480}
481
482static int etm_trace_id(struct coresight_device *csdev)
483{
484 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
485
486 return etm_get_trace_id(drvdata);
487}
488
489static int etm_enable_perf(struct coresight_device *csdev,
490 struct perf_event *event)
491{
492 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
493
494 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
495 return -EINVAL;
496
497 /* Configure the tracer based on the session's specifics */
498 etm_parse_event_config(drvdata, event);
499 /* And enable it */
500 return etm_enable_hw(drvdata);
501}
502
503static int etm_enable_sysfs(struct coresight_device *csdev)
504{
505 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
506 struct etm_enable_arg arg = { };
507 int ret;
508
509 spin_lock(&drvdata->spinlock);
510
511 /*
512 * Configure the ETM only if the CPU is online. If it isn't online
513 * hw configuration will take place on the local CPU during bring up.
514 */
515 if (cpu_online(drvdata->cpu)) {
516 arg.drvdata = drvdata;
517 ret = smp_call_function_single(drvdata->cpu,
518 etm_enable_hw_smp_call, &arg, 1);
519 if (!ret)
520 ret = arg.rc;
521 if (!ret)
522 drvdata->sticky_enable = true;
523 } else {
524 ret = -ENODEV;
525 }
526
527 spin_unlock(&drvdata->spinlock);
528
529 if (!ret)
530 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
531 return ret;
532}
533
534static int etm_enable(struct coresight_device *csdev,
535 struct perf_event *event, u32 mode)
536{
537 int ret;
538 u32 val;
539 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
540
541 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
542
543 /* Someone is already using the tracer */
544 if (val)
545 return -EBUSY;
546
547 switch (mode) {
548 case CS_MODE_SYSFS:
549 ret = etm_enable_sysfs(csdev);
550 break;
551 case CS_MODE_PERF:
552 ret = etm_enable_perf(csdev, event);
553 break;
554 default:
555 ret = -EINVAL;
556 }
557
558 /* The tracer didn't start */
559 if (ret)
560 local_set(&drvdata->mode, CS_MODE_DISABLED);
561
562 return ret;
563}
564
565static void etm_disable_hw(void *info)
566{
567 int i;
568 struct etm_drvdata *drvdata = info;
569 struct etm_config *config = &drvdata->config;
570 struct coresight_device *csdev = drvdata->csdev;
571
572 CS_UNLOCK(drvdata->base);
573 etm_set_prog(drvdata);
574
575 /* Read back sequencer and counters for post trace analysis */
576 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
577
578 for (i = 0; i < drvdata->nr_cntr; i++)
579 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
580
581 etm_set_pwrdwn(drvdata);
582 coresight_disclaim_device_unlocked(csdev);
583
584 CS_LOCK(drvdata->base);
585
586 dev_dbg(&drvdata->csdev->dev,
587 "cpu: %d disable smp call done\n", drvdata->cpu);
588}
589
590static void etm_disable_perf(struct coresight_device *csdev)
591{
592 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
593
594 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
595 return;
596
597 CS_UNLOCK(drvdata->base);
598
599 /* Setting the prog bit disables tracing immediately */
600 etm_set_prog(drvdata);
601
602 /*
603 * There is no way to know when the tracer will be used again so
604 * power down the tracer.
605 */
606 etm_set_pwrdwn(drvdata);
607 coresight_disclaim_device_unlocked(csdev);
608
609 CS_LOCK(drvdata->base);
610}
611
612static void etm_disable_sysfs(struct coresight_device *csdev)
613{
614 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
615
616 /*
617 * Taking hotplug lock here protects from clocks getting disabled
618 * with tracing being left on (crash scenario) if user disable occurs
619 * after cpu online mask indicates the cpu is offline but before the
620 * DYING hotplug callback is serviced by the ETM driver.
621 */
622 cpus_read_lock();
623 spin_lock(&drvdata->spinlock);
624
625 /*
626 * Executing etm_disable_hw on the cpu whose ETM is being disabled
627 * ensures that register writes occur when cpu is powered.
628 */
629 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
630
631 spin_unlock(&drvdata->spinlock);
632 cpus_read_unlock();
633
634 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
635}
636
637static void etm_disable(struct coresight_device *csdev,
638 struct perf_event *event)
639{
640 u32 mode;
641 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
642
643 /*
644 * For as long as the tracer isn't disabled another entity can't
645 * change its status. As such we can read the status here without
646 * fearing it will change under us.
647 */
648 mode = local_read(&drvdata->mode);
649
650 switch (mode) {
651 case CS_MODE_DISABLED:
652 break;
653 case CS_MODE_SYSFS:
654 etm_disable_sysfs(csdev);
655 break;
656 case CS_MODE_PERF:
657 etm_disable_perf(csdev);
658 break;
659 default:
660 WARN_ON_ONCE(mode);
661 return;
662 }
663
664 if (mode)
665 local_set(&drvdata->mode, CS_MODE_DISABLED);
666}
667
668static const struct coresight_ops_source etm_source_ops = {
669 .cpu_id = etm_cpu_id,
670 .trace_id = etm_trace_id,
671 .enable = etm_enable,
672 .disable = etm_disable,
673};
674
675static const struct coresight_ops etm_cs_ops = {
676 .source_ops = &etm_source_ops,
677};
678
679static int etm_online_cpu(unsigned int cpu)
680{
681 if (!etmdrvdata[cpu])
682 return 0;
683
684 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
685 coresight_enable(etmdrvdata[cpu]->csdev);
686 return 0;
687}
688
689static int etm_starting_cpu(unsigned int cpu)
690{
691 if (!etmdrvdata[cpu])
692 return 0;
693
694 spin_lock(&etmdrvdata[cpu]->spinlock);
695 if (!etmdrvdata[cpu]->os_unlock) {
696 etm_os_unlock(etmdrvdata[cpu]);
697 etmdrvdata[cpu]->os_unlock = true;
698 }
699
700 if (local_read(&etmdrvdata[cpu]->mode))
701 etm_enable_hw(etmdrvdata[cpu]);
702 spin_unlock(&etmdrvdata[cpu]->spinlock);
703 return 0;
704}
705
706static int etm_dying_cpu(unsigned int cpu)
707{
708 if (!etmdrvdata[cpu])
709 return 0;
710
711 spin_lock(&etmdrvdata[cpu]->spinlock);
712 if (local_read(&etmdrvdata[cpu]->mode))
713 etm_disable_hw(etmdrvdata[cpu]);
714 spin_unlock(&etmdrvdata[cpu]->spinlock);
715 return 0;
716}
717
718static bool etm_arch_supported(u8 arch)
719{
720 switch (arch) {
721 case ETM_ARCH_V3_3:
722 break;
723 case ETM_ARCH_V3_5:
724 break;
725 case PFT_ARCH_V1_0:
726 break;
727 case PFT_ARCH_V1_1:
728 break;
729 default:
730 return false;
731 }
732 return true;
733}
734
735static void etm_init_arch_data(void *info)
736{
737 u32 etmidr;
738 u32 etmccr;
739 struct etm_drvdata *drvdata = info;
740
741 /* Make sure all registers are accessible */
742 etm_os_unlock(drvdata);
743
744 CS_UNLOCK(drvdata->base);
745
746 /* First dummy read */
747 (void)etm_readl(drvdata, ETMPDSR);
748 /* Provide power to ETM: ETMPDCR[3] == 1 */
749 etm_set_pwrup(drvdata);
750 /*
751 * Clear power down bit since when this bit is set writes to
752 * certain registers might be ignored.
753 */
754 etm_clr_pwrdwn(drvdata);
755 /*
756 * Set prog bit. It will be set from reset but this is included to
757 * ensure it is set
758 */
759 etm_set_prog(drvdata);
760
761 /* Find all capabilities */
762 etmidr = etm_readl(drvdata, ETMIDR);
763 drvdata->arch = BMVAL(etmidr, 4, 11);
764 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
765
766 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
767 etmccr = etm_readl(drvdata, ETMCCR);
768 drvdata->etmccr = etmccr;
769 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
770 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
771 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
772 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
773 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
774
775 etm_set_pwrdwn(drvdata);
776 etm_clr_pwrup(drvdata);
777 CS_LOCK(drvdata->base);
778}
779
780static void etm_init_trace_id(struct etm_drvdata *drvdata)
781{
782 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
783}
784
785static int __init etm_hp_setup(void)
786{
787 int ret;
788
789 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
790 "arm/coresight:starting",
791 etm_starting_cpu, etm_dying_cpu);
792
793 if (ret)
794 return ret;
795
796 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
797 "arm/coresight:online",
798 etm_online_cpu, NULL);
799
800 /* HP dyn state ID returned in ret on success */
801 if (ret > 0) {
802 hp_online = ret;
803 return 0;
804 }
805
806 /* failed dyn state - remove others */
807 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
808
809 return ret;
810}
811
812static void etm_hp_clear(void)
813{
814 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
815 if (hp_online) {
816 cpuhp_remove_state_nocalls(hp_online);
817 hp_online = 0;
818 }
819}
820
821static int etm_probe(struct amba_device *adev, const struct amba_id *id)
822{
823 int ret;
824 void __iomem *base;
825 struct device *dev = &adev->dev;
826 struct coresight_platform_data *pdata = NULL;
827 struct etm_drvdata *drvdata;
828 struct resource *res = &adev->res;
829 struct coresight_desc desc = { 0 };
830
831 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
832 if (!drvdata)
833 return -ENOMEM;
834
835 drvdata->use_cp14 = fwnode_property_read_bool(dev->fwnode, "arm,cp14");
836 dev_set_drvdata(dev, drvdata);
837
838 /* Validity for the resource is already checked by the AMBA core */
839 base = devm_ioremap_resource(dev, res);
840 if (IS_ERR(base))
841 return PTR_ERR(base);
842
843 drvdata->base = base;
844 desc.access = CSDEV_ACCESS_IOMEM(base);
845
846 spin_lock_init(&drvdata->spinlock);
847
848 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
849 if (!IS_ERR(drvdata->atclk)) {
850 ret = clk_prepare_enable(drvdata->atclk);
851 if (ret)
852 return ret;
853 }
854
855 drvdata->cpu = coresight_get_cpu(dev);
856 if (drvdata->cpu < 0)
857 return drvdata->cpu;
858
859 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
860 if (!desc.name)
861 return -ENOMEM;
862
863 if (smp_call_function_single(drvdata->cpu,
864 etm_init_arch_data, drvdata, 1))
865 dev_err(dev, "ETM arch init failed\n");
866
867 if (etm_arch_supported(drvdata->arch) == false)
868 return -EINVAL;
869
870 etm_init_trace_id(drvdata);
871 etm_set_default(&drvdata->config);
872
873 pdata = coresight_get_platform_data(dev);
874 if (IS_ERR(pdata))
875 return PTR_ERR(pdata);
876
877 adev->dev.platform_data = pdata;
878
879 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
880 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
881 desc.ops = &etm_cs_ops;
882 desc.pdata = pdata;
883 desc.dev = dev;
884 desc.groups = coresight_etm_groups;
885 drvdata->csdev = coresight_register(&desc);
886 if (IS_ERR(drvdata->csdev))
887 return PTR_ERR(drvdata->csdev);
888
889 ret = etm_perf_symlink(drvdata->csdev, true);
890 if (ret) {
891 coresight_unregister(drvdata->csdev);
892 return ret;
893 }
894
895 etmdrvdata[drvdata->cpu] = drvdata;
896
897 pm_runtime_put(&adev->dev);
898 dev_info(&drvdata->csdev->dev,
899 "%s initialized\n", (char *)coresight_get_uci_data(id));
900 if (boot_enable) {
901 coresight_enable(drvdata->csdev);
902 drvdata->boot_enable = true;
903 }
904
905 return 0;
906}
907
908static void clear_etmdrvdata(void *info)
909{
910 int cpu = *(int *)info;
911
912 etmdrvdata[cpu] = NULL;
913}
914
915static void etm_remove(struct amba_device *adev)
916{
917 struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
918
919 etm_perf_symlink(drvdata->csdev, false);
920
921 /*
922 * Taking hotplug lock here to avoid racing between etm_remove and
923 * CPU hotplug call backs.
924 */
925 cpus_read_lock();
926 /*
927 * The readers for etmdrvdata[] are CPU hotplug call backs
928 * and PM notification call backs. Change etmdrvdata[i] on
929 * CPU i ensures these call backs has consistent view
930 * inside one call back function.
931 */
932 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
933 etmdrvdata[drvdata->cpu] = NULL;
934
935 cpus_read_unlock();
936
937 coresight_unregister(drvdata->csdev);
938}
939
940#ifdef CONFIG_PM
941static int etm_runtime_suspend(struct device *dev)
942{
943 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
944
945 if (drvdata && !IS_ERR(drvdata->atclk))
946 clk_disable_unprepare(drvdata->atclk);
947
948 return 0;
949}
950
951static int etm_runtime_resume(struct device *dev)
952{
953 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
954
955 if (drvdata && !IS_ERR(drvdata->atclk))
956 clk_prepare_enable(drvdata->atclk);
957
958 return 0;
959}
960#endif
961
962static const struct dev_pm_ops etm_dev_pm_ops = {
963 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
964};
965
966static const struct amba_id etm_ids[] = {
967 /* ETM 3.3 */
968 CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"),
969 /* ETM 3.5 - Cortex-A5 */
970 CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"),
971 /* ETM 3.5 */
972 CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"),
973 /* PTM 1.0 */
974 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"),
975 /* PTM 1.1 */
976 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"),
977 /* PTM 1.1 Qualcomm */
978 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
979 { 0, 0},
980};
981
982MODULE_DEVICE_TABLE(amba, etm_ids);
983
984static struct amba_driver etm_driver = {
985 .drv = {
986 .name = "coresight-etm3x",
987 .owner = THIS_MODULE,
988 .pm = &etm_dev_pm_ops,
989 .suppress_bind_attrs = true,
990 },
991 .probe = etm_probe,
992 .remove = etm_remove,
993 .id_table = etm_ids,
994};
995
996static int __init etm_init(void)
997{
998 int ret;
999
1000 ret = etm_hp_setup();
1001
1002 /* etm_hp_setup() does its own cleanup - exit on error */
1003 if (ret)
1004 return ret;
1005
1006 ret = amba_driver_register(&etm_driver);
1007 if (ret) {
1008 pr_err("Error registering etm3x driver\n");
1009 etm_hp_clear();
1010 }
1011
1012 return ret;
1013}
1014
1015static void __exit etm_exit(void)
1016{
1017 amba_driver_unregister(&etm_driver);
1018 etm_hp_clear();
1019}
1020
1021module_init(etm_init);
1022module_exit(etm_exit);
1023
1024MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1025MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1026MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver");
1027MODULE_LICENSE("GPL v2");