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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX8 NWL MIPI DSI host driver
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2020 Purism SPC
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/math64.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/mux/consumer.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/phy/phy.h>
19#include <linux/regmap.h>
20#include <linux/reset.h>
21#include <linux/sys_soc.h>
22#include <linux/time64.h>
23
24#include <drm/drm_bridge.h>
25#include <drm/drm_mipi_dsi.h>
26#include <drm/drm_of.h>
27#include <drm/drm_panel.h>
28#include <drm/drm_print.h>
29
30#include <video/mipi_display.h>
31
32#include "nwl-dsi.h"
33
34#define DRV_NAME "nwl-dsi"
35
36/* i.MX8 NWL quirks */
37/* i.MX8MQ errata E11418 */
38#define E11418_HS_MODE_QUIRK BIT(0)
39
40#define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
41
42enum transfer_direction {
43 DSI_PACKET_SEND,
44 DSI_PACKET_RECEIVE,
45};
46
47#define NWL_DSI_ENDPOINT_LCDIF 0
48#define NWL_DSI_ENDPOINT_DCSS 1
49
50struct nwl_dsi_plat_clk_config {
51 const char *id;
52 struct clk *clk;
53 bool present;
54};
55
56struct nwl_dsi_transfer {
57 const struct mipi_dsi_msg *msg;
58 struct mipi_dsi_packet packet;
59 struct completion completed;
60
61 int status; /* status of transmission */
62 enum transfer_direction direction;
63 bool need_bta;
64 u8 cmd;
65 u16 rx_word_count;
66 size_t tx_len; /* in bytes */
67 size_t rx_len; /* in bytes */
68};
69
70struct nwl_dsi {
71 struct drm_bridge bridge;
72 struct mipi_dsi_host dsi_host;
73 struct drm_bridge *panel_bridge;
74 struct device *dev;
75 struct phy *phy;
76 union phy_configure_opts phy_cfg;
77 unsigned int quirks;
78
79 struct regmap *regmap;
80 int irq;
81 /*
82 * The DSI host controller needs this reset sequence according to NWL:
83 * 1. Deassert pclk reset to get access to DSI regs
84 * 2. Configure DSI Host and DPHY and enable DPHY
85 * 3. Deassert ESC and BYTE resets to allow host TX operations)
86 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
87 * 5. Deassert DPI reset so DPI receives pixels and starts sending
88 * DSI data
89 *
90 * TODO: Since panel_bridges do their DSI setup in enable we
91 * currently have 4. and 5. swapped.
92 */
93 struct reset_control *rst_byte;
94 struct reset_control *rst_esc;
95 struct reset_control *rst_dpi;
96 struct reset_control *rst_pclk;
97 struct mux_control *mux;
98
99 /* DSI clocks */
100 struct clk *phy_ref_clk;
101 struct clk *rx_esc_clk;
102 struct clk *tx_esc_clk;
103 struct clk *core_clk;
104 /*
105 * hardware bug: the i.MX8MQ needs this clock on during reset
106 * even when not using LCDIF.
107 */
108 struct clk *lcdif_clk;
109
110 /* dsi lanes */
111 u32 lanes;
112 enum mipi_dsi_pixel_format format;
113 struct drm_display_mode mode;
114 unsigned long dsi_mode_flags;
115 int error;
116
117 struct nwl_dsi_transfer *xfer;
118};
119
120static const struct regmap_config nwl_dsi_regmap_config = {
121 .reg_bits = 16,
122 .val_bits = 32,
123 .reg_stride = 4,
124 .max_register = NWL_DSI_IRQ_MASK2,
125 .name = DRV_NAME,
126};
127
128static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
129{
130 return container_of(bridge, struct nwl_dsi, bridge);
131}
132
133static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
134{
135 int ret = dsi->error;
136
137 dsi->error = 0;
138 return ret;
139}
140
141static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
142{
143 int ret;
144
145 if (dsi->error)
146 return;
147
148 ret = regmap_write(dsi->regmap, reg, val);
149 if (ret < 0) {
150 DRM_DEV_ERROR(dsi->dev,
151 "Failed to write NWL DSI reg 0x%x: %d\n", reg,
152 ret);
153 dsi->error = ret;
154 }
155}
156
157static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
158{
159 unsigned int val;
160 int ret;
161
162 if (dsi->error)
163 return 0;
164
165 ret = regmap_read(dsi->regmap, reg, &val);
166 if (ret < 0) {
167 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
168 reg, ret);
169 dsi->error = ret;
170 }
171 return val;
172}
173
174static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
175{
176 switch (format) {
177 case MIPI_DSI_FMT_RGB565:
178 return NWL_DSI_PIXEL_FORMAT_16;
179 case MIPI_DSI_FMT_RGB666:
180 return NWL_DSI_PIXEL_FORMAT_18L;
181 case MIPI_DSI_FMT_RGB666_PACKED:
182 return NWL_DSI_PIXEL_FORMAT_18;
183 case MIPI_DSI_FMT_RGB888:
184 return NWL_DSI_PIXEL_FORMAT_24;
185 default:
186 return -EINVAL;
187 }
188}
189
190/*
191 * ps2bc - Picoseconds to byte clock cycles
192 */
193static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
194{
195 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
196
197 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
198 dsi->lanes * 8 * NSEC_PER_SEC);
199}
200
201/*
202 * ui2bc - UI time periods to byte clock cycles
203 */
204static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
205{
206 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
207
208 return DIV64_U64_ROUND_UP(ui * dsi->lanes,
209 dsi->mode.clock * 1000 * bpp);
210}
211
212/*
213 * us2bc - micro seconds to lp clock cycles
214 */
215static u32 us2lp(u32 lp_clk_rate, unsigned long us)
216{
217 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
218}
219
220static int nwl_dsi_config_host(struct nwl_dsi *dsi)
221{
222 u32 cycles;
223 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
224
225 if (dsi->lanes < 1 || dsi->lanes > 4)
226 return -EINVAL;
227
228 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
229 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
230
231 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
232 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
233 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
234 } else {
235 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
236 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
237 }
238
239 /* values in byte clock cycles */
240 cycles = ui2bc(dsi, cfg->clk_pre);
241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
242 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
243 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
244 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
245 cycles += ui2bc(dsi, cfg->clk_pre);
246 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
247 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
248 cycles = ps2bc(dsi, cfg->hs_exit);
249 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
250 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
251
252 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
253 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
254 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
255 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
256 /* In LP clock cycles */
257 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
258 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
259 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
260
261 return nwl_dsi_clear_error(dsi);
262}
263
264static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
265{
266 u32 mode;
267 int color_format;
268 bool burst_mode;
269 int hfront_porch, hback_porch, vfront_porch, vback_porch;
270 int hsync_len, vsync_len;
271
272 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
273 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
274 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
275
276 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
277 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
278 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
279
280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
289
290 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
291 if (color_format < 0) {
292 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
293 dsi->format);
294 return color_format;
295 }
296 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
297
298 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
299 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
300 /*
301 * Adjusting input polarity based on the video mode results in
302 * a black screen so always pick active low:
303 */
304 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
305 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
306 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
307 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
308
309 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
310 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
311
312 if (burst_mode) {
313 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
314 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
315 } else {
316 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
317 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
318 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
319 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
320 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
321 dsi->mode.hdisplay);
322 }
323
324 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
325 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
326 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
327
328 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
329 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
330 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
331 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
332
333 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
334 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
335 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
336 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
337
338 return nwl_dsi_clear_error(dsi);
339}
340
341static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
342{
343 u32 irq_enable;
344
345 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
346 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
347
348 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
349 NWL_DSI_RX_PKT_HDR_RCVD_MASK |
350 NWL_DSI_TX_FIFO_OVFLW_MASK |
351 NWL_DSI_HS_TX_TIMEOUT_MASK);
352
353 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
354
355 return nwl_dsi_clear_error(dsi);
356}
357
358static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
359 struct mipi_dsi_device *device)
360{
361 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
362 struct device *dev = dsi->dev;
363
364 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
365 device->format, device->mode_flags);
366
367 if (device->lanes < 1 || device->lanes > 4)
368 return -EINVAL;
369
370 dsi->lanes = device->lanes;
371 dsi->format = device->format;
372 dsi->dsi_mode_flags = device->mode_flags;
373
374 return 0;
375}
376
377static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
378{
379 struct device *dev = dsi->dev;
380 struct nwl_dsi_transfer *xfer = dsi->xfer;
381 int err;
382 u8 *payload = xfer->msg->rx_buf;
383 u32 val;
384 u16 word_count;
385 u8 channel;
386 u8 data_type;
387
388 xfer->status = 0;
389
390 if (xfer->rx_word_count == 0) {
391 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
392 return false;
393 /* Get the RX header and parse it */
394 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
395 err = nwl_dsi_clear_error(dsi);
396 if (err)
397 xfer->status = err;
398 word_count = NWL_DSI_WC(val);
399 channel = NWL_DSI_RX_VC(val);
400 data_type = NWL_DSI_RX_DT(val);
401
402 if (channel != xfer->msg->channel) {
403 DRM_DEV_ERROR(dev,
404 "[%02X] Channel mismatch (%u != %u)\n",
405 xfer->cmd, channel, xfer->msg->channel);
406 xfer->status = -EINVAL;
407 return true;
408 }
409
410 switch (data_type) {
411 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
412 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
413 if (xfer->msg->rx_len > 1) {
414 /* read second byte */
415 payload[1] = word_count >> 8;
416 ++xfer->rx_len;
417 }
418 fallthrough;
419 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
420 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
421 if (xfer->msg->rx_len > 0) {
422 /* read first byte */
423 payload[0] = word_count & 0xff;
424 ++xfer->rx_len;
425 }
426 xfer->status = xfer->rx_len;
427 return true;
428 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
429 word_count &= 0xff;
430 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
431 xfer->cmd, word_count);
432 xfer->status = -EPROTO;
433 return true;
434 }
435
436 if (word_count > xfer->msg->rx_len) {
437 DRM_DEV_ERROR(dev,
438 "[%02X] Receive buffer too small: %zu (< %u)\n",
439 xfer->cmd, xfer->msg->rx_len, word_count);
440 xfer->status = -EINVAL;
441 return true;
442 }
443
444 xfer->rx_word_count = word_count;
445 } else {
446 /* Set word_count from previous header read */
447 word_count = xfer->rx_word_count;
448 }
449
450 /* If RX payload is not yet received, wait for it */
451 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
452 return false;
453
454 /* Read the RX payload */
455 while (word_count >= 4) {
456 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
457 payload[0] = (val >> 0) & 0xff;
458 payload[1] = (val >> 8) & 0xff;
459 payload[2] = (val >> 16) & 0xff;
460 payload[3] = (val >> 24) & 0xff;
461 payload += 4;
462 xfer->rx_len += 4;
463 word_count -= 4;
464 }
465
466 if (word_count > 0) {
467 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
468 switch (word_count) {
469 case 3:
470 payload[2] = (val >> 16) & 0xff;
471 ++xfer->rx_len;
472 fallthrough;
473 case 2:
474 payload[1] = (val >> 8) & 0xff;
475 ++xfer->rx_len;
476 fallthrough;
477 case 1:
478 payload[0] = (val >> 0) & 0xff;
479 ++xfer->rx_len;
480 break;
481 }
482 }
483
484 xfer->status = xfer->rx_len;
485 err = nwl_dsi_clear_error(dsi);
486 if (err)
487 xfer->status = err;
488
489 return true;
490}
491
492static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
493{
494 struct nwl_dsi_transfer *xfer = dsi->xfer;
495 bool end_packet = false;
496
497 if (!xfer)
498 return;
499
500 if (xfer->direction == DSI_PACKET_SEND &&
501 status & NWL_DSI_TX_PKT_DONE) {
502 xfer->status = xfer->tx_len;
503 end_packet = true;
504 } else if (status & NWL_DSI_DPHY_DIRECTION &&
505 ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
506 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
507 end_packet = nwl_dsi_read_packet(dsi, status);
508 }
509
510 if (end_packet)
511 complete(&xfer->completed);
512}
513
514static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
515{
516 struct nwl_dsi_transfer *xfer = dsi->xfer;
517 struct mipi_dsi_packet *pkt = &xfer->packet;
518 const u8 *payload;
519 size_t length;
520 u16 word_count;
521 u8 hs_mode;
522 u32 val;
523 u32 hs_workaround = 0;
524
525 /* Send the payload, if any */
526 length = pkt->payload_length;
527 payload = pkt->payload;
528
529 while (length >= 4) {
530 val = *(u32 *)payload;
531 hs_workaround |= !(val & 0xFFFF00);
532 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
533 payload += 4;
534 length -= 4;
535 }
536 /* Send the rest of the payload */
537 val = 0;
538 switch (length) {
539 case 3:
540 val |= payload[2] << 16;
541 fallthrough;
542 case 2:
543 val |= payload[1] << 8;
544 hs_workaround |= !(val & 0xFFFF00);
545 fallthrough;
546 case 1:
547 val |= payload[0];
548 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
549 break;
550 }
551 xfer->tx_len = pkt->payload_length;
552
553 /*
554 * Send the header
555 * header[0] = Virtual Channel + Data Type
556 * header[1] = Word Count LSB (LP) or first param (SP)
557 * header[2] = Word Count MSB (LP) or second param (SP)
558 */
559 word_count = pkt->header[1] | (pkt->header[2] << 8);
560 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
561 DRM_DEV_DEBUG_DRIVER(dsi->dev,
562 "Using hs mode workaround for cmd 0x%x\n",
563 xfer->cmd);
564 hs_mode = 1;
565 } else {
566 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
567 }
568 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
569 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
570 NWL_DSI_BTA_TX(xfer->need_bta);
571 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
572
573 /* Send packet command */
574 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
575}
576
577static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
578 const struct mipi_dsi_msg *msg)
579{
580 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
581 struct nwl_dsi_transfer xfer;
582 ssize_t ret = 0;
583
584 /* Create packet to be sent */
585 dsi->xfer = &xfer;
586 ret = mipi_dsi_create_packet(&xfer.packet, msg);
587 if (ret < 0) {
588 dsi->xfer = NULL;
589 return ret;
590 }
591
592 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
593 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
594 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
595 msg->type & MIPI_DSI_DCS_READ) &&
596 msg->rx_len > 0 && msg->rx_buf)
597 xfer.direction = DSI_PACKET_RECEIVE;
598 else
599 xfer.direction = DSI_PACKET_SEND;
600
601 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
602 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
603 xfer.msg = msg;
604 xfer.status = -ETIMEDOUT;
605 xfer.rx_word_count = 0;
606 xfer.rx_len = 0;
607 xfer.cmd = 0x00;
608 if (msg->tx_len > 0)
609 xfer.cmd = ((u8 *)(msg->tx_buf))[0];
610 init_completion(&xfer.completed);
611
612 ret = clk_prepare_enable(dsi->rx_esc_clk);
613 if (ret < 0) {
614 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
615 ret);
616 return ret;
617 }
618 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
619 clk_get_rate(dsi->rx_esc_clk));
620
621 /* Initiate the DSI packet transmision */
622 nwl_dsi_begin_transmission(dsi);
623
624 if (!wait_for_completion_timeout(&xfer.completed,
625 NWL_DSI_MIPI_FIFO_TIMEOUT)) {
626 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
627 xfer.cmd);
628 ret = -ETIMEDOUT;
629 } else {
630 ret = xfer.status;
631 }
632
633 clk_disable_unprepare(dsi->rx_esc_clk);
634
635 return ret;
636}
637
638static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
639 .attach = nwl_dsi_host_attach,
640 .transfer = nwl_dsi_host_transfer,
641};
642
643static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
644{
645 u32 irq_status;
646 struct nwl_dsi *dsi = data;
647
648 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
649
650 if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
651 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
652
653 if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
654 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
655
656 if (irq_status & NWL_DSI_TX_PKT_DONE ||
657 irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
658 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
659 nwl_dsi_finish_transmission(dsi, irq_status);
660
661 return IRQ_HANDLED;
662}
663
664static int nwl_dsi_enable(struct nwl_dsi *dsi)
665{
666 struct device *dev = dsi->dev;
667 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
668 int ret;
669
670 if (!dsi->lanes) {
671 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
672 return -EINVAL;
673 }
674
675 ret = phy_init(dsi->phy);
676 if (ret < 0) {
677 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
678 return ret;
679 }
680
681 ret = phy_configure(dsi->phy, phy_cfg);
682 if (ret < 0) {
683 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
684 goto uninit_phy;
685 }
686
687 ret = clk_prepare_enable(dsi->tx_esc_clk);
688 if (ret < 0) {
689 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
690 ret);
691 goto uninit_phy;
692 }
693 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
694 clk_get_rate(dsi->tx_esc_clk));
695
696 ret = nwl_dsi_config_host(dsi);
697 if (ret < 0) {
698 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
699 goto disable_clock;
700 }
701
702 ret = nwl_dsi_config_dpi(dsi);
703 if (ret < 0) {
704 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
705 goto disable_clock;
706 }
707
708 ret = phy_power_on(dsi->phy);
709 if (ret < 0) {
710 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
711 goto disable_clock;
712 }
713
714 ret = nwl_dsi_init_interrupts(dsi);
715 if (ret < 0)
716 goto power_off_phy;
717
718 return ret;
719
720power_off_phy:
721 phy_power_off(dsi->phy);
722disable_clock:
723 clk_disable_unprepare(dsi->tx_esc_clk);
724uninit_phy:
725 phy_exit(dsi->phy);
726
727 return ret;
728}
729
730static int nwl_dsi_disable(struct nwl_dsi *dsi)
731{
732 struct device *dev = dsi->dev;
733
734 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
735
736 phy_power_off(dsi->phy);
737 phy_exit(dsi->phy);
738
739 /* Disabling the clock before the phy breaks enabling dsi again */
740 clk_disable_unprepare(dsi->tx_esc_clk);
741
742 return 0;
743}
744
745static void nwl_dsi_bridge_disable(struct drm_bridge *bridge)
746{
747 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
748 int ret;
749
750 nwl_dsi_disable(dsi);
751
752 ret = reset_control_assert(dsi->rst_dpi);
753 if (ret < 0) {
754 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
755 return;
756 }
757 ret = reset_control_assert(dsi->rst_byte);
758 if (ret < 0) {
759 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
760 return;
761 }
762 ret = reset_control_assert(dsi->rst_esc);
763 if (ret < 0) {
764 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
765 return;
766 }
767 ret = reset_control_assert(dsi->rst_pclk);
768 if (ret < 0) {
769 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
770 return;
771 }
772
773 clk_disable_unprepare(dsi->core_clk);
774 clk_disable_unprepare(dsi->lcdif_clk);
775
776 pm_runtime_put(dsi->dev);
777}
778
779static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
780 const struct drm_display_mode *mode,
781 union phy_configure_opts *phy_opts)
782{
783 unsigned long rate;
784 int ret;
785
786 if (dsi->lanes < 1 || dsi->lanes > 4)
787 return -EINVAL;
788
789 /*
790 * So far the DPHY spec minimal timings work for both mixel
791 * dphy and nwl dsi host
792 */
793 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
794 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
795 &phy_opts->mipi_dphy);
796 if (ret < 0)
797 return ret;
798
799 rate = clk_get_rate(dsi->tx_esc_clk);
800 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
801 phy_opts->mipi_dphy.lp_clk_rate = rate;
802
803 return 0;
804}
805
806static bool nwl_dsi_bridge_mode_fixup(struct drm_bridge *bridge,
807 const struct drm_display_mode *mode,
808 struct drm_display_mode *adjusted_mode)
809{
810 /* At least LCDIF + NWL needs active high sync */
811 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
812 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
813
814 return true;
815}
816
817static enum drm_mode_status
818nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
819 const struct drm_display_info *info,
820 const struct drm_display_mode *mode)
821{
822 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
823 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
824
825 if (mode->clock * bpp > 15000000 * dsi->lanes)
826 return MODE_CLOCK_HIGH;
827
828 if (mode->clock * bpp < 80000 * dsi->lanes)
829 return MODE_CLOCK_LOW;
830
831 return MODE_OK;
832}
833
834static void
835nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
836 const struct drm_display_mode *mode,
837 const struct drm_display_mode *adjusted_mode)
838{
839 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
840 struct device *dev = dsi->dev;
841 union phy_configure_opts new_cfg;
842 unsigned long phy_ref_rate;
843 int ret;
844
845 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
846 if (ret < 0)
847 return;
848
849 /*
850 * If hs clock is unchanged, we're all good - all parameters are
851 * derived from it atm.
852 */
853 if (new_cfg.mipi_dphy.hs_clk_rate == dsi->phy_cfg.mipi_dphy.hs_clk_rate)
854 return;
855
856 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
857 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
858 /* Save the new desired phy config */
859 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
860
861 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
862 drm_mode_debug_printmodeline(adjusted_mode);
863}
864
865static void nwl_dsi_bridge_pre_enable(struct drm_bridge *bridge)
866{
867 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
868 int ret;
869
870 pm_runtime_get_sync(dsi->dev);
871
872 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
873 return;
874 if (clk_prepare_enable(dsi->core_clk) < 0)
875 return;
876
877 /* Step 1 from DSI reset-out instructions */
878 ret = reset_control_deassert(dsi->rst_pclk);
879 if (ret < 0) {
880 DRM_DEV_ERROR(dsi->dev, "Failed to deassert PCLK: %d\n", ret);
881 return;
882 }
883
884 /* Step 2 from DSI reset-out instructions */
885 nwl_dsi_enable(dsi);
886
887 /* Step 3 from DSI reset-out instructions */
888 ret = reset_control_deassert(dsi->rst_esc);
889 if (ret < 0) {
890 DRM_DEV_ERROR(dsi->dev, "Failed to deassert ESC: %d\n", ret);
891 return;
892 }
893 ret = reset_control_deassert(dsi->rst_byte);
894 if (ret < 0) {
895 DRM_DEV_ERROR(dsi->dev, "Failed to deassert BYTE: %d\n", ret);
896 return;
897 }
898}
899
900static void nwl_dsi_bridge_enable(struct drm_bridge *bridge)
901{
902 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
903 int ret;
904
905 /* Step 5 from DSI reset-out instructions */
906 ret = reset_control_deassert(dsi->rst_dpi);
907 if (ret < 0)
908 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
909}
910
911static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
912 enum drm_bridge_attach_flags flags)
913{
914 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
915 struct drm_bridge *panel_bridge;
916 struct drm_panel *panel;
917 int ret;
918
919 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
920 &panel_bridge);
921 if (ret)
922 return ret;
923
924 if (panel) {
925 panel_bridge = drm_panel_bridge_add(panel);
926 if (IS_ERR(panel_bridge))
927 return PTR_ERR(panel_bridge);
928 }
929 dsi->panel_bridge = panel_bridge;
930
931 if (!dsi->panel_bridge)
932 return -EPROBE_DEFER;
933
934 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
935 flags);
936}
937
938static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
939{ struct nwl_dsi *dsi = bridge_to_dsi(bridge);
940
941 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
942}
943
944static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
945 .pre_enable = nwl_dsi_bridge_pre_enable,
946 .enable = nwl_dsi_bridge_enable,
947 .disable = nwl_dsi_bridge_disable,
948 .mode_fixup = nwl_dsi_bridge_mode_fixup,
949 .mode_set = nwl_dsi_bridge_mode_set,
950 .mode_valid = nwl_dsi_bridge_mode_valid,
951 .attach = nwl_dsi_bridge_attach,
952 .detach = nwl_dsi_bridge_detach,
953};
954
955static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
956{
957 struct platform_device *pdev = to_platform_device(dsi->dev);
958 struct clk *clk;
959 void __iomem *base;
960 int ret;
961
962 dsi->phy = devm_phy_get(dsi->dev, "dphy");
963 if (IS_ERR(dsi->phy)) {
964 ret = PTR_ERR(dsi->phy);
965 if (ret != -EPROBE_DEFER)
966 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
967 return ret;
968 }
969
970 clk = devm_clk_get(dsi->dev, "lcdif");
971 if (IS_ERR(clk)) {
972 ret = PTR_ERR(clk);
973 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
974 ret);
975 return ret;
976 }
977 dsi->lcdif_clk = clk;
978
979 clk = devm_clk_get(dsi->dev, "core");
980 if (IS_ERR(clk)) {
981 ret = PTR_ERR(clk);
982 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
983 ret);
984 return ret;
985 }
986 dsi->core_clk = clk;
987
988 clk = devm_clk_get(dsi->dev, "phy_ref");
989 if (IS_ERR(clk)) {
990 ret = PTR_ERR(clk);
991 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
992 ret);
993 return ret;
994 }
995 dsi->phy_ref_clk = clk;
996
997 clk = devm_clk_get(dsi->dev, "rx_esc");
998 if (IS_ERR(clk)) {
999 ret = PTR_ERR(clk);
1000 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1001 ret);
1002 return ret;
1003 }
1004 dsi->rx_esc_clk = clk;
1005
1006 clk = devm_clk_get(dsi->dev, "tx_esc");
1007 if (IS_ERR(clk)) {
1008 ret = PTR_ERR(clk);
1009 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1010 ret);
1011 return ret;
1012 }
1013 dsi->tx_esc_clk = clk;
1014
1015 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1016 if (IS_ERR(dsi->mux)) {
1017 ret = PTR_ERR(dsi->mux);
1018 if (ret != -EPROBE_DEFER)
1019 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1020 return ret;
1021 }
1022
1023 base = devm_platform_ioremap_resource(pdev, 0);
1024 if (IS_ERR(base))
1025 return PTR_ERR(base);
1026
1027 dsi->regmap =
1028 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1029 if (IS_ERR(dsi->regmap)) {
1030 ret = PTR_ERR(dsi->regmap);
1031 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1032 ret);
1033 return ret;
1034 }
1035
1036 dsi->irq = platform_get_irq(pdev, 0);
1037 if (dsi->irq < 0) {
1038 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1039 dsi->irq);
1040 return dsi->irq;
1041 }
1042
1043 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1044 if (IS_ERR(dsi->rst_pclk)) {
1045 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1046 PTR_ERR(dsi->rst_pclk));
1047 return PTR_ERR(dsi->rst_pclk);
1048 }
1049 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1050 if (IS_ERR(dsi->rst_byte)) {
1051 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1052 PTR_ERR(dsi->rst_byte));
1053 return PTR_ERR(dsi->rst_byte);
1054 }
1055 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1056 if (IS_ERR(dsi->rst_esc)) {
1057 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1058 PTR_ERR(dsi->rst_esc));
1059 return PTR_ERR(dsi->rst_esc);
1060 }
1061 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1062 if (IS_ERR(dsi->rst_dpi)) {
1063 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1064 PTR_ERR(dsi->rst_dpi));
1065 return PTR_ERR(dsi->rst_dpi);
1066 }
1067 return 0;
1068}
1069
1070static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1071{
1072 struct device_node *remote;
1073 u32 use_dcss = 1;
1074 int ret;
1075
1076 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1077 NWL_DSI_ENDPOINT_LCDIF);
1078 if (remote) {
1079 use_dcss = 0;
1080 } else {
1081 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1082 NWL_DSI_ENDPOINT_DCSS);
1083 if (!remote) {
1084 DRM_DEV_ERROR(dsi->dev,
1085 "No valid input endpoint found\n");
1086 return -EINVAL;
1087 }
1088 }
1089
1090 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1091 (use_dcss) ? "DCSS" : "LCDIF");
1092 ret = mux_control_try_select(dsi->mux, use_dcss);
1093 if (ret < 0)
1094 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1095
1096 of_node_put(remote);
1097 return ret;
1098}
1099
1100static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1101{
1102 int ret;
1103
1104 ret = mux_control_deselect(dsi->mux);
1105 if (ret < 0)
1106 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1107
1108 return ret;
1109}
1110
1111static const struct drm_bridge_timings nwl_dsi_timings = {
1112 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1113};
1114
1115static const struct of_device_id nwl_dsi_dt_ids[] = {
1116 { .compatible = "fsl,imx8mq-nwl-dsi", },
1117 { /* sentinel */ }
1118};
1119MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
1120
1121static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
1122 { .soc_id = "i.MX8MQ", .revision = "2.0",
1123 .data = (void *)E11418_HS_MODE_QUIRK },
1124 { /* sentinel. */ },
1125};
1126
1127static int nwl_dsi_probe(struct platform_device *pdev)
1128{
1129 struct device *dev = &pdev->dev;
1130 const struct soc_device_attribute *attr;
1131 struct nwl_dsi *dsi;
1132 int ret;
1133
1134 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1135 if (!dsi)
1136 return -ENOMEM;
1137
1138 dsi->dev = dev;
1139
1140 ret = nwl_dsi_parse_dt(dsi);
1141 if (ret)
1142 return ret;
1143
1144 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1145 dev_name(dev), dsi);
1146 if (ret < 0) {
1147 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1148 ret);
1149 return ret;
1150 }
1151
1152 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1153 dsi->dsi_host.dev = dev;
1154 ret = mipi_dsi_host_register(&dsi->dsi_host);
1155 if (ret) {
1156 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1157 return ret;
1158 }
1159
1160 attr = soc_device_match(nwl_dsi_quirks_match);
1161 if (attr)
1162 dsi->quirks = (uintptr_t)attr->data;
1163
1164 dsi->bridge.driver_private = dsi;
1165 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1166 dsi->bridge.of_node = dev->of_node;
1167 dsi->bridge.timings = &nwl_dsi_timings;
1168
1169 dev_set_drvdata(dev, dsi);
1170 pm_runtime_enable(dev);
1171
1172 ret = nwl_dsi_select_input(dsi);
1173 if (ret < 0) {
1174 mipi_dsi_host_unregister(&dsi->dsi_host);
1175 return ret;
1176 }
1177
1178 drm_bridge_add(&dsi->bridge);
1179 return 0;
1180}
1181
1182static int nwl_dsi_remove(struct platform_device *pdev)
1183{
1184 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1185
1186 nwl_dsi_deselect_input(dsi);
1187 mipi_dsi_host_unregister(&dsi->dsi_host);
1188 drm_bridge_remove(&dsi->bridge);
1189 pm_runtime_disable(&pdev->dev);
1190 return 0;
1191}
1192
1193static struct platform_driver nwl_dsi_driver = {
1194 .probe = nwl_dsi_probe,
1195 .remove = nwl_dsi_remove,
1196 .driver = {
1197 .of_match_table = nwl_dsi_dt_ids,
1198 .name = DRV_NAME,
1199 },
1200};
1201
1202module_platform_driver(nwl_dsi_driver);
1203
1204MODULE_AUTHOR("NXP Semiconductor");
1205MODULE_AUTHOR("Purism SPC");
1206MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
1207MODULE_LICENSE("GPL"); /* GPLv2 or later */
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * i.MX8 NWL MIPI DSI host driver
4 *
5 * Copyright (C) 2017 NXP
6 * Copyright (C) 2020 Purism SPC
7 */
8
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/irq.h>
12#include <linux/math64.h>
13#include <linux/mfd/syscon.h>
14#include <linux/module.h>
15#include <linux/mux/consumer.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/phy/phy.h>
19#include <linux/regmap.h>
20#include <linux/reset.h>
21#include <linux/sys_soc.h>
22#include <linux/time64.h>
23
24#include <drm/drm_atomic_state_helper.h>
25#include <drm/drm_bridge.h>
26#include <drm/drm_mipi_dsi.h>
27#include <drm/drm_of.h>
28#include <drm/drm_panel.h>
29#include <drm/drm_print.h>
30
31#include <video/mipi_display.h>
32
33#include "nwl-dsi.h"
34
35#define DRV_NAME "nwl-dsi"
36
37/* i.MX8 NWL quirks */
38/* i.MX8MQ errata E11418 */
39#define E11418_HS_MODE_QUIRK BIT(0)
40
41#define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500)
42
43enum transfer_direction {
44 DSI_PACKET_SEND,
45 DSI_PACKET_RECEIVE,
46};
47
48#define NWL_DSI_ENDPOINT_LCDIF 0
49#define NWL_DSI_ENDPOINT_DCSS 1
50
51struct nwl_dsi_plat_clk_config {
52 const char *id;
53 struct clk *clk;
54 bool present;
55};
56
57struct nwl_dsi_transfer {
58 const struct mipi_dsi_msg *msg;
59 struct mipi_dsi_packet packet;
60 struct completion completed;
61
62 int status; /* status of transmission */
63 enum transfer_direction direction;
64 bool need_bta;
65 u8 cmd;
66 u16 rx_word_count;
67 size_t tx_len; /* in bytes */
68 size_t rx_len; /* in bytes */
69};
70
71struct nwl_dsi {
72 struct drm_bridge bridge;
73 struct mipi_dsi_host dsi_host;
74 struct drm_bridge *panel_bridge;
75 struct device *dev;
76 struct phy *phy;
77 union phy_configure_opts phy_cfg;
78 unsigned int quirks;
79
80 struct regmap *regmap;
81 int irq;
82 /*
83 * The DSI host controller needs this reset sequence according to NWL:
84 * 1. Deassert pclk reset to get access to DSI regs
85 * 2. Configure DSI Host and DPHY and enable DPHY
86 * 3. Deassert ESC and BYTE resets to allow host TX operations)
87 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
88 * 5. Deassert DPI reset so DPI receives pixels and starts sending
89 * DSI data
90 *
91 * TODO: Since panel_bridges do their DSI setup in enable we
92 * currently have 4. and 5. swapped.
93 */
94 struct reset_control *rst_byte;
95 struct reset_control *rst_esc;
96 struct reset_control *rst_dpi;
97 struct reset_control *rst_pclk;
98 struct mux_control *mux;
99
100 /* DSI clocks */
101 struct clk *phy_ref_clk;
102 struct clk *rx_esc_clk;
103 struct clk *tx_esc_clk;
104 struct clk *core_clk;
105 /*
106 * hardware bug: the i.MX8MQ needs this clock on during reset
107 * even when not using LCDIF.
108 */
109 struct clk *lcdif_clk;
110
111 /* dsi lanes */
112 u32 lanes;
113 enum mipi_dsi_pixel_format format;
114 struct drm_display_mode mode;
115 unsigned long dsi_mode_flags;
116 int error;
117
118 struct nwl_dsi_transfer *xfer;
119};
120
121static const struct regmap_config nwl_dsi_regmap_config = {
122 .reg_bits = 16,
123 .val_bits = 32,
124 .reg_stride = 4,
125 .max_register = NWL_DSI_IRQ_MASK2,
126 .name = DRV_NAME,
127};
128
129static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge)
130{
131 return container_of(bridge, struct nwl_dsi, bridge);
132}
133
134static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
135{
136 int ret = dsi->error;
137
138 dsi->error = 0;
139 return ret;
140}
141
142static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
143{
144 int ret;
145
146 if (dsi->error)
147 return;
148
149 ret = regmap_write(dsi->regmap, reg, val);
150 if (ret < 0) {
151 DRM_DEV_ERROR(dsi->dev,
152 "Failed to write NWL DSI reg 0x%x: %d\n", reg,
153 ret);
154 dsi->error = ret;
155 }
156}
157
158static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
159{
160 unsigned int val;
161 int ret;
162
163 if (dsi->error)
164 return 0;
165
166 ret = regmap_read(dsi->regmap, reg, &val);
167 if (ret < 0) {
168 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
169 reg, ret);
170 dsi->error = ret;
171 }
172 return val;
173}
174
175static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format)
176{
177 switch (format) {
178 case MIPI_DSI_FMT_RGB565:
179 return NWL_DSI_PIXEL_FORMAT_16;
180 case MIPI_DSI_FMT_RGB666:
181 return NWL_DSI_PIXEL_FORMAT_18L;
182 case MIPI_DSI_FMT_RGB666_PACKED:
183 return NWL_DSI_PIXEL_FORMAT_18;
184 case MIPI_DSI_FMT_RGB888:
185 return NWL_DSI_PIXEL_FORMAT_24;
186 default:
187 return -EINVAL;
188 }
189}
190
191/*
192 * ps2bc - Picoseconds to byte clock cycles
193 */
194static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
195{
196 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
197
198 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
199 dsi->lanes * 8ULL * NSEC_PER_SEC);
200}
201
202/*
203 * ui2bc - UI time periods to byte clock cycles
204 */
205static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui)
206{
207 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
208
209 return DIV64_U64_ROUND_UP(ui * dsi->lanes,
210 dsi->mode.clock * 1000 * bpp);
211}
212
213/*
214 * us2bc - micro seconds to lp clock cycles
215 */
216static u32 us2lp(u32 lp_clk_rate, unsigned long us)
217{
218 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC);
219}
220
221static int nwl_dsi_config_host(struct nwl_dsi *dsi)
222{
223 u32 cycles;
224 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
225
226 if (dsi->lanes < 1 || dsi->lanes > 4)
227 return -EINVAL;
228
229 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
230 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
231
232 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
233 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
234 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
235 } else {
236 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
237 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
238 }
239
240 /* values in byte clock cycles */
241 cycles = ui2bc(dsi, cfg->clk_pre);
242 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
243 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
244 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
245 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
246 cycles += ui2bc(dsi, cfg->clk_pre);
247 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
248 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
249 cycles = ps2bc(dsi, cfg->hs_exit);
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
252
253 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
254 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
255 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
256 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
257 /* In LP clock cycles */
258 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup);
259 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
260 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
261
262 return nwl_dsi_clear_error(dsi);
263}
264
265static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
266{
267 u32 mode;
268 int color_format;
269 bool burst_mode;
270 int hfront_porch, hback_porch, vfront_porch, vback_porch;
271 int hsync_len, vsync_len;
272
273 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
274 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
275 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
276
277 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
278 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
279 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
280
281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
283 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
284 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
285 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
286 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
287 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
289 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
290
291 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
292 if (color_format < 0) {
293 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
294 dsi->format);
295 return color_format;
296 }
297 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
298
299 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
300 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
301 /*
302 * Adjusting input polarity based on the video mode results in
303 * a black screen so always pick active low:
304 */
305 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
306 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW);
307 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
308 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW);
309
310 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
311 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
312
313 if (burst_mode) {
314 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
315 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
316 } else {
317 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
318 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES :
319 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS);
320 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
321 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
322 dsi->mode.hdisplay);
323 }
324
325 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
326 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
327 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
328
329 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
330 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
331 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
332 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
333
334 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
335 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
336 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
337 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
338
339 return nwl_dsi_clear_error(dsi);
340}
341
342static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
343{
344 u32 irq_enable;
345
346 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff);
347 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
348
349 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK |
350 NWL_DSI_RX_PKT_HDR_RCVD_MASK |
351 NWL_DSI_TX_FIFO_OVFLW_MASK |
352 NWL_DSI_HS_TX_TIMEOUT_MASK);
353
354 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
355
356 return nwl_dsi_clear_error(dsi);
357}
358
359static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host,
360 struct mipi_dsi_device *device)
361{
362 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
363 struct device *dev = dsi->dev;
364
365 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes,
366 device->format, device->mode_flags);
367
368 if (device->lanes < 1 || device->lanes > 4)
369 return -EINVAL;
370
371 dsi->lanes = device->lanes;
372 dsi->format = device->format;
373 dsi->dsi_mode_flags = device->mode_flags;
374
375 return 0;
376}
377
378static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
379{
380 struct device *dev = dsi->dev;
381 struct nwl_dsi_transfer *xfer = dsi->xfer;
382 int err;
383 u8 *payload = xfer->msg->rx_buf;
384 u32 val;
385 u16 word_count;
386 u8 channel;
387 u8 data_type;
388
389 xfer->status = 0;
390
391 if (xfer->rx_word_count == 0) {
392 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD))
393 return false;
394 /* Get the RX header and parse it */
395 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
396 err = nwl_dsi_clear_error(dsi);
397 if (err)
398 xfer->status = err;
399 word_count = NWL_DSI_WC(val);
400 channel = NWL_DSI_RX_VC(val);
401 data_type = NWL_DSI_RX_DT(val);
402
403 if (channel != xfer->msg->channel) {
404 DRM_DEV_ERROR(dev,
405 "[%02X] Channel mismatch (%u != %u)\n",
406 xfer->cmd, channel, xfer->msg->channel);
407 xfer->status = -EINVAL;
408 return true;
409 }
410
411 switch (data_type) {
412 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
413 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
414 if (xfer->msg->rx_len > 1) {
415 /* read second byte */
416 payload[1] = word_count >> 8;
417 ++xfer->rx_len;
418 }
419 fallthrough;
420 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
421 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
422 if (xfer->msg->rx_len > 0) {
423 /* read first byte */
424 payload[0] = word_count & 0xff;
425 ++xfer->rx_len;
426 }
427 xfer->status = xfer->rx_len;
428 return true;
429 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
430 word_count &= 0xff;
431 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n",
432 xfer->cmd, word_count);
433 xfer->status = -EPROTO;
434 return true;
435 }
436
437 if (word_count > xfer->msg->rx_len) {
438 DRM_DEV_ERROR(dev,
439 "[%02X] Receive buffer too small: %zu (< %u)\n",
440 xfer->cmd, xfer->msg->rx_len, word_count);
441 xfer->status = -EINVAL;
442 return true;
443 }
444
445 xfer->rx_word_count = word_count;
446 } else {
447 /* Set word_count from previous header read */
448 word_count = xfer->rx_word_count;
449 }
450
451 /* If RX payload is not yet received, wait for it */
452 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD))
453 return false;
454
455 /* Read the RX payload */
456 while (word_count >= 4) {
457 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
458 payload[0] = (val >> 0) & 0xff;
459 payload[1] = (val >> 8) & 0xff;
460 payload[2] = (val >> 16) & 0xff;
461 payload[3] = (val >> 24) & 0xff;
462 payload += 4;
463 xfer->rx_len += 4;
464 word_count -= 4;
465 }
466
467 if (word_count > 0) {
468 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
469 switch (word_count) {
470 case 3:
471 payload[2] = (val >> 16) & 0xff;
472 ++xfer->rx_len;
473 fallthrough;
474 case 2:
475 payload[1] = (val >> 8) & 0xff;
476 ++xfer->rx_len;
477 fallthrough;
478 case 1:
479 payload[0] = (val >> 0) & 0xff;
480 ++xfer->rx_len;
481 break;
482 }
483 }
484
485 xfer->status = xfer->rx_len;
486 err = nwl_dsi_clear_error(dsi);
487 if (err)
488 xfer->status = err;
489
490 return true;
491}
492
493static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
494{
495 struct nwl_dsi_transfer *xfer = dsi->xfer;
496 bool end_packet = false;
497
498 if (!xfer)
499 return;
500
501 if (xfer->direction == DSI_PACKET_SEND &&
502 status & NWL_DSI_TX_PKT_DONE) {
503 xfer->status = xfer->tx_len;
504 end_packet = true;
505 } else if (status & NWL_DSI_DPHY_DIRECTION &&
506 ((status & (NWL_DSI_RX_PKT_HDR_RCVD |
507 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) {
508 end_packet = nwl_dsi_read_packet(dsi, status);
509 }
510
511 if (end_packet)
512 complete(&xfer->completed);
513}
514
515static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
516{
517 struct nwl_dsi_transfer *xfer = dsi->xfer;
518 struct mipi_dsi_packet *pkt = &xfer->packet;
519 const u8 *payload;
520 size_t length;
521 u16 word_count;
522 u8 hs_mode;
523 u32 val;
524 u32 hs_workaround = 0;
525
526 /* Send the payload, if any */
527 length = pkt->payload_length;
528 payload = pkt->payload;
529
530 while (length >= 4) {
531 val = *(u32 *)payload;
532 hs_workaround |= !(val & 0xFFFF00);
533 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
534 payload += 4;
535 length -= 4;
536 }
537 /* Send the rest of the payload */
538 val = 0;
539 switch (length) {
540 case 3:
541 val |= payload[2] << 16;
542 fallthrough;
543 case 2:
544 val |= payload[1] << 8;
545 hs_workaround |= !(val & 0xFFFF00);
546 fallthrough;
547 case 1:
548 val |= payload[0];
549 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
550 break;
551 }
552 xfer->tx_len = pkt->payload_length;
553
554 /*
555 * Send the header
556 * header[0] = Virtual Channel + Data Type
557 * header[1] = Word Count LSB (LP) or first param (SP)
558 * header[2] = Word Count MSB (LP) or second param (SP)
559 */
560 word_count = pkt->header[1] | (pkt->header[2] << 8);
561 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
562 DRM_DEV_DEBUG_DRIVER(dsi->dev,
563 "Using hs mode workaround for cmd 0x%x\n",
564 xfer->cmd);
565 hs_mode = 1;
566 } else {
567 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1;
568 }
569 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) |
570 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) |
571 NWL_DSI_BTA_TX(xfer->need_bta);
572 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
573
574 /* Send packet command */
575 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
576}
577
578static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host,
579 const struct mipi_dsi_msg *msg)
580{
581 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
582 struct nwl_dsi_transfer xfer;
583 ssize_t ret = 0;
584
585 /* Create packet to be sent */
586 dsi->xfer = &xfer;
587 ret = mipi_dsi_create_packet(&xfer.packet, msg);
588 if (ret < 0) {
589 dsi->xfer = NULL;
590 return ret;
591 }
592
593 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM ||
594 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM ||
595 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM ||
596 msg->type & MIPI_DSI_DCS_READ) &&
597 msg->rx_len > 0 && msg->rx_buf)
598 xfer.direction = DSI_PACKET_RECEIVE;
599 else
600 xfer.direction = DSI_PACKET_SEND;
601
602 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE);
603 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0;
604 xfer.msg = msg;
605 xfer.status = -ETIMEDOUT;
606 xfer.rx_word_count = 0;
607 xfer.rx_len = 0;
608 xfer.cmd = 0x00;
609 if (msg->tx_len > 0)
610 xfer.cmd = ((u8 *)(msg->tx_buf))[0];
611 init_completion(&xfer.completed);
612
613 ret = clk_prepare_enable(dsi->rx_esc_clk);
614 if (ret < 0) {
615 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
616 ret);
617 return ret;
618 }
619 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
620 clk_get_rate(dsi->rx_esc_clk));
621
622 /* Initiate the DSI packet transmision */
623 nwl_dsi_begin_transmission(dsi);
624
625 if (!wait_for_completion_timeout(&xfer.completed,
626 NWL_DSI_MIPI_FIFO_TIMEOUT)) {
627 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n",
628 xfer.cmd);
629 ret = -ETIMEDOUT;
630 } else {
631 ret = xfer.status;
632 }
633
634 clk_disable_unprepare(dsi->rx_esc_clk);
635
636 return ret;
637}
638
639static const struct mipi_dsi_host_ops nwl_dsi_host_ops = {
640 .attach = nwl_dsi_host_attach,
641 .transfer = nwl_dsi_host_transfer,
642};
643
644static irqreturn_t nwl_dsi_irq_handler(int irq, void *data)
645{
646 u32 irq_status;
647 struct nwl_dsi *dsi = data;
648
649 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
650
651 if (irq_status & NWL_DSI_TX_FIFO_OVFLW)
652 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
653
654 if (irq_status & NWL_DSI_HS_TX_TIMEOUT)
655 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
656
657 if (irq_status & NWL_DSI_TX_PKT_DONE ||
658 irq_status & NWL_DSI_RX_PKT_HDR_RCVD ||
659 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)
660 nwl_dsi_finish_transmission(dsi, irq_status);
661
662 return IRQ_HANDLED;
663}
664
665static int nwl_dsi_mode_set(struct nwl_dsi *dsi)
666{
667 struct device *dev = dsi->dev;
668 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
669 int ret;
670
671 if (!dsi->lanes) {
672 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
673 return -EINVAL;
674 }
675
676 ret = phy_init(dsi->phy);
677 if (ret < 0) {
678 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret);
679 return ret;
680 }
681
682 ret = phy_configure(dsi->phy, phy_cfg);
683 if (ret < 0) {
684 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret);
685 goto uninit_phy;
686 }
687
688 ret = clk_prepare_enable(dsi->tx_esc_clk);
689 if (ret < 0) {
690 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
691 ret);
692 goto uninit_phy;
693 }
694 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
695 clk_get_rate(dsi->tx_esc_clk));
696
697 ret = nwl_dsi_config_host(dsi);
698 if (ret < 0) {
699 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret);
700 goto disable_clock;
701 }
702
703 ret = nwl_dsi_config_dpi(dsi);
704 if (ret < 0) {
705 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret);
706 goto disable_clock;
707 }
708
709 ret = phy_power_on(dsi->phy);
710 if (ret < 0) {
711 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret);
712 goto disable_clock;
713 }
714
715 ret = nwl_dsi_init_interrupts(dsi);
716 if (ret < 0)
717 goto power_off_phy;
718
719 return ret;
720
721power_off_phy:
722 phy_power_off(dsi->phy);
723disable_clock:
724 clk_disable_unprepare(dsi->tx_esc_clk);
725uninit_phy:
726 phy_exit(dsi->phy);
727
728 return ret;
729}
730
731static int nwl_dsi_disable(struct nwl_dsi *dsi)
732{
733 struct device *dev = dsi->dev;
734
735 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n");
736
737 phy_power_off(dsi->phy);
738 phy_exit(dsi->phy);
739
740 /* Disabling the clock before the phy breaks enabling dsi again */
741 clk_disable_unprepare(dsi->tx_esc_clk);
742
743 return 0;
744}
745
746static void
747nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge,
748 struct drm_bridge_state *old_bridge_state)
749{
750 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
751 int ret;
752
753 nwl_dsi_disable(dsi);
754
755 ret = reset_control_assert(dsi->rst_dpi);
756 if (ret < 0) {
757 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
758 return;
759 }
760 ret = reset_control_assert(dsi->rst_byte);
761 if (ret < 0) {
762 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
763 return;
764 }
765 ret = reset_control_assert(dsi->rst_esc);
766 if (ret < 0) {
767 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
768 return;
769 }
770 ret = reset_control_assert(dsi->rst_pclk);
771 if (ret < 0) {
772 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
773 return;
774 }
775
776 clk_disable_unprepare(dsi->core_clk);
777 clk_disable_unprepare(dsi->lcdif_clk);
778
779 pm_runtime_put(dsi->dev);
780}
781
782static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
783 const struct drm_display_mode *mode,
784 union phy_configure_opts *phy_opts)
785{
786 unsigned long rate;
787 int ret;
788
789 if (dsi->lanes < 1 || dsi->lanes > 4)
790 return -EINVAL;
791
792 /*
793 * So far the DPHY spec minimal timings work for both mixel
794 * dphy and nwl dsi host
795 */
796 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000,
797 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
798 &phy_opts->mipi_dphy);
799 if (ret < 0)
800 return ret;
801
802 rate = clk_get_rate(dsi->tx_esc_clk);
803 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
804 phy_opts->mipi_dphy.lp_clk_rate = rate;
805
806 return 0;
807}
808
809static enum drm_mode_status
810nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge,
811 const struct drm_display_info *info,
812 const struct drm_display_mode *mode)
813{
814 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
815 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
816
817 if (mode->clock * bpp > 15000000 * dsi->lanes)
818 return MODE_CLOCK_HIGH;
819
820 if (mode->clock * bpp < 80000 * dsi->lanes)
821 return MODE_CLOCK_LOW;
822
823 return MODE_OK;
824}
825
826static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge,
827 struct drm_bridge_state *bridge_state,
828 struct drm_crtc_state *crtc_state,
829 struct drm_connector_state *conn_state)
830{
831 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
832
833 /* At least LCDIF + NWL needs active high sync */
834 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
835 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC);
836
837 /*
838 * Do a full modeset if crtc_state->active is changed to be true.
839 * This ensures our ->mode_set() is called to get the DSI controller
840 * and the PHY ready to send DCS commands, when only the connector's
841 * DPMS is brought out of "Off" status.
842 */
843 if (crtc_state->active_changed && crtc_state->active)
844 crtc_state->mode_changed = true;
845
846 return 0;
847}
848
849static void
850nwl_dsi_bridge_mode_set(struct drm_bridge *bridge,
851 const struct drm_display_mode *mode,
852 const struct drm_display_mode *adjusted_mode)
853{
854 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
855 struct device *dev = dsi->dev;
856 union phy_configure_opts new_cfg;
857 unsigned long phy_ref_rate;
858 int ret;
859
860 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
861 if (ret < 0)
862 return;
863
864 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
865 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate);
866 /* Save the new desired phy config */
867 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
868
869 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode));
870 drm_mode_debug_printmodeline(adjusted_mode);
871
872 pm_runtime_get_sync(dev);
873
874 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
875 return;
876 if (clk_prepare_enable(dsi->core_clk) < 0)
877 return;
878
879 /* Step 1 from DSI reset-out instructions */
880 ret = reset_control_deassert(dsi->rst_pclk);
881 if (ret < 0) {
882 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret);
883 return;
884 }
885
886 /* Step 2 from DSI reset-out instructions */
887 nwl_dsi_mode_set(dsi);
888
889 /* Step 3 from DSI reset-out instructions */
890 ret = reset_control_deassert(dsi->rst_esc);
891 if (ret < 0) {
892 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret);
893 return;
894 }
895 ret = reset_control_deassert(dsi->rst_byte);
896 if (ret < 0) {
897 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret);
898 return;
899 }
900}
901
902static void
903nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge,
904 struct drm_bridge_state *old_bridge_state)
905{
906 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
907 int ret;
908
909 /* Step 5 from DSI reset-out instructions */
910 ret = reset_control_deassert(dsi->rst_dpi);
911 if (ret < 0)
912 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
913}
914
915static int nwl_dsi_bridge_attach(struct drm_bridge *bridge,
916 enum drm_bridge_attach_flags flags)
917{
918 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
919 struct drm_bridge *panel_bridge;
920 struct drm_panel *panel;
921 int ret;
922
923 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel,
924 &panel_bridge);
925 if (ret)
926 return ret;
927
928 if (panel) {
929 panel_bridge = drm_panel_bridge_add(panel);
930 if (IS_ERR(panel_bridge))
931 return PTR_ERR(panel_bridge);
932 }
933 dsi->panel_bridge = panel_bridge;
934
935 if (!dsi->panel_bridge)
936 return -EPROBE_DEFER;
937
938 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
939 flags);
940}
941
942static void nwl_dsi_bridge_detach(struct drm_bridge *bridge)
943{ struct nwl_dsi *dsi = bridge_to_dsi(bridge);
944
945 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0);
946}
947
948static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = {
949 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
950 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
951 .atomic_reset = drm_atomic_helper_bridge_reset,
952 .atomic_check = nwl_dsi_bridge_atomic_check,
953 .atomic_enable = nwl_dsi_bridge_atomic_enable,
954 .atomic_disable = nwl_dsi_bridge_atomic_disable,
955 .mode_set = nwl_dsi_bridge_mode_set,
956 .mode_valid = nwl_dsi_bridge_mode_valid,
957 .attach = nwl_dsi_bridge_attach,
958 .detach = nwl_dsi_bridge_detach,
959};
960
961static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
962{
963 struct platform_device *pdev = to_platform_device(dsi->dev);
964 struct clk *clk;
965 void __iomem *base;
966 int ret;
967
968 dsi->phy = devm_phy_get(dsi->dev, "dphy");
969 if (IS_ERR(dsi->phy)) {
970 ret = PTR_ERR(dsi->phy);
971 if (ret != -EPROBE_DEFER)
972 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
973 return ret;
974 }
975
976 clk = devm_clk_get(dsi->dev, "lcdif");
977 if (IS_ERR(clk)) {
978 ret = PTR_ERR(clk);
979 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
980 ret);
981 return ret;
982 }
983 dsi->lcdif_clk = clk;
984
985 clk = devm_clk_get(dsi->dev, "core");
986 if (IS_ERR(clk)) {
987 ret = PTR_ERR(clk);
988 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
989 ret);
990 return ret;
991 }
992 dsi->core_clk = clk;
993
994 clk = devm_clk_get(dsi->dev, "phy_ref");
995 if (IS_ERR(clk)) {
996 ret = PTR_ERR(clk);
997 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
998 ret);
999 return ret;
1000 }
1001 dsi->phy_ref_clk = clk;
1002
1003 clk = devm_clk_get(dsi->dev, "rx_esc");
1004 if (IS_ERR(clk)) {
1005 ret = PTR_ERR(clk);
1006 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1007 ret);
1008 return ret;
1009 }
1010 dsi->rx_esc_clk = clk;
1011
1012 clk = devm_clk_get(dsi->dev, "tx_esc");
1013 if (IS_ERR(clk)) {
1014 ret = PTR_ERR(clk);
1015 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1016 ret);
1017 return ret;
1018 }
1019 dsi->tx_esc_clk = clk;
1020
1021 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1022 if (IS_ERR(dsi->mux)) {
1023 ret = PTR_ERR(dsi->mux);
1024 if (ret != -EPROBE_DEFER)
1025 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1026 return ret;
1027 }
1028
1029 base = devm_platform_ioremap_resource(pdev, 0);
1030 if (IS_ERR(base))
1031 return PTR_ERR(base);
1032
1033 dsi->regmap =
1034 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1035 if (IS_ERR(dsi->regmap)) {
1036 ret = PTR_ERR(dsi->regmap);
1037 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1038 ret);
1039 return ret;
1040 }
1041
1042 dsi->irq = platform_get_irq(pdev, 0);
1043 if (dsi->irq < 0) {
1044 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1045 dsi->irq);
1046 return dsi->irq;
1047 }
1048
1049 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1050 if (IS_ERR(dsi->rst_pclk)) {
1051 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1052 PTR_ERR(dsi->rst_pclk));
1053 return PTR_ERR(dsi->rst_pclk);
1054 }
1055 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1056 if (IS_ERR(dsi->rst_byte)) {
1057 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1058 PTR_ERR(dsi->rst_byte));
1059 return PTR_ERR(dsi->rst_byte);
1060 }
1061 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1062 if (IS_ERR(dsi->rst_esc)) {
1063 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1064 PTR_ERR(dsi->rst_esc));
1065 return PTR_ERR(dsi->rst_esc);
1066 }
1067 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1068 if (IS_ERR(dsi->rst_dpi)) {
1069 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1070 PTR_ERR(dsi->rst_dpi));
1071 return PTR_ERR(dsi->rst_dpi);
1072 }
1073 return 0;
1074}
1075
1076static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1077{
1078 struct device_node *remote;
1079 u32 use_dcss = 1;
1080 int ret;
1081
1082 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1083 NWL_DSI_ENDPOINT_LCDIF);
1084 if (remote) {
1085 use_dcss = 0;
1086 } else {
1087 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1088 NWL_DSI_ENDPOINT_DCSS);
1089 if (!remote) {
1090 DRM_DEV_ERROR(dsi->dev,
1091 "No valid input endpoint found\n");
1092 return -EINVAL;
1093 }
1094 }
1095
1096 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1097 (use_dcss) ? "DCSS" : "LCDIF");
1098 ret = mux_control_try_select(dsi->mux, use_dcss);
1099 if (ret < 0)
1100 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1101
1102 of_node_put(remote);
1103 return ret;
1104}
1105
1106static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1107{
1108 int ret;
1109
1110 ret = mux_control_deselect(dsi->mux);
1111 if (ret < 0)
1112 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1113
1114 return ret;
1115}
1116
1117static const struct drm_bridge_timings nwl_dsi_timings = {
1118 .input_bus_flags = DRM_BUS_FLAG_DE_LOW,
1119};
1120
1121static const struct of_device_id nwl_dsi_dt_ids[] = {
1122 { .compatible = "fsl,imx8mq-nwl-dsi", },
1123 { /* sentinel */ }
1124};
1125MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids);
1126
1127static const struct soc_device_attribute nwl_dsi_quirks_match[] = {
1128 { .soc_id = "i.MX8MQ", .revision = "2.0",
1129 .data = (void *)E11418_HS_MODE_QUIRK },
1130 { /* sentinel. */ },
1131};
1132
1133static int nwl_dsi_probe(struct platform_device *pdev)
1134{
1135 struct device *dev = &pdev->dev;
1136 const struct soc_device_attribute *attr;
1137 struct nwl_dsi *dsi;
1138 int ret;
1139
1140 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1141 if (!dsi)
1142 return -ENOMEM;
1143
1144 dsi->dev = dev;
1145
1146 ret = nwl_dsi_parse_dt(dsi);
1147 if (ret)
1148 return ret;
1149
1150 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1151 dev_name(dev), dsi);
1152 if (ret < 0) {
1153 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1154 ret);
1155 return ret;
1156 }
1157
1158 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1159 dsi->dsi_host.dev = dev;
1160 ret = mipi_dsi_host_register(&dsi->dsi_host);
1161 if (ret) {
1162 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret);
1163 return ret;
1164 }
1165
1166 attr = soc_device_match(nwl_dsi_quirks_match);
1167 if (attr)
1168 dsi->quirks = (uintptr_t)attr->data;
1169
1170 dsi->bridge.driver_private = dsi;
1171 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1172 dsi->bridge.of_node = dev->of_node;
1173 dsi->bridge.timings = &nwl_dsi_timings;
1174
1175 dev_set_drvdata(dev, dsi);
1176 pm_runtime_enable(dev);
1177
1178 ret = nwl_dsi_select_input(dsi);
1179 if (ret < 0) {
1180 mipi_dsi_host_unregister(&dsi->dsi_host);
1181 return ret;
1182 }
1183
1184 drm_bridge_add(&dsi->bridge);
1185 return 0;
1186}
1187
1188static int nwl_dsi_remove(struct platform_device *pdev)
1189{
1190 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1191
1192 nwl_dsi_deselect_input(dsi);
1193 mipi_dsi_host_unregister(&dsi->dsi_host);
1194 drm_bridge_remove(&dsi->bridge);
1195 pm_runtime_disable(&pdev->dev);
1196 return 0;
1197}
1198
1199static struct platform_driver nwl_dsi_driver = {
1200 .probe = nwl_dsi_probe,
1201 .remove = nwl_dsi_remove,
1202 .driver = {
1203 .of_match_table = nwl_dsi_dt_ids,
1204 .name = DRV_NAME,
1205 },
1206};
1207
1208module_platform_driver(nwl_dsi_driver);
1209
1210MODULE_AUTHOR("NXP Semiconductor");
1211MODULE_AUTHOR("Purism SPC");
1212MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver");
1213MODULE_LICENSE("GPL"); /* GPLv2 or later */