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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU9_DRIVER_IF_H
25#define SMU9_DRIVER_IF_H
26
27#include "smu9.h"
28
29/**** IMPORTANT ***
30 * SMU TEAM: Always increment the interface version if
31 * any structure is changed in this file
32 */
33#define SMU9_DRIVER_IF_VERSION 0xE
34
35#define PPTABLE_V10_SMU_VERSION 1
36
37#define NUM_GFXCLK_DPM_LEVELS 8
38#define NUM_UVD_DPM_LEVELS 8
39#define NUM_VCE_DPM_LEVELS 8
40#define NUM_MP0CLK_DPM_LEVELS 8
41#define NUM_UCLK_DPM_LEVELS 4
42#define NUM_SOCCLK_DPM_LEVELS 8
43#define NUM_DCEFCLK_DPM_LEVELS 8
44#define NUM_LINK_LEVELS 2
45
46#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
47#define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
48#define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
49#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
50#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
51#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
52#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
53#define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
54
55#define MIN_GFXCLK_DPM_LEVEL 0
56#define MIN_UVD_DPM_LEVEL 0
57#define MIN_VCE_DPM_LEVEL 0
58#define MIN_MP0CLK_DPM_LEVEL 0
59#define MIN_UCLK_DPM_LEVEL 0
60#define MIN_SOCCLK_DPM_LEVEL 0
61#define MIN_DCEFCLK_DPM_LEVEL 0
62#define MIN_LINK_DPM_LEVEL 0
63
64#define NUM_EVV_VOLTAGE_LEVELS 8
65#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
66#define MIN_EVV_VOLTAGE_LEVEL 0
67
68#define NUM_PSP_LEVEL_MAP 4
69
70/* Gemini Modes */
71#define PPSMC_GeminiModeNone 0 /* Single GPU board */
72#define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */
73#define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */
74
75/* Voltage Modes for DPMs */
76#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
77#define VOLTAGE_MODE_AVFS_WORST_CASE 1
78#define VOLTAGE_MODE_STATIC 2
79
80typedef struct {
81 uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
82 uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
83 uint16_t SsSlewFrac;
84 uint8_t SsOn;
85 uint8_t Did; /* DID */
86} PllSetting_t;
87
88typedef struct {
89 int32_t a0;
90 int32_t a1;
91 int32_t a2;
92
93 uint8_t a0_shift;
94 uint8_t a1_shift;
95 uint8_t a2_shift;
96 uint8_t padding;
97} GbVdroopTable_t;
98
99typedef struct {
100 int32_t m1;
101 int32_t m2;
102 int32_t b;
103
104 uint8_t m1_shift;
105 uint8_t m2_shift;
106 uint8_t b_shift;
107 uint8_t padding;
108} QuadraticInt_t;
109
110#define NUM_DSPCLK_LEVELS 8
111
112typedef enum {
113 DSPCLK_DCEFCLK = 0,
114 DSPCLK_DISPCLK,
115 DSPCLK_PIXCLK,
116 DSPCLK_PHYCLK,
117 DSPCLK_COUNT,
118} DSPCLK_e;
119
120typedef struct {
121 uint16_t Freq; /* in MHz */
122 uint16_t Vid; /* min voltage in SVI2 VID */
123} DisplayClockTable_t;
124
125typedef struct {
126 /* PowerTune */
127 uint16_t SocketPowerLimit; /* Watts */
128 uint16_t TdcLimit; /* Amps */
129 uint16_t EdcLimit; /* Amps */
130 uint16_t TedgeLimit; /* Celcius */
131 uint16_t ThotspotLimit; /* Celcius */
132 uint16_t ThbmLimit; /* Celcius */
133 uint16_t Tvr_socLimit; /* Celcius */
134 uint16_t Tvr_memLimit; /* Celcius */
135 uint16_t Tliquid1Limit; /* Celcius */
136 uint16_t Tliquid2Limit; /* Celcius */
137 uint16_t TplxLimit; /* Celcius */
138 uint16_t LoadLineResistance; /* in mOhms */
139 uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */
140
141 /* External Component Communication Settings */
142 uint8_t Liquid1_I2C_address;
143 uint8_t Liquid2_I2C_address;
144 uint8_t Vr_I2C_address;
145 uint8_t Plx_I2C_address;
146
147 uint8_t GeminiMode;
148 uint8_t spare17[3];
149 uint32_t GeminiApertureHigh;
150 uint32_t GeminiApertureLow;
151
152 uint8_t Liquid_I2C_LineSCL;
153 uint8_t Liquid_I2C_LineSDA;
154 uint8_t Vr_I2C_LineSCL;
155 uint8_t Vr_I2C_LineSDA;
156 uint8_t Plx_I2C_LineSCL;
157 uint8_t Plx_I2C_LineSDA;
158 uint8_t paddingx[2];
159
160 /* ULV Settings */
161 uint8_t UlvOffsetVid; /* SVI2 VID */
162 uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
163 uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
164 uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
165
166 /* VDDCR_SOC Voltages */
167 uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];
168
169 /* This is the minimum voltage needed to run the SOC. */
170 uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
171 uint8_t MaxVoltageVid; /* Maximum Voltage allowable */
172 uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
173 uint8_t padding8;
174
175 uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
176 uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
177 uint8_t padding8_2[2];
178
179 /* SOC Frequencies */
180 PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS];
181
182 uint8_t SocclkDid [NUM_SOCCLK_DPM_LEVELS]; /* DID */
183 uint8_t SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS];
184
185 uint8_t VclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
186 uint8_t DclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
187 uint8_t UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS];
188
189 uint8_t EclkDid [NUM_VCE_DPM_LEVELS]; /* DID */
190 uint8_t VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS];
191
192 uint8_t Mp0clkDid [NUM_MP0CLK_DPM_LEVELS]; /* DID */
193 uint8_t Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS];
194
195 DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
196 QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT];
197
198 uint8_t GfxDpmVoltageMode;
199 uint8_t SocDpmVoltageMode;
200 uint8_t UclkDpmVoltageMode;
201 uint8_t UvdDpmVoltageMode;
202
203 uint8_t VceDpmVoltageMode;
204 uint8_t Mp0DpmVoltageMode;
205 uint8_t DisplayDpmVoltageMode;
206 uint8_t padding8_3;
207
208 uint16_t GfxclkSlewRate;
209 uint16_t padding;
210
211 uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */
212
213 /* Alpha parameters for clock averages. ("255"=1) */
214 uint8_t GfxclkAverageAlpha;
215 uint8_t SocclkAverageAlpha;
216 uint8_t UclkAverageAlpha;
217 uint8_t GfxActivityAverageAlpha;
218
219 /* UCLK States */
220 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
221 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
222 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
223 uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
224 uint8_t paddingUclk[3];
225 uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */
226 uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */
227
228 /* CKS Settings */
229 uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];
230 uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
231
232 /* MP0 Mapping Table */
233 uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];
234
235 /* Link DPM Settings */
236 uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
237 uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
238 uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
239 uint8_t paddingLinkDpm[2];
240
241 /* Fan Control */
242 uint16_t FanStopTemp; /* Celcius */
243 uint16_t FanStartTemp; /* Celcius */
244
245 uint16_t FanGainEdge;
246 uint16_t FanGainHotspot;
247 uint16_t FanGainLiquid;
248 uint16_t FanGainVrVddc;
249 uint16_t FanGainVrMvdd;
250 uint16_t FanGainPlx;
251 uint16_t FanGainHbm;
252 uint16_t FanPwmMin;
253 uint16_t FanAcousticLimitRpm;
254 uint16_t FanThrottlingRpm;
255 uint16_t FanMaximumRpm;
256 uint16_t FanTargetTemperature;
257 uint16_t FanTargetGfxclk;
258 uint8_t FanZeroRpmEnable;
259 uint8_t FanSpare;
260
261 /* The following are AFC override parameters. Leave at 0 to use FW defaults. */
262 int16_t FuzzyFan_ErrorSetDelta;
263 int16_t FuzzyFan_ErrorRateSetDelta;
264 int16_t FuzzyFan_PwmSetDelta;
265 uint16_t FuzzyFan_Reserved;
266
267 /* GPIO Settings */
268 uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */
269 uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */
270 uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */
271 uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */
272 uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */
273 uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */
274 uint8_t Padding1; /* replace GPIO pin configured for CTF */
275 uint8_t Padding2; /* replace GPIO polarity for CTF */
276
277 /* LED Display Settings */
278 uint8_t LedPin0; /* GPIO number for LedPin[0] */
279 uint8_t LedPin1; /* GPIO number for LedPin[1] */
280 uint8_t LedPin2; /* GPIO number for LedPin[2] */
281 uint8_t padding8_4;
282
283 /* AVFS */
284 uint8_t OverrideBtcGbCksOn;
285 uint8_t OverrideAvfsGbCksOn;
286 uint8_t PaddingAvfs8[2];
287
288 GbVdroopTable_t BtcGbVdroopTableCksOn;
289 GbVdroopTable_t BtcGbVdroopTableCksOff;
290
291 QuadraticInt_t AvfsGbCksOn; /* Replacement equation */
292 QuadraticInt_t AvfsGbCksOff; /* Replacement equation */
293
294 uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
295
296 /* Ageing Guardband Parameters */
297 uint32_t AConstant[3];
298 uint16_t DC_tol_sigma;
299 uint16_t Platform_mean;
300 uint16_t Platform_sigma;
301 uint16_t PSM_Age_CompFactor;
302
303 uint32_t DpmLevelPowerDelta;
304
305 uint8_t EnableBoostState;
306 uint8_t AConstant_Shift;
307 uint8_t DC_tol_sigma_Shift;
308 uint8_t PSM_Age_CompFactor_Shift;
309
310 uint16_t BoostStartTemperature;
311 uint16_t BoostStopTemperature;
312
313 PllSetting_t GfxBoostState;
314
315 uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS];
316 GbVdroopTable_t AcgBtcGbVdroopTable;
317 QuadraticInt_t AcgAvfsGb;
318
319 /* ACG Frequency Table, in Mhz */
320 uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];
321
322 /* Padding - ignore */
323 uint32_t MmHubPadding[3]; /* SMU internal use */
324
325} PPTable_t;
326
327typedef struct {
328 uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
329 uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
330 uint16_t MinUclk;
331 uint16_t MaxUclk;
332
333 uint8_t WmSetting;
334 uint8_t Padding[3];
335} WatermarkRowGeneric_t;
336
337#define NUM_WM_RANGES 4
338
339typedef enum {
340 WM_SOCCLK = 0,
341 WM_DCEFCLK,
342 WM_COUNT,
343} WM_CLOCK_e;
344
345typedef struct {
346 /* Watermarks */
347 WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
348
349 uint32_t MmHubPadding[7]; /* SMU internal use */
350} Watermarks_t;
351
352#ifdef PPTABLE_V10_SMU_VERSION
353typedef struct {
354 float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
355 float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
356 float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
357 float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
358 float DcBtcGb;
359
360 uint32_t MmHubPadding[7]; /* SMU internal use */
361} AvfsTable_t;
362#else
363typedef struct {
364 uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
365 uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
366 uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
367 uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
368 uint32_t DcBtcGb;
369
370 uint32_t MmHubPadding[7]; /* SMU internal use */
371} AvfsTable_t;
372#endif
373
374typedef struct {
375 uint16_t avgPsmCount[30];
376 uint16_t minPsmCount[30];
377 float avgPsmVoltage[30];
378 float minPsmVoltage[30];
379
380 uint32_t MmHubPadding[7]; /* SMU internal use */
381} AvfsDebugTable_t;
382
383typedef struct {
384 uint8_t AvfsEn;
385 uint8_t AvfsVersion;
386 uint8_t Padding[2];
387
388 int32_t VFT0_m1; /* Q8.24 */
389 int32_t VFT0_m2; /* Q12.12 */
390 int32_t VFT0_b; /* Q32 */
391
392 int32_t VFT1_m1; /* Q8.16 */
393 int32_t VFT1_m2; /* Q12.12 */
394 int32_t VFT1_b; /* Q32 */
395
396 int32_t VFT2_m1; /* Q8.16 */
397 int32_t VFT2_m2; /* Q12.12 */
398 int32_t VFT2_b; /* Q32 */
399
400 int32_t AvfsGb0_m1; /* Q8.16 */
401 int32_t AvfsGb0_m2; /* Q12.12 */
402 int32_t AvfsGb0_b; /* Q32 */
403
404 int32_t AcBtcGb_m1; /* Q8.24 */
405 int32_t AcBtcGb_m2; /* Q12.12 */
406 int32_t AcBtcGb_b; /* Q32 */
407
408 uint32_t AvfsTempCold;
409 uint32_t AvfsTempMid;
410 uint32_t AvfsTempHot;
411
412 uint32_t InversionVoltage; /* in mV with 2 fractional bits */
413
414 int32_t P2V_m1; /* Q8.24 */
415 int32_t P2V_m2; /* Q12.12 */
416 int32_t P2V_b; /* Q32 */
417
418 uint32_t P2VCharzFreq; /* in 10KHz units */
419
420 uint32_t EnabledAvfsModules;
421
422 uint32_t MmHubPadding[7]; /* SMU internal use */
423} AvfsFuseOverride_t;
424
425/* These defines are used with the following messages:
426 * SMC_MSG_TransferTableDram2Smu
427 * SMC_MSG_TransferTableSmu2Dram
428 */
429#define TABLE_PPTABLE 0
430#define TABLE_WATERMARKS 1
431#define TABLE_AVFS 2
432#define TABLE_AVFS_PSM_DEBUG 3
433#define TABLE_AVFS_FUSE_OVERRIDE 4
434#define TABLE_PMSTATUSLOG 5
435#define TABLE_COUNT 6
436
437/* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
438#define UCLK_SWITCH_SLOW 0
439#define UCLK_SWITCH_FAST 1
440
441/* GFX DIDT Configuration */
442#define SQ_Enable_MASK 0x1
443#define SQ_IR_MASK 0x2
444#define SQ_PCC_MASK 0x4
445#define SQ_EDC_MASK 0x8
446
447#define TCP_Enable_MASK 0x100
448#define TCP_IR_MASK 0x200
449#define TCP_PCC_MASK 0x400
450#define TCP_EDC_MASK 0x800
451
452#define TD_Enable_MASK 0x10000
453#define TD_IR_MASK 0x20000
454#define TD_PCC_MASK 0x40000
455#define TD_EDC_MASK 0x80000
456
457#define DB_Enable_MASK 0x1000000
458#define DB_IR_MASK 0x2000000
459#define DB_PCC_MASK 0x4000000
460#define DB_EDC_MASK 0x8000000
461
462#define SQ_Enable_SHIFT 0
463#define SQ_IR_SHIFT 1
464#define SQ_PCC_SHIFT 2
465#define SQ_EDC_SHIFT 3
466
467#define TCP_Enable_SHIFT 8
468#define TCP_IR_SHIFT 9
469#define TCP_PCC_SHIFT 10
470#define TCP_EDC_SHIFT 11
471
472#define TD_Enable_SHIFT 16
473#define TD_IR_SHIFT 17
474#define TD_PCC_SHIFT 18
475#define TD_EDC_SHIFT 19
476
477#define DB_Enable_SHIFT 24
478#define DB_IR_SHIFT 25
479#define DB_PCC_SHIFT 26
480#define DB_EDC_SHIFT 27
481
482#define REMOVE_FMAX_MARGIN_BIT 0x0
483#define REMOVE_DCTOL_MARGIN_BIT 0x1
484#define REMOVE_PLATFORM_MARGIN_BIT 0x2
485
486#endif