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1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef SMU13_DRIVER_IF_ALDEBARAN_H
25#define SMU13_DRIVER_IF_ALDEBARAN_H
26
27#define NUM_VCLK_DPM_LEVELS 8
28#define NUM_DCLK_DPM_LEVELS 8
29#define NUM_SOCCLK_DPM_LEVELS 8
30#define NUM_LCLK_DPM_LEVELS 8
31#define NUM_UCLK_DPM_LEVELS 4
32#define NUM_FCLK_DPM_LEVELS 8
33#define NUM_XGMI_DPM_LEVELS 4
34
35// Feature Control Defines
36#define FEATURE_DATA_CALCULATIONS 0
37#define FEATURE_DPM_GFXCLK_BIT 1
38#define FEATURE_DPM_UCLK_BIT 2
39#define FEATURE_DPM_SOCCLK_BIT 3
40#define FEATURE_DPM_FCLK_BIT 4
41#define FEATURE_DPM_LCLK_BIT 5
42#define FEATURE_DPM_XGMI_BIT 6
43#define FEATURE_DS_GFXCLK_BIT 7
44#define FEATURE_DS_SOCCLK_BIT 8
45#define FEATURE_DS_LCLK_BIT 9
46#define FEATURE_DS_FCLK_BIT 10
47#define FEATURE_DS_UCLK_BIT 11
48#define FEATURE_GFX_SS_BIT 12
49#define FEATURE_DPM_VCN_BIT 13
50#define FEATURE_RSMU_SMN_CG_BIT 14
51#define FEATURE_WAFL_CG_BIT 15
52#define FEATURE_PPT_BIT 16
53#define FEATURE_TDC_BIT 17
54#define FEATURE_APCC_PLUS_BIT 18
55#define FEATURE_APCC_DFLL_BIT 19
56#define FEATURE_FW_CTF_BIT 20
57#define FEATURE_THERMAL_BIT 21
58#define FEATURE_OUT_OF_BAND_MONITOR_BIT 22
59#define FEATURE_SPARE_23_BIT 23
60#define FEATURE_XGMI_PER_LINK_PWR_DWN 24
61#define FEATURE_DF_CSTATE 25
62#define FEATURE_FUSE_CG_BIT 26
63#define FEATURE_MP1_CG_BIT 27
64#define FEATURE_SMUIO_CG_BIT 28
65#define FEATURE_THM_CG_BIT 29
66#define FEATURE_CLK_CG_BIT 30
67#define FEATURE_EDC_BIT 31
68#define FEATURE_SPARE_32_BIT 32
69#define FEATURE_SPARE_33_BIT 33
70#define FEATURE_SPARE_34_BIT 34
71#define FEATURE_SPARE_35_BIT 35
72#define FEATURE_SPARE_36_BIT 36
73#define FEATURE_SPARE_37_BIT 37
74#define FEATURE_SPARE_38_BIT 38
75#define FEATURE_SPARE_39_BIT 39
76#define FEATURE_SPARE_40_BIT 40
77#define FEATURE_SPARE_41_BIT 41
78#define FEATURE_SPARE_42_BIT 42
79#define FEATURE_SPARE_43_BIT 43
80#define FEATURE_SPARE_44_BIT 44
81#define FEATURE_SPARE_45_BIT 45
82#define FEATURE_SPARE_46_BIT 46
83#define FEATURE_SPARE_47_BIT 47
84#define FEATURE_SPARE_48_BIT 48
85#define FEATURE_SPARE_49_BIT 49
86#define FEATURE_SPARE_50_BIT 50
87#define FEATURE_SPARE_51_BIT 51
88#define FEATURE_SPARE_52_BIT 52
89#define FEATURE_SPARE_53_BIT 53
90#define FEATURE_SPARE_54_BIT 54
91#define FEATURE_SPARE_55_BIT 55
92#define FEATURE_SPARE_56_BIT 56
93#define FEATURE_SPARE_57_BIT 57
94#define FEATURE_SPARE_58_BIT 58
95#define FEATURE_SPARE_59_BIT 59
96#define FEATURE_SPARE_60_BIT 60
97#define FEATURE_SPARE_61_BIT 61
98#define FEATURE_SPARE_62_BIT 62
99#define FEATURE_SPARE_63_BIT 63
100
101#define NUM_FEATURES 64
102
103// I2C Config Bit Defines
104#define I2C_CONTROLLER_ENABLED 1
105#define I2C_CONTROLLER_DISABLED 0
106
107// Throttler Status Bits.
108// These are aligned with the out of band monitor alarm bits for common throttlers
109#define THROTTLER_PPT0_BIT 0
110#define THROTTLER_PPT1_BIT 1
111#define THROTTLER_TDC_GFX_BIT 2
112#define THROTTLER_TDC_SOC_BIT 3
113#define THROTTLER_TDC_HBM_BIT 4
114#define THROTTLER_SPARE_5 5
115#define THROTTLER_TEMP_GPU_BIT 6
116#define THROTTLER_TEMP_MEM_BIT 7
117#define THORTTLER_SPARE_8 8
118#define THORTTLER_SPARE_9 9
119#define THORTTLER_SPARE_10 10
120#define THROTTLER_TEMP_VR_GFX_BIT 11
121#define THROTTLER_TEMP_VR_SOC_BIT 12
122#define THROTTLER_TEMP_VR_MEM_BIT 13
123#define THORTTLER_SPARE_14 14
124#define THORTTLER_SPARE_15 15
125#define THORTTLER_SPARE_16 16
126#define THORTTLER_SPARE_17 17
127#define THORTTLER_SPARE_18 18
128#define THROTTLER_APCC_BIT 19
129
130// Table transfer status
131#define TABLE_TRANSFER_OK 0x0
132#define TABLE_TRANSFER_FAILED 0xFF
133#define TABLE_TRANSFER_PENDING 0xAB
134
135//I2C Interface
136#define NUM_I2C_CONTROLLERS 8
137
138#define I2C_CONTROLLER_ENABLED 1
139#define I2C_CONTROLLER_DISABLED 0
140
141#define MAX_SW_I2C_COMMANDS 24
142
143typedef enum {
144 I2C_CONTROLLER_PORT_0, //CKSVII2C0
145 I2C_CONTROLLER_PORT_1, //CKSVII2C1
146 I2C_CONTROLLER_PORT_COUNT,
147} I2cControllerPort_e;
148
149typedef enum {
150 I2C_CONTROLLER_THROTTLER_TYPE_NONE,
151 I2C_CONTROLLER_THROTTLER_VR_GFX0,
152 I2C_CONTROLLER_THROTTLER_VR_GFX1,
153 I2C_CONTROLLER_THROTTLER_VR_SOC,
154 I2C_CONTROLLER_THROTTLER_VR_MEM,
155 I2C_CONTROLLER_THROTTLER_COUNT,
156} I2cControllerThrottler_e;
157
158typedef enum {
159 I2C_CONTROLLER_PROTOCOL_VR_MP2855,
160 I2C_CONTROLLER_PROTOCOL_COUNT,
161} I2cControllerProtocol_e;
162
163typedef struct {
164 uint8_t Enabled;
165 uint8_t Speed;
166 uint8_t SlaveAddress;
167 uint8_t ControllerPort;
168 uint8_t ThermalThrotter;
169 uint8_t I2cProtocol;
170 uint8_t PaddingConfig[2];
171} I2cControllerConfig_t;
172
173typedef enum {
174 I2C_PORT_SVD_SCL,
175 I2C_PORT_GPIO,
176} I2cPort_e;
177
178typedef enum {
179 I2C_SPEED_FAST_50K, //50 Kbits/s
180 I2C_SPEED_FAST_100K, //100 Kbits/s
181 I2C_SPEED_FAST_400K, //400 Kbits/s
182 I2C_SPEED_FAST_PLUS_1M, //1 Mbits/s (in fast mode)
183 I2C_SPEED_HIGH_1M, //1 Mbits/s (in high speed mode)
184 I2C_SPEED_HIGH_2M, //2.3 Mbits/s
185 I2C_SPEED_COUNT,
186} I2cSpeed_e;
187
188typedef enum {
189 I2C_CMD_READ,
190 I2C_CMD_WRITE,
191 I2C_CMD_COUNT,
192} I2cCmdType_e;
193
194#define CMDCONFIG_STOP_BIT 0
195#define CMDCONFIG_RESTART_BIT 1
196#define CMDCONFIG_READWRITE_BIT 2 //bit should be 0 for read, 1 for write
197
198#define CMDCONFIG_STOP_MASK (1 << CMDCONFIG_STOP_BIT)
199#define CMDCONFIG_RESTART_MASK (1 << CMDCONFIG_RESTART_BIT)
200#define CMDCONFIG_READWRITE_MASK (1 << CMDCONFIG_READWRITE_BIT)
201
202typedef struct {
203 uint8_t ReadWriteData; //Return data for read. Data to send for write
204 uint8_t CmdConfig; //Includes whether associated command should have a stop or restart command, and is a read or write
205} SwI2cCmd_t; //SW I2C Command Table
206
207typedef struct {
208 uint8_t I2CcontrollerPort; //CKSVII2C0(0) or //CKSVII2C1(1)
209 uint8_t I2CSpeed; //Use I2cSpeed_e to indicate speed to select
210 uint8_t SlaveAddress; //Slave address of device
211 uint8_t NumCmds; //Number of commands
212 SwI2cCmd_t SwI2cCmds[MAX_SW_I2C_COMMANDS];
213} SwI2cRequest_t; // SW I2C Request Table
214
215typedef struct {
216 SwI2cRequest_t SwI2cRequest;
217 uint32_t Spare[8];
218 uint32_t MmHubPadding[8]; // SMU internal use
219} SwI2cRequestExternal_t;
220
221typedef struct {
222 uint32_t a; // store in IEEE float format in this variable
223 uint32_t b; // store in IEEE float format in this variable
224 uint32_t c; // store in IEEE float format in this variable
225} QuadraticInt_t;
226
227typedef struct {
228 uint32_t m; // store in IEEE float format in this variable
229 uint32_t b; // store in IEEE float format in this variable
230} LinearInt_t;
231
232typedef enum {
233 GFXCLK_SOURCE_PLL,
234 GFXCLK_SOURCE_DFLL,
235 GFXCLK_SOURCE_COUNT,
236} GfxclkSrc_e;
237
238typedef enum {
239 PPCLK_GFXCLK,
240 PPCLK_VCLK,
241 PPCLK_DCLK,
242 PPCLK_SOCCLK,
243 PPCLK_UCLK,
244 PPCLK_FCLK,
245 PPCLK_LCLK,
246 PPCLK_COUNT,
247} PPCLK_e;
248
249typedef enum {
250 GPIO_INT_POLARITY_ACTIVE_LOW,
251 GPIO_INT_POLARITY_ACTIVE_HIGH,
252} GpioIntPolarity_e;
253
254//PPSMC_MSG_SetUclkDpmMode
255typedef enum {
256 UCLK_DPM_MODE_BANDWIDTH,
257 UCLK_DPM_MODE_LATENCY,
258} UCLK_DPM_MODE_e;
259
260typedef struct {
261 uint8_t StartupLevel;
262 uint8_t NumDiscreteLevels; // Set to 2 (Fmin, Fmax) when using fine grained DPM, otherwise set to # discrete levels used
263 uint16_t SsFmin; // Fmin for SS curve. If SS curve is selected, will use V@SSFmin for F <= Fmin
264 LinearInt_t ConversionToAvfsClk; // Transfer function to AVFS Clock (GHz->GHz)
265 QuadraticInt_t SsCurve; // Slow-slow curve (GHz->V)
266} DpmDescriptor_t;
267
268typedef struct {
269 uint32_t Version;
270
271 // SECTION: Feature Enablement
272 uint32_t FeaturesToRun[2];
273
274 // SECTION: Infrastructure Limits
275 uint16_t PptLimit; // Watts
276 uint16_t TdcLimitGfx; // Amps
277 uint16_t TdcLimitSoc; // Amps
278 uint16_t TdcLimitHbm; // Amps
279 uint16_t ThotspotLimit; // Celcius
280 uint16_t TmemLimit; // Celcius
281 uint16_t Tvr_gfxLimit; // Celcius
282 uint16_t Tvr_memLimit; // Celcius
283 uint16_t Tvr_socLimit; // Celcius
284 uint16_t PaddingLimit;
285
286 // SECTION: Voltage Control Parameters
287 uint16_t MaxVoltageGfx; // In mV(Q2) Maximum Voltage allowable of VDD_GFX
288 uint16_t MaxVoltageSoc; // In mV(Q2) Maximum Voltage allowable of VDD_SOC
289
290 //SECTION: DPM Config 1
291 DpmDescriptor_t DpmDescriptor[PPCLK_COUNT];
292
293 uint8_t DidTableVclk[NUM_VCLK_DPM_LEVELS]; //PPCLK_VCLK
294 uint8_t DidTableDclk[NUM_DCLK_DPM_LEVELS]; //PPCLK_DCLK
295 uint8_t DidTableSocclk[NUM_SOCCLK_DPM_LEVELS]; //PPCLK_SOCCLK
296 uint8_t DidTableLclk[NUM_LCLK_DPM_LEVELS]; //PPCLK_LCLK
297 uint32_t FidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
298 uint8_t DidTableFclk[NUM_FCLK_DPM_LEVELS]; //PPCLK_FCLK
299 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
300 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
301
302 uint32_t StartupFidPll0; //GFXAVFSCLK, SOCCLK, MP0CLK, MPIOCLK, DXIOCLK
303 uint32_t StartupFidPll4; //VCLK, DCLK, WAFLCLK
304 uint32_t StartupFidPll5; //SMNCLK, MP1CLK, LCLK
305
306 uint8_t StartupSmnclkDid;
307 uint8_t StartupMp0clkDid;
308 uint8_t StartupMp1clkDid;
309 uint8_t StartupWaflclkDid;
310 uint8_t StartupGfxavfsclkDid;
311 uint8_t StartupMpioclkDid;
312 uint8_t StartupDxioclkDid;
313 uint8_t spare123;
314
315 uint8_t StartupVidGpu0Svi0Plane0; //VDDCR_GFX0
316 uint8_t StartupVidGpu0Svi0Plane1; //VDDCR_SOC
317 uint8_t StartupVidGpu0Svi1Plane0; //VDDCR_HBM
318 uint8_t StartupVidGpu0Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed]
319
320 uint8_t StartupVidGpu1Svi0Plane0; //VDDCR_GFX1
321 uint8_t StartupVidGpu1Svi0Plane1; //UNUSED [0 = plane is not used and should not be programmed]
322 uint8_t StartupVidGpu1Svi1Plane0; //UNUSED [0 = plane is not used and should not be programmed]
323 uint8_t StartupVidGpu1Svi1Plane1; //UNUSED [0 = plane is not used and should not be programmed]
324
325 // GFXCLK DPM
326 uint16_t GfxclkFmax; // In MHz
327 uint16_t GfxclkFmin; // In MHz
328 uint16_t GfxclkFidle; // In MHz
329 uint16_t GfxclkFinit; // In MHz
330 uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL]
331 uint8_t spare1[2];
332 uint8_t StartupGfxclkDid;
333 uint32_t StartupGfxclkFid;
334
335 // SECTION: AVFS
336 uint16_t GFX_Guardband_Freq[8]; // MHz [unsigned]
337 int16_t GFX_Guardband_Voltage_Cold[8]; // mV [signed]
338 int16_t GFX_Guardband_Voltage_Mid[8]; // mV [signed]
339 int16_t GFX_Guardband_Voltage_Hot[8]; // mV [signed]
340
341 uint16_t SOC_Guardband_Freq[8]; // MHz [unsigned]
342 int16_t SOC_Guardband_Voltage_Cold[8]; // mV [signed]
343 int16_t SOC_Guardband_Voltage_Mid[8]; // mV [signed]
344 int16_t SOC_Guardband_Voltage_Hot[8]; // mV [signed]
345
346 // VDDCR_GFX BTC
347 uint16_t DcBtcEnabled;
348 int16_t DcBtcMin; // mV [signed]
349 int16_t DcBtcMax; // mV [signed]
350 int16_t DcBtcGb; // mV [signed]
351
352 // SECTION: XGMI
353 uint8_t XgmiLinkSpeed[NUM_XGMI_DPM_LEVELS]; //Gbps [EX: 32 = 32Gbps]
354 uint8_t XgmiLinkWidth[NUM_XGMI_DPM_LEVELS]; //Width [EX: 16 = x16]
355 uint8_t XgmiStartupLevel;
356 uint8_t spare12[3];
357
358 // GFX Vmin
359 uint16_t GFX_PPVmin_Enabled;
360 uint16_t GFX_Vmin_Plat_Offset_Hot; // mV
361 uint16_t GFX_Vmin_Plat_Offset_Cold; // mV
362 uint16_t GFX_Vmin_Hot_T0; // mV
363 uint16_t GFX_Vmin_Cold_T0; // mV
364 uint16_t GFX_Vmin_Hot_Eol; // mV
365 uint16_t GFX_Vmin_Cold_Eol; // mV
366 uint16_t GFX_Vmin_Aging_Offset; // mV
367 uint16_t GFX_Vmin_Temperature_Hot; // 'C
368 uint16_t GFX_Vmin_Temperature_Cold; // 'C
369
370 // SOC Vmin
371 uint16_t SOC_PPVmin_Enabled;
372 uint16_t SOC_Vmin_Plat_Offset_Hot; // mV
373 uint16_t SOC_Vmin_Plat_Offset_Cold; // mV
374 uint16_t SOC_Vmin_Hot_T0; // mV
375 uint16_t SOC_Vmin_Cold_T0; // mV
376 uint16_t SOC_Vmin_Hot_Eol; // mV
377 uint16_t SOC_Vmin_Cold_Eol; // mV
378 uint16_t SOC_Vmin_Aging_Offset; // mV
379 uint16_t SOC_Vmin_Temperature_Hot; // 'C
380 uint16_t SOC_Vmin_Temperature_Cold; // 'C
381
382 // APCC Settings
383 uint32_t ApccPlusResidencyLimit; //PCC residency % (0-100)
384
385 // Determinism
386 uint16_t DeterminismVoltageOffset; //mV
387 uint16_t spare22;
388
389 // reserved
390 uint32_t spare3[14];
391
392 // SECTION: BOARD PARAMETERS
393 // Telemetry Settings
394 uint16_t GfxMaxCurrent; // in Amps
395 int8_t GfxOffset; // in Amps
396 uint8_t Padding_TelemetryGfx;
397
398 uint16_t SocMaxCurrent; // in Amps
399 int8_t SocOffset; // in Amps
400 uint8_t Padding_TelemetrySoc;
401
402 uint16_t MemMaxCurrent; // in Amps
403 int8_t MemOffset; // in Amps
404 uint8_t Padding_TelemetryMem;
405
406 uint16_t BoardMaxCurrent; // in Amps
407 int8_t BoardOffset; // in Amps
408 uint8_t Padding_TelemetryBoardInput;
409
410 // Platform input telemetry voltage coefficient
411 uint32_t BoardVoltageCoeffA; // decode by /1000
412 uint32_t BoardVoltageCoeffB; // decode by /1000
413
414 // GPIO Settings
415 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
416 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
417 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
418 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
419
420 // UCLK Spread Spectrum
421 uint8_t UclkSpreadEnabled; // on or off
422 uint8_t UclkSpreadPercent; // Q4.4
423 uint16_t UclkSpreadFreq; // kHz
424
425 // FCLK Spread Spectrum
426 uint8_t FclkSpreadEnabled; // on or off
427 uint8_t FclkSpreadPercent; // Q4.4
428 uint16_t FclkSpreadFreq; // kHz
429
430 // I2C Controller Structure
431 I2cControllerConfig_t I2cControllers[NUM_I2C_CONTROLLERS];
432
433 // GPIO pins for I2C communications with 2nd controller for Input Telemetry Sequence
434 uint8_t GpioI2cScl; // Serial Clock
435 uint8_t GpioI2cSda; // Serial Data
436 uint16_t spare5;
437
438 uint16_t XgmiMaxCurrent; // in Amps
439 int8_t XgmiOffset; // in Amps
440 uint8_t Padding_TelemetryXgmi;
441
442 uint16_t EdcPowerLimit;
443 uint16_t spare6;
444
445 //reserved
446 uint32_t reserved[14];
447
448} PPTable_t;
449
450typedef struct {
451 // Time constant parameters for clock averages in ms
452 uint16_t GfxclkAverageLpfTau;
453 uint16_t SocclkAverageLpfTau;
454 uint16_t UclkAverageLpfTau;
455 uint16_t GfxActivityLpfTau;
456 uint16_t UclkActivityLpfTau;
457
458 uint16_t SocketPowerLpfTau;
459
460 uint32_t Spare[8];
461 // Padding - ignore
462 uint32_t MmHubPadding[8]; // SMU internal use
463} DriverSmuConfig_t;
464
465typedef struct {
466 uint16_t CurrClock[PPCLK_COUNT];
467 uint16_t Padding1 ;
468 uint16_t AverageGfxclkFrequency;
469 uint16_t AverageSocclkFrequency;
470 uint16_t AverageUclkFrequency ;
471 uint16_t AverageGfxActivity ;
472 uint16_t AverageUclkActivity ;
473 uint8_t CurrSocVoltageOffset ;
474 uint8_t CurrGfxVoltageOffset ;
475 uint8_t CurrMemVidOffset ;
476 uint8_t Padding8 ;
477 uint16_t AverageSocketPower ;
478 uint16_t TemperatureEdge ;
479 uint16_t TemperatureHotspot ;
480 uint16_t TemperatureHBM ; // Max
481 uint16_t TemperatureVrGfx ;
482 uint16_t TemperatureVrSoc ;
483 uint16_t TemperatureVrMem ;
484 uint32_t ThrottlerStatus ;
485
486 uint32_t PublicSerialNumLower32;
487 uint32_t PublicSerialNumUpper32;
488 uint16_t TemperatureAllHBM[4] ;
489 uint32_t GfxBusyAcc ;
490 uint32_t DramBusyAcc ;
491 uint32_t EnergyAcc64bitLow ; //15.259uJ resolution
492 uint32_t EnergyAcc64bitHigh ;
493 uint32_t TimeStampLow ; //10ns resolution
494 uint32_t TimeStampHigh ;
495
496 // Padding - ignore
497 uint32_t MmHubPadding[8]; // SMU internal use
498} SmuMetrics_t;
499
500
501typedef struct {
502 uint16_t avgPsmCount[76];
503 uint16_t minPsmCount[76];
504 float avgPsmVoltage[76];
505 float minPsmVoltage[76];
506
507 uint32_t MmHubPadding[8]; // SMU internal use
508} AvfsDebugTable_t;
509
510// These defines are used with the following messages:
511// SMC_MSG_TransferTableDram2Smu
512// SMC_MSG_TransferTableSmu2Dram
513#define TABLE_PPTABLE 0
514#define TABLE_AVFS_PSM_DEBUG 1
515#define TABLE_AVFS_FUSE_OVERRIDE 2
516#define TABLE_PMSTATUSLOG 3
517#define TABLE_SMU_METRICS 4
518#define TABLE_DRIVER_SMU_CONFIG 5
519#define TABLE_I2C_COMMANDS 6
520#define TABLE_COUNT 7
521
522#endif