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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/debugfs.h>
33
34#include <drm/amdgpu_drm.h>
35#include "amdgpu.h"
36#include "atom.h"
37
38/*
39 * Rings
40 * Most engines on the GPU are fed via ring buffers. Ring
41 * buffers are areas of GPU accessible memory that the host
42 * writes commands into and the GPU reads commands out of.
43 * There is a rptr (read pointer) that determines where the
44 * GPU is currently reading, and a wptr (write pointer)
45 * which determines where the host has written. When the
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
48 * wptr. The GPU then starts fetching commands and executes
49 * them until the pointers are equal again.
50 */
51
52/**
53 * amdgpu_ring_alloc - allocate space on the ring buffer
54 *
55 * @adev: amdgpu_device pointer
56 * @ring: amdgpu_ring structure holding ring information
57 * @ndw: number of dwords to allocate in the ring buffer
58 *
59 * Allocate @ndw dwords in the ring buffer (all asics).
60 * Returns 0 on success, error on failure.
61 */
62int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
63{
64 /* Align requested size with padding so unlock_commit can
65 * pad safely */
66 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
67
68 /* Make sure we aren't trying to allocate more space
69 * than the maximum for one submission
70 */
71 if (WARN_ON_ONCE(ndw > ring->max_dw))
72 return -ENOMEM;
73
74 ring->count_dw = ndw;
75 ring->wptr_old = ring->wptr;
76
77 if (ring->funcs->begin_use)
78 ring->funcs->begin_use(ring);
79
80 return 0;
81}
82
83/** amdgpu_ring_insert_nop - insert NOP packets
84 *
85 * @ring: amdgpu_ring structure holding ring information
86 * @count: the number of NOP packets to insert
87 *
88 * This is the generic insert_nop function for rings except SDMA
89 */
90void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
91{
92 int i;
93
94 for (i = 0; i < count; i++)
95 amdgpu_ring_write(ring, ring->funcs->nop);
96}
97
98/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
99 *
100 * @ring: amdgpu_ring structure holding ring information
101 * @ib: IB to add NOP packets to
102 *
103 * This is the generic pad_ib function for rings except SDMA
104 */
105void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
106{
107 while (ib->length_dw & ring->funcs->align_mask)
108 ib->ptr[ib->length_dw++] = ring->funcs->nop;
109}
110
111/**
112 * amdgpu_ring_commit - tell the GPU to execute the new
113 * commands on the ring buffer
114 *
115 * @adev: amdgpu_device pointer
116 * @ring: amdgpu_ring structure holding ring information
117 *
118 * Update the wptr (write pointer) to tell the GPU to
119 * execute new commands on the ring buffer (all asics).
120 */
121void amdgpu_ring_commit(struct amdgpu_ring *ring)
122{
123 uint32_t count;
124
125 /* We pad to match fetch size */
126 count = ring->funcs->align_mask + 1 -
127 (ring->wptr & ring->funcs->align_mask);
128 count %= ring->funcs->align_mask + 1;
129 ring->funcs->insert_nop(ring, count);
130
131 mb();
132 amdgpu_ring_set_wptr(ring);
133
134 if (ring->funcs->end_use)
135 ring->funcs->end_use(ring);
136}
137
138/**
139 * amdgpu_ring_undo - reset the wptr
140 *
141 * @ring: amdgpu_ring structure holding ring information
142 *
143 * Reset the driver's copy of the wptr (all asics).
144 */
145void amdgpu_ring_undo(struct amdgpu_ring *ring)
146{
147 ring->wptr = ring->wptr_old;
148
149 if (ring->funcs->end_use)
150 ring->funcs->end_use(ring);
151}
152
153/**
154 * amdgpu_ring_init - init driver ring struct.
155 *
156 * @adev: amdgpu_device pointer
157 * @ring: amdgpu_ring structure holding ring information
158 * @max_ndw: maximum number of dw for ring alloc
159 * @nop: nop packet for this ring
160 *
161 * Initialize the driver information for the selected ring (all asics).
162 * Returns 0 on success, error on failure.
163 */
164int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
165 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
166 unsigned int irq_type, unsigned int hw_prio)
167{
168 int r, i;
169 int sched_hw_submission = amdgpu_sched_hw_submission;
170 u32 *num_sched;
171 u32 hw_ip;
172
173 /* Set the hw submission limit higher for KIQ because
174 * it's used for a number of gfx/compute tasks by both
175 * KFD and KGD which may have outstanding fences and
176 * it doesn't really use the gpu scheduler anyway;
177 * KIQ tasks get submitted directly to the ring.
178 */
179 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
180 sched_hw_submission = max(sched_hw_submission, 256);
181 else if (ring == &adev->sdma.instance[0].page)
182 sched_hw_submission = 256;
183
184 if (ring->adev == NULL) {
185 if (adev->num_rings >= AMDGPU_MAX_RINGS)
186 return -EINVAL;
187
188 ring->adev = adev;
189 ring->idx = adev->num_rings++;
190 adev->rings[ring->idx] = ring;
191 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
192 if (r)
193 return r;
194 }
195
196 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
197 if (r) {
198 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
199 return r;
200 }
201
202 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
203 if (r) {
204 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
205 return r;
206 }
207
208 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
209 if (r) {
210 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
211 return r;
212 }
213
214 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
215 if (r) {
216 dev_err(adev->dev,
217 "(%d) ring trail_fence_offs wb alloc failed\n", r);
218 return r;
219 }
220 ring->trail_fence_gpu_addr =
221 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
222 ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
223
224 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
225 if (r) {
226 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
227 return r;
228 }
229 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
230 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
231 /* always set cond_exec_polling to CONTINUE */
232 *ring->cond_exe_cpu_addr = 1;
233
234 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
235 if (r) {
236 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
237 return r;
238 }
239
240 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
241
242 ring->buf_mask = (ring->ring_size / 4) - 1;
243 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
244 0xffffffffffffffff : ring->buf_mask;
245 /* Allocate ring buffer */
246 if (ring->ring_obj == NULL) {
247 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
248 AMDGPU_GEM_DOMAIN_GTT,
249 &ring->ring_obj,
250 &ring->gpu_addr,
251 (void **)&ring->ring);
252 if (r) {
253 dev_err(adev->dev, "(%d) ring create failed\n", r);
254 return r;
255 }
256 amdgpu_ring_clear_ring(ring);
257 }
258
259 ring->max_dw = max_dw;
260 ring->priority = DRM_SCHED_PRIORITY_NORMAL;
261 mutex_init(&ring->priority_mutex);
262
263 if (!ring->no_scheduler) {
264 hw_ip = ring->funcs->type;
265 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
266 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
267 &ring->sched;
268 }
269
270 for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
271 atomic_set(&ring->num_jobs[i], 0);
272
273 return 0;
274}
275
276/**
277 * amdgpu_ring_fini - tear down the driver ring struct.
278 *
279 * @adev: amdgpu_device pointer
280 * @ring: amdgpu_ring structure holding ring information
281 *
282 * Tear down the driver information for the selected ring (all asics).
283 */
284void amdgpu_ring_fini(struct amdgpu_ring *ring)
285{
286
287 /* Not to finish a ring which is not initialized */
288 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
289 return;
290
291 ring->sched.ready = false;
292
293 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
294 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
295
296 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
297 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
298
299 amdgpu_bo_free_kernel(&ring->ring_obj,
300 &ring->gpu_addr,
301 (void **)&ring->ring);
302
303 dma_fence_put(ring->vmid_wait);
304 ring->vmid_wait = NULL;
305 ring->me = 0;
306
307 ring->adev->rings[ring->idx] = NULL;
308}
309
310/**
311 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
312 *
313 * @adev: amdgpu_device pointer
314 * @reg0: register to write
315 * @reg1: register to wait on
316 * @ref: reference value to write/wait on
317 * @mask: mask to wait on
318 *
319 * Helper for rings that don't support write and wait in a
320 * single oneshot packet.
321 */
322void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
323 uint32_t reg0, uint32_t reg1,
324 uint32_t ref, uint32_t mask)
325{
326 amdgpu_ring_emit_wreg(ring, reg0, ref);
327 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
328}
329
330/**
331 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
332 *
333 * @ring: ring to try the recovery on
334 * @vmid: VMID we try to get going again
335 * @fence: timedout fence
336 *
337 * Tries to get a ring proceeding again when it is stuck.
338 */
339bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
340 struct dma_fence *fence)
341{
342 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
343
344 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
345 return false;
346
347 atomic_inc(&ring->adev->gpu_reset_counter);
348 while (!dma_fence_is_signaled(fence) &&
349 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
350 ring->funcs->soft_recovery(ring, vmid);
351
352 return dma_fence_is_signaled(fence);
353}
354
355/*
356 * Debugfs info
357 */
358#if defined(CONFIG_DEBUG_FS)
359
360/* Layout of file is 12 bytes consisting of
361 * - rptr
362 * - wptr
363 * - driver's copy of wptr
364 *
365 * followed by n-words of ring data
366 */
367static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
368 size_t size, loff_t *pos)
369{
370 struct amdgpu_ring *ring = file_inode(f)->i_private;
371 int r, i;
372 uint32_t value, result, early[3];
373
374 if (*pos & 3 || size & 3)
375 return -EINVAL;
376
377 result = 0;
378
379 if (*pos < 12) {
380 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
381 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
382 early[2] = ring->wptr & ring->buf_mask;
383 for (i = *pos / 4; i < 3 && size; i++) {
384 r = put_user(early[i], (uint32_t *)buf);
385 if (r)
386 return r;
387 buf += 4;
388 result += 4;
389 size -= 4;
390 *pos += 4;
391 }
392 }
393
394 while (size) {
395 if (*pos >= (ring->ring_size + 12))
396 return result;
397
398 value = ring->ring[(*pos - 12)/4];
399 r = put_user(value, (uint32_t*)buf);
400 if (r)
401 return r;
402 buf += 4;
403 result += 4;
404 size -= 4;
405 *pos += 4;
406 }
407
408 return result;
409}
410
411static const struct file_operations amdgpu_debugfs_ring_fops = {
412 .owner = THIS_MODULE,
413 .read = amdgpu_debugfs_ring_read,
414 .llseek = default_llseek
415};
416
417#endif
418
419int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
420 struct amdgpu_ring *ring)
421{
422#if defined(CONFIG_DEBUG_FS)
423 struct drm_minor *minor = adev->ddev->primary;
424 struct dentry *ent, *root = minor->debugfs_root;
425 char name[32];
426
427 sprintf(name, "amdgpu_ring_%s", ring->name);
428
429 ent = debugfs_create_file(name,
430 S_IFREG | S_IRUGO, root,
431 ring, &amdgpu_debugfs_ring_fops);
432 if (!ent)
433 return -ENOMEM;
434
435 i_size_write(ent->d_inode, ring->ring_size + 12);
436 ring->ent = ent;
437#endif
438 return 0;
439}
440
441/**
442 * amdgpu_ring_test_helper - tests ring and set sched readiness status
443 *
444 * @ring: ring to try the recovery on
445 *
446 * Tests ring and set sched readiness status
447 *
448 * Returns 0 on success, error on failure.
449 */
450int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
451{
452 struct amdgpu_device *adev = ring->adev;
453 int r;
454
455 r = amdgpu_ring_test_ring(ring);
456 if (r)
457 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
458 ring->name, r);
459 else
460 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
461 ring->name);
462
463 ring->sched.ready = !r;
464 return r;
465}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 * Christian König
28 */
29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/debugfs.h>
33
34#include <drm/amdgpu_drm.h>
35#include "amdgpu.h"
36#include "atom.h"
37
38/*
39 * Rings
40 * Most engines on the GPU are fed via ring buffers. Ring
41 * buffers are areas of GPU accessible memory that the host
42 * writes commands into and the GPU reads commands out of.
43 * There is a rptr (read pointer) that determines where the
44 * GPU is currently reading, and a wptr (write pointer)
45 * which determines where the host has written. When the
46 * pointers are equal, the ring is idle. When the host
47 * writes commands to the ring buffer, it increments the
48 * wptr. The GPU then starts fetching commands and executes
49 * them until the pointers are equal again.
50 */
51
52/**
53 * amdgpu_ring_alloc - allocate space on the ring buffer
54 *
55 * @ring: amdgpu_ring structure holding ring information
56 * @ndw: number of dwords to allocate in the ring buffer
57 *
58 * Allocate @ndw dwords in the ring buffer (all asics).
59 * Returns 0 on success, error on failure.
60 */
61int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
62{
63 /* Align requested size with padding so unlock_commit can
64 * pad safely */
65 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
66
67 /* Make sure we aren't trying to allocate more space
68 * than the maximum for one submission
69 */
70 if (WARN_ON_ONCE(ndw > ring->max_dw))
71 return -ENOMEM;
72
73 ring->count_dw = ndw;
74 ring->wptr_old = ring->wptr;
75
76 if (ring->funcs->begin_use)
77 ring->funcs->begin_use(ring);
78
79 return 0;
80}
81
82/** amdgpu_ring_insert_nop - insert NOP packets
83 *
84 * @ring: amdgpu_ring structure holding ring information
85 * @count: the number of NOP packets to insert
86 *
87 * This is the generic insert_nop function for rings except SDMA
88 */
89void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
90{
91 int i;
92
93 for (i = 0; i < count; i++)
94 amdgpu_ring_write(ring, ring->funcs->nop);
95}
96
97/**
98 * amdgpu_ring_generic_pad_ib - pad IB with NOP packets
99 *
100 * @ring: amdgpu_ring structure holding ring information
101 * @ib: IB to add NOP packets to
102 *
103 * This is the generic pad_ib function for rings except SDMA
104 */
105void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
106{
107 while (ib->length_dw & ring->funcs->align_mask)
108 ib->ptr[ib->length_dw++] = ring->funcs->nop;
109}
110
111/**
112 * amdgpu_ring_commit - tell the GPU to execute the new
113 * commands on the ring buffer
114 *
115 * @ring: amdgpu_ring structure holding ring information
116 *
117 * Update the wptr (write pointer) to tell the GPU to
118 * execute new commands on the ring buffer (all asics).
119 */
120void amdgpu_ring_commit(struct amdgpu_ring *ring)
121{
122 uint32_t count;
123
124 /* We pad to match fetch size */
125 count = ring->funcs->align_mask + 1 -
126 (ring->wptr & ring->funcs->align_mask);
127 count %= ring->funcs->align_mask + 1;
128 ring->funcs->insert_nop(ring, count);
129
130 mb();
131 amdgpu_ring_set_wptr(ring);
132
133 if (ring->funcs->end_use)
134 ring->funcs->end_use(ring);
135}
136
137/**
138 * amdgpu_ring_undo - reset the wptr
139 *
140 * @ring: amdgpu_ring structure holding ring information
141 *
142 * Reset the driver's copy of the wptr (all asics).
143 */
144void amdgpu_ring_undo(struct amdgpu_ring *ring)
145{
146 ring->wptr = ring->wptr_old;
147
148 if (ring->funcs->end_use)
149 ring->funcs->end_use(ring);
150}
151
152/**
153 * amdgpu_ring_init - init driver ring struct.
154 *
155 * @adev: amdgpu_device pointer
156 * @ring: amdgpu_ring structure holding ring information
157 * @max_dw: maximum number of dw for ring alloc
158 * @irq_src: interrupt source to use for this ring
159 * @irq_type: interrupt type to use for this ring
160 * @hw_prio: ring priority (NORMAL/HIGH)
161 * @sched_score: optional score atomic shared with other schedulers
162 *
163 * Initialize the driver information for the selected ring (all asics).
164 * Returns 0 on success, error on failure.
165 */
166int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
167 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
168 unsigned int irq_type, unsigned int hw_prio,
169 atomic_t *sched_score)
170{
171 int r;
172 int sched_hw_submission = amdgpu_sched_hw_submission;
173 u32 *num_sched;
174 u32 hw_ip;
175
176 /* Set the hw submission limit higher for KIQ because
177 * it's used for a number of gfx/compute tasks by both
178 * KFD and KGD which may have outstanding fences and
179 * it doesn't really use the gpu scheduler anyway;
180 * KIQ tasks get submitted directly to the ring.
181 */
182 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
183 sched_hw_submission = max(sched_hw_submission, 256);
184 else if (ring == &adev->sdma.instance[0].page)
185 sched_hw_submission = 256;
186
187 if (ring->adev == NULL) {
188 if (adev->num_rings >= AMDGPU_MAX_RINGS)
189 return -EINVAL;
190
191 ring->adev = adev;
192 ring->idx = adev->num_rings++;
193 adev->rings[ring->idx] = ring;
194 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission,
195 sched_score);
196 if (r)
197 return r;
198 }
199
200 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
201 if (r) {
202 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
203 return r;
204 }
205
206 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
207 if (r) {
208 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
209 return r;
210 }
211
212 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
213 if (r) {
214 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
215 return r;
216 }
217
218 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
219 if (r) {
220 dev_err(adev->dev,
221 "(%d) ring trail_fence_offs wb alloc failed\n", r);
222 return r;
223 }
224 ring->trail_fence_gpu_addr =
225 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
226 ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
227
228 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
229 if (r) {
230 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
231 return r;
232 }
233 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
234 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
235 /* always set cond_exec_polling to CONTINUE */
236 *ring->cond_exe_cpu_addr = 1;
237
238 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
239 if (r) {
240 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
241 return r;
242 }
243
244 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
245
246 ring->buf_mask = (ring->ring_size / 4) - 1;
247 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
248 0xffffffffffffffff : ring->buf_mask;
249 /* Allocate ring buffer */
250 if (ring->ring_obj == NULL) {
251 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
252 AMDGPU_GEM_DOMAIN_GTT,
253 &ring->ring_obj,
254 &ring->gpu_addr,
255 (void **)&ring->ring);
256 if (r) {
257 dev_err(adev->dev, "(%d) ring create failed\n", r);
258 return r;
259 }
260 amdgpu_ring_clear_ring(ring);
261 }
262
263 ring->max_dw = max_dw;
264 ring->hw_prio = hw_prio;
265
266 if (!ring->no_scheduler) {
267 hw_ip = ring->funcs->type;
268 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
269 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
270 &ring->sched;
271 }
272
273 return 0;
274}
275
276/**
277 * amdgpu_ring_fini - tear down the driver ring struct.
278 *
279 * @ring: amdgpu_ring structure holding ring information
280 *
281 * Tear down the driver information for the selected ring (all asics).
282 */
283void amdgpu_ring_fini(struct amdgpu_ring *ring)
284{
285
286 /* Not to finish a ring which is not initialized */
287 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
288 return;
289
290 ring->sched.ready = false;
291
292 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
293 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
294
295 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
296 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
297
298 amdgpu_bo_free_kernel(&ring->ring_obj,
299 &ring->gpu_addr,
300 (void **)&ring->ring);
301
302 dma_fence_put(ring->vmid_wait);
303 ring->vmid_wait = NULL;
304 ring->me = 0;
305
306 ring->adev->rings[ring->idx] = NULL;
307}
308
309/**
310 * amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
311 *
312 * @ring: ring to write to
313 * @reg0: register to write
314 * @reg1: register to wait on
315 * @ref: reference value to write/wait on
316 * @mask: mask to wait on
317 *
318 * Helper for rings that don't support write and wait in a
319 * single oneshot packet.
320 */
321void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
322 uint32_t reg0, uint32_t reg1,
323 uint32_t ref, uint32_t mask)
324{
325 amdgpu_ring_emit_wreg(ring, reg0, ref);
326 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
327}
328
329/**
330 * amdgpu_ring_soft_recovery - try to soft recover a ring lockup
331 *
332 * @ring: ring to try the recovery on
333 * @vmid: VMID we try to get going again
334 * @fence: timedout fence
335 *
336 * Tries to get a ring proceeding again when it is stuck.
337 */
338bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
339 struct dma_fence *fence)
340{
341 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
342
343 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
344 return false;
345
346 atomic_inc(&ring->adev->gpu_reset_counter);
347 while (!dma_fence_is_signaled(fence) &&
348 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
349 ring->funcs->soft_recovery(ring, vmid);
350
351 return dma_fence_is_signaled(fence);
352}
353
354/*
355 * Debugfs info
356 */
357#if defined(CONFIG_DEBUG_FS)
358
359/* Layout of file is 12 bytes consisting of
360 * - rptr
361 * - wptr
362 * - driver's copy of wptr
363 *
364 * followed by n-words of ring data
365 */
366static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
367 size_t size, loff_t *pos)
368{
369 struct amdgpu_ring *ring = file_inode(f)->i_private;
370 int r, i;
371 uint32_t value, result, early[3];
372
373 if (*pos & 3 || size & 3)
374 return -EINVAL;
375
376 result = 0;
377
378 if (*pos < 12) {
379 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
380 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
381 early[2] = ring->wptr & ring->buf_mask;
382 for (i = *pos / 4; i < 3 && size; i++) {
383 r = put_user(early[i], (uint32_t *)buf);
384 if (r)
385 return r;
386 buf += 4;
387 result += 4;
388 size -= 4;
389 *pos += 4;
390 }
391 }
392
393 while (size) {
394 if (*pos >= (ring->ring_size + 12))
395 return result;
396
397 value = ring->ring[(*pos - 12)/4];
398 r = put_user(value, (uint32_t *)buf);
399 if (r)
400 return r;
401 buf += 4;
402 result += 4;
403 size -= 4;
404 *pos += 4;
405 }
406
407 return result;
408}
409
410static const struct file_operations amdgpu_debugfs_ring_fops = {
411 .owner = THIS_MODULE,
412 .read = amdgpu_debugfs_ring_read,
413 .llseek = default_llseek
414};
415
416#endif
417
418int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
419 struct amdgpu_ring *ring)
420{
421#if defined(CONFIG_DEBUG_FS)
422 struct drm_minor *minor = adev_to_drm(adev)->primary;
423 struct dentry *ent, *root = minor->debugfs_root;
424 char name[32];
425
426 sprintf(name, "amdgpu_ring_%s", ring->name);
427
428 ent = debugfs_create_file(name,
429 S_IFREG | S_IRUGO, root,
430 ring, &amdgpu_debugfs_ring_fops);
431 if (IS_ERR(ent))
432 return PTR_ERR(ent);
433
434 i_size_write(ent->d_inode, ring->ring_size + 12);
435 ring->ent = ent;
436#endif
437 return 0;
438}
439
440/**
441 * amdgpu_ring_test_helper - tests ring and set sched readiness status
442 *
443 * @ring: ring to try the recovery on
444 *
445 * Tests ring and set sched readiness status
446 *
447 * Returns 0 on success, error on failure.
448 */
449int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
450{
451 struct amdgpu_device *adev = ring->adev;
452 int r;
453
454 r = amdgpu_ring_test_ring(ring);
455 if (r)
456 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
457 ring->name, r);
458 else
459 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
460 ring->name);
461
462 ring->sched.ready = !r;
463 return r;
464}