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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29/**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45#include <linux/irq.h>
46#include <linux/pci.h>
47
48#include <drm/drm_crtc_helper.h>
49#include <drm/drm_irq.h>
50#include <drm/drm_vblank.h>
51#include <drm/amdgpu_drm.h>
52#include "amdgpu.h"
53#include "amdgpu_ih.h"
54#include "atom.h"
55#include "amdgpu_connectors.h"
56#include "amdgpu_trace.h"
57#include "amdgpu_amdkfd.h"
58#include "amdgpu_ras.h"
59
60#include <linux/pm_runtime.h>
61
62#ifdef CONFIG_DRM_AMD_DC
63#include "amdgpu_dm_irq.h"
64#endif
65
66#define AMDGPU_WAIT_IDLE_TIMEOUT 200
67
68/**
69 * amdgpu_hotplug_work_func - work handler for display hotplug event
70 *
71 * @work: work struct pointer
72 *
73 * This is the hotplug event work handler (all ASICs).
74 * The work gets scheduled from the IRQ handler if there
75 * was a hotplug interrupt. It walks through the connector table
76 * and calls hotplug handler for each connector. After this, it sends
77 * a DRM hotplug event to alert userspace.
78 *
79 * This design approach is required in order to defer hotplug event handling
80 * from the IRQ handler to a work handler because hotplug handler has to use
81 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
82 * sleep).
83 */
84static void amdgpu_hotplug_work_func(struct work_struct *work)
85{
86 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
87 hotplug_work);
88 struct drm_device *dev = adev->ddev;
89 struct drm_mode_config *mode_config = &dev->mode_config;
90 struct drm_connector *connector;
91 struct drm_connector_list_iter iter;
92
93 mutex_lock(&mode_config->mutex);
94 drm_connector_list_iter_begin(dev, &iter);
95 drm_for_each_connector_iter(connector, &iter)
96 amdgpu_connector_hotplug(connector);
97 drm_connector_list_iter_end(&iter);
98 mutex_unlock(&mode_config->mutex);
99 /* Just fire off a uevent and let userspace tell us what to do */
100 drm_helper_hpd_irq_event(dev);
101}
102
103/**
104 * amdgpu_irq_disable_all - disable *all* interrupts
105 *
106 * @adev: amdgpu device pointer
107 *
108 * Disable all types of interrupts from all sources.
109 */
110void amdgpu_irq_disable_all(struct amdgpu_device *adev)
111{
112 unsigned long irqflags;
113 unsigned i, j, k;
114 int r;
115
116 spin_lock_irqsave(&adev->irq.lock, irqflags);
117 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
118 if (!adev->irq.client[i].sources)
119 continue;
120
121 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
122 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
123
124 if (!src || !src->funcs->set || !src->num_types)
125 continue;
126
127 for (k = 0; k < src->num_types; ++k) {
128 atomic_set(&src->enabled_types[k], 0);
129 r = src->funcs->set(adev, src, k,
130 AMDGPU_IRQ_STATE_DISABLE);
131 if (r)
132 DRM_ERROR("error disabling interrupt (%d)\n",
133 r);
134 }
135 }
136 }
137 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
138}
139
140/**
141 * amdgpu_irq_handler - IRQ handler
142 *
143 * @irq: IRQ number (unused)
144 * @arg: pointer to DRM device
145 *
146 * IRQ handler for amdgpu driver (all ASICs).
147 *
148 * Returns:
149 * result of handling the IRQ, as defined by &irqreturn_t
150 */
151irqreturn_t amdgpu_irq_handler(int irq, void *arg)
152{
153 struct drm_device *dev = (struct drm_device *) arg;
154 struct amdgpu_device *adev = dev->dev_private;
155 irqreturn_t ret;
156
157 ret = amdgpu_ih_process(adev, &adev->irq.ih);
158 if (ret == IRQ_HANDLED)
159 pm_runtime_mark_last_busy(dev->dev);
160
161 /* For the hardware that cannot enable bif ring for both ras_controller_irq
162 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
163 * register to check whether the interrupt is triggered or not, and properly
164 * ack the interrupt if it is there
165 */
166 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
167 if (adev->nbio.funcs &&
168 adev->nbio.funcs->handle_ras_controller_intr_no_bifring)
169 adev->nbio.funcs->handle_ras_controller_intr_no_bifring(adev);
170
171 if (adev->nbio.funcs &&
172 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring)
173 adev->nbio.funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
174 }
175
176 return ret;
177}
178
179/**
180 * amdgpu_irq_handle_ih1 - kick of processing for IH1
181 *
182 * @work: work structure in struct amdgpu_irq
183 *
184 * Kick of processing IH ring 1.
185 */
186static void amdgpu_irq_handle_ih1(struct work_struct *work)
187{
188 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
189 irq.ih1_work);
190
191 amdgpu_ih_process(adev, &adev->irq.ih1);
192}
193
194/**
195 * amdgpu_irq_handle_ih2 - kick of processing for IH2
196 *
197 * @work: work structure in struct amdgpu_irq
198 *
199 * Kick of processing IH ring 2.
200 */
201static void amdgpu_irq_handle_ih2(struct work_struct *work)
202{
203 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
204 irq.ih2_work);
205
206 amdgpu_ih_process(adev, &adev->irq.ih2);
207}
208
209/**
210 * amdgpu_msi_ok - check whether MSI functionality is enabled
211 *
212 * @adev: amdgpu device pointer (unused)
213 *
214 * Checks whether MSI functionality has been disabled via module parameter
215 * (all ASICs).
216 *
217 * Returns:
218 * *true* if MSIs are allowed to be enabled or *false* otherwise
219 */
220static bool amdgpu_msi_ok(struct amdgpu_device *adev)
221{
222 if (amdgpu_msi == 1)
223 return true;
224 else if (amdgpu_msi == 0)
225 return false;
226
227 return true;
228}
229
230/**
231 * amdgpu_irq_init - initialize interrupt handling
232 *
233 * @adev: amdgpu device pointer
234 *
235 * Sets up work functions for hotplug and reset interrupts, enables MSI
236 * functionality, initializes vblank, hotplug and reset interrupt handling.
237 *
238 * Returns:
239 * 0 on success or error code on failure
240 */
241int amdgpu_irq_init(struct amdgpu_device *adev)
242{
243 int r = 0;
244
245 spin_lock_init(&adev->irq.lock);
246
247 /* Enable MSI if not disabled by module parameter */
248 adev->irq.msi_enabled = false;
249
250 if (amdgpu_msi_ok(adev)) {
251 int nvec = pci_msix_vec_count(adev->pdev);
252 unsigned int flags;
253
254 if (nvec <= 0) {
255 flags = PCI_IRQ_MSI;
256 } else {
257 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
258 }
259 /* we only need one vector */
260 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
261 if (nvec > 0) {
262 adev->irq.msi_enabled = true;
263 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
264 }
265 }
266
267 if (!amdgpu_device_has_dc_support(adev)) {
268 if (!adev->enable_virtual_display)
269 /* Disable vblank IRQs aggressively for power-saving */
270 /* XXX: can this be enabled for DC? */
271 adev->ddev->vblank_disable_immediate = true;
272
273 r = drm_vblank_init(adev->ddev, adev->mode_info.num_crtc);
274 if (r)
275 return r;
276
277 /* Pre-DCE11 */
278 INIT_WORK(&adev->hotplug_work,
279 amdgpu_hotplug_work_func);
280 }
281
282 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
283 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
284
285 adev->irq.installed = true;
286 /* Use vector 0 for MSI-X */
287 r = drm_irq_install(adev->ddev, pci_irq_vector(adev->pdev, 0));
288 if (r) {
289 adev->irq.installed = false;
290 if (!amdgpu_device_has_dc_support(adev))
291 flush_work(&adev->hotplug_work);
292 return r;
293 }
294 adev->ddev->max_vblank_count = 0x00ffffff;
295
296 DRM_DEBUG("amdgpu: irq initialized.\n");
297 return 0;
298}
299
300/**
301 * amdgpu_irq_fini - shut down interrupt handling
302 *
303 * @adev: amdgpu device pointer
304 *
305 * Tears down work functions for hotplug and reset interrupts, disables MSI
306 * functionality, shuts down vblank, hotplug and reset interrupt handling,
307 * turns off interrupts from all sources (all ASICs).
308 */
309void amdgpu_irq_fini(struct amdgpu_device *adev)
310{
311 unsigned i, j;
312
313 if (adev->irq.installed) {
314 drm_irq_uninstall(adev->ddev);
315 adev->irq.installed = false;
316 if (adev->irq.msi_enabled)
317 pci_free_irq_vectors(adev->pdev);
318 if (!amdgpu_device_has_dc_support(adev))
319 flush_work(&adev->hotplug_work);
320 }
321
322 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
323 if (!adev->irq.client[i].sources)
324 continue;
325
326 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
327 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
328
329 if (!src)
330 continue;
331
332 kfree(src->enabled_types);
333 src->enabled_types = NULL;
334 if (src->data) {
335 kfree(src->data);
336 kfree(src);
337 adev->irq.client[i].sources[j] = NULL;
338 }
339 }
340 kfree(adev->irq.client[i].sources);
341 adev->irq.client[i].sources = NULL;
342 }
343}
344
345/**
346 * amdgpu_irq_add_id - register IRQ source
347 *
348 * @adev: amdgpu device pointer
349 * @client_id: client id
350 * @src_id: source id
351 * @source: IRQ source pointer
352 *
353 * Registers IRQ source on a client.
354 *
355 * Returns:
356 * 0 on success or error code otherwise
357 */
358int amdgpu_irq_add_id(struct amdgpu_device *adev,
359 unsigned client_id, unsigned src_id,
360 struct amdgpu_irq_src *source)
361{
362 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
363 return -EINVAL;
364
365 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
366 return -EINVAL;
367
368 if (!source->funcs)
369 return -EINVAL;
370
371 if (!adev->irq.client[client_id].sources) {
372 adev->irq.client[client_id].sources =
373 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
374 sizeof(struct amdgpu_irq_src *),
375 GFP_KERNEL);
376 if (!adev->irq.client[client_id].sources)
377 return -ENOMEM;
378 }
379
380 if (adev->irq.client[client_id].sources[src_id] != NULL)
381 return -EINVAL;
382
383 if (source->num_types && !source->enabled_types) {
384 atomic_t *types;
385
386 types = kcalloc(source->num_types, sizeof(atomic_t),
387 GFP_KERNEL);
388 if (!types)
389 return -ENOMEM;
390
391 source->enabled_types = types;
392 }
393
394 adev->irq.client[client_id].sources[src_id] = source;
395 return 0;
396}
397
398/**
399 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
400 *
401 * @adev: amdgpu device pointer
402 * @ih: interrupt ring instance
403 *
404 * Dispatches IRQ to IP blocks.
405 */
406void amdgpu_irq_dispatch(struct amdgpu_device *adev,
407 struct amdgpu_ih_ring *ih)
408{
409 u32 ring_index = ih->rptr >> 2;
410 struct amdgpu_iv_entry entry;
411 unsigned client_id, src_id;
412 struct amdgpu_irq_src *src;
413 bool handled = false;
414 int r;
415
416 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
417 amdgpu_ih_decode_iv(adev, &entry);
418
419 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
420
421 client_id = entry.client_id;
422 src_id = entry.src_id;
423
424 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
425 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
426
427 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
428 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
429
430 } else if (adev->irq.virq[src_id]) {
431 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
432
433 } else if (!adev->irq.client[client_id].sources) {
434 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
435 client_id, src_id);
436
437 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
438 r = src->funcs->process(adev, src, &entry);
439 if (r < 0)
440 DRM_ERROR("error processing interrupt (%d)\n", r);
441 else if (r)
442 handled = true;
443
444 } else {
445 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
446 }
447
448 /* Send it to amdkfd as well if it isn't already handled */
449 if (!handled)
450 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
451}
452
453/**
454 * amdgpu_irq_update - update hardware interrupt state
455 *
456 * @adev: amdgpu device pointer
457 * @src: interrupt source pointer
458 * @type: type of interrupt
459 *
460 * Updates interrupt state for the specific source (all ASICs).
461 */
462int amdgpu_irq_update(struct amdgpu_device *adev,
463 struct amdgpu_irq_src *src, unsigned type)
464{
465 unsigned long irqflags;
466 enum amdgpu_interrupt_state state;
467 int r;
468
469 spin_lock_irqsave(&adev->irq.lock, irqflags);
470
471 /* We need to determine after taking the lock, otherwise
472 we might disable just enabled interrupts again */
473 if (amdgpu_irq_enabled(adev, src, type))
474 state = AMDGPU_IRQ_STATE_ENABLE;
475 else
476 state = AMDGPU_IRQ_STATE_DISABLE;
477
478 r = src->funcs->set(adev, src, type, state);
479 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
480 return r;
481}
482
483/**
484 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
485 *
486 * @adev: amdgpu device pointer
487 *
488 * Updates state of all types of interrupts on all sources on resume after
489 * reset.
490 */
491void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
492{
493 int i, j, k;
494
495 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
496 if (!adev->irq.client[i].sources)
497 continue;
498
499 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
500 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
501
502 if (!src)
503 continue;
504 for (k = 0; k < src->num_types; k++)
505 amdgpu_irq_update(adev, src, k);
506 }
507 }
508}
509
510/**
511 * amdgpu_irq_get - enable interrupt
512 *
513 * @adev: amdgpu device pointer
514 * @src: interrupt source pointer
515 * @type: type of interrupt
516 *
517 * Enables specified type of interrupt on the specified source (all ASICs).
518 *
519 * Returns:
520 * 0 on success or error code otherwise
521 */
522int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
523 unsigned type)
524{
525 if (!adev->ddev->irq_enabled)
526 return -ENOENT;
527
528 if (type >= src->num_types)
529 return -EINVAL;
530
531 if (!src->enabled_types || !src->funcs->set)
532 return -EINVAL;
533
534 if (atomic_inc_return(&src->enabled_types[type]) == 1)
535 return amdgpu_irq_update(adev, src, type);
536
537 return 0;
538}
539
540/**
541 * amdgpu_irq_put - disable interrupt
542 *
543 * @adev: amdgpu device pointer
544 * @src: interrupt source pointer
545 * @type: type of interrupt
546 *
547 * Enables specified type of interrupt on the specified source (all ASICs).
548 *
549 * Returns:
550 * 0 on success or error code otherwise
551 */
552int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
553 unsigned type)
554{
555 if (!adev->ddev->irq_enabled)
556 return -ENOENT;
557
558 if (type >= src->num_types)
559 return -EINVAL;
560
561 if (!src->enabled_types || !src->funcs->set)
562 return -EINVAL;
563
564 if (atomic_dec_and_test(&src->enabled_types[type]))
565 return amdgpu_irq_update(adev, src, type);
566
567 return 0;
568}
569
570/**
571 * amdgpu_irq_enabled - check whether interrupt is enabled or not
572 *
573 * @adev: amdgpu device pointer
574 * @src: interrupt source pointer
575 * @type: type of interrupt
576 *
577 * Checks whether the given type of interrupt is enabled on the given source.
578 *
579 * Returns:
580 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
581 * invalid parameters
582 */
583bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
584 unsigned type)
585{
586 if (!adev->ddev->irq_enabled)
587 return false;
588
589 if (type >= src->num_types)
590 return false;
591
592 if (!src->enabled_types || !src->funcs->set)
593 return false;
594
595 return !!atomic_read(&src->enabled_types[type]);
596}
597
598/* XXX: Generic IRQ handling */
599static void amdgpu_irq_mask(struct irq_data *irqd)
600{
601 /* XXX */
602}
603
604static void amdgpu_irq_unmask(struct irq_data *irqd)
605{
606 /* XXX */
607}
608
609/* amdgpu hardware interrupt chip descriptor */
610static struct irq_chip amdgpu_irq_chip = {
611 .name = "amdgpu-ih",
612 .irq_mask = amdgpu_irq_mask,
613 .irq_unmask = amdgpu_irq_unmask,
614};
615
616/**
617 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
618 *
619 * @d: amdgpu IRQ domain pointer (unused)
620 * @irq: virtual IRQ number
621 * @hwirq: hardware irq number
622 *
623 * Current implementation assigns simple interrupt handler to the given virtual
624 * IRQ.
625 *
626 * Returns:
627 * 0 on success or error code otherwise
628 */
629static int amdgpu_irqdomain_map(struct irq_domain *d,
630 unsigned int irq, irq_hw_number_t hwirq)
631{
632 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
633 return -EPERM;
634
635 irq_set_chip_and_handler(irq,
636 &amdgpu_irq_chip, handle_simple_irq);
637 return 0;
638}
639
640/* Implementation of methods for amdgpu IRQ domain */
641static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
642 .map = amdgpu_irqdomain_map,
643};
644
645/**
646 * amdgpu_irq_add_domain - create a linear IRQ domain
647 *
648 * @adev: amdgpu device pointer
649 *
650 * Creates an IRQ domain for GPU interrupt sources
651 * that may be driven by another driver (e.g., ACP).
652 *
653 * Returns:
654 * 0 on success or error code otherwise
655 */
656int amdgpu_irq_add_domain(struct amdgpu_device *adev)
657{
658 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
659 &amdgpu_hw_irqdomain_ops, adev);
660 if (!adev->irq.domain) {
661 DRM_ERROR("GPU irq add domain failed\n");
662 return -ENODEV;
663 }
664
665 return 0;
666}
667
668/**
669 * amdgpu_irq_remove_domain - remove the IRQ domain
670 *
671 * @adev: amdgpu device pointer
672 *
673 * Removes the IRQ domain for GPU interrupt sources
674 * that may be driven by another driver (e.g., ACP).
675 */
676void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
677{
678 if (adev->irq.domain) {
679 irq_domain_remove(adev->irq.domain);
680 adev->irq.domain = NULL;
681 }
682}
683
684/**
685 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
686 *
687 * @adev: amdgpu device pointer
688 * @src_id: IH source id
689 *
690 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
691 * Use this for components that generate a GPU interrupt, but are driven
692 * by a different driver (e.g., ACP).
693 *
694 * Returns:
695 * Linux IRQ
696 */
697unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
698{
699 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
700
701 return adev->irq.virq[src_id];
702}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29/**
30 * DOC: Interrupt Handling
31 *
32 * Interrupts generated within GPU hardware raise interrupt requests that are
33 * passed to amdgpu IRQ handler which is responsible for detecting source and
34 * type of the interrupt and dispatching matching handlers. If handling an
35 * interrupt requires calling kernel functions that may sleep processing is
36 * dispatched to work handlers.
37 *
38 * If MSI functionality is not disabled by module parameter then MSI
39 * support will be enabled.
40 *
41 * For GPU interrupt sources that may be driven by another driver, IRQ domain
42 * support is used (with mapping between virtual and hardware IRQs).
43 */
44
45#include <linux/irq.h>
46#include <linux/pci.h>
47
48#include <drm/drm_crtc_helper.h>
49#include <drm/drm_irq.h>
50#include <drm/drm_vblank.h>
51#include <drm/amdgpu_drm.h>
52#include <drm/drm_drv.h>
53#include "amdgpu.h"
54#include "amdgpu_ih.h"
55#include "atom.h"
56#include "amdgpu_connectors.h"
57#include "amdgpu_trace.h"
58#include "amdgpu_amdkfd.h"
59#include "amdgpu_ras.h"
60
61#include <linux/pm_runtime.h>
62
63#ifdef CONFIG_DRM_AMD_DC
64#include "amdgpu_dm_irq.h"
65#endif
66
67#define AMDGPU_WAIT_IDLE_TIMEOUT 200
68
69const char *soc15_ih_clientid_name[] = {
70 "IH",
71 "SDMA2 or ACP",
72 "ATHUB",
73 "BIF",
74 "SDMA3 or DCE",
75 "SDMA4 or ISP",
76 "VMC1 or PCIE0",
77 "RLC",
78 "SDMA0",
79 "SDMA1",
80 "SE0SH",
81 "SE1SH",
82 "SE2SH",
83 "SE3SH",
84 "VCN1 or UVD1",
85 "THM",
86 "VCN or UVD",
87 "SDMA5 or VCE0",
88 "VMC",
89 "SDMA6 or XDMA",
90 "GRBM_CP",
91 "ATS",
92 "ROM_SMUIO",
93 "DF",
94 "SDMA7 or VCE1",
95 "PWR",
96 "reserved",
97 "UTCL2",
98 "EA",
99 "UTCL2LOG",
100 "MP0",
101 "MP1"
102};
103
104/**
105 * amdgpu_hotplug_work_func - work handler for display hotplug event
106 *
107 * @work: work struct pointer
108 *
109 * This is the hotplug event work handler (all ASICs).
110 * The work gets scheduled from the IRQ handler if there
111 * was a hotplug interrupt. It walks through the connector table
112 * and calls hotplug handler for each connector. After this, it sends
113 * a DRM hotplug event to alert userspace.
114 *
115 * This design approach is required in order to defer hotplug event handling
116 * from the IRQ handler to a work handler because hotplug handler has to use
117 * mutexes which cannot be locked in an IRQ handler (since &mutex_lock may
118 * sleep).
119 */
120static void amdgpu_hotplug_work_func(struct work_struct *work)
121{
122 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
123 hotplug_work);
124 struct drm_device *dev = adev_to_drm(adev);
125 struct drm_mode_config *mode_config = &dev->mode_config;
126 struct drm_connector *connector;
127 struct drm_connector_list_iter iter;
128
129 mutex_lock(&mode_config->mutex);
130 drm_connector_list_iter_begin(dev, &iter);
131 drm_for_each_connector_iter(connector, &iter)
132 amdgpu_connector_hotplug(connector);
133 drm_connector_list_iter_end(&iter);
134 mutex_unlock(&mode_config->mutex);
135 /* Just fire off a uevent and let userspace tell us what to do */
136 drm_helper_hpd_irq_event(dev);
137}
138
139/**
140 * amdgpu_irq_disable_all - disable *all* interrupts
141 *
142 * @adev: amdgpu device pointer
143 *
144 * Disable all types of interrupts from all sources.
145 */
146void amdgpu_irq_disable_all(struct amdgpu_device *adev)
147{
148 unsigned long irqflags;
149 unsigned i, j, k;
150 int r;
151
152 spin_lock_irqsave(&adev->irq.lock, irqflags);
153 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
154 if (!adev->irq.client[i].sources)
155 continue;
156
157 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
158 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
159
160 if (!src || !src->funcs->set || !src->num_types)
161 continue;
162
163 for (k = 0; k < src->num_types; ++k) {
164 atomic_set(&src->enabled_types[k], 0);
165 r = src->funcs->set(adev, src, k,
166 AMDGPU_IRQ_STATE_DISABLE);
167 if (r)
168 DRM_ERROR("error disabling interrupt (%d)\n",
169 r);
170 }
171 }
172 }
173 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
174}
175
176/**
177 * amdgpu_irq_handler - IRQ handler
178 *
179 * @irq: IRQ number (unused)
180 * @arg: pointer to DRM device
181 *
182 * IRQ handler for amdgpu driver (all ASICs).
183 *
184 * Returns:
185 * result of handling the IRQ, as defined by &irqreturn_t
186 */
187irqreturn_t amdgpu_irq_handler(int irq, void *arg)
188{
189 struct drm_device *dev = (struct drm_device *) arg;
190 struct amdgpu_device *adev = drm_to_adev(dev);
191 irqreturn_t ret;
192
193 ret = amdgpu_ih_process(adev, &adev->irq.ih);
194 if (ret == IRQ_HANDLED)
195 pm_runtime_mark_last_busy(dev->dev);
196
197 /* For the hardware that cannot enable bif ring for both ras_controller_irq
198 * and ras_err_evnet_athub_irq ih cookies, the driver has to poll status
199 * register to check whether the interrupt is triggered or not, and properly
200 * ack the interrupt if it is there
201 */
202 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF)) {
203 if (adev->nbio.ras_funcs &&
204 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring)
205 adev->nbio.ras_funcs->handle_ras_controller_intr_no_bifring(adev);
206
207 if (adev->nbio.ras_funcs &&
208 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring)
209 adev->nbio.ras_funcs->handle_ras_err_event_athub_intr_no_bifring(adev);
210 }
211
212 return ret;
213}
214
215/**
216 * amdgpu_irq_handle_ih1 - kick of processing for IH1
217 *
218 * @work: work structure in struct amdgpu_irq
219 *
220 * Kick of processing IH ring 1.
221 */
222static void amdgpu_irq_handle_ih1(struct work_struct *work)
223{
224 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
225 irq.ih1_work);
226
227 amdgpu_ih_process(adev, &adev->irq.ih1);
228}
229
230/**
231 * amdgpu_irq_handle_ih2 - kick of processing for IH2
232 *
233 * @work: work structure in struct amdgpu_irq
234 *
235 * Kick of processing IH ring 2.
236 */
237static void amdgpu_irq_handle_ih2(struct work_struct *work)
238{
239 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
240 irq.ih2_work);
241
242 amdgpu_ih_process(adev, &adev->irq.ih2);
243}
244
245/**
246 * amdgpu_irq_handle_ih_soft - kick of processing for ih_soft
247 *
248 * @work: work structure in struct amdgpu_irq
249 *
250 * Kick of processing IH soft ring.
251 */
252static void amdgpu_irq_handle_ih_soft(struct work_struct *work)
253{
254 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
255 irq.ih_soft_work);
256
257 amdgpu_ih_process(adev, &adev->irq.ih_soft);
258}
259
260/**
261 * amdgpu_msi_ok - check whether MSI functionality is enabled
262 *
263 * @adev: amdgpu device pointer (unused)
264 *
265 * Checks whether MSI functionality has been disabled via module parameter
266 * (all ASICs).
267 *
268 * Returns:
269 * *true* if MSIs are allowed to be enabled or *false* otherwise
270 */
271static bool amdgpu_msi_ok(struct amdgpu_device *adev)
272{
273 if (amdgpu_msi == 1)
274 return true;
275 else if (amdgpu_msi == 0)
276 return false;
277
278 return true;
279}
280
281static void amdgpu_restore_msix(struct amdgpu_device *adev)
282{
283 u16 ctrl;
284
285 pci_read_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
286 if (!(ctrl & PCI_MSIX_FLAGS_ENABLE))
287 return;
288
289 /* VF FLR */
290 ctrl &= ~PCI_MSIX_FLAGS_ENABLE;
291 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
292 ctrl |= PCI_MSIX_FLAGS_ENABLE;
293 pci_write_config_word(adev->pdev, adev->pdev->msix_cap + PCI_MSIX_FLAGS, ctrl);
294}
295
296/**
297 * amdgpu_irq_init - initialize interrupt handling
298 *
299 * @adev: amdgpu device pointer
300 *
301 * Sets up work functions for hotplug and reset interrupts, enables MSI
302 * functionality, initializes vblank, hotplug and reset interrupt handling.
303 *
304 * Returns:
305 * 0 on success or error code on failure
306 */
307int amdgpu_irq_init(struct amdgpu_device *adev)
308{
309 int r = 0;
310
311 spin_lock_init(&adev->irq.lock);
312
313 /* Enable MSI if not disabled by module parameter */
314 adev->irq.msi_enabled = false;
315
316 if (amdgpu_msi_ok(adev)) {
317 int nvec = pci_msix_vec_count(adev->pdev);
318 unsigned int flags;
319
320 if (nvec <= 0) {
321 flags = PCI_IRQ_MSI;
322 } else {
323 flags = PCI_IRQ_MSI | PCI_IRQ_MSIX;
324 }
325 /* we only need one vector */
326 nvec = pci_alloc_irq_vectors(adev->pdev, 1, 1, flags);
327 if (nvec > 0) {
328 adev->irq.msi_enabled = true;
329 dev_dbg(adev->dev, "using MSI/MSI-X.\n");
330 }
331 }
332
333 if (!amdgpu_device_has_dc_support(adev)) {
334 if (!adev->enable_virtual_display)
335 /* Disable vblank IRQs aggressively for power-saving */
336 /* XXX: can this be enabled for DC? */
337 adev_to_drm(adev)->vblank_disable_immediate = true;
338
339 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
340 if (r)
341 return r;
342
343 /* Pre-DCE11 */
344 INIT_WORK(&adev->hotplug_work,
345 amdgpu_hotplug_work_func);
346 }
347
348 INIT_WORK(&adev->irq.ih1_work, amdgpu_irq_handle_ih1);
349 INIT_WORK(&adev->irq.ih2_work, amdgpu_irq_handle_ih2);
350 INIT_WORK(&adev->irq.ih_soft_work, amdgpu_irq_handle_ih_soft);
351
352 adev->irq.installed = true;
353 /* Use vector 0 for MSI-X */
354 r = drm_irq_install(adev_to_drm(adev), pci_irq_vector(adev->pdev, 0));
355 if (r) {
356 adev->irq.installed = false;
357 if (!amdgpu_device_has_dc_support(adev))
358 flush_work(&adev->hotplug_work);
359 return r;
360 }
361 adev_to_drm(adev)->max_vblank_count = 0x00ffffff;
362
363 DRM_DEBUG("amdgpu: irq initialized.\n");
364 return 0;
365}
366
367
368void amdgpu_irq_fini_hw(struct amdgpu_device *adev)
369{
370 if (adev->irq.installed) {
371 drm_irq_uninstall(&adev->ddev);
372 adev->irq.installed = false;
373 if (adev->irq.msi_enabled)
374 pci_free_irq_vectors(adev->pdev);
375
376 if (!amdgpu_device_has_dc_support(adev))
377 flush_work(&adev->hotplug_work);
378 }
379
380 amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft);
381 amdgpu_ih_ring_fini(adev, &adev->irq.ih);
382 amdgpu_ih_ring_fini(adev, &adev->irq.ih1);
383 amdgpu_ih_ring_fini(adev, &adev->irq.ih2);
384}
385
386/**
387 * amdgpu_irq_fini - shut down interrupt handling
388 *
389 * @adev: amdgpu device pointer
390 *
391 * Tears down work functions for hotplug and reset interrupts, disables MSI
392 * functionality, shuts down vblank, hotplug and reset interrupt handling,
393 * turns off interrupts from all sources (all ASICs).
394 */
395void amdgpu_irq_fini_sw(struct amdgpu_device *adev)
396{
397 unsigned i, j;
398
399 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
400 if (!adev->irq.client[i].sources)
401 continue;
402
403 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
404 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
405
406 if (!src)
407 continue;
408
409 kfree(src->enabled_types);
410 src->enabled_types = NULL;
411 }
412 kfree(adev->irq.client[i].sources);
413 adev->irq.client[i].sources = NULL;
414 }
415}
416
417/**
418 * amdgpu_irq_add_id - register IRQ source
419 *
420 * @adev: amdgpu device pointer
421 * @client_id: client id
422 * @src_id: source id
423 * @source: IRQ source pointer
424 *
425 * Registers IRQ source on a client.
426 *
427 * Returns:
428 * 0 on success or error code otherwise
429 */
430int amdgpu_irq_add_id(struct amdgpu_device *adev,
431 unsigned client_id, unsigned src_id,
432 struct amdgpu_irq_src *source)
433{
434 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX)
435 return -EINVAL;
436
437 if (src_id >= AMDGPU_MAX_IRQ_SRC_ID)
438 return -EINVAL;
439
440 if (!source->funcs)
441 return -EINVAL;
442
443 if (!adev->irq.client[client_id].sources) {
444 adev->irq.client[client_id].sources =
445 kcalloc(AMDGPU_MAX_IRQ_SRC_ID,
446 sizeof(struct amdgpu_irq_src *),
447 GFP_KERNEL);
448 if (!adev->irq.client[client_id].sources)
449 return -ENOMEM;
450 }
451
452 if (adev->irq.client[client_id].sources[src_id] != NULL)
453 return -EINVAL;
454
455 if (source->num_types && !source->enabled_types) {
456 atomic_t *types;
457
458 types = kcalloc(source->num_types, sizeof(atomic_t),
459 GFP_KERNEL);
460 if (!types)
461 return -ENOMEM;
462
463 source->enabled_types = types;
464 }
465
466 adev->irq.client[client_id].sources[src_id] = source;
467 return 0;
468}
469
470/**
471 * amdgpu_irq_dispatch - dispatch IRQ to IP blocks
472 *
473 * @adev: amdgpu device pointer
474 * @ih: interrupt ring instance
475 *
476 * Dispatches IRQ to IP blocks.
477 */
478void amdgpu_irq_dispatch(struct amdgpu_device *adev,
479 struct amdgpu_ih_ring *ih)
480{
481 u32 ring_index = ih->rptr >> 2;
482 struct amdgpu_iv_entry entry;
483 unsigned client_id, src_id;
484 struct amdgpu_irq_src *src;
485 bool handled = false;
486 int r;
487
488 entry.ih = ih;
489 entry.iv_entry = (const uint32_t *)&ih->ring[ring_index];
490 amdgpu_ih_decode_iv(adev, &entry);
491
492 trace_amdgpu_iv(ih - &adev->irq.ih, &entry);
493
494 client_id = entry.client_id;
495 src_id = entry.src_id;
496
497 if (client_id >= AMDGPU_IRQ_CLIENTID_MAX) {
498 DRM_DEBUG("Invalid client_id in IV: %d\n", client_id);
499
500 } else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
501 DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
502
503 } else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
504 adev->irq.virq[src_id]) {
505 generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id));
506
507 } else if (!adev->irq.client[client_id].sources) {
508 DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n",
509 client_id, src_id);
510
511 } else if ((src = adev->irq.client[client_id].sources[src_id])) {
512 r = src->funcs->process(adev, src, &entry);
513 if (r < 0)
514 DRM_ERROR("error processing interrupt (%d)\n", r);
515 else if (r)
516 handled = true;
517
518 } else {
519 DRM_DEBUG("Unhandled interrupt src_id: %d\n", src_id);
520 }
521
522 /* Send it to amdkfd as well if it isn't already handled */
523 if (!handled)
524 amdgpu_amdkfd_interrupt(adev, entry.iv_entry);
525}
526
527/**
528 * amdgpu_irq_delegate - delegate IV to soft IH ring
529 *
530 * @adev: amdgpu device pointer
531 * @entry: IV entry
532 * @num_dw: size of IV
533 *
534 * Delegate the IV to the soft IH ring and schedule processing of it. Used
535 * if the hardware delegation to IH1 or IH2 doesn't work for some reason.
536 */
537void amdgpu_irq_delegate(struct amdgpu_device *adev,
538 struct amdgpu_iv_entry *entry,
539 unsigned int num_dw)
540{
541 amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw);
542 schedule_work(&adev->irq.ih_soft_work);
543}
544
545/**
546 * amdgpu_irq_update - update hardware interrupt state
547 *
548 * @adev: amdgpu device pointer
549 * @src: interrupt source pointer
550 * @type: type of interrupt
551 *
552 * Updates interrupt state for the specific source (all ASICs).
553 */
554int amdgpu_irq_update(struct amdgpu_device *adev,
555 struct amdgpu_irq_src *src, unsigned type)
556{
557 unsigned long irqflags;
558 enum amdgpu_interrupt_state state;
559 int r;
560
561 spin_lock_irqsave(&adev->irq.lock, irqflags);
562
563 /* We need to determine after taking the lock, otherwise
564 we might disable just enabled interrupts again */
565 if (amdgpu_irq_enabled(adev, src, type))
566 state = AMDGPU_IRQ_STATE_ENABLE;
567 else
568 state = AMDGPU_IRQ_STATE_DISABLE;
569
570 r = src->funcs->set(adev, src, type, state);
571 spin_unlock_irqrestore(&adev->irq.lock, irqflags);
572 return r;
573}
574
575/**
576 * amdgpu_irq_gpu_reset_resume_helper - update interrupt states on all sources
577 *
578 * @adev: amdgpu device pointer
579 *
580 * Updates state of all types of interrupts on all sources on resume after
581 * reset.
582 */
583void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev)
584{
585 int i, j, k;
586
587 if (amdgpu_sriov_vf(adev))
588 amdgpu_restore_msix(adev);
589
590 for (i = 0; i < AMDGPU_IRQ_CLIENTID_MAX; ++i) {
591 if (!adev->irq.client[i].sources)
592 continue;
593
594 for (j = 0; j < AMDGPU_MAX_IRQ_SRC_ID; ++j) {
595 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j];
596
597 if (!src || !src->funcs || !src->funcs->set)
598 continue;
599 for (k = 0; k < src->num_types; k++)
600 amdgpu_irq_update(adev, src, k);
601 }
602 }
603}
604
605/**
606 * amdgpu_irq_get - enable interrupt
607 *
608 * @adev: amdgpu device pointer
609 * @src: interrupt source pointer
610 * @type: type of interrupt
611 *
612 * Enables specified type of interrupt on the specified source (all ASICs).
613 *
614 * Returns:
615 * 0 on success or error code otherwise
616 */
617int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
618 unsigned type)
619{
620 if (!adev_to_drm(adev)->irq_enabled)
621 return -ENOENT;
622
623 if (type >= src->num_types)
624 return -EINVAL;
625
626 if (!src->enabled_types || !src->funcs->set)
627 return -EINVAL;
628
629 if (atomic_inc_return(&src->enabled_types[type]) == 1)
630 return amdgpu_irq_update(adev, src, type);
631
632 return 0;
633}
634
635/**
636 * amdgpu_irq_put - disable interrupt
637 *
638 * @adev: amdgpu device pointer
639 * @src: interrupt source pointer
640 * @type: type of interrupt
641 *
642 * Enables specified type of interrupt on the specified source (all ASICs).
643 *
644 * Returns:
645 * 0 on success or error code otherwise
646 */
647int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
648 unsigned type)
649{
650 if (!adev_to_drm(adev)->irq_enabled)
651 return -ENOENT;
652
653 if (type >= src->num_types)
654 return -EINVAL;
655
656 if (!src->enabled_types || !src->funcs->set)
657 return -EINVAL;
658
659 if (atomic_dec_and_test(&src->enabled_types[type]))
660 return amdgpu_irq_update(adev, src, type);
661
662 return 0;
663}
664
665/**
666 * amdgpu_irq_enabled - check whether interrupt is enabled or not
667 *
668 * @adev: amdgpu device pointer
669 * @src: interrupt source pointer
670 * @type: type of interrupt
671 *
672 * Checks whether the given type of interrupt is enabled on the given source.
673 *
674 * Returns:
675 * *true* if interrupt is enabled, *false* if interrupt is disabled or on
676 * invalid parameters
677 */
678bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src,
679 unsigned type)
680{
681 if (!adev_to_drm(adev)->irq_enabled)
682 return false;
683
684 if (type >= src->num_types)
685 return false;
686
687 if (!src->enabled_types || !src->funcs->set)
688 return false;
689
690 return !!atomic_read(&src->enabled_types[type]);
691}
692
693/* XXX: Generic IRQ handling */
694static void amdgpu_irq_mask(struct irq_data *irqd)
695{
696 /* XXX */
697}
698
699static void amdgpu_irq_unmask(struct irq_data *irqd)
700{
701 /* XXX */
702}
703
704/* amdgpu hardware interrupt chip descriptor */
705static struct irq_chip amdgpu_irq_chip = {
706 .name = "amdgpu-ih",
707 .irq_mask = amdgpu_irq_mask,
708 .irq_unmask = amdgpu_irq_unmask,
709};
710
711/**
712 * amdgpu_irqdomain_map - create mapping between virtual and hardware IRQ numbers
713 *
714 * @d: amdgpu IRQ domain pointer (unused)
715 * @irq: virtual IRQ number
716 * @hwirq: hardware irq number
717 *
718 * Current implementation assigns simple interrupt handler to the given virtual
719 * IRQ.
720 *
721 * Returns:
722 * 0 on success or error code otherwise
723 */
724static int amdgpu_irqdomain_map(struct irq_domain *d,
725 unsigned int irq, irq_hw_number_t hwirq)
726{
727 if (hwirq >= AMDGPU_MAX_IRQ_SRC_ID)
728 return -EPERM;
729
730 irq_set_chip_and_handler(irq,
731 &amdgpu_irq_chip, handle_simple_irq);
732 return 0;
733}
734
735/* Implementation of methods for amdgpu IRQ domain */
736static const struct irq_domain_ops amdgpu_hw_irqdomain_ops = {
737 .map = amdgpu_irqdomain_map,
738};
739
740/**
741 * amdgpu_irq_add_domain - create a linear IRQ domain
742 *
743 * @adev: amdgpu device pointer
744 *
745 * Creates an IRQ domain for GPU interrupt sources
746 * that may be driven by another driver (e.g., ACP).
747 *
748 * Returns:
749 * 0 on success or error code otherwise
750 */
751int amdgpu_irq_add_domain(struct amdgpu_device *adev)
752{
753 adev->irq.domain = irq_domain_add_linear(NULL, AMDGPU_MAX_IRQ_SRC_ID,
754 &amdgpu_hw_irqdomain_ops, adev);
755 if (!adev->irq.domain) {
756 DRM_ERROR("GPU irq add domain failed\n");
757 return -ENODEV;
758 }
759
760 return 0;
761}
762
763/**
764 * amdgpu_irq_remove_domain - remove the IRQ domain
765 *
766 * @adev: amdgpu device pointer
767 *
768 * Removes the IRQ domain for GPU interrupt sources
769 * that may be driven by another driver (e.g., ACP).
770 */
771void amdgpu_irq_remove_domain(struct amdgpu_device *adev)
772{
773 if (adev->irq.domain) {
774 irq_domain_remove(adev->irq.domain);
775 adev->irq.domain = NULL;
776 }
777}
778
779/**
780 * amdgpu_irq_create_mapping - create mapping between domain Linux IRQs
781 *
782 * @adev: amdgpu device pointer
783 * @src_id: IH source id
784 *
785 * Creates mapping between a domain IRQ (GPU IH src id) and a Linux IRQ
786 * Use this for components that generate a GPU interrupt, but are driven
787 * by a different driver (e.g., ACP).
788 *
789 * Returns:
790 * Linux IRQ
791 */
792unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id)
793{
794 adev->irq.virq[src_id] = irq_create_mapping(adev->irq.domain, src_id);
795
796 return adev->irq.virq[src_id];
797}