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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu_amdkfd.h"
24#include "amd_shared.h"
25
26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "amdgpu_dma_buf.h"
29#include <linux/module.h>
30#include <linux/dma-buf.h>
31#include "amdgpu_xgmi.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34/* Total memory size in system memory and all GPU VRAM. Used to
35 * estimate worst case amount of memory to reserve for page tables
36 */
37uint64_t amdgpu_amdkfd_total_mem_size;
38
39int amdgpu_amdkfd_init(void)
40{
41 struct sysinfo si;
42 int ret;
43
44 si_meminfo(&si);
45 amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;
46 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
47
48#ifdef CONFIG_HSA_AMD
49 ret = kgd2kfd_init();
50 amdgpu_amdkfd_gpuvm_init_mem_limits();
51#else
52 ret = -ENOENT;
53#endif
54
55 return ret;
56}
57
58void amdgpu_amdkfd_fini(void)
59{
60 kgd2kfd_exit();
61}
62
63void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
64{
65 bool vf = amdgpu_sriov_vf(adev);
66
67 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
68 adev->pdev, adev->asic_type, vf);
69
70 if (adev->kfd.dev)
71 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
72}
73
74/**
75 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
76 * setup amdkfd
77 *
78 * @adev: amdgpu_device pointer
79 * @aperture_base: output returning doorbell aperture base physical address
80 * @aperture_size: output returning doorbell aperture size in bytes
81 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
82 *
83 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
84 * takes doorbells required for its own rings and reports the setup to amdkfd.
85 * amdgpu reserved doorbells are at the start of the doorbell aperture.
86 */
87static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
88 phys_addr_t *aperture_base,
89 size_t *aperture_size,
90 size_t *start_offset)
91{
92 /*
93 * The first num_doorbells are used by amdgpu.
94 * amdkfd takes whatever's left in the aperture.
95 */
96 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
97 *aperture_base = adev->doorbell.base;
98 *aperture_size = adev->doorbell.size;
99 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
100 } else {
101 *aperture_base = 0;
102 *aperture_size = 0;
103 *start_offset = 0;
104 }
105}
106
107void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
108{
109 int i;
110 int last_valid_bit;
111
112 if (adev->kfd.dev) {
113 struct kgd2kfd_shared_resources gpu_resources = {
114 .compute_vmid_bitmap =
115 ((1 << AMDGPU_NUM_VMID) - 1) -
116 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
117 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
118 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
119 .gpuvm_size = min(adev->vm_manager.max_pfn
120 << AMDGPU_GPU_PAGE_SHIFT,
121 AMDGPU_GMC_HOLE_START),
122 .drm_render_minor = adev->ddev->render->index,
123 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
124
125 };
126
127 /* this is going to have a few of the MSBs set that we need to
128 * clear
129 */
130 bitmap_complement(gpu_resources.cp_queue_bitmap,
131 adev->gfx.mec.queue_bitmap,
132 KGD_MAX_QUEUES);
133
134 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
135 * nbits is not compile time constant
136 */
137 last_valid_bit = 1 /* only first MEC can have compute queues */
138 * adev->gfx.mec.num_pipe_per_mec
139 * adev->gfx.mec.num_queue_per_pipe;
140 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
141 clear_bit(i, gpu_resources.cp_queue_bitmap);
142
143 amdgpu_doorbell_get_kfd_info(adev,
144 &gpu_resources.doorbell_physical_address,
145 &gpu_resources.doorbell_aperture_size,
146 &gpu_resources.doorbell_start_offset);
147
148 /* Since SOC15, BIF starts to statically use the
149 * lower 12 bits of doorbell addresses for routing
150 * based on settings in registers like
151 * SDMA0_DOORBELL_RANGE etc..
152 * In order to route a doorbell to CP engine, the lower
153 * 12 bits of its address has to be outside the range
154 * set for SDMA, VCN, and IH blocks.
155 */
156 if (adev->asic_type >= CHIP_VEGA10) {
157 gpu_resources.non_cp_doorbells_start =
158 adev->doorbell_index.first_non_cp;
159 gpu_resources.non_cp_doorbells_end =
160 adev->doorbell_index.last_non_cp;
161 }
162
163 kgd2kfd_device_init(adev->kfd.dev, adev->ddev, &gpu_resources);
164 }
165}
166
167void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
168{
169 if (adev->kfd.dev) {
170 kgd2kfd_device_exit(adev->kfd.dev);
171 adev->kfd.dev = NULL;
172 }
173}
174
175void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
176 const void *ih_ring_entry)
177{
178 if (adev->kfd.dev)
179 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
180}
181
182void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
183{
184 if (adev->kfd.dev)
185 kgd2kfd_suspend(adev->kfd.dev, run_pm);
186}
187
188int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
189{
190 int r = 0;
191
192 if (adev->kfd.dev)
193 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
194
195 return r;
196}
197
198int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
199{
200 int r = 0;
201
202 if (adev->kfd.dev)
203 r = kgd2kfd_pre_reset(adev->kfd.dev);
204
205 return r;
206}
207
208int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
209{
210 int r = 0;
211
212 if (adev->kfd.dev)
213 r = kgd2kfd_post_reset(adev->kfd.dev);
214
215 return r;
216}
217
218void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
219{
220 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
221
222 if (amdgpu_device_should_recover_gpu(adev))
223 amdgpu_device_gpu_recover(adev, NULL);
224}
225
226int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
227 void **mem_obj, uint64_t *gpu_addr,
228 void **cpu_ptr, bool cp_mqd_gfx9)
229{
230 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
231 struct amdgpu_bo *bo = NULL;
232 struct amdgpu_bo_param bp;
233 int r;
234 void *cpu_ptr_tmp = NULL;
235
236 memset(&bp, 0, sizeof(bp));
237 bp.size = size;
238 bp.byte_align = PAGE_SIZE;
239 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
240 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
241 bp.type = ttm_bo_type_kernel;
242 bp.resv = NULL;
243
244 if (cp_mqd_gfx9)
245 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
246
247 r = amdgpu_bo_create(adev, &bp, &bo);
248 if (r) {
249 dev_err(adev->dev,
250 "failed to allocate BO for amdkfd (%d)\n", r);
251 return r;
252 }
253
254 /* map the buffer */
255 r = amdgpu_bo_reserve(bo, true);
256 if (r) {
257 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
258 goto allocate_mem_reserve_bo_failed;
259 }
260
261 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
262 if (r) {
263 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
264 goto allocate_mem_pin_bo_failed;
265 }
266
267 r = amdgpu_ttm_alloc_gart(&bo->tbo);
268 if (r) {
269 dev_err(adev->dev, "%p bind failed\n", bo);
270 goto allocate_mem_kmap_bo_failed;
271 }
272
273 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
274 if (r) {
275 dev_err(adev->dev,
276 "(%d) failed to map bo to kernel for amdkfd\n", r);
277 goto allocate_mem_kmap_bo_failed;
278 }
279
280 *mem_obj = bo;
281 *gpu_addr = amdgpu_bo_gpu_offset(bo);
282 *cpu_ptr = cpu_ptr_tmp;
283
284 amdgpu_bo_unreserve(bo);
285
286 return 0;
287
288allocate_mem_kmap_bo_failed:
289 amdgpu_bo_unpin(bo);
290allocate_mem_pin_bo_failed:
291 amdgpu_bo_unreserve(bo);
292allocate_mem_reserve_bo_failed:
293 amdgpu_bo_unref(&bo);
294
295 return r;
296}
297
298void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
299{
300 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
301
302 amdgpu_bo_reserve(bo, true);
303 amdgpu_bo_kunmap(bo);
304 amdgpu_bo_unpin(bo);
305 amdgpu_bo_unreserve(bo);
306 amdgpu_bo_unref(&(bo));
307}
308
309int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
310 void **mem_obj)
311{
312 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
313 struct amdgpu_bo *bo = NULL;
314 struct amdgpu_bo_param bp;
315 int r;
316
317 memset(&bp, 0, sizeof(bp));
318 bp.size = size;
319 bp.byte_align = 1;
320 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
321 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
322 bp.type = ttm_bo_type_device;
323 bp.resv = NULL;
324
325 r = amdgpu_bo_create(adev, &bp, &bo);
326 if (r) {
327 dev_err(adev->dev,
328 "failed to allocate gws BO for amdkfd (%d)\n", r);
329 return r;
330 }
331
332 *mem_obj = bo;
333 return 0;
334}
335
336void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
337{
338 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
339
340 amdgpu_bo_unref(&bo);
341}
342
343uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
344 enum kgd_engine_type type)
345{
346 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
347
348 switch (type) {
349 case KGD_ENGINE_PFP:
350 return adev->gfx.pfp_fw_version;
351
352 case KGD_ENGINE_ME:
353 return adev->gfx.me_fw_version;
354
355 case KGD_ENGINE_CE:
356 return adev->gfx.ce_fw_version;
357
358 case KGD_ENGINE_MEC1:
359 return adev->gfx.mec_fw_version;
360
361 case KGD_ENGINE_MEC2:
362 return adev->gfx.mec2_fw_version;
363
364 case KGD_ENGINE_RLC:
365 return adev->gfx.rlc_fw_version;
366
367 case KGD_ENGINE_SDMA1:
368 return adev->sdma.instance[0].fw_version;
369
370 case KGD_ENGINE_SDMA2:
371 return adev->sdma.instance[1].fw_version;
372
373 default:
374 return 0;
375 }
376
377 return 0;
378}
379
380void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
381 struct kfd_local_mem_info *mem_info)
382{
383 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
384 uint64_t address_mask = adev->dev->dma_mask ? ~*adev->dev->dma_mask :
385 ~((1ULL << 32) - 1);
386 resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size;
387
388 memset(mem_info, 0, sizeof(*mem_info));
389 if (!(adev->gmc.aper_base & address_mask || aper_limit & address_mask)) {
390 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
391 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
392 adev->gmc.visible_vram_size;
393 } else {
394 mem_info->local_mem_size_public = 0;
395 mem_info->local_mem_size_private = adev->gmc.real_vram_size;
396 }
397 mem_info->vram_width = adev->gmc.vram_width;
398
399 pr_debug("Address base: %pap limit %pap public 0x%llx private 0x%llx\n",
400 &adev->gmc.aper_base, &aper_limit,
401 mem_info->local_mem_size_public,
402 mem_info->local_mem_size_private);
403
404 if (amdgpu_sriov_vf(adev))
405 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
406 else if (adev->pm.dpm_enabled) {
407 if (amdgpu_emu_mode == 1)
408 mem_info->mem_clk_max = 0;
409 else
410 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
411 } else
412 mem_info->mem_clk_max = 100;
413}
414
415uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
416{
417 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
418
419 if (adev->gfx.funcs->get_gpu_clock_counter)
420 return adev->gfx.funcs->get_gpu_clock_counter(adev);
421 return 0;
422}
423
424uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
425{
426 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
427
428 /* the sclk is in quantas of 10kHz */
429 if (amdgpu_sriov_vf(adev))
430 return adev->clock.default_sclk / 100;
431 else if (adev->pm.dpm_enabled)
432 return amdgpu_dpm_get_sclk(adev, false) / 100;
433 else
434 return 100;
435}
436
437void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
438{
439 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
440 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
441
442 memset(cu_info, 0, sizeof(*cu_info));
443 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
444 return;
445
446 cu_info->cu_active_number = acu_info.number;
447 cu_info->cu_ao_mask = acu_info.ao_cu_mask;
448 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
449 sizeof(acu_info.bitmap));
450 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
451 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
452 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
453 cu_info->simd_per_cu = acu_info.simd_per_cu;
454 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
455 cu_info->wave_front_size = acu_info.wave_front_size;
456 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
457 cu_info->lds_size = acu_info.lds_size;
458}
459
460int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
461 struct kgd_dev **dma_buf_kgd,
462 uint64_t *bo_size, void *metadata_buffer,
463 size_t buffer_size, uint32_t *metadata_size,
464 uint32_t *flags)
465{
466 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
467 struct dma_buf *dma_buf;
468 struct drm_gem_object *obj;
469 struct amdgpu_bo *bo;
470 uint64_t metadata_flags;
471 int r = -EINVAL;
472
473 dma_buf = dma_buf_get(dma_buf_fd);
474 if (IS_ERR(dma_buf))
475 return PTR_ERR(dma_buf);
476
477 if (dma_buf->ops != &amdgpu_dmabuf_ops)
478 /* Can't handle non-graphics buffers */
479 goto out_put;
480
481 obj = dma_buf->priv;
482 if (obj->dev->driver != adev->ddev->driver)
483 /* Can't handle buffers from different drivers */
484 goto out_put;
485
486 adev = obj->dev->dev_private;
487 bo = gem_to_amdgpu_bo(obj);
488 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
489 AMDGPU_GEM_DOMAIN_GTT)))
490 /* Only VRAM and GTT BOs are supported */
491 goto out_put;
492
493 r = 0;
494 if (dma_buf_kgd)
495 *dma_buf_kgd = (struct kgd_dev *)adev;
496 if (bo_size)
497 *bo_size = amdgpu_bo_size(bo);
498 if (metadata_size)
499 *metadata_size = bo->metadata_size;
500 if (metadata_buffer)
501 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
502 metadata_size, &metadata_flags);
503 if (flags) {
504 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
505 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
506 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
507
508 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
509 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
510 }
511
512out_put:
513 dma_buf_put(dma_buf);
514 return r;
515}
516
517uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
518{
519 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
520
521 return amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
522}
523
524uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
525{
526 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
527
528 return adev->gmc.xgmi.hive_id;
529}
530
531uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
532{
533 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
534
535 return adev->unique_id;
536}
537
538uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
539{
540 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
541 struct amdgpu_device *adev = (struct amdgpu_device *)dst;
542 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
543
544 if (ret < 0) {
545 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
546 adev->gmc.xgmi.physical_node_id,
547 peer_adev->gmc.xgmi.physical_node_id, ret);
548 ret = 0;
549 }
550 return (uint8_t)ret;
551}
552
553uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
554{
555 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
556
557 return adev->rmmio_remap.bus_addr;
558}
559
560uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
561{
562 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
563
564 return adev->gds.gws_size;
565}
566
567uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
568{
569 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
570
571 return adev->rev_id;
572}
573
574int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
575 uint32_t vmid, uint64_t gpu_addr,
576 uint32_t *ib_cmd, uint32_t ib_len)
577{
578 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
579 struct amdgpu_job *job;
580 struct amdgpu_ib *ib;
581 struct amdgpu_ring *ring;
582 struct dma_fence *f = NULL;
583 int ret;
584
585 switch (engine) {
586 case KGD_ENGINE_MEC1:
587 ring = &adev->gfx.compute_ring[0];
588 break;
589 case KGD_ENGINE_SDMA1:
590 ring = &adev->sdma.instance[0].ring;
591 break;
592 case KGD_ENGINE_SDMA2:
593 ring = &adev->sdma.instance[1].ring;
594 break;
595 default:
596 pr_err("Invalid engine in IB submission: %d\n", engine);
597 ret = -EINVAL;
598 goto err;
599 }
600
601 ret = amdgpu_job_alloc(adev, 1, &job, NULL);
602 if (ret)
603 goto err;
604
605 ib = &job->ibs[0];
606 memset(ib, 0, sizeof(struct amdgpu_ib));
607
608 ib->gpu_addr = gpu_addr;
609 ib->ptr = ib_cmd;
610 ib->length_dw = ib_len;
611 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
612 job->vmid = vmid;
613
614 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
615 if (ret) {
616 DRM_ERROR("amdgpu: failed to schedule IB.\n");
617 goto err_ib_sched;
618 }
619
620 ret = dma_fence_wait(f, false);
621
622err_ib_sched:
623 dma_fence_put(f);
624 amdgpu_job_free(job);
625err:
626 return ret;
627}
628
629void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
630{
631 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
632
633 amdgpu_dpm_switch_power_profile(adev,
634 PP_SMC_POWER_PROFILE_COMPUTE,
635 !idle);
636}
637
638bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
639{
640 if (adev->kfd.dev)
641 return vmid >= adev->vm_manager.first_kfd_vmid;
642
643 return false;
644}
645
646int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
647{
648 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
649
650 if (adev->family == AMDGPU_FAMILY_AI) {
651 int i;
652
653 for (i = 0; i < adev->num_vmhubs; i++)
654 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
655 } else {
656 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
657 }
658
659 return 0;
660}
661
662int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid)
663{
664 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
665 const uint32_t flush_type = 0;
666 bool all_hub = false;
667
668 if (adev->family == AMDGPU_FAMILY_AI)
669 all_hub = true;
670
671 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
672}
673
674bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
675{
676 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
677
678 return adev->have_atomics_support;
679}
680
681#ifndef CONFIG_HSA_AMD
682bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm)
683{
684 return false;
685}
686
687void amdgpu_amdkfd_unreserve_memory_limit(struct amdgpu_bo *bo)
688{
689}
690
691int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo)
692{
693 return 0;
694}
695
696void amdgpu_amdkfd_gpuvm_destroy_cb(struct amdgpu_device *adev,
697 struct amdgpu_vm *vm)
698{
699}
700
701struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f)
702{
703 return NULL;
704}
705
706int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm)
707{
708 return 0;
709}
710
711struct kfd_dev *kgd2kfd_probe(struct kgd_dev *kgd, struct pci_dev *pdev,
712 unsigned int asic_type, bool vf)
713{
714 return NULL;
715}
716
717bool kgd2kfd_device_init(struct kfd_dev *kfd,
718 struct drm_device *ddev,
719 const struct kgd2kfd_shared_resources *gpu_resources)
720{
721 return false;
722}
723
724void kgd2kfd_device_exit(struct kfd_dev *kfd)
725{
726}
727
728void kgd2kfd_exit(void)
729{
730}
731
732void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm)
733{
734}
735
736int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm)
737{
738 return 0;
739}
740
741int kgd2kfd_pre_reset(struct kfd_dev *kfd)
742{
743 return 0;
744}
745
746int kgd2kfd_post_reset(struct kfd_dev *kfd)
747{
748 return 0;
749}
750
751void kgd2kfd_interrupt(struct kfd_dev *kfd, const void *ih_ring_entry)
752{
753}
754
755void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd)
756{
757}
758#endif
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include "amdgpu_amdkfd.h"
24#include "amd_shared.h"
25
26#include "amdgpu.h"
27#include "amdgpu_gfx.h"
28#include "amdgpu_dma_buf.h"
29#include <linux/module.h>
30#include <linux/dma-buf.h>
31#include "amdgpu_xgmi.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34/* Total memory size in system memory and all GPU VRAM. Used to
35 * estimate worst case amount of memory to reserve for page tables
36 */
37uint64_t amdgpu_amdkfd_total_mem_size;
38
39static bool kfd_initialized;
40
41int amdgpu_amdkfd_init(void)
42{
43 struct sysinfo si;
44 int ret;
45
46 si_meminfo(&si);
47 amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;
48 amdgpu_amdkfd_total_mem_size *= si.mem_unit;
49
50 ret = kgd2kfd_init();
51 amdgpu_amdkfd_gpuvm_init_mem_limits();
52 kfd_initialized = !ret;
53
54 return ret;
55}
56
57void amdgpu_amdkfd_fini(void)
58{
59 if (kfd_initialized) {
60 kgd2kfd_exit();
61 kfd_initialized = false;
62 }
63}
64
65void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
66{
67 bool vf = amdgpu_sriov_vf(adev);
68
69 if (!kfd_initialized)
70 return;
71
72 adev->kfd.dev = kgd2kfd_probe((struct kgd_dev *)adev,
73 adev->pdev, adev->asic_type, vf);
74
75 if (adev->kfd.dev)
76 amdgpu_amdkfd_total_mem_size += adev->gmc.real_vram_size;
77}
78
79/**
80 * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
81 * setup amdkfd
82 *
83 * @adev: amdgpu_device pointer
84 * @aperture_base: output returning doorbell aperture base physical address
85 * @aperture_size: output returning doorbell aperture size in bytes
86 * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
87 *
88 * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
89 * takes doorbells required for its own rings and reports the setup to amdkfd.
90 * amdgpu reserved doorbells are at the start of the doorbell aperture.
91 */
92static void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
93 phys_addr_t *aperture_base,
94 size_t *aperture_size,
95 size_t *start_offset)
96{
97 /*
98 * The first num_doorbells are used by amdgpu.
99 * amdkfd takes whatever's left in the aperture.
100 */
101 if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
102 *aperture_base = adev->doorbell.base;
103 *aperture_size = adev->doorbell.size;
104 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
105 } else {
106 *aperture_base = 0;
107 *aperture_size = 0;
108 *start_offset = 0;
109 }
110}
111
112void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
113{
114 int i;
115 int last_valid_bit;
116
117 if (adev->kfd.dev) {
118 struct kgd2kfd_shared_resources gpu_resources = {
119 .compute_vmid_bitmap =
120 ((1 << AMDGPU_NUM_VMID) - 1) -
121 ((1 << adev->vm_manager.first_kfd_vmid) - 1),
122 .num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
123 .num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe,
124 .gpuvm_size = min(adev->vm_manager.max_pfn
125 << AMDGPU_GPU_PAGE_SHIFT,
126 AMDGPU_GMC_HOLE_START),
127 .drm_render_minor = adev_to_drm(adev)->render->index,
128 .sdma_doorbell_idx = adev->doorbell_index.sdma_engine,
129
130 };
131
132 /* this is going to have a few of the MSBs set that we need to
133 * clear
134 */
135 bitmap_complement(gpu_resources.cp_queue_bitmap,
136 adev->gfx.mec.queue_bitmap,
137 KGD_MAX_QUEUES);
138
139 /* According to linux/bitmap.h we shouldn't use bitmap_clear if
140 * nbits is not compile time constant
141 */
142 last_valid_bit = 1 /* only first MEC can have compute queues */
143 * adev->gfx.mec.num_pipe_per_mec
144 * adev->gfx.mec.num_queue_per_pipe;
145 for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
146 clear_bit(i, gpu_resources.cp_queue_bitmap);
147
148 amdgpu_doorbell_get_kfd_info(adev,
149 &gpu_resources.doorbell_physical_address,
150 &gpu_resources.doorbell_aperture_size,
151 &gpu_resources.doorbell_start_offset);
152
153 /* Since SOC15, BIF starts to statically use the
154 * lower 12 bits of doorbell addresses for routing
155 * based on settings in registers like
156 * SDMA0_DOORBELL_RANGE etc..
157 * In order to route a doorbell to CP engine, the lower
158 * 12 bits of its address has to be outside the range
159 * set for SDMA, VCN, and IH blocks.
160 */
161 if (adev->asic_type >= CHIP_VEGA10) {
162 gpu_resources.non_cp_doorbells_start =
163 adev->doorbell_index.first_non_cp;
164 gpu_resources.non_cp_doorbells_end =
165 adev->doorbell_index.last_non_cp;
166 }
167
168 adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,
169 adev_to_drm(adev), &gpu_resources);
170 }
171}
172
173void amdgpu_amdkfd_device_fini_sw(struct amdgpu_device *adev)
174{
175 if (adev->kfd.dev) {
176 kgd2kfd_device_exit(adev->kfd.dev);
177 adev->kfd.dev = NULL;
178 }
179}
180
181void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
182 const void *ih_ring_entry)
183{
184 if (adev->kfd.dev)
185 kgd2kfd_interrupt(adev->kfd.dev, ih_ring_entry);
186}
187
188void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm)
189{
190 if (adev->kfd.dev)
191 kgd2kfd_suspend(adev->kfd.dev, run_pm);
192}
193
194int amdgpu_amdkfd_resume_iommu(struct amdgpu_device *adev)
195{
196 int r = 0;
197
198 if (adev->kfd.dev)
199 r = kgd2kfd_resume_iommu(adev->kfd.dev);
200
201 return r;
202}
203
204int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm)
205{
206 int r = 0;
207
208 if (adev->kfd.dev)
209 r = kgd2kfd_resume(adev->kfd.dev, run_pm);
210
211 return r;
212}
213
214int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev)
215{
216 int r = 0;
217
218 if (adev->kfd.dev)
219 r = kgd2kfd_pre_reset(adev->kfd.dev);
220
221 return r;
222}
223
224int amdgpu_amdkfd_post_reset(struct amdgpu_device *adev)
225{
226 int r = 0;
227
228 if (adev->kfd.dev)
229 r = kgd2kfd_post_reset(adev->kfd.dev);
230
231 return r;
232}
233
234void amdgpu_amdkfd_gpu_reset(struct kgd_dev *kgd)
235{
236 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
237
238 if (amdgpu_device_should_recover_gpu(adev))
239 amdgpu_device_gpu_recover(adev, NULL);
240}
241
242int amdgpu_amdkfd_alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
243 void **mem_obj, uint64_t *gpu_addr,
244 void **cpu_ptr, bool cp_mqd_gfx9)
245{
246 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
247 struct amdgpu_bo *bo = NULL;
248 struct amdgpu_bo_param bp;
249 int r;
250 void *cpu_ptr_tmp = NULL;
251
252 memset(&bp, 0, sizeof(bp));
253 bp.size = size;
254 bp.byte_align = PAGE_SIZE;
255 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
256 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
257 bp.type = ttm_bo_type_kernel;
258 bp.resv = NULL;
259 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
260
261 if (cp_mqd_gfx9)
262 bp.flags |= AMDGPU_GEM_CREATE_CP_MQD_GFX9;
263
264 r = amdgpu_bo_create(adev, &bp, &bo);
265 if (r) {
266 dev_err(adev->dev,
267 "failed to allocate BO for amdkfd (%d)\n", r);
268 return r;
269 }
270
271 /* map the buffer */
272 r = amdgpu_bo_reserve(bo, true);
273 if (r) {
274 dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
275 goto allocate_mem_reserve_bo_failed;
276 }
277
278 r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
279 if (r) {
280 dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
281 goto allocate_mem_pin_bo_failed;
282 }
283
284 r = amdgpu_ttm_alloc_gart(&bo->tbo);
285 if (r) {
286 dev_err(adev->dev, "%p bind failed\n", bo);
287 goto allocate_mem_kmap_bo_failed;
288 }
289
290 r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
291 if (r) {
292 dev_err(adev->dev,
293 "(%d) failed to map bo to kernel for amdkfd\n", r);
294 goto allocate_mem_kmap_bo_failed;
295 }
296
297 *mem_obj = bo;
298 *gpu_addr = amdgpu_bo_gpu_offset(bo);
299 *cpu_ptr = cpu_ptr_tmp;
300
301 amdgpu_bo_unreserve(bo);
302
303 return 0;
304
305allocate_mem_kmap_bo_failed:
306 amdgpu_bo_unpin(bo);
307allocate_mem_pin_bo_failed:
308 amdgpu_bo_unreserve(bo);
309allocate_mem_reserve_bo_failed:
310 amdgpu_bo_unref(&bo);
311
312 return r;
313}
314
315void amdgpu_amdkfd_free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
316{
317 struct amdgpu_bo *bo = (struct amdgpu_bo *) mem_obj;
318
319 amdgpu_bo_reserve(bo, true);
320 amdgpu_bo_kunmap(bo);
321 amdgpu_bo_unpin(bo);
322 amdgpu_bo_unreserve(bo);
323 amdgpu_bo_unref(&(bo));
324}
325
326int amdgpu_amdkfd_alloc_gws(struct kgd_dev *kgd, size_t size,
327 void **mem_obj)
328{
329 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
330 struct amdgpu_bo *bo = NULL;
331 struct amdgpu_bo_user *ubo;
332 struct amdgpu_bo_param bp;
333 int r;
334
335 memset(&bp, 0, sizeof(bp));
336 bp.size = size;
337 bp.byte_align = 1;
338 bp.domain = AMDGPU_GEM_DOMAIN_GWS;
339 bp.flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
340 bp.type = ttm_bo_type_device;
341 bp.resv = NULL;
342 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
343
344 r = amdgpu_bo_create_user(adev, &bp, &ubo);
345 if (r) {
346 dev_err(adev->dev,
347 "failed to allocate gws BO for amdkfd (%d)\n", r);
348 return r;
349 }
350
351 bo = &ubo->bo;
352 *mem_obj = bo;
353 return 0;
354}
355
356void amdgpu_amdkfd_free_gws(struct kgd_dev *kgd, void *mem_obj)
357{
358 struct amdgpu_bo *bo = (struct amdgpu_bo *)mem_obj;
359
360 amdgpu_bo_unref(&bo);
361}
362
363uint32_t amdgpu_amdkfd_get_fw_version(struct kgd_dev *kgd,
364 enum kgd_engine_type type)
365{
366 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
367
368 switch (type) {
369 case KGD_ENGINE_PFP:
370 return adev->gfx.pfp_fw_version;
371
372 case KGD_ENGINE_ME:
373 return adev->gfx.me_fw_version;
374
375 case KGD_ENGINE_CE:
376 return adev->gfx.ce_fw_version;
377
378 case KGD_ENGINE_MEC1:
379 return adev->gfx.mec_fw_version;
380
381 case KGD_ENGINE_MEC2:
382 return adev->gfx.mec2_fw_version;
383
384 case KGD_ENGINE_RLC:
385 return adev->gfx.rlc_fw_version;
386
387 case KGD_ENGINE_SDMA1:
388 return adev->sdma.instance[0].fw_version;
389
390 case KGD_ENGINE_SDMA2:
391 return adev->sdma.instance[1].fw_version;
392
393 default:
394 return 0;
395 }
396
397 return 0;
398}
399
400void amdgpu_amdkfd_get_local_mem_info(struct kgd_dev *kgd,
401 struct kfd_local_mem_info *mem_info)
402{
403 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
404
405 memset(mem_info, 0, sizeof(*mem_info));
406
407 mem_info->local_mem_size_public = adev->gmc.visible_vram_size;
408 mem_info->local_mem_size_private = adev->gmc.real_vram_size -
409 adev->gmc.visible_vram_size;
410
411 mem_info->vram_width = adev->gmc.vram_width;
412
413 pr_debug("Address base: %pap public 0x%llx private 0x%llx\n",
414 &adev->gmc.aper_base,
415 mem_info->local_mem_size_public,
416 mem_info->local_mem_size_private);
417
418 if (amdgpu_sriov_vf(adev))
419 mem_info->mem_clk_max = adev->clock.default_mclk / 100;
420 else if (adev->pm.dpm_enabled) {
421 if (amdgpu_emu_mode == 1)
422 mem_info->mem_clk_max = 0;
423 else
424 mem_info->mem_clk_max = amdgpu_dpm_get_mclk(adev, false) / 100;
425 } else
426 mem_info->mem_clk_max = 100;
427}
428
429uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd)
430{
431 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
432
433 if (adev->gfx.funcs->get_gpu_clock_counter)
434 return adev->gfx.funcs->get_gpu_clock_counter(adev);
435 return 0;
436}
437
438uint32_t amdgpu_amdkfd_get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
439{
440 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
441
442 /* the sclk is in quantas of 10kHz */
443 if (amdgpu_sriov_vf(adev))
444 return adev->clock.default_sclk / 100;
445 else if (adev->pm.dpm_enabled)
446 return amdgpu_dpm_get_sclk(adev, false) / 100;
447 else
448 return 100;
449}
450
451void amdgpu_amdkfd_get_cu_info(struct kgd_dev *kgd, struct kfd_cu_info *cu_info)
452{
453 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
454 struct amdgpu_cu_info acu_info = adev->gfx.cu_info;
455
456 memset(cu_info, 0, sizeof(*cu_info));
457 if (sizeof(cu_info->cu_bitmap) != sizeof(acu_info.bitmap))
458 return;
459
460 cu_info->cu_active_number = acu_info.number;
461 cu_info->cu_ao_mask = acu_info.ao_cu_mask;
462 memcpy(&cu_info->cu_bitmap[0], &acu_info.bitmap[0],
463 sizeof(acu_info.bitmap));
464 cu_info->num_shader_engines = adev->gfx.config.max_shader_engines;
465 cu_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
466 cu_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
467 cu_info->simd_per_cu = acu_info.simd_per_cu;
468 cu_info->max_waves_per_simd = acu_info.max_waves_per_simd;
469 cu_info->wave_front_size = acu_info.wave_front_size;
470 cu_info->max_scratch_slots_per_cu = acu_info.max_scratch_slots_per_cu;
471 cu_info->lds_size = acu_info.lds_size;
472}
473
474int amdgpu_amdkfd_get_dmabuf_info(struct kgd_dev *kgd, int dma_buf_fd,
475 struct kgd_dev **dma_buf_kgd,
476 uint64_t *bo_size, void *metadata_buffer,
477 size_t buffer_size, uint32_t *metadata_size,
478 uint32_t *flags)
479{
480 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
481 struct dma_buf *dma_buf;
482 struct drm_gem_object *obj;
483 struct amdgpu_bo *bo;
484 uint64_t metadata_flags;
485 int r = -EINVAL;
486
487 dma_buf = dma_buf_get(dma_buf_fd);
488 if (IS_ERR(dma_buf))
489 return PTR_ERR(dma_buf);
490
491 if (dma_buf->ops != &amdgpu_dmabuf_ops)
492 /* Can't handle non-graphics buffers */
493 goto out_put;
494
495 obj = dma_buf->priv;
496 if (obj->dev->driver != adev_to_drm(adev)->driver)
497 /* Can't handle buffers from different drivers */
498 goto out_put;
499
500 adev = drm_to_adev(obj->dev);
501 bo = gem_to_amdgpu_bo(obj);
502 if (!(bo->preferred_domains & (AMDGPU_GEM_DOMAIN_VRAM |
503 AMDGPU_GEM_DOMAIN_GTT)))
504 /* Only VRAM and GTT BOs are supported */
505 goto out_put;
506
507 r = 0;
508 if (dma_buf_kgd)
509 *dma_buf_kgd = (struct kgd_dev *)adev;
510 if (bo_size)
511 *bo_size = amdgpu_bo_size(bo);
512 if (metadata_buffer)
513 r = amdgpu_bo_get_metadata(bo, metadata_buffer, buffer_size,
514 metadata_size, &metadata_flags);
515 if (flags) {
516 *flags = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ?
517 KFD_IOC_ALLOC_MEM_FLAGS_VRAM
518 : KFD_IOC_ALLOC_MEM_FLAGS_GTT;
519
520 if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
521 *flags |= KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC;
522 }
523
524out_put:
525 dma_buf_put(dma_buf);
526 return r;
527}
528
529uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd)
530{
531 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
532 struct ttm_resource_manager *vram_man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
533
534 return amdgpu_vram_mgr_usage(vram_man);
535}
536
537uint64_t amdgpu_amdkfd_get_hive_id(struct kgd_dev *kgd)
538{
539 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
540
541 return adev->gmc.xgmi.hive_id;
542}
543
544uint64_t amdgpu_amdkfd_get_unique_id(struct kgd_dev *kgd)
545{
546 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
547
548 return adev->unique_id;
549}
550
551uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct kgd_dev *dst, struct kgd_dev *src)
552{
553 struct amdgpu_device *peer_adev = (struct amdgpu_device *)src;
554 struct amdgpu_device *adev = (struct amdgpu_device *)dst;
555 int ret = amdgpu_xgmi_get_hops_count(adev, peer_adev);
556
557 if (ret < 0) {
558 DRM_ERROR("amdgpu: failed to get xgmi hops count between node %d and %d. ret = %d\n",
559 adev->gmc.xgmi.physical_node_id,
560 peer_adev->gmc.xgmi.physical_node_id, ret);
561 ret = 0;
562 }
563 return (uint8_t)ret;
564}
565
566uint64_t amdgpu_amdkfd_get_mmio_remap_phys_addr(struct kgd_dev *kgd)
567{
568 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
569
570 return adev->rmmio_remap.bus_addr;
571}
572
573uint32_t amdgpu_amdkfd_get_num_gws(struct kgd_dev *kgd)
574{
575 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
576
577 return adev->gds.gws_size;
578}
579
580uint32_t amdgpu_amdkfd_get_asic_rev_id(struct kgd_dev *kgd)
581{
582 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
583
584 return adev->rev_id;
585}
586
587int amdgpu_amdkfd_get_noretry(struct kgd_dev *kgd)
588{
589 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
590
591 return adev->gmc.noretry;
592}
593
594int amdgpu_amdkfd_submit_ib(struct kgd_dev *kgd, enum kgd_engine_type engine,
595 uint32_t vmid, uint64_t gpu_addr,
596 uint32_t *ib_cmd, uint32_t ib_len)
597{
598 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
599 struct amdgpu_job *job;
600 struct amdgpu_ib *ib;
601 struct amdgpu_ring *ring;
602 struct dma_fence *f = NULL;
603 int ret;
604
605 switch (engine) {
606 case KGD_ENGINE_MEC1:
607 ring = &adev->gfx.compute_ring[0];
608 break;
609 case KGD_ENGINE_SDMA1:
610 ring = &adev->sdma.instance[0].ring;
611 break;
612 case KGD_ENGINE_SDMA2:
613 ring = &adev->sdma.instance[1].ring;
614 break;
615 default:
616 pr_err("Invalid engine in IB submission: %d\n", engine);
617 ret = -EINVAL;
618 goto err;
619 }
620
621 ret = amdgpu_job_alloc(adev, 1, &job, NULL);
622 if (ret)
623 goto err;
624
625 ib = &job->ibs[0];
626 memset(ib, 0, sizeof(struct amdgpu_ib));
627
628 ib->gpu_addr = gpu_addr;
629 ib->ptr = ib_cmd;
630 ib->length_dw = ib_len;
631 /* This works for NO_HWS. TODO: need to handle without knowing VMID */
632 job->vmid = vmid;
633
634 ret = amdgpu_ib_schedule(ring, 1, ib, job, &f);
635
636 if (ret) {
637 DRM_ERROR("amdgpu: failed to schedule IB.\n");
638 goto err_ib_sched;
639 }
640
641 ret = dma_fence_wait(f, false);
642
643err_ib_sched:
644 dma_fence_put(f);
645 amdgpu_job_free(job);
646err:
647 return ret;
648}
649
650void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle)
651{
652 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
653
654 amdgpu_dpm_switch_power_profile(adev,
655 PP_SMC_POWER_PROFILE_COMPUTE,
656 !idle);
657}
658
659bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid)
660{
661 if (adev->kfd.dev)
662 return vmid >= adev->vm_manager.first_kfd_vmid;
663
664 return false;
665}
666
667int amdgpu_amdkfd_flush_gpu_tlb_vmid(struct kgd_dev *kgd, uint16_t vmid)
668{
669 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
670
671 if (adev->family == AMDGPU_FAMILY_AI) {
672 int i;
673
674 for (i = 0; i < adev->num_vmhubs; i++)
675 amdgpu_gmc_flush_gpu_tlb(adev, vmid, i, 0);
676 } else {
677 amdgpu_gmc_flush_gpu_tlb(adev, vmid, AMDGPU_GFXHUB_0, 0);
678 }
679
680 return 0;
681}
682
683int amdgpu_amdkfd_flush_gpu_tlb_pasid(struct kgd_dev *kgd, uint16_t pasid,
684 enum TLB_FLUSH_TYPE flush_type)
685{
686 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
687 bool all_hub = false;
688
689 if (adev->family == AMDGPU_FAMILY_AI)
690 all_hub = true;
691
692 return amdgpu_gmc_flush_gpu_tlb_pasid(adev, pasid, flush_type, all_hub);
693}
694
695bool amdgpu_amdkfd_have_atomics_support(struct kgd_dev *kgd)
696{
697 struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
698
699 return adev->have_atomics_support;
700}