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1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Texas Instruments System Control Interface (TISCI) Protocol
4 *
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
8 *
9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
10 */
11
12#ifndef __TI_SCI_H
13#define __TI_SCI_H
14
15/* Generic Messages */
16#define TI_SCI_MSG_ENABLE_WDT 0x0000
17#define TI_SCI_MSG_WAKE_RESET 0x0001
18#define TI_SCI_MSG_VERSION 0x0002
19#define TI_SCI_MSG_WAKE_REASON 0x0003
20#define TI_SCI_MSG_GOODBYE 0x0004
21#define TI_SCI_MSG_SYS_RESET 0x0005
22
23/* Device requests */
24#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
25#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
26#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
27
28/* Clock requests */
29#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
30#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
31#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
32#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
33#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
34#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
35#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
36#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
37
38/* Resource Management Requests */
39#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
40
41/* IRQ requests */
42#define TI_SCI_MSG_SET_IRQ 0x1000
43#define TI_SCI_MSG_FREE_IRQ 0x1001
44
45/* NAVSS resource management */
46/* Ringacc requests */
47#define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
48#define TI_SCI_MSG_RM_RING_FREE 0x1101
49#define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
50#define TI_SCI_MSG_RM_RING_RESET 0x1103
51#define TI_SCI_MSG_RM_RING_CFG 0x1110
52#define TI_SCI_MSG_RM_RING_GET_CFG 0x1111
53
54/* PSI-L requests */
55#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
56#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
57
58#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
59#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
60#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
61#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
62#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
63#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
64
65#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
66#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
67#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
68#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
69#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
70#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
71#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
72#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
73
74/* Processor Control requests */
75#define TI_SCI_MSG_PROC_REQUEST 0xc000
76#define TI_SCI_MSG_PROC_RELEASE 0xc001
77#define TI_SCI_MSG_PROC_HANDOVER 0xc005
78#define TI_SCI_MSG_SET_CONFIG 0xc100
79#define TI_SCI_MSG_SET_CTRL 0xc101
80#define TI_SCI_MSG_GET_STATUS 0xc400
81
82/**
83 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
84 * @type: Type of messages: One of TI_SCI_MSG* values
85 * @host: Host of the message
86 * @seq: Message identifier indicating a transfer sequence
87 * @flags: Flag for the message
88 */
89struct ti_sci_msg_hdr {
90 u16 type;
91 u8 host;
92 u8 seq;
93#define TI_SCI_MSG_FLAG(val) (1 << (val))
94#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
95#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
96#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
97#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
98#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
99 /* Additional Flags */
100 u32 flags;
101} __packed;
102
103/**
104 * struct ti_sci_msg_resp_version - Response for a message
105 * @hdr: Generic header
106 * @firmware_description: String describing the firmware
107 * @firmware_revision: Firmware revision
108 * @abi_major: Major version of the ABI that firmware supports
109 * @abi_minor: Minor version of the ABI that firmware supports
110 *
111 * In general, ABI version changes follow the rule that minor version increments
112 * are backward compatible. Major revision changes in ABI may not be
113 * backward compatible.
114 *
115 * Response to a generic message with message type TI_SCI_MSG_VERSION
116 */
117struct ti_sci_msg_resp_version {
118 struct ti_sci_msg_hdr hdr;
119 char firmware_description[32];
120 u16 firmware_revision;
121 u8 abi_major;
122 u8 abi_minor;
123} __packed;
124
125/**
126 * struct ti_sci_msg_req_reboot - Reboot the SoC
127 * @hdr: Generic Header
128 *
129 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
130 * ACK/NACK message.
131 */
132struct ti_sci_msg_req_reboot {
133 struct ti_sci_msg_hdr hdr;
134} __packed;
135
136/**
137 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
138 * @hdr: Generic header
139 * @id: Indicates which device to modify
140 * @reserved: Reserved space in message, must be 0 for backward compatibility
141 * @state: The desired state of the device.
142 *
143 * Certain flags can also be set to alter the device state:
144 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
145 * The meaning of this flag will vary slightly from device to device and from
146 * SoC to SoC but it generally allows the device to wake the SoC out of deep
147 * suspend states.
148 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
149 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
150 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
151 * If another host already has this device set to STATE_RETENTION or STATE_ON,
152 * the message will fail. Once successful, other hosts attempting to set
153 * STATE_RETENTION or STATE_ON will fail.
154 *
155 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
156 * ACK/NACK message.
157 */
158struct ti_sci_msg_req_set_device_state {
159 /* Additional hdr->flags options */
160#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
161#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
162#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
163 struct ti_sci_msg_hdr hdr;
164 u32 id;
165 u32 reserved;
166
167#define MSG_DEVICE_SW_STATE_AUTO_OFF 0
168#define MSG_DEVICE_SW_STATE_RETENTION 1
169#define MSG_DEVICE_SW_STATE_ON 2
170 u8 state;
171} __packed;
172
173/**
174 * struct ti_sci_msg_req_get_device_state - Request to get device.
175 * @hdr: Generic header
176 * @id: Device Identifier
177 *
178 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
179 * information
180 */
181struct ti_sci_msg_req_get_device_state {
182 struct ti_sci_msg_hdr hdr;
183 u32 id;
184} __packed;
185
186/**
187 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
188 * @hdr: Generic header
189 * @context_loss_count: Indicates how many times the device has lost context. A
190 * driver can use this monotonic counter to determine if the device has
191 * lost context since the last time this message was exchanged.
192 * @resets: Programmed state of the reset lines.
193 * @programmed_state: The state as programmed by set_device.
194 * - Uses the MSG_DEVICE_SW_* macros
195 * @current_state: The actual state of the hardware.
196 *
197 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
198 */
199struct ti_sci_msg_resp_get_device_state {
200 struct ti_sci_msg_hdr hdr;
201 u32 context_loss_count;
202 u32 resets;
203 u8 programmed_state;
204#define MSG_DEVICE_HW_STATE_OFF 0
205#define MSG_DEVICE_HW_STATE_ON 1
206#define MSG_DEVICE_HW_STATE_TRANS 2
207 u8 current_state;
208} __packed;
209
210/**
211 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
212 * configuration of the device
213 * @hdr: Generic header
214 * @id: Indicates which device to modify
215 * @resets: A bit field of resets for the device. The meaning, behavior,
216 * and usage of the reset flags are device specific. 0 for a bit
217 * indicates releasing the reset represented by that bit while 1
218 * indicates keeping it held.
219 *
220 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
221 * ACK/NACK message.
222 */
223struct ti_sci_msg_req_set_device_resets {
224 struct ti_sci_msg_hdr hdr;
225 u32 id;
226 u32 resets;
227} __packed;
228
229/**
230 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
231 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
232 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
233 * via spread spectrum clocking.
234 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
235 * frequency to be changed while it is running so long as it
236 * is within the min/max limits.
237 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
238 * is only applicable to clock inputs on the SoC pseudo-device.
239 * @dev_id: Device identifier this request is for
240 * @clk_id: Clock identifier for the device for this request.
241 * Each device has it's own set of clock inputs. This indexes
242 * which clock input to modify. Set to 255 if clock ID is
243 * greater than or equal to 255.
244 * @request_state: Request the state for the clock to be set to.
245 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
246 * it can be disabled, regardless of the state of the device
247 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
248 * automatically manage the state of this clock. If the device
249 * is enabled, then the clock is enabled. If the device is set
250 * to off or retention, then the clock is internally set as not
251 * being required by the device.(default)
252 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
253 * regardless of the state of the device.
254 * @clk_id_32: Clock identifier for the device for this request.
255 * Only to be used if the clock ID is greater than or equal to
256 * 255.
257 *
258 * Normally, all required clocks are managed by TISCI entity, this is used
259 * only for specific control *IF* required. Auto managed state is
260 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
261 * will explicitly control.
262 *
263 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
264 * ACK or NACK message.
265 */
266struct ti_sci_msg_req_set_clock_state {
267 /* Additional hdr->flags options */
268#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
269#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
270#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
271 struct ti_sci_msg_hdr hdr;
272 u32 dev_id;
273 u8 clk_id;
274#define MSG_CLOCK_SW_STATE_UNREQ 0
275#define MSG_CLOCK_SW_STATE_AUTO 1
276#define MSG_CLOCK_SW_STATE_REQ 2
277 u8 request_state;
278 u32 clk_id_32;
279} __packed;
280
281/**
282 * struct ti_sci_msg_req_get_clock_state - Request for clock state
283 * @hdr: Generic Header
284 * @dev_id: Device identifier this request is for
285 * @clk_id: Clock identifier for the device for this request.
286 * Each device has it's own set of clock inputs. This indexes
287 * which clock input to get state of. Set to 255 if the clock
288 * ID is greater than or equal to 255.
289 * @clk_id_32: Clock identifier for the device for the request.
290 * Only to be used if the clock ID is greater than or equal to
291 * 255.
292 *
293 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
294 * of the clock
295 */
296struct ti_sci_msg_req_get_clock_state {
297 struct ti_sci_msg_hdr hdr;
298 u32 dev_id;
299 u8 clk_id;
300 u32 clk_id_32;
301} __packed;
302
303/**
304 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
305 * @hdr: Generic Header
306 * @programmed_state: Any programmed state of the clock. This is one of
307 * MSG_CLOCK_SW_STATE* values.
308 * @current_state: Current state of the clock. This is one of:
309 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
310 * MSG_CLOCK_HW_STATE_READY: Clock is ready
311 *
312 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
313 */
314struct ti_sci_msg_resp_get_clock_state {
315 struct ti_sci_msg_hdr hdr;
316 u8 programmed_state;
317#define MSG_CLOCK_HW_STATE_NOT_READY 0
318#define MSG_CLOCK_HW_STATE_READY 1
319 u8 current_state;
320} __packed;
321
322/**
323 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
324 * @hdr: Generic Header
325 * @dev_id: Device identifier this request is for
326 * @clk_id: Clock identifier for the device for this request.
327 * Each device has it's own set of clock inputs. This indexes
328 * which clock input to modify. Set to 255 if clock ID is
329 * greater than or equal to 255.
330 * @parent_id: The new clock parent is selectable by an index via this
331 * parameter. Set to 255 if clock ID is greater than or
332 * equal to 255.
333 * @clk_id_32: Clock identifier if @clk_id field is 255.
334 * @parent_id_32: Parent identifier if @parent_id is 255.
335 *
336 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
337 * ACK / NACK message.
338 */
339struct ti_sci_msg_req_set_clock_parent {
340 struct ti_sci_msg_hdr hdr;
341 u32 dev_id;
342 u8 clk_id;
343 u8 parent_id;
344 u32 clk_id_32;
345 u32 parent_id_32;
346} __packed;
347
348/**
349 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
350 * @hdr: Generic Header
351 * @dev_id: Device identifier this request is for
352 * @clk_id: Clock identifier for the device for this request.
353 * Each device has it's own set of clock inputs. This indexes
354 * which clock input to get the parent for. If this field
355 * contains 255, the actual clock identifier is stored in
356 * @clk_id_32.
357 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
358 *
359 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
360 */
361struct ti_sci_msg_req_get_clock_parent {
362 struct ti_sci_msg_hdr hdr;
363 u32 dev_id;
364 u8 clk_id;
365 u32 clk_id_32;
366} __packed;
367
368/**
369 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
370 * @hdr: Generic Header
371 * @parent_id: The current clock parent. If set to 255, the current parent
372 * ID can be found from the @parent_id_32 field.
373 * @parent_id_32: Current clock parent if @parent_id field is set to
374 * 255.
375 *
376 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
377 */
378struct ti_sci_msg_resp_get_clock_parent {
379 struct ti_sci_msg_hdr hdr;
380 u8 parent_id;
381 u32 parent_id_32;
382} __packed;
383
384/**
385 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
386 * @hdr: Generic header
387 * @dev_id: Device identifier this request is for
388 * @clk_id: Clock identifier for the device for this request. Set to
389 * 255 if clock ID is greater than or equal to 255.
390 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
391 *
392 * This request provides information about how many clock parent options
393 * are available for a given clock to a device. This is typically used
394 * for input clocks.
395 *
396 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
397 * message, or NACK in case of inability to satisfy request.
398 */
399struct ti_sci_msg_req_get_clock_num_parents {
400 struct ti_sci_msg_hdr hdr;
401 u32 dev_id;
402 u8 clk_id;
403 u32 clk_id_32;
404} __packed;
405
406/**
407 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
408 * @hdr: Generic header
409 * @num_parents: Number of clock parents. If set to 255, the actual
410 * number of parents is stored into @num_parents_32
411 * field instead.
412 * @num_parents_32: Number of clock parents if @num_parents field is
413 * set to 255.
414 *
415 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
416 */
417struct ti_sci_msg_resp_get_clock_num_parents {
418 struct ti_sci_msg_hdr hdr;
419 u8 num_parents;
420 u32 num_parents_32;
421} __packed;
422
423/**
424 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
425 * @hdr: Generic Header
426 * @dev_id: Device identifier this request is for
427 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
428 * allowable programmed frequency and does not account for clock
429 * tolerances and jitter.
430 * @target_freq_hz: The target clock frequency. A frequency will be found
431 * as close to this target frequency as possible.
432 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
433 * allowable programmed frequency and does not account for clock
434 * tolerances and jitter.
435 * @clk_id: Clock identifier for the device for this request. Set to
436 * 255 if clock identifier is greater than or equal to 255.
437 * @clk_id_32: Clock identifier if @clk_id is set to 255.
438 *
439 * NOTE: Normally clock frequency management is automatically done by TISCI
440 * entity. In case of specific requests, TISCI evaluates capability to achieve
441 * requested frequency within provided range and responds with
442 * result message.
443 *
444 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
445 * or NACK in case of inability to satisfy request.
446 */
447struct ti_sci_msg_req_query_clock_freq {
448 struct ti_sci_msg_hdr hdr;
449 u32 dev_id;
450 u64 min_freq_hz;
451 u64 target_freq_hz;
452 u64 max_freq_hz;
453 u8 clk_id;
454 u32 clk_id_32;
455} __packed;
456
457/**
458 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
459 * @hdr: Generic Header
460 * @freq_hz: Frequency that is the best match in Hz.
461 *
462 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
463 * cannot be satisfied, the message will be of type NACK.
464 */
465struct ti_sci_msg_resp_query_clock_freq {
466 struct ti_sci_msg_hdr hdr;
467 u64 freq_hz;
468} __packed;
469
470/**
471 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
472 * @hdr: Generic Header
473 * @dev_id: Device identifier this request is for
474 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
475 * allowable programmed frequency and does not account for clock
476 * tolerances and jitter.
477 * @target_freq_hz: The target clock frequency. The clock will be programmed
478 * at a rate as close to this target frequency as possible.
479 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
480 * allowable programmed frequency and does not account for clock
481 * tolerances and jitter.
482 * @clk_id: Clock identifier for the device for this request. Set to
483 * 255 if clock ID is greater than or equal to 255.
484 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
485 *
486 * NOTE: Normally clock frequency management is automatically done by TISCI
487 * entity. In case of specific requests, TISCI evaluates capability to achieve
488 * requested range and responds with success/failure message.
489 *
490 * This sets the desired frequency for a clock within an allowable
491 * range. This message will fail on an enabled clock unless
492 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
493 * if other clocks have their frequency modified due to this message,
494 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
495 *
496 * Calling set frequency on a clock input to the SoC pseudo-device will
497 * inform the PMMC of that clock's frequency. Setting a frequency of
498 * zero will indicate the clock is disabled.
499 *
500 * Calling set frequency on clock outputs from the SoC pseudo-device will
501 * function similarly to setting the clock frequency on a device.
502 *
503 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
504 * message.
505 */
506struct ti_sci_msg_req_set_clock_freq {
507 struct ti_sci_msg_hdr hdr;
508 u32 dev_id;
509 u64 min_freq_hz;
510 u64 target_freq_hz;
511 u64 max_freq_hz;
512 u8 clk_id;
513 u32 clk_id_32;
514} __packed;
515
516/**
517 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
518 * @hdr: Generic Header
519 * @dev_id: Device identifier this request is for
520 * @clk_id: Clock identifier for the device for this request. Set to
521 * 255 if clock ID is greater than or equal to 255.
522 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
523 *
524 * NOTE: Normally clock frequency management is automatically done by TISCI
525 * entity. In some cases, clock frequencies are configured by host.
526 *
527 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
528 * that the clock is currently at.
529 */
530struct ti_sci_msg_req_get_clock_freq {
531 struct ti_sci_msg_hdr hdr;
532 u32 dev_id;
533 u8 clk_id;
534 u32 clk_id_32;
535} __packed;
536
537/**
538 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
539 * @hdr: Generic Header
540 * @freq_hz: Frequency that the clock is currently on, in Hz.
541 *
542 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
543 */
544struct ti_sci_msg_resp_get_clock_freq {
545 struct ti_sci_msg_hdr hdr;
546 u64 freq_hz;
547} __packed;
548
549#define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
550
551/**
552 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
553 * range of resources.
554 * @hdr: Generic Header
555 * @type: Unique resource assignment type
556 * @subtype: Resource assignment subtype within the resource type.
557 * @secondary_host: Host processing entity to which the resources are
558 * allocated. This is required only when the destination
559 * host id id different from ti sci interface host id,
560 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
561 *
562 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
563 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
564 */
565struct ti_sci_msg_req_get_resource_range {
566 struct ti_sci_msg_hdr hdr;
567#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
568#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
569 u16 type;
570 u8 subtype;
571 u8 secondary_host;
572} __packed;
573
574/**
575 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
576 * @hdr: Generic Header
577 * @range_start: Start index of the resource range.
578 * @range_num: Number of resources in the range.
579 *
580 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
581 */
582struct ti_sci_msg_resp_get_resource_range {
583 struct ti_sci_msg_hdr hdr;
584 u16 range_start;
585 u16 range_num;
586} __packed;
587
588/**
589 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
590 * between the dev and the host.
591 * @hdr: Generic Header
592 * @valid_params: Bit fields defining the validity of interrupt source
593 * parameters. If a bit is not set, then corresponding
594 * field is not valid and will not be used for route set.
595 * Bit field definitions:
596 * 0 - Valid bit for @dst_id
597 * 1 - Valid bit for @dst_host_irq
598 * 2 - Valid bit for @ia_id
599 * 3 - Valid bit for @vint
600 * 4 - Valid bit for @global_event
601 * 5 - Valid bit for @vint_status_bit_index
602 * 31 - Valid bit for @secondary_host
603 * @src_id: IRQ source peripheral ID.
604 * @src_index: IRQ source index within the peripheral
605 * @dst_id: IRQ Destination ID. Based on the architecture it can be
606 * IRQ controller or host processor ID.
607 * @dst_host_irq: IRQ number of the destination host IRQ controller
608 * @ia_id: Device ID of the interrupt aggregator in which the
609 * vint resides.
610 * @vint: Virtual interrupt number if the interrupt route
611 * is through an interrupt aggregator.
612 * @global_event: Global event that is to be mapped to interrupt
613 * aggregator virtual interrupt status bit.
614 * @vint_status_bit: Virtual interrupt status bit if the interrupt route
615 * utilizes an interrupt aggregator status bit.
616 * @secondary_host: Host ID of the IRQ destination computing entity. This is
617 * required only when destination host id is different
618 * from ti sci interface host id.
619 *
620 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.
621 * Response is generic ACK / NACK message.
622 */
623struct ti_sci_msg_req_manage_irq {
624 struct ti_sci_msg_hdr hdr;
625#define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)
626#define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1)
627#define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)
628#define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3)
629#define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4)
630#define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5)
631#define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31)
632 u32 valid_params;
633 u16 src_id;
634 u16 src_index;
635 u16 dst_id;
636 u16 dst_host_irq;
637 u16 ia_id;
638 u16 vint;
639 u16 global_event;
640 u8 vint_status_bit;
641 u8 secondary_host;
642} __packed;
643
644/**
645 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
646 *
647 * Configures the non-real-time registers of a Navigator Subsystem ring.
648 * @hdr: Generic Header
649 * @valid_params: Bitfield defining validity of ring configuration parameters.
650 * The ring configuration fields are not valid, and will not be used for
651 * ring configuration, if their corresponding valid bit is zero.
652 * Valid bit usage:
653 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
654 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
655 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
656 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
657 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
658 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
659 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
660 * @index: ring index to be configured.
661 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
662 * RING_BA_LO register
663 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
664 * RING_BA_HI register.
665 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
666 * modes.
667 * @mode: Specifies the mode the ring is to be configured.
668 * @size: Specifies encoded ring element size. To calculate the encoded size use
669 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
670 * greater than 256.
671 * @order_id: Specifies the ring's bus order ID.
672 */
673struct ti_sci_msg_rm_ring_cfg_req {
674 struct ti_sci_msg_hdr hdr;
675 u32 valid_params;
676 u16 nav_id;
677 u16 index;
678 u32 addr_lo;
679 u32 addr_hi;
680 u32 count;
681 u8 mode;
682 u8 size;
683 u8 order_id;
684} __packed;
685
686/**
687 * struct ti_sci_msg_rm_ring_get_cfg_req - Get RA ring's configuration
688 *
689 * Gets the configuration of the non-real-time register fields of a ring. The
690 * host, or a supervisor of the host, who owns the ring must be the requesting
691 * host. The values of the non-real-time registers are returned in
692 * @ti_sci_msg_rm_ring_get_cfg_resp.
693 *
694 * @hdr: Generic Header
695 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
696 * @index: ring index.
697 */
698struct ti_sci_msg_rm_ring_get_cfg_req {
699 struct ti_sci_msg_hdr hdr;
700 u16 nav_id;
701 u16 index;
702} __packed;
703
704/**
705 * struct ti_sci_msg_rm_ring_get_cfg_resp - Ring get configuration response
706 *
707 * Response received by host processor after RM has handled
708 * @ti_sci_msg_rm_ring_get_cfg_req. The response contains the ring's
709 * non-real-time register values.
710 *
711 * @hdr: Generic Header
712 * @addr_lo: Ring 32 LSBs of base address
713 * @addr_hi: Ring 16 MSBs of base address.
714 * @count: Ring number of elements.
715 * @mode: Ring mode.
716 * @size: encoded Ring element size
717 * @order_id: ing order ID.
718 */
719struct ti_sci_msg_rm_ring_get_cfg_resp {
720 struct ti_sci_msg_hdr hdr;
721 u32 addr_lo;
722 u32 addr_hi;
723 u32 count;
724 u8 mode;
725 u8 size;
726 u8 order_id;
727} __packed;
728
729/**
730 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
731 * thread
732 * @hdr: Generic Header
733 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
734 * used to pair the source and destination threads.
735 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
736 *
737 * UDMAP transmit channels mapped to source threads will have their
738 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
739 * is successful.
740
741 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
742 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
743 * the destination thread is not greater than or equal to 0x8000.
744 *
745 * UDMAP receive channels mapped to destination threads will have their
746 * RCHAN_THRD_ID register programmed with the source thread if the pairing
747 * is successful.
748 *
749 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
750 * message.
751 */
752struct ti_sci_msg_psil_pair {
753 struct ti_sci_msg_hdr hdr;
754 u32 nav_id;
755 u32 src_thread;
756 u32 dst_thread;
757} __packed;
758
759/**
760 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
761 * destination thread
762 * @hdr: Generic Header
763 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
764 * used to unpair the source and destination threads.
765 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
766 *
767 * UDMAP transmit channels mapped to source threads will have their
768 * TCHAN_THRD_ID register cleared if the unpairing is successful.
769 *
770 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
771 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
772 * the destination thread is not greater than or equal to 0x8000.
773 *
774 * UDMAP receive channels mapped to destination threads will have their
775 * RCHAN_THRD_ID register cleared if the unpairing is successful.
776 *
777 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
778 * message.
779 */
780struct ti_sci_msg_psil_unpair {
781 struct ti_sci_msg_hdr hdr;
782 u32 nav_id;
783 u32 src_thread;
784 u32 dst_thread;
785} __packed;
786
787/**
788 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
789 * message
790 * @hdr: Generic Header
791 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
792 * allocated
793 * @flow_index: UDMAP receive flow index for non-optional configuration.
794 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
795 * @rx_einfo_present: UDMAP receive flow extended packet info present.
796 * @rx_psinfo_present: UDMAP receive flow PS words present.
797 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
798 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
799 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
800 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
801 * @rx_sop_offset: UDMAP receive flow start of packet offset.
802 * @rx_dest_qnum: UDMAP receive flow destination queue number.
803 * @rx_ps_location: UDMAP receive flow PS words location.
804 * 0 - end of packet descriptor
805 * 1 - Beginning of the data buffer
806 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
807 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
808 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
809 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
810 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
811 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
812 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
813 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
814 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
815 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
816 * configured and sent.
817 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
818 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
819 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
820 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
821 *
822 * For detailed information on the settings, see the UDMAP section of the TRM.
823 */
824struct ti_sci_msg_udmap_rx_flow_cfg {
825 struct ti_sci_msg_hdr hdr;
826 u32 nav_id;
827 u32 flow_index;
828 u32 rx_ch_index;
829 u8 rx_einfo_present;
830 u8 rx_psinfo_present;
831 u8 rx_error_handling;
832 u8 rx_desc_type;
833 u16 rx_sop_offset;
834 u16 rx_dest_qnum;
835 u8 rx_ps_location;
836 u8 rx_src_tag_hi;
837 u8 rx_src_tag_lo;
838 u8 rx_dest_tag_hi;
839 u8 rx_dest_tag_lo;
840 u8 rx_src_tag_hi_sel;
841 u8 rx_src_tag_lo_sel;
842 u8 rx_dest_tag_hi_sel;
843 u8 rx_dest_tag_lo_sel;
844 u8 rx_size_thresh_en;
845 u16 rx_fdq0_sz0_qnum;
846 u16 rx_fdq1_qnum;
847 u16 rx_fdq2_qnum;
848 u16 rx_fdq3_qnum;
849} __packed;
850
851/**
852 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
853 * flow optional configuration
854 * @hdr: Generic Header
855 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
856 * allocated
857 * @flow_index: UDMAP receive flow index for optional configuration.
858 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
859 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
860 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
861 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
862 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
863 * threshold 1.
864 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
865 * threshold 2.
866 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
867 * threshold 3.
868 *
869 * For detailed information on the settings, see the UDMAP section of the TRM.
870 */
871struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
872 struct ti_sci_msg_hdr hdr;
873 u32 nav_id;
874 u32 flow_index;
875 u32 rx_ch_index;
876 u16 rx_size_thresh0;
877 u16 rx_size_thresh1;
878 u16 rx_size_thresh2;
879 u16 rx_fdq0_sz1_qnum;
880 u16 rx_fdq0_sz2_qnum;
881 u16 rx_fdq0_sz3_qnum;
882} __packed;
883
884/**
885 * Configures a Navigator Subsystem UDMAP transmit channel
886 *
887 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
888 * transmit channel. The channel index must be assigned to the host defined
889 * in the TISCI header via the RM board configuration resource assignment
890 * range list.
891 *
892 * @hdr: Generic Header
893 *
894 * @valid_params: Bitfield defining validity of tx channel configuration
895 * parameters. The tx channel configuration fields are not valid, and will not
896 * be used for ch configuration, if their corresponding valid bit is zero.
897 * Valid bit usage:
898 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
899 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
900 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
901 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
902 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
903 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
904 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
905 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
906 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
907 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
908 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
909 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
910 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
911 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
912 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
913 *
914 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
915 *
916 * @index: UDMAP transmit channel index.
917 *
918 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
919 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
920 * register.
921 *
922 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
923 * configuration to be programmed into the tx_filt_einfo field of the
924 * channel's TCHAN_TCFG register.
925 *
926 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
927 * configuration to be programmed into the tx_filt_pswords field of the
928 * channel's TCHAN_TCFG register.
929 *
930 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
931 * interpretation configuration to be programmed into the tx_atype field of
932 * the channel's TCHAN_TCFG register.
933 *
934 * @tx_chan_type: UDMAP transmit channel functional channel type and work
935 * passing mechanism configuration to be programmed into the tx_chan_type
936 * field of the channel's TCHAN_TCFG register.
937 *
938 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
939 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
940 * TCHAN_TCFG register.
941 *
942 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
943 * fetch configuration to be programmed into the tx_fetch_size field of the
944 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
945 * word count that can pass through the channel for any allowed descriptor type.
946 *
947 * @tx_credit_count: UDMAP transmit channel transfer request credit count
948 * configuration to be programmed into the count field of the TCHAN_TCREDIT
949 * register. Specifies how many credits for complete TRs are available.
950 *
951 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
952 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
953 * completion queue must be assigned to the host, or a subordinate of the host,
954 * requesting configuration of the transmit channel.
955 *
956 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
957 * into the priority field of the channel's TCHAN_TPRI_CTRL register.
958 *
959 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
960 * qos field of the channel's TCHAN_TPRI_CTRL register.
961 *
962 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
963 * the orderid field of the channel's TCHAN_TPRI_CTRL register.
964 *
965 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
966 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
967 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
968 * section of the TRM for restrictions regarding this parameter.
969 *
970 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
971 * configuration to be programmed into the priority field of the channel's
972 * TCHAN_TST_SCHED register.
973 *
974 * @tx_burst_size: UDMAP transmit channel burst size configuration to be
975 * programmed into the tx_burst_size field of the TCHAN_TCFG register.
976 */
977struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
978 struct ti_sci_msg_hdr hdr;
979 u32 valid_params;
980 u16 nav_id;
981 u16 index;
982 u8 tx_pause_on_err;
983 u8 tx_filt_einfo;
984 u8 tx_filt_pswords;
985 u8 tx_atype;
986 u8 tx_chan_type;
987 u8 tx_supr_tdpkt;
988 u16 tx_fetch_size;
989 u8 tx_credit_count;
990 u16 txcq_qnum;
991 u8 tx_priority;
992 u8 tx_qos;
993 u8 tx_orderid;
994 u16 fdepth;
995 u8 tx_sched_priority;
996 u8 tx_burst_size;
997} __packed;
998
999/**
1000 * Configures a Navigator Subsystem UDMAP receive channel
1001 *
1002 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
1003 * receive channel. The channel index must be assigned to the host defined
1004 * in the TISCI header via the RM board configuration resource assignment
1005 * range list.
1006 *
1007 * @hdr: Generic Header
1008 *
1009 * @valid_params: Bitfield defining validity of rx channel configuration
1010 * parameters.
1011 * The rx channel configuration fields are not valid, and will not be used for
1012 * ch configuration, if their corresponding valid bit is zero.
1013 * Valid bit usage:
1014 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
1015 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
1016 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
1017 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
1018 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
1019 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1020 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1021 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1022 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1023 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1024 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1025 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1026 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1027 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
1028 *
1029 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1030 *
1031 * @index: UDMAP receive channel index.
1032 *
1033 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1034 * fetch configuration to be programmed into the rx_fetch_size field of the
1035 * channel's RCHAN_RCFG register.
1036 *
1037 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1038 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1039 * The specified completion queue must be assigned to the host, or a subordinate
1040 * of the host, requesting configuration of the receive channel.
1041 *
1042 * @rx_priority: UDMAP receive channel receive priority value to be programmed
1043 * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1044 *
1045 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1046 * qos field of the channel's RCHAN_RPRI_CTRL register.
1047 *
1048 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1049 * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1050 *
1051 * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1052 * configuration to be programmed into the priority field of the channel's
1053 * RCHAN_RST_SCHED register.
1054 *
1055 * @flowid_start: UDMAP receive channel additional flows starting index
1056 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1057 * register. Specifies the starting index for flow IDs the receive channel is to
1058 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1059 * set as valid and configured together. The starting flow ID set by
1060 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1061 * of flows beyond the default flows statically mapped to receive channels.
1062 * The additional flows must be assigned to the host, or a subordinate of the
1063 * host, requesting configuration of the receive channel.
1064 *
1065 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1066 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1067 * This field specifies how many flow IDs are in the additional contiguous range
1068 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
1069 * set as valid and configured together. Disabling the valid_params field bit
1070 * for flowid_cnt indicates no flow IDs other than the default are to be
1071 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1072 * cannot be greater than the number of receive flows in the receive channel's
1073 * Navigator Subsystem. The additional flows must be assigned to the host, or a
1074 * subordinate of the host, requesting configuration of the receive channel.
1075 *
1076 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1077 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1078 * register.
1079 *
1080 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1081 * interpretation configuration to be programmed into the rx_atype field of the
1082 * channel's RCHAN_RCFG register.
1083 *
1084 * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1085 * mechanism configuration to be programmed into the rx_chan_type field of the
1086 * channel's RCHAN_RCFG register.
1087 *
1088 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1089 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1090 *
1091 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1092 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1093 *
1094 * @rx_burst_size: UDMAP receive channel burst size configuration to be
1095 * programmed into the rx_burst_size field of the RCHAN_RCFG register.
1096 */
1097struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1098 struct ti_sci_msg_hdr hdr;
1099 u32 valid_params;
1100 u16 nav_id;
1101 u16 index;
1102 u16 rx_fetch_size;
1103 u16 rxcq_qnum;
1104 u8 rx_priority;
1105 u8 rx_qos;
1106 u8 rx_orderid;
1107 u8 rx_sched_priority;
1108 u16 flowid_start;
1109 u16 flowid_cnt;
1110 u8 rx_pause_on_err;
1111 u8 rx_atype;
1112 u8 rx_chan_type;
1113 u8 rx_ignore_short;
1114 u8 rx_ignore_long;
1115 u8 rx_burst_size;
1116} __packed;
1117
1118/**
1119 * Configures a Navigator Subsystem UDMAP receive flow
1120 *
1121 * Configures a Navigator Subsystem UDMAP receive flow's registers.
1122 * Configuration does not include the flow registers which handle size-based
1123 * free descriptor queue routing.
1124 *
1125 * The flow index must be assigned to the host defined in the TISCI header via
1126 * the RM board configuration resource assignment range list.
1127 *
1128 * @hdr: Standard TISCI header
1129 *
1130 * @valid_params
1131 * Bitfield defining validity of rx flow configuration parameters. The
1132 * rx flow configuration fields are not valid, and will not be used for flow
1133 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1134 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1135 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1136 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1137 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1138 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1139 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1140 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1141 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1142 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1143 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1144 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1145 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1146 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1147 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1148 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1149 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1150 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1151 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1152 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1153 *
1154 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1155 * allocated
1156 *
1157 * @flow_index: UDMAP receive flow index for non-optional configuration.
1158 *
1159 * @rx_einfo_present:
1160 * UDMAP receive flow extended packet info present configuration to be
1161 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1162 *
1163 * @rx_psinfo_present:
1164 * UDMAP receive flow PS words present configuration to be programmed into the
1165 * rx_psinfo_present field of the flow's RFLOW_RFA register.
1166 *
1167 * @rx_error_handling:
1168 * UDMAP receive flow error handling configuration to be programmed into the
1169 * rx_error_handling field of the flow's RFLOW_RFA register.
1170 *
1171 * @rx_desc_type:
1172 * UDMAP receive flow descriptor type configuration to be programmed into the
1173 * rx_desc_type field field of the flow's RFLOW_RFA register.
1174 *
1175 * @rx_sop_offset:
1176 * UDMAP receive flow start of packet offset configuration to be programmed
1177 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
1178 * section of the TRM for more information on this setting. Valid values for
1179 * this field are 0-255 bytes.
1180 *
1181 * @rx_dest_qnum:
1182 * UDMAP receive flow destination queue configuration to be programmed into the
1183 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
1184 * destination queue must be valid within the Navigator Subsystem and must be
1185 * owned by the host, or a subordinate of the host, requesting allocation and
1186 * configuration of the receive flow.
1187 *
1188 * @rx_src_tag_hi:
1189 * UDMAP receive flow source tag high byte constant configuration to be
1190 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1191 * See the UDMAP section of the TRM for more information on this setting.
1192 *
1193 * @rx_src_tag_lo:
1194 * UDMAP receive flow source tag low byte constant configuration to be
1195 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1196 * See the UDMAP section of the TRM for more information on this setting.
1197 *
1198 * @rx_dest_tag_hi:
1199 * UDMAP receive flow destination tag high byte constant configuration to be
1200 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1201 * See the UDMAP section of the TRM for more information on this setting.
1202 *
1203 * @rx_dest_tag_lo:
1204 * UDMAP receive flow destination tag low byte constant configuration to be
1205 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1206 * See the UDMAP section of the TRM for more information on this setting.
1207 *
1208 * @rx_src_tag_hi_sel:
1209 * UDMAP receive flow source tag high byte selector configuration to be
1210 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
1211 * the UDMAP section of the TRM for more information on this setting.
1212 *
1213 * @rx_src_tag_lo_sel:
1214 * UDMAP receive flow source tag low byte selector configuration to be
1215 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
1216 * the UDMAP section of the TRM for more information on this setting.
1217 *
1218 * @rx_dest_tag_hi_sel:
1219 * UDMAP receive flow destination tag high byte selector configuration to be
1220 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
1221 * the UDMAP section of the TRM for more information on this setting.
1222 *
1223 * @rx_dest_tag_lo_sel:
1224 * UDMAP receive flow destination tag low byte selector configuration to be
1225 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
1226 * the UDMAP section of the TRM for more information on this setting.
1227 *
1228 * @rx_fdq0_sz0_qnum:
1229 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1230 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
1231 * UDMAP section of the TRM for more information on this setting. The specified
1232 * free queue must be valid within the Navigator Subsystem and must be owned
1233 * by the host, or a subordinate of the host, requesting allocation and
1234 * configuration of the receive flow.
1235 *
1236 * @rx_fdq1_qnum:
1237 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1238 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
1239 * UDMAP section of the TRM for more information on this setting. The specified
1240 * free queue must be valid within the Navigator Subsystem and must be owned
1241 * by the host, or a subordinate of the host, requesting allocation and
1242 * configuration of the receive flow.
1243 *
1244 * @rx_fdq2_qnum:
1245 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1246 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
1247 * UDMAP section of the TRM for more information on this setting. The specified
1248 * free queue must be valid within the Navigator Subsystem and must be owned
1249 * by the host, or a subordinate of the host, requesting allocation and
1250 * configuration of the receive flow.
1251 *
1252 * @rx_fdq3_qnum:
1253 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1254 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
1255 * UDMAP section of the TRM for more information on this setting. The specified
1256 * free queue must be valid within the Navigator Subsystem and must be owned
1257 * by the host, or a subordinate of the host, requesting allocation and
1258 * configuration of the receive flow.
1259 *
1260 * @rx_ps_location:
1261 * UDMAP receive flow PS words location configuration to be programmed into the
1262 * rx_ps_location field of the flow's RFLOW_RFA register.
1263 */
1264struct ti_sci_msg_rm_udmap_flow_cfg_req {
1265 struct ti_sci_msg_hdr hdr;
1266 u32 valid_params;
1267 u16 nav_id;
1268 u16 flow_index;
1269 u8 rx_einfo_present;
1270 u8 rx_psinfo_present;
1271 u8 rx_error_handling;
1272 u8 rx_desc_type;
1273 u16 rx_sop_offset;
1274 u16 rx_dest_qnum;
1275 u8 rx_src_tag_hi;
1276 u8 rx_src_tag_lo;
1277 u8 rx_dest_tag_hi;
1278 u8 rx_dest_tag_lo;
1279 u8 rx_src_tag_hi_sel;
1280 u8 rx_src_tag_lo_sel;
1281 u8 rx_dest_tag_hi_sel;
1282 u8 rx_dest_tag_lo_sel;
1283 u16 rx_fdq0_sz0_qnum;
1284 u16 rx_fdq1_qnum;
1285 u16 rx_fdq2_qnum;
1286 u16 rx_fdq3_qnum;
1287 u8 rx_ps_location;
1288} __packed;
1289
1290/**
1291 * struct ti_sci_msg_req_proc_request - Request a processor
1292 * @hdr: Generic Header
1293 * @processor_id: ID of processor being requested
1294 *
1295 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
1296 * message.
1297 */
1298struct ti_sci_msg_req_proc_request {
1299 struct ti_sci_msg_hdr hdr;
1300 u8 processor_id;
1301} __packed;
1302
1303/**
1304 * struct ti_sci_msg_req_proc_release - Release a processor
1305 * @hdr: Generic Header
1306 * @processor_id: ID of processor being released
1307 *
1308 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
1309 * message.
1310 */
1311struct ti_sci_msg_req_proc_release {
1312 struct ti_sci_msg_hdr hdr;
1313 u8 processor_id;
1314} __packed;
1315
1316/**
1317 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
1318 * @hdr: Generic Header
1319 * @processor_id: ID of processor being handed over
1320 * @host_id: Host ID the control needs to be transferred to
1321 *
1322 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1323 * message.
1324 */
1325struct ti_sci_msg_req_proc_handover {
1326 struct ti_sci_msg_hdr hdr;
1327 u8 processor_id;
1328 u8 host_id;
1329} __packed;
1330
1331/* Boot Vector masks */
1332#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
1333#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
1334#define TI_SCI_ADDR_HIGH_SHIFT 32
1335
1336/**
1337 * struct ti_sci_msg_req_set_config - Set Processor boot configuration
1338 * @hdr: Generic Header
1339 * @processor_id: ID of processor being configured
1340 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
1341 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
1342 * @config_flags_set: Optional Processor specific Config Flags to set.
1343 * Setting a bit here implies the corresponding mode
1344 * will be set
1345 * @config_flags_clear: Optional Processor specific Config Flags to clear.
1346 * Setting a bit here implies the corresponding mode
1347 * will be cleared
1348 *
1349 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1350 * message.
1351 */
1352struct ti_sci_msg_req_set_config {
1353 struct ti_sci_msg_hdr hdr;
1354 u8 processor_id;
1355 u32 bootvector_low;
1356 u32 bootvector_high;
1357 u32 config_flags_set;
1358 u32 config_flags_clear;
1359} __packed;
1360
1361/**
1362 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
1363 * @hdr: Generic Header
1364 * @processor_id: ID of processor being configured
1365 * @control_flags_set: Optional Processor specific Control Flags to set.
1366 * Setting a bit here implies the corresponding mode
1367 * will be set
1368 * @control_flags_clear:Optional Processor specific Control Flags to clear.
1369 * Setting a bit here implies the corresponding mode
1370 * will be cleared
1371 *
1372 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
1373 * message.
1374 */
1375struct ti_sci_msg_req_set_ctrl {
1376 struct ti_sci_msg_hdr hdr;
1377 u8 processor_id;
1378 u32 control_flags_set;
1379 u32 control_flags_clear;
1380} __packed;
1381
1382/**
1383 * struct ti_sci_msg_req_get_status - Processor boot status request
1384 * @hdr: Generic Header
1385 * @processor_id: ID of processor whose status is being requested
1386 *
1387 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate
1388 * message, or NACK in case of inability to satisfy request.
1389 */
1390struct ti_sci_msg_req_get_status {
1391 struct ti_sci_msg_hdr hdr;
1392 u8 processor_id;
1393} __packed;
1394
1395/**
1396 * struct ti_sci_msg_resp_get_status - Processor boot status response
1397 * @hdr: Generic Header
1398 * @processor_id: ID of processor whose status is returned
1399 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
1400 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
1401 * @config_flags: Optional Processor specific Config Flags set currently
1402 * @control_flags: Optional Processor specific Control Flags set currently
1403 * @status_flags: Optional Processor specific Status Flags set currently
1404 *
1405 * Response structure to a TI_SCI_MSG_GET_STATUS request.
1406 */
1407struct ti_sci_msg_resp_get_status {
1408 struct ti_sci_msg_hdr hdr;
1409 u8 processor_id;
1410 u32 bootvector_low;
1411 u32 bootvector_high;
1412 u32 config_flags;
1413 u32 control_flags;
1414 u32 status_flags;
1415} __packed;
1416
1417#endif /* __TI_SCI_H */
1/* SPDX-License-Identifier: BSD-3-Clause */
2/*
3 * Texas Instruments System Control Interface (TISCI) Protocol
4 *
5 * Communication protocol with TI SCI hardware
6 * The system works in a message response protocol
7 * See: http://processors.wiki.ti.com/index.php/TISCI for details
8 *
9 * Copyright (C) 2015-2016 Texas Instruments Incorporated - https://www.ti.com/
10 */
11
12#ifndef __TI_SCI_H
13#define __TI_SCI_H
14
15/* Generic Messages */
16#define TI_SCI_MSG_ENABLE_WDT 0x0000
17#define TI_SCI_MSG_WAKE_RESET 0x0001
18#define TI_SCI_MSG_VERSION 0x0002
19#define TI_SCI_MSG_WAKE_REASON 0x0003
20#define TI_SCI_MSG_GOODBYE 0x0004
21#define TI_SCI_MSG_SYS_RESET 0x0005
22
23/* Device requests */
24#define TI_SCI_MSG_SET_DEVICE_STATE 0x0200
25#define TI_SCI_MSG_GET_DEVICE_STATE 0x0201
26#define TI_SCI_MSG_SET_DEVICE_RESETS 0x0202
27
28/* Clock requests */
29#define TI_SCI_MSG_SET_CLOCK_STATE 0x0100
30#define TI_SCI_MSG_GET_CLOCK_STATE 0x0101
31#define TI_SCI_MSG_SET_CLOCK_PARENT 0x0102
32#define TI_SCI_MSG_GET_CLOCK_PARENT 0x0103
33#define TI_SCI_MSG_GET_NUM_CLOCK_PARENTS 0x0104
34#define TI_SCI_MSG_SET_CLOCK_FREQ 0x010c
35#define TI_SCI_MSG_QUERY_CLOCK_FREQ 0x010d
36#define TI_SCI_MSG_GET_CLOCK_FREQ 0x010e
37
38/* Resource Management Requests */
39#define TI_SCI_MSG_GET_RESOURCE_RANGE 0x1500
40
41/* IRQ requests */
42#define TI_SCI_MSG_SET_IRQ 0x1000
43#define TI_SCI_MSG_FREE_IRQ 0x1001
44
45/* NAVSS resource management */
46/* Ringacc requests */
47#define TI_SCI_MSG_RM_RING_ALLOCATE 0x1100
48#define TI_SCI_MSG_RM_RING_FREE 0x1101
49#define TI_SCI_MSG_RM_RING_RECONFIG 0x1102
50#define TI_SCI_MSG_RM_RING_RESET 0x1103
51#define TI_SCI_MSG_RM_RING_CFG 0x1110
52
53/* PSI-L requests */
54#define TI_SCI_MSG_RM_PSIL_PAIR 0x1280
55#define TI_SCI_MSG_RM_PSIL_UNPAIR 0x1281
56
57#define TI_SCI_MSG_RM_UDMAP_TX_ALLOC 0x1200
58#define TI_SCI_MSG_RM_UDMAP_TX_FREE 0x1201
59#define TI_SCI_MSG_RM_UDMAP_RX_ALLOC 0x1210
60#define TI_SCI_MSG_RM_UDMAP_RX_FREE 0x1211
61#define TI_SCI_MSG_RM_UDMAP_FLOW_CFG 0x1220
62#define TI_SCI_MSG_RM_UDMAP_OPT_FLOW_CFG 0x1221
63
64#define TISCI_MSG_RM_UDMAP_TX_CH_CFG 0x1205
65#define TISCI_MSG_RM_UDMAP_TX_CH_GET_CFG 0x1206
66#define TISCI_MSG_RM_UDMAP_RX_CH_CFG 0x1215
67#define TISCI_MSG_RM_UDMAP_RX_CH_GET_CFG 0x1216
68#define TISCI_MSG_RM_UDMAP_FLOW_CFG 0x1230
69#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_CFG 0x1231
70#define TISCI_MSG_RM_UDMAP_FLOW_GET_CFG 0x1232
71#define TISCI_MSG_RM_UDMAP_FLOW_SIZE_THRESH_GET_CFG 0x1233
72
73/* Processor Control requests */
74#define TI_SCI_MSG_PROC_REQUEST 0xc000
75#define TI_SCI_MSG_PROC_RELEASE 0xc001
76#define TI_SCI_MSG_PROC_HANDOVER 0xc005
77#define TI_SCI_MSG_SET_CONFIG 0xc100
78#define TI_SCI_MSG_SET_CTRL 0xc101
79#define TI_SCI_MSG_GET_STATUS 0xc400
80
81/**
82 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
83 * @type: Type of messages: One of TI_SCI_MSG* values
84 * @host: Host of the message
85 * @seq: Message identifier indicating a transfer sequence
86 * @flags: Flag for the message
87 */
88struct ti_sci_msg_hdr {
89 u16 type;
90 u8 host;
91 u8 seq;
92#define TI_SCI_MSG_FLAG(val) (1 << (val))
93#define TI_SCI_FLAG_REQ_GENERIC_NORESPONSE 0x0
94#define TI_SCI_FLAG_REQ_ACK_ON_RECEIVED TI_SCI_MSG_FLAG(0)
95#define TI_SCI_FLAG_REQ_ACK_ON_PROCESSED TI_SCI_MSG_FLAG(1)
96#define TI_SCI_FLAG_RESP_GENERIC_NACK 0x0
97#define TI_SCI_FLAG_RESP_GENERIC_ACK TI_SCI_MSG_FLAG(1)
98 /* Additional Flags */
99 u32 flags;
100} __packed;
101
102/**
103 * struct ti_sci_msg_resp_version - Response for a message
104 * @hdr: Generic header
105 * @firmware_description: String describing the firmware
106 * @firmware_revision: Firmware revision
107 * @abi_major: Major version of the ABI that firmware supports
108 * @abi_minor: Minor version of the ABI that firmware supports
109 *
110 * In general, ABI version changes follow the rule that minor version increments
111 * are backward compatible. Major revision changes in ABI may not be
112 * backward compatible.
113 *
114 * Response to a generic message with message type TI_SCI_MSG_VERSION
115 */
116struct ti_sci_msg_resp_version {
117 struct ti_sci_msg_hdr hdr;
118 char firmware_description[32];
119 u16 firmware_revision;
120 u8 abi_major;
121 u8 abi_minor;
122} __packed;
123
124/**
125 * struct ti_sci_msg_req_reboot - Reboot the SoC
126 * @hdr: Generic Header
127 *
128 * Request type is TI_SCI_MSG_SYS_RESET, responded with a generic
129 * ACK/NACK message.
130 */
131struct ti_sci_msg_req_reboot {
132 struct ti_sci_msg_hdr hdr;
133} __packed;
134
135/**
136 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
137 * @hdr: Generic header
138 * @id: Indicates which device to modify
139 * @reserved: Reserved space in message, must be 0 for backward compatibility
140 * @state: The desired state of the device.
141 *
142 * Certain flags can also be set to alter the device state:
143 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
144 * The meaning of this flag will vary slightly from device to device and from
145 * SoC to SoC but it generally allows the device to wake the SoC out of deep
146 * suspend states.
147 * + MSG_FLAG_DEVICE_RESET_ISO - Enable reset isolation for this device.
148 * + MSG_FLAG_DEVICE_EXCLUSIVE - Claim this device exclusively. When passed
149 * with STATE_RETENTION or STATE_ON, it will claim the device exclusively.
150 * If another host already has this device set to STATE_RETENTION or STATE_ON,
151 * the message will fail. Once successful, other hosts attempting to set
152 * STATE_RETENTION or STATE_ON will fail.
153 *
154 * Request type is TI_SCI_MSG_SET_DEVICE_STATE, responded with a generic
155 * ACK/NACK message.
156 */
157struct ti_sci_msg_req_set_device_state {
158 /* Additional hdr->flags options */
159#define MSG_FLAG_DEVICE_WAKE_ENABLED TI_SCI_MSG_FLAG(8)
160#define MSG_FLAG_DEVICE_RESET_ISO TI_SCI_MSG_FLAG(9)
161#define MSG_FLAG_DEVICE_EXCLUSIVE TI_SCI_MSG_FLAG(10)
162 struct ti_sci_msg_hdr hdr;
163 u32 id;
164 u32 reserved;
165
166#define MSG_DEVICE_SW_STATE_AUTO_OFF 0
167#define MSG_DEVICE_SW_STATE_RETENTION 1
168#define MSG_DEVICE_SW_STATE_ON 2
169 u8 state;
170} __packed;
171
172/**
173 * struct ti_sci_msg_req_get_device_state - Request to get device.
174 * @hdr: Generic header
175 * @id: Device Identifier
176 *
177 * Request type is TI_SCI_MSG_GET_DEVICE_STATE, responded device state
178 * information
179 */
180struct ti_sci_msg_req_get_device_state {
181 struct ti_sci_msg_hdr hdr;
182 u32 id;
183} __packed;
184
185/**
186 * struct ti_sci_msg_resp_get_device_state - Response to get device request.
187 * @hdr: Generic header
188 * @context_loss_count: Indicates how many times the device has lost context. A
189 * driver can use this monotonic counter to determine if the device has
190 * lost context since the last time this message was exchanged.
191 * @resets: Programmed state of the reset lines.
192 * @programmed_state: The state as programmed by set_device.
193 * - Uses the MSG_DEVICE_SW_* macros
194 * @current_state: The actual state of the hardware.
195 *
196 * Response to request TI_SCI_MSG_GET_DEVICE_STATE.
197 */
198struct ti_sci_msg_resp_get_device_state {
199 struct ti_sci_msg_hdr hdr;
200 u32 context_loss_count;
201 u32 resets;
202 u8 programmed_state;
203#define MSG_DEVICE_HW_STATE_OFF 0
204#define MSG_DEVICE_HW_STATE_ON 1
205#define MSG_DEVICE_HW_STATE_TRANS 2
206 u8 current_state;
207} __packed;
208
209/**
210 * struct ti_sci_msg_req_set_device_resets - Set the desired resets
211 * configuration of the device
212 * @hdr: Generic header
213 * @id: Indicates which device to modify
214 * @resets: A bit field of resets for the device. The meaning, behavior,
215 * and usage of the reset flags are device specific. 0 for a bit
216 * indicates releasing the reset represented by that bit while 1
217 * indicates keeping it held.
218 *
219 * Request type is TI_SCI_MSG_SET_DEVICE_RESETS, responded with a generic
220 * ACK/NACK message.
221 */
222struct ti_sci_msg_req_set_device_resets {
223 struct ti_sci_msg_hdr hdr;
224 u32 id;
225 u32 resets;
226} __packed;
227
228/**
229 * struct ti_sci_msg_req_set_clock_state - Request to setup a Clock state
230 * @hdr: Generic Header, Certain flags can be set specific to the clocks:
231 * MSG_FLAG_CLOCK_ALLOW_SSC: Allow this clock to be modified
232 * via spread spectrum clocking.
233 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE: Allow this clock's
234 * frequency to be changed while it is running so long as it
235 * is within the min/max limits.
236 * MSG_FLAG_CLOCK_INPUT_TERM: Enable input termination, this
237 * is only applicable to clock inputs on the SoC pseudo-device.
238 * @dev_id: Device identifier this request is for
239 * @clk_id: Clock identifier for the device for this request.
240 * Each device has it's own set of clock inputs. This indexes
241 * which clock input to modify. Set to 255 if clock ID is
242 * greater than or equal to 255.
243 * @request_state: Request the state for the clock to be set to.
244 * MSG_CLOCK_SW_STATE_UNREQ: The IP does not require this clock,
245 * it can be disabled, regardless of the state of the device
246 * MSG_CLOCK_SW_STATE_AUTO: Allow the System Controller to
247 * automatically manage the state of this clock. If the device
248 * is enabled, then the clock is enabled. If the device is set
249 * to off or retention, then the clock is internally set as not
250 * being required by the device.(default)
251 * MSG_CLOCK_SW_STATE_REQ: Configure the clock to be enabled,
252 * regardless of the state of the device.
253 * @clk_id_32: Clock identifier for the device for this request.
254 * Only to be used if the clock ID is greater than or equal to
255 * 255.
256 *
257 * Normally, all required clocks are managed by TISCI entity, this is used
258 * only for specific control *IF* required. Auto managed state is
259 * MSG_CLOCK_SW_STATE_AUTO, in other states, TISCI entity assume remote
260 * will explicitly control.
261 *
262 * Request type is TI_SCI_MSG_SET_CLOCK_STATE, response is a generic
263 * ACK or NACK message.
264 */
265struct ti_sci_msg_req_set_clock_state {
266 /* Additional hdr->flags options */
267#define MSG_FLAG_CLOCK_ALLOW_SSC TI_SCI_MSG_FLAG(8)
268#define MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE TI_SCI_MSG_FLAG(9)
269#define MSG_FLAG_CLOCK_INPUT_TERM TI_SCI_MSG_FLAG(10)
270 struct ti_sci_msg_hdr hdr;
271 u32 dev_id;
272 u8 clk_id;
273#define MSG_CLOCK_SW_STATE_UNREQ 0
274#define MSG_CLOCK_SW_STATE_AUTO 1
275#define MSG_CLOCK_SW_STATE_REQ 2
276 u8 request_state;
277 u32 clk_id_32;
278} __packed;
279
280/**
281 * struct ti_sci_msg_req_get_clock_state - Request for clock state
282 * @hdr: Generic Header
283 * @dev_id: Device identifier this request is for
284 * @clk_id: Clock identifier for the device for this request.
285 * Each device has it's own set of clock inputs. This indexes
286 * which clock input to get state of. Set to 255 if the clock
287 * ID is greater than or equal to 255.
288 * @clk_id_32: Clock identifier for the device for the request.
289 * Only to be used if the clock ID is greater than or equal to
290 * 255.
291 *
292 * Request type is TI_SCI_MSG_GET_CLOCK_STATE, response is state
293 * of the clock
294 */
295struct ti_sci_msg_req_get_clock_state {
296 struct ti_sci_msg_hdr hdr;
297 u32 dev_id;
298 u8 clk_id;
299 u32 clk_id_32;
300} __packed;
301
302/**
303 * struct ti_sci_msg_resp_get_clock_state - Response to get clock state
304 * @hdr: Generic Header
305 * @programmed_state: Any programmed state of the clock. This is one of
306 * MSG_CLOCK_SW_STATE* values.
307 * @current_state: Current state of the clock. This is one of:
308 * MSG_CLOCK_HW_STATE_NOT_READY: Clock is not ready
309 * MSG_CLOCK_HW_STATE_READY: Clock is ready
310 *
311 * Response to TI_SCI_MSG_GET_CLOCK_STATE.
312 */
313struct ti_sci_msg_resp_get_clock_state {
314 struct ti_sci_msg_hdr hdr;
315 u8 programmed_state;
316#define MSG_CLOCK_HW_STATE_NOT_READY 0
317#define MSG_CLOCK_HW_STATE_READY 1
318 u8 current_state;
319} __packed;
320
321/**
322 * struct ti_sci_msg_req_set_clock_parent - Set the clock parent
323 * @hdr: Generic Header
324 * @dev_id: Device identifier this request is for
325 * @clk_id: Clock identifier for the device for this request.
326 * Each device has it's own set of clock inputs. This indexes
327 * which clock input to modify. Set to 255 if clock ID is
328 * greater than or equal to 255.
329 * @parent_id: The new clock parent is selectable by an index via this
330 * parameter. Set to 255 if clock ID is greater than or
331 * equal to 255.
332 * @clk_id_32: Clock identifier if @clk_id field is 255.
333 * @parent_id_32: Parent identifier if @parent_id is 255.
334 *
335 * Request type is TI_SCI_MSG_SET_CLOCK_PARENT, response is generic
336 * ACK / NACK message.
337 */
338struct ti_sci_msg_req_set_clock_parent {
339 struct ti_sci_msg_hdr hdr;
340 u32 dev_id;
341 u8 clk_id;
342 u8 parent_id;
343 u32 clk_id_32;
344 u32 parent_id_32;
345} __packed;
346
347/**
348 * struct ti_sci_msg_req_get_clock_parent - Get the clock parent
349 * @hdr: Generic Header
350 * @dev_id: Device identifier this request is for
351 * @clk_id: Clock identifier for the device for this request.
352 * Each device has it's own set of clock inputs. This indexes
353 * which clock input to get the parent for. If this field
354 * contains 255, the actual clock identifier is stored in
355 * @clk_id_32.
356 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
357 *
358 * Request type is TI_SCI_MSG_GET_CLOCK_PARENT, response is parent information
359 */
360struct ti_sci_msg_req_get_clock_parent {
361 struct ti_sci_msg_hdr hdr;
362 u32 dev_id;
363 u8 clk_id;
364 u32 clk_id_32;
365} __packed;
366
367/**
368 * struct ti_sci_msg_resp_get_clock_parent - Response with clock parent
369 * @hdr: Generic Header
370 * @parent_id: The current clock parent. If set to 255, the current parent
371 * ID can be found from the @parent_id_32 field.
372 * @parent_id_32: Current clock parent if @parent_id field is set to
373 * 255.
374 *
375 * Response to TI_SCI_MSG_GET_CLOCK_PARENT.
376 */
377struct ti_sci_msg_resp_get_clock_parent {
378 struct ti_sci_msg_hdr hdr;
379 u8 parent_id;
380 u32 parent_id_32;
381} __packed;
382
383/**
384 * struct ti_sci_msg_req_get_clock_num_parents - Request to get clock parents
385 * @hdr: Generic header
386 * @dev_id: Device identifier this request is for
387 * @clk_id: Clock identifier for the device for this request. Set to
388 * 255 if clock ID is greater than or equal to 255.
389 * @clk_id_32: Clock identifier if the @clk_id field contains 255.
390 *
391 * This request provides information about how many clock parent options
392 * are available for a given clock to a device. This is typically used
393 * for input clocks.
394 *
395 * Request type is TI_SCI_MSG_GET_NUM_CLOCK_PARENTS, response is appropriate
396 * message, or NACK in case of inability to satisfy request.
397 */
398struct ti_sci_msg_req_get_clock_num_parents {
399 struct ti_sci_msg_hdr hdr;
400 u32 dev_id;
401 u8 clk_id;
402 u32 clk_id_32;
403} __packed;
404
405/**
406 * struct ti_sci_msg_resp_get_clock_num_parents - Response for get clk parents
407 * @hdr: Generic header
408 * @num_parents: Number of clock parents. If set to 255, the actual
409 * number of parents is stored into @num_parents_32
410 * field instead.
411 * @num_parents_32: Number of clock parents if @num_parents field is
412 * set to 255.
413 *
414 * Response to TI_SCI_MSG_GET_NUM_CLOCK_PARENTS
415 */
416struct ti_sci_msg_resp_get_clock_num_parents {
417 struct ti_sci_msg_hdr hdr;
418 u8 num_parents;
419 u32 num_parents_32;
420} __packed;
421
422/**
423 * struct ti_sci_msg_req_query_clock_freq - Request to query a frequency
424 * @hdr: Generic Header
425 * @dev_id: Device identifier this request is for
426 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
427 * allowable programmed frequency and does not account for clock
428 * tolerances and jitter.
429 * @target_freq_hz: The target clock frequency. A frequency will be found
430 * as close to this target frequency as possible.
431 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
432 * allowable programmed frequency and does not account for clock
433 * tolerances and jitter.
434 * @clk_id: Clock identifier for the device for this request. Set to
435 * 255 if clock identifier is greater than or equal to 255.
436 * @clk_id_32: Clock identifier if @clk_id is set to 255.
437 *
438 * NOTE: Normally clock frequency management is automatically done by TISCI
439 * entity. In case of specific requests, TISCI evaluates capability to achieve
440 * requested frequency within provided range and responds with
441 * result message.
442 *
443 * Request type is TI_SCI_MSG_QUERY_CLOCK_FREQ, response is appropriate message,
444 * or NACK in case of inability to satisfy request.
445 */
446struct ti_sci_msg_req_query_clock_freq {
447 struct ti_sci_msg_hdr hdr;
448 u32 dev_id;
449 u64 min_freq_hz;
450 u64 target_freq_hz;
451 u64 max_freq_hz;
452 u8 clk_id;
453 u32 clk_id_32;
454} __packed;
455
456/**
457 * struct ti_sci_msg_resp_query_clock_freq - Response to a clock frequency query
458 * @hdr: Generic Header
459 * @freq_hz: Frequency that is the best match in Hz.
460 *
461 * Response to request type TI_SCI_MSG_QUERY_CLOCK_FREQ. NOTE: if the request
462 * cannot be satisfied, the message will be of type NACK.
463 */
464struct ti_sci_msg_resp_query_clock_freq {
465 struct ti_sci_msg_hdr hdr;
466 u64 freq_hz;
467} __packed;
468
469/**
470 * struct ti_sci_msg_req_set_clock_freq - Request to setup a clock frequency
471 * @hdr: Generic Header
472 * @dev_id: Device identifier this request is for
473 * @min_freq_hz: The minimum allowable frequency in Hz. This is the minimum
474 * allowable programmed frequency and does not account for clock
475 * tolerances and jitter.
476 * @target_freq_hz: The target clock frequency. The clock will be programmed
477 * at a rate as close to this target frequency as possible.
478 * @max_freq_hz: The maximum allowable frequency in Hz. This is the maximum
479 * allowable programmed frequency and does not account for clock
480 * tolerances and jitter.
481 * @clk_id: Clock identifier for the device for this request. Set to
482 * 255 if clock ID is greater than or equal to 255.
483 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
484 *
485 * NOTE: Normally clock frequency management is automatically done by TISCI
486 * entity. In case of specific requests, TISCI evaluates capability to achieve
487 * requested range and responds with success/failure message.
488 *
489 * This sets the desired frequency for a clock within an allowable
490 * range. This message will fail on an enabled clock unless
491 * MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE is set for the clock. Additionally,
492 * if other clocks have their frequency modified due to this message,
493 * they also must have the MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE or be disabled.
494 *
495 * Calling set frequency on a clock input to the SoC pseudo-device will
496 * inform the PMMC of that clock's frequency. Setting a frequency of
497 * zero will indicate the clock is disabled.
498 *
499 * Calling set frequency on clock outputs from the SoC pseudo-device will
500 * function similarly to setting the clock frequency on a device.
501 *
502 * Request type is TI_SCI_MSG_SET_CLOCK_FREQ, response is a generic ACK/NACK
503 * message.
504 */
505struct ti_sci_msg_req_set_clock_freq {
506 struct ti_sci_msg_hdr hdr;
507 u32 dev_id;
508 u64 min_freq_hz;
509 u64 target_freq_hz;
510 u64 max_freq_hz;
511 u8 clk_id;
512 u32 clk_id_32;
513} __packed;
514
515/**
516 * struct ti_sci_msg_req_get_clock_freq - Request to get the clock frequency
517 * @hdr: Generic Header
518 * @dev_id: Device identifier this request is for
519 * @clk_id: Clock identifier for the device for this request. Set to
520 * 255 if clock ID is greater than or equal to 255.
521 * @clk_id_32: Clock identifier if @clk_id field is set to 255.
522 *
523 * NOTE: Normally clock frequency management is automatically done by TISCI
524 * entity. In some cases, clock frequencies are configured by host.
525 *
526 * Request type is TI_SCI_MSG_GET_CLOCK_FREQ, responded with clock frequency
527 * that the clock is currently at.
528 */
529struct ti_sci_msg_req_get_clock_freq {
530 struct ti_sci_msg_hdr hdr;
531 u32 dev_id;
532 u8 clk_id;
533 u32 clk_id_32;
534} __packed;
535
536/**
537 * struct ti_sci_msg_resp_get_clock_freq - Response of clock frequency request
538 * @hdr: Generic Header
539 * @freq_hz: Frequency that the clock is currently on, in Hz.
540 *
541 * Response to request type TI_SCI_MSG_GET_CLOCK_FREQ.
542 */
543struct ti_sci_msg_resp_get_clock_freq {
544 struct ti_sci_msg_hdr hdr;
545 u64 freq_hz;
546} __packed;
547
548#define TI_SCI_IRQ_SECONDARY_HOST_INVALID 0xff
549
550/**
551 * struct ti_sci_msg_req_get_resource_range - Request to get a host's assigned
552 * range of resources.
553 * @hdr: Generic Header
554 * @type: Unique resource assignment type
555 * @subtype: Resource assignment subtype within the resource type.
556 * @secondary_host: Host processing entity to which the resources are
557 * allocated. This is required only when the destination
558 * host id id different from ti sci interface host id,
559 * else TI_SCI_IRQ_SECONDARY_HOST_INVALID can be passed.
560 *
561 * Request type is TI_SCI_MSG_GET_RESOURCE_RANGE. Responded with requested
562 * resource range which is of type TI_SCI_MSG_GET_RESOURCE_RANGE.
563 */
564struct ti_sci_msg_req_get_resource_range {
565 struct ti_sci_msg_hdr hdr;
566#define MSG_RM_RESOURCE_TYPE_MASK GENMASK(9, 0)
567#define MSG_RM_RESOURCE_SUBTYPE_MASK GENMASK(5, 0)
568 u16 type;
569 u8 subtype;
570 u8 secondary_host;
571} __packed;
572
573/**
574 * struct ti_sci_msg_resp_get_resource_range - Response to resource get range.
575 * @hdr: Generic Header
576 * @range_start: Start index of the first resource range.
577 * @range_num: Number of resources in the first range.
578 * @range_start_sec: Start index of the second resource range.
579 * @range_num_sec: Number of resources in the second range.
580 *
581 * Response to request TI_SCI_MSG_GET_RESOURCE_RANGE.
582 */
583struct ti_sci_msg_resp_get_resource_range {
584 struct ti_sci_msg_hdr hdr;
585 u16 range_start;
586 u16 range_num;
587 u16 range_start_sec;
588 u16 range_num_sec;
589} __packed;
590
591/**
592 * struct ti_sci_msg_req_manage_irq - Request to configure/release the route
593 * between the dev and the host.
594 * @hdr: Generic Header
595 * @valid_params: Bit fields defining the validity of interrupt source
596 * parameters. If a bit is not set, then corresponding
597 * field is not valid and will not be used for route set.
598 * Bit field definitions:
599 * 0 - Valid bit for @dst_id
600 * 1 - Valid bit for @dst_host_irq
601 * 2 - Valid bit for @ia_id
602 * 3 - Valid bit for @vint
603 * 4 - Valid bit for @global_event
604 * 5 - Valid bit for @vint_status_bit_index
605 * 31 - Valid bit for @secondary_host
606 * @src_id: IRQ source peripheral ID.
607 * @src_index: IRQ source index within the peripheral
608 * @dst_id: IRQ Destination ID. Based on the architecture it can be
609 * IRQ controller or host processor ID.
610 * @dst_host_irq: IRQ number of the destination host IRQ controller
611 * @ia_id: Device ID of the interrupt aggregator in which the
612 * vint resides.
613 * @vint: Virtual interrupt number if the interrupt route
614 * is through an interrupt aggregator.
615 * @global_event: Global event that is to be mapped to interrupt
616 * aggregator virtual interrupt status bit.
617 * @vint_status_bit: Virtual interrupt status bit if the interrupt route
618 * utilizes an interrupt aggregator status bit.
619 * @secondary_host: Host ID of the IRQ destination computing entity. This is
620 * required only when destination host id is different
621 * from ti sci interface host id.
622 *
623 * Request type is TI_SCI_MSG_SET/RELEASE_IRQ.
624 * Response is generic ACK / NACK message.
625 */
626struct ti_sci_msg_req_manage_irq {
627 struct ti_sci_msg_hdr hdr;
628#define MSG_FLAG_DST_ID_VALID TI_SCI_MSG_FLAG(0)
629#define MSG_FLAG_DST_HOST_IRQ_VALID TI_SCI_MSG_FLAG(1)
630#define MSG_FLAG_IA_ID_VALID TI_SCI_MSG_FLAG(2)
631#define MSG_FLAG_VINT_VALID TI_SCI_MSG_FLAG(3)
632#define MSG_FLAG_GLB_EVNT_VALID TI_SCI_MSG_FLAG(4)
633#define MSG_FLAG_VINT_STS_BIT_VALID TI_SCI_MSG_FLAG(5)
634#define MSG_FLAG_SHOST_VALID TI_SCI_MSG_FLAG(31)
635 u32 valid_params;
636 u16 src_id;
637 u16 src_index;
638 u16 dst_id;
639 u16 dst_host_irq;
640 u16 ia_id;
641 u16 vint;
642 u16 global_event;
643 u8 vint_status_bit;
644 u8 secondary_host;
645} __packed;
646
647/**
648 * struct ti_sci_msg_rm_ring_cfg_req - Configure a Navigator Subsystem ring
649 *
650 * Configures the non-real-time registers of a Navigator Subsystem ring.
651 * @hdr: Generic Header
652 * @valid_params: Bitfield defining validity of ring configuration parameters.
653 * The ring configuration fields are not valid, and will not be used for
654 * ring configuration, if their corresponding valid bit is zero.
655 * Valid bit usage:
656 * 0 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_lo
657 * 1 - Valid bit for @tisci_msg_rm_ring_cfg_req addr_hi
658 * 2 - Valid bit for @tisci_msg_rm_ring_cfg_req count
659 * 3 - Valid bit for @tisci_msg_rm_ring_cfg_req mode
660 * 4 - Valid bit for @tisci_msg_rm_ring_cfg_req size
661 * 5 - Valid bit for @tisci_msg_rm_ring_cfg_req order_id
662 * 6 - Valid bit for @tisci_msg_rm_ring_cfg_req virtid
663 * 7 - Valid bit for @tisci_msg_rm_ring_cfg_req ASEL
664 * @nav_id: Device ID of Navigator Subsystem from which the ring is allocated
665 * @index: ring index to be configured.
666 * @addr_lo: 32 LSBs of ring base address to be programmed into the ring's
667 * RING_BA_LO register
668 * @addr_hi: 16 MSBs of ring base address to be programmed into the ring's
669 * RING_BA_HI register.
670 * @count: Number of ring elements. Must be even if mode is CREDENTIALS or QM
671 * modes.
672 * @mode: Specifies the mode the ring is to be configured.
673 * @size: Specifies encoded ring element size. To calculate the encoded size use
674 * the formula (log2(size_bytes) - 2), where size_bytes cannot be
675 * greater than 256.
676 * @order_id: Specifies the ring's bus order ID.
677 * @virtid: Ring virt ID value
678 * @asel: Ring ASEL (address select) value to be set into the ASEL field of the
679 * ring's RING_BA_HI register.
680 */
681struct ti_sci_msg_rm_ring_cfg_req {
682 struct ti_sci_msg_hdr hdr;
683 u32 valid_params;
684 u16 nav_id;
685 u16 index;
686 u32 addr_lo;
687 u32 addr_hi;
688 u32 count;
689 u8 mode;
690 u8 size;
691 u8 order_id;
692 u16 virtid;
693 u8 asel;
694} __packed;
695
696/**
697 * struct ti_sci_msg_psil_pair - Pairs a PSI-L source thread to a destination
698 * thread
699 * @hdr: Generic Header
700 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
701 * used to pair the source and destination threads.
702 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
703 *
704 * UDMAP transmit channels mapped to source threads will have their
705 * TCHAN_THRD_ID register programmed with the destination thread if the pairing
706 * is successful.
707
708 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
709 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
710 * the destination thread is not greater than or equal to 0x8000.
711 *
712 * UDMAP receive channels mapped to destination threads will have their
713 * RCHAN_THRD_ID register programmed with the source thread if the pairing
714 * is successful.
715 *
716 * Request type is TI_SCI_MSG_RM_PSIL_PAIR, response is a generic ACK or NACK
717 * message.
718 */
719struct ti_sci_msg_psil_pair {
720 struct ti_sci_msg_hdr hdr;
721 u32 nav_id;
722 u32 src_thread;
723 u32 dst_thread;
724} __packed;
725
726/**
727 * struct ti_sci_msg_psil_unpair - Unpairs a PSI-L source thread from a
728 * destination thread
729 * @hdr: Generic Header
730 * @nav_id: SoC Navigator Subsystem device ID whose PSI-L config proxy is
731 * used to unpair the source and destination threads.
732 * @src_thread: PSI-L source thread ID within the PSI-L System thread map.
733 *
734 * UDMAP transmit channels mapped to source threads will have their
735 * TCHAN_THRD_ID register cleared if the unpairing is successful.
736 *
737 * @dst_thread: PSI-L destination thread ID within the PSI-L System thread map.
738 * PSI-L destination threads start at index 0x8000. The request is NACK'd if
739 * the destination thread is not greater than or equal to 0x8000.
740 *
741 * UDMAP receive channels mapped to destination threads will have their
742 * RCHAN_THRD_ID register cleared if the unpairing is successful.
743 *
744 * Request type is TI_SCI_MSG_RM_PSIL_UNPAIR, response is a generic ACK or NACK
745 * message.
746 */
747struct ti_sci_msg_psil_unpair {
748 struct ti_sci_msg_hdr hdr;
749 u32 nav_id;
750 u32 src_thread;
751 u32 dst_thread;
752} __packed;
753
754/**
755 * struct ti_sci_msg_udmap_rx_flow_cfg - UDMAP receive flow configuration
756 * message
757 * @hdr: Generic Header
758 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
759 * allocated
760 * @flow_index: UDMAP receive flow index for non-optional configuration.
761 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
762 * @rx_einfo_present: UDMAP receive flow extended packet info present.
763 * @rx_psinfo_present: UDMAP receive flow PS words present.
764 * @rx_error_handling: UDMAP receive flow error handling configuration. Valid
765 * values are TI_SCI_RM_UDMAP_RX_FLOW_ERR_DROP/RETRY.
766 * @rx_desc_type: UDMAP receive flow descriptor type. It can be one of
767 * TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST/MONO.
768 * @rx_sop_offset: UDMAP receive flow start of packet offset.
769 * @rx_dest_qnum: UDMAP receive flow destination queue number.
770 * @rx_ps_location: UDMAP receive flow PS words location.
771 * 0 - end of packet descriptor
772 * 1 - Beginning of the data buffer
773 * @rx_src_tag_hi: UDMAP receive flow source tag high byte constant
774 * @rx_src_tag_lo: UDMAP receive flow source tag low byte constant
775 * @rx_dest_tag_hi: UDMAP receive flow destination tag high byte constant
776 * @rx_dest_tag_lo: UDMAP receive flow destination tag low byte constant
777 * @rx_src_tag_hi_sel: UDMAP receive flow source tag high byte selector
778 * @rx_src_tag_lo_sel: UDMAP receive flow source tag low byte selector
779 * @rx_dest_tag_hi_sel: UDMAP receive flow destination tag high byte selector
780 * @rx_dest_tag_lo_sel: UDMAP receive flow destination tag low byte selector
781 * @rx_size_thresh_en: UDMAP receive flow packet size based free buffer queue
782 * enable. If enabled, the ti_sci_rm_udmap_rx_flow_opt_cfg also need to be
783 * configured and sent.
784 * @rx_fdq0_sz0_qnum: UDMAP receive flow free descriptor queue 0.
785 * @rx_fdq1_qnum: UDMAP receive flow free descriptor queue 1.
786 * @rx_fdq2_qnum: UDMAP receive flow free descriptor queue 2.
787 * @rx_fdq3_qnum: UDMAP receive flow free descriptor queue 3.
788 *
789 * For detailed information on the settings, see the UDMAP section of the TRM.
790 */
791struct ti_sci_msg_udmap_rx_flow_cfg {
792 struct ti_sci_msg_hdr hdr;
793 u32 nav_id;
794 u32 flow_index;
795 u32 rx_ch_index;
796 u8 rx_einfo_present;
797 u8 rx_psinfo_present;
798 u8 rx_error_handling;
799 u8 rx_desc_type;
800 u16 rx_sop_offset;
801 u16 rx_dest_qnum;
802 u8 rx_ps_location;
803 u8 rx_src_tag_hi;
804 u8 rx_src_tag_lo;
805 u8 rx_dest_tag_hi;
806 u8 rx_dest_tag_lo;
807 u8 rx_src_tag_hi_sel;
808 u8 rx_src_tag_lo_sel;
809 u8 rx_dest_tag_hi_sel;
810 u8 rx_dest_tag_lo_sel;
811 u8 rx_size_thresh_en;
812 u16 rx_fdq0_sz0_qnum;
813 u16 rx_fdq1_qnum;
814 u16 rx_fdq2_qnum;
815 u16 rx_fdq3_qnum;
816} __packed;
817
818/**
819 * struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg - parameters for UDMAP receive
820 * flow optional configuration
821 * @hdr: Generic Header
822 * @nav_id: SoC Navigator Subsystem device ID from which the receive flow is
823 * allocated
824 * @flow_index: UDMAP receive flow index for optional configuration.
825 * @rx_ch_index: Specifies the index of the receive channel using the flow_index
826 * @rx_size_thresh0: UDMAP receive flow packet size threshold 0.
827 * @rx_size_thresh1: UDMAP receive flow packet size threshold 1.
828 * @rx_size_thresh2: UDMAP receive flow packet size threshold 2.
829 * @rx_fdq0_sz1_qnum: UDMAP receive flow free descriptor queue for size
830 * threshold 1.
831 * @rx_fdq0_sz2_qnum: UDMAP receive flow free descriptor queue for size
832 * threshold 2.
833 * @rx_fdq0_sz3_qnum: UDMAP receive flow free descriptor queue for size
834 * threshold 3.
835 *
836 * For detailed information on the settings, see the UDMAP section of the TRM.
837 */
838struct rm_ti_sci_msg_udmap_rx_flow_opt_cfg {
839 struct ti_sci_msg_hdr hdr;
840 u32 nav_id;
841 u32 flow_index;
842 u32 rx_ch_index;
843 u16 rx_size_thresh0;
844 u16 rx_size_thresh1;
845 u16 rx_size_thresh2;
846 u16 rx_fdq0_sz1_qnum;
847 u16 rx_fdq0_sz2_qnum;
848 u16 rx_fdq0_sz3_qnum;
849} __packed;
850
851/**
852 * Configures a Navigator Subsystem UDMAP transmit channel
853 *
854 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
855 * transmit channel. The channel index must be assigned to the host defined
856 * in the TISCI header via the RM board configuration resource assignment
857 * range list.
858 *
859 * @hdr: Generic Header
860 *
861 * @valid_params: Bitfield defining validity of tx channel configuration
862 * parameters. The tx channel configuration fields are not valid, and will not
863 * be used for ch configuration, if their corresponding valid bit is zero.
864 * Valid bit usage:
865 * 0 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_pause_on_err
866 * 1 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_atype
867 * 2 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_chan_type
868 * 3 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_fetch_size
869 * 4 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::txcq_qnum
870 * 5 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_priority
871 * 6 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_qos
872 * 7 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_orderid
873 * 8 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_sched_priority
874 * 9 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_einfo
875 * 10 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_filt_pswords
876 * 11 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_supr_tdpkt
877 * 12 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_credit_count
878 * 13 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::fdepth
879 * 14 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_burst_size
880 * 15 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::tx_tdtype
881 * 16 - Valid bit for @ref ti_sci_msg_rm_udmap_tx_ch_cfg::extended_ch_type
882 *
883 * @nav_id: SoC device ID of Navigator Subsystem where tx channel is located
884 *
885 * @index: UDMAP transmit channel index.
886 *
887 * @tx_pause_on_err: UDMAP transmit channel pause on error configuration to
888 * be programmed into the tx_pause_on_err field of the channel's TCHAN_TCFG
889 * register.
890 *
891 * @tx_filt_einfo: UDMAP transmit channel extended packet information passing
892 * configuration to be programmed into the tx_filt_einfo field of the
893 * channel's TCHAN_TCFG register.
894 *
895 * @tx_filt_pswords: UDMAP transmit channel protocol specific word passing
896 * configuration to be programmed into the tx_filt_pswords field of the
897 * channel's TCHAN_TCFG register.
898 *
899 * @tx_atype: UDMAP transmit channel non Ring Accelerator access pointer
900 * interpretation configuration to be programmed into the tx_atype field of
901 * the channel's TCHAN_TCFG register.
902 *
903 * @tx_chan_type: UDMAP transmit channel functional channel type and work
904 * passing mechanism configuration to be programmed into the tx_chan_type
905 * field of the channel's TCHAN_TCFG register.
906 *
907 * @tx_supr_tdpkt: UDMAP transmit channel teardown packet generation suppression
908 * configuration to be programmed into the tx_supr_tdpkt field of the channel's
909 * TCHAN_TCFG register.
910 *
911 * @tx_fetch_size: UDMAP transmit channel number of 32-bit descriptor words to
912 * fetch configuration to be programmed into the tx_fetch_size field of the
913 * channel's TCHAN_TCFG register. The user must make sure to set the maximum
914 * word count that can pass through the channel for any allowed descriptor type.
915 *
916 * @tx_credit_count: UDMAP transmit channel transfer request credit count
917 * configuration to be programmed into the count field of the TCHAN_TCREDIT
918 * register. Specifies how many credits for complete TRs are available.
919 *
920 * @txcq_qnum: UDMAP transmit channel completion queue configuration to be
921 * programmed into the txcq_qnum field of the TCHAN_TCQ register. The specified
922 * completion queue must be assigned to the host, or a subordinate of the host,
923 * requesting configuration of the transmit channel.
924 *
925 * @tx_priority: UDMAP transmit channel transmit priority value to be programmed
926 * into the priority field of the channel's TCHAN_TPRI_CTRL register.
927 *
928 * @tx_qos: UDMAP transmit channel transmit qos value to be programmed into the
929 * qos field of the channel's TCHAN_TPRI_CTRL register.
930 *
931 * @tx_orderid: UDMAP transmit channel bus order id value to be programmed into
932 * the orderid field of the channel's TCHAN_TPRI_CTRL register.
933 *
934 * @fdepth: UDMAP transmit channel FIFO depth configuration to be programmed
935 * into the fdepth field of the TCHAN_TFIFO_DEPTH register. Sets the number of
936 * Tx FIFO bytes which are allowed to be stored for the channel. Check the UDMAP
937 * section of the TRM for restrictions regarding this parameter.
938 *
939 * @tx_sched_priority: UDMAP transmit channel tx scheduling priority
940 * configuration to be programmed into the priority field of the channel's
941 * TCHAN_TST_SCHED register.
942 *
943 * @tx_burst_size: UDMAP transmit channel burst size configuration to be
944 * programmed into the tx_burst_size field of the TCHAN_TCFG register.
945 *
946 * @tx_tdtype: UDMAP transmit channel teardown type configuration to be
947 * programmed into the tdtype field of the TCHAN_TCFG register:
948 * 0 - Return immediately
949 * 1 - Wait for completion message from remote peer
950 *
951 * @extended_ch_type: Valid for BCDMA.
952 * 0 - the channel is split tx channel (tchan)
953 * 1 - the channel is block copy channel (bchan)
954 */
955struct ti_sci_msg_rm_udmap_tx_ch_cfg_req {
956 struct ti_sci_msg_hdr hdr;
957 u32 valid_params;
958 u16 nav_id;
959 u16 index;
960 u8 tx_pause_on_err;
961 u8 tx_filt_einfo;
962 u8 tx_filt_pswords;
963 u8 tx_atype;
964 u8 tx_chan_type;
965 u8 tx_supr_tdpkt;
966 u16 tx_fetch_size;
967 u8 tx_credit_count;
968 u16 txcq_qnum;
969 u8 tx_priority;
970 u8 tx_qos;
971 u8 tx_orderid;
972 u16 fdepth;
973 u8 tx_sched_priority;
974 u8 tx_burst_size;
975 u8 tx_tdtype;
976 u8 extended_ch_type;
977} __packed;
978
979/**
980 * Configures a Navigator Subsystem UDMAP receive channel
981 *
982 * Configures the non-real-time registers of a Navigator Subsystem UDMAP
983 * receive channel. The channel index must be assigned to the host defined
984 * in the TISCI header via the RM board configuration resource assignment
985 * range list.
986 *
987 * @hdr: Generic Header
988 *
989 * @valid_params: Bitfield defining validity of rx channel configuration
990 * parameters.
991 * The rx channel configuration fields are not valid, and will not be used for
992 * ch configuration, if their corresponding valid bit is zero.
993 * Valid bit usage:
994 * 0 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_pause_on_err
995 * 1 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
996 * 2 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
997 * 3 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_fetch_size
998 * 4 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rxcq_qnum
999 * 5 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_priority
1000 * 6 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_qos
1001 * 7 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_orderid
1002 * 8 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
1003 * 9 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_start
1004 * 10 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::flowid_cnt
1005 * 11 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_short
1006 * 12 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_ignore_long
1007 * 14 - Valid bit for @ti_sci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size
1008 *
1009 * @nav_id: SoC device ID of Navigator Subsystem where rx channel is located
1010 *
1011 * @index: UDMAP receive channel index.
1012 *
1013 * @rx_fetch_size: UDMAP receive channel number of 32-bit descriptor words to
1014 * fetch configuration to be programmed into the rx_fetch_size field of the
1015 * channel's RCHAN_RCFG register.
1016 *
1017 * @rxcq_qnum: UDMAP receive channel completion queue configuration to be
1018 * programmed into the rxcq_qnum field of the RCHAN_RCQ register.
1019 * The specified completion queue must be assigned to the host, or a subordinate
1020 * of the host, requesting configuration of the receive channel.
1021 *
1022 * @rx_priority: UDMAP receive channel receive priority value to be programmed
1023 * into the priority field of the channel's RCHAN_RPRI_CTRL register.
1024 *
1025 * @rx_qos: UDMAP receive channel receive qos value to be programmed into the
1026 * qos field of the channel's RCHAN_RPRI_CTRL register.
1027 *
1028 * @rx_orderid: UDMAP receive channel bus order id value to be programmed into
1029 * the orderid field of the channel's RCHAN_RPRI_CTRL register.
1030 *
1031 * @rx_sched_priority: UDMAP receive channel rx scheduling priority
1032 * configuration to be programmed into the priority field of the channel's
1033 * RCHAN_RST_SCHED register.
1034 *
1035 * @flowid_start: UDMAP receive channel additional flows starting index
1036 * configuration to program into the flow_start field of the RCHAN_RFLOW_RNG
1037 * register. Specifies the starting index for flow IDs the receive channel is to
1038 * make use of beyond the default flow. flowid_start and @ref flowid_cnt must be
1039 * set as valid and configured together. The starting flow ID set by
1040 * @ref flowid_cnt must be a flow index within the Navigator Subsystem's subset
1041 * of flows beyond the default flows statically mapped to receive channels.
1042 * The additional flows must be assigned to the host, or a subordinate of the
1043 * host, requesting configuration of the receive channel.
1044 *
1045 * @flowid_cnt: UDMAP receive channel additional flows count configuration to
1046 * program into the flowid_cnt field of the RCHAN_RFLOW_RNG register.
1047 * This field specifies how many flow IDs are in the additional contiguous range
1048 * of legal flow IDs for the channel. @ref flowid_start and flowid_cnt must be
1049 * set as valid and configured together. Disabling the valid_params field bit
1050 * for flowid_cnt indicates no flow IDs other than the default are to be
1051 * allocated and used by the receive channel. @ref flowid_start plus flowid_cnt
1052 * cannot be greater than the number of receive flows in the receive channel's
1053 * Navigator Subsystem. The additional flows must be assigned to the host, or a
1054 * subordinate of the host, requesting configuration of the receive channel.
1055 *
1056 * @rx_pause_on_err: UDMAP receive channel pause on error configuration to be
1057 * programmed into the rx_pause_on_err field of the channel's RCHAN_RCFG
1058 * register.
1059 *
1060 * @rx_atype: UDMAP receive channel non Ring Accelerator access pointer
1061 * interpretation configuration to be programmed into the rx_atype field of the
1062 * channel's RCHAN_RCFG register.
1063 *
1064 * @rx_chan_type: UDMAP receive channel functional channel type and work passing
1065 * mechanism configuration to be programmed into the rx_chan_type field of the
1066 * channel's RCHAN_RCFG register.
1067 *
1068 * @rx_ignore_short: UDMAP receive channel short packet treatment configuration
1069 * to be programmed into the rx_ignore_short field of the RCHAN_RCFG register.
1070 *
1071 * @rx_ignore_long: UDMAP receive channel long packet treatment configuration to
1072 * be programmed into the rx_ignore_long field of the RCHAN_RCFG register.
1073 *
1074 * @rx_burst_size: UDMAP receive channel burst size configuration to be
1075 * programmed into the rx_burst_size field of the RCHAN_RCFG register.
1076 */
1077struct ti_sci_msg_rm_udmap_rx_ch_cfg_req {
1078 struct ti_sci_msg_hdr hdr;
1079 u32 valid_params;
1080 u16 nav_id;
1081 u16 index;
1082 u16 rx_fetch_size;
1083 u16 rxcq_qnum;
1084 u8 rx_priority;
1085 u8 rx_qos;
1086 u8 rx_orderid;
1087 u8 rx_sched_priority;
1088 u16 flowid_start;
1089 u16 flowid_cnt;
1090 u8 rx_pause_on_err;
1091 u8 rx_atype;
1092 u8 rx_chan_type;
1093 u8 rx_ignore_short;
1094 u8 rx_ignore_long;
1095 u8 rx_burst_size;
1096} __packed;
1097
1098/**
1099 * Configures a Navigator Subsystem UDMAP receive flow
1100 *
1101 * Configures a Navigator Subsystem UDMAP receive flow's registers.
1102 * Configuration does not include the flow registers which handle size-based
1103 * free descriptor queue routing.
1104 *
1105 * The flow index must be assigned to the host defined in the TISCI header via
1106 * the RM board configuration resource assignment range list.
1107 *
1108 * @hdr: Standard TISCI header
1109 *
1110 * @valid_params
1111 * Bitfield defining validity of rx flow configuration parameters. The
1112 * rx flow configuration fields are not valid, and will not be used for flow
1113 * configuration, if their corresponding valid bit is zero. Valid bit usage:
1114 * 0 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
1115 * 1 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
1116 * 2 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
1117 * 3 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_desc_type
1118 * 4 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
1119 * 5 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_qnum
1120 * 6 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi
1121 * 7 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo
1122 * 8 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi
1123 * 9 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo
1124 * 10 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_hi_sel
1125 * 11 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_src_tag_lo_sel
1126 * 12 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_hi_sel
1127 * 13 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_dest_tag_lo_sel
1128 * 14 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq0_sz0_qnum
1129 * 15 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq1_sz0_qnum
1130 * 16 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq2_sz0_qnum
1131 * 17 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_fdq3_sz0_qnum
1132 * 18 - Valid bit for @tisci_msg_rm_udmap_flow_cfg_req::rx_ps_location
1133 *
1134 * @nav_id: SoC device ID of Navigator Subsystem from which the receive flow is
1135 * allocated
1136 *
1137 * @flow_index: UDMAP receive flow index for non-optional configuration.
1138 *
1139 * @rx_einfo_present:
1140 * UDMAP receive flow extended packet info present configuration to be
1141 * programmed into the rx_einfo_present field of the flow's RFLOW_RFA register.
1142 *
1143 * @rx_psinfo_present:
1144 * UDMAP receive flow PS words present configuration to be programmed into the
1145 * rx_psinfo_present field of the flow's RFLOW_RFA register.
1146 *
1147 * @rx_error_handling:
1148 * UDMAP receive flow error handling configuration to be programmed into the
1149 * rx_error_handling field of the flow's RFLOW_RFA register.
1150 *
1151 * @rx_desc_type:
1152 * UDMAP receive flow descriptor type configuration to be programmed into the
1153 * rx_desc_type field field of the flow's RFLOW_RFA register.
1154 *
1155 * @rx_sop_offset:
1156 * UDMAP receive flow start of packet offset configuration to be programmed
1157 * into the rx_sop_offset field of the RFLOW_RFA register. See the UDMAP
1158 * section of the TRM for more information on this setting. Valid values for
1159 * this field are 0-255 bytes.
1160 *
1161 * @rx_dest_qnum:
1162 * UDMAP receive flow destination queue configuration to be programmed into the
1163 * rx_dest_qnum field of the flow's RFLOW_RFA register. The specified
1164 * destination queue must be valid within the Navigator Subsystem and must be
1165 * owned by the host, or a subordinate of the host, requesting allocation and
1166 * configuration of the receive flow.
1167 *
1168 * @rx_src_tag_hi:
1169 * UDMAP receive flow source tag high byte constant configuration to be
1170 * programmed into the rx_src_tag_hi field of the flow's RFLOW_RFB register.
1171 * See the UDMAP section of the TRM for more information on this setting.
1172 *
1173 * @rx_src_tag_lo:
1174 * UDMAP receive flow source tag low byte constant configuration to be
1175 * programmed into the rx_src_tag_lo field of the flow's RFLOW_RFB register.
1176 * See the UDMAP section of the TRM for more information on this setting.
1177 *
1178 * @rx_dest_tag_hi:
1179 * UDMAP receive flow destination tag high byte constant configuration to be
1180 * programmed into the rx_dest_tag_hi field of the flow's RFLOW_RFB register.
1181 * See the UDMAP section of the TRM for more information on this setting.
1182 *
1183 * @rx_dest_tag_lo:
1184 * UDMAP receive flow destination tag low byte constant configuration to be
1185 * programmed into the rx_dest_tag_lo field of the flow's RFLOW_RFB register.
1186 * See the UDMAP section of the TRM for more information on this setting.
1187 *
1188 * @rx_src_tag_hi_sel:
1189 * UDMAP receive flow source tag high byte selector configuration to be
1190 * programmed into the rx_src_tag_hi_sel field of the RFLOW_RFC register. See
1191 * the UDMAP section of the TRM for more information on this setting.
1192 *
1193 * @rx_src_tag_lo_sel:
1194 * UDMAP receive flow source tag low byte selector configuration to be
1195 * programmed into the rx_src_tag_lo_sel field of the RFLOW_RFC register. See
1196 * the UDMAP section of the TRM for more information on this setting.
1197 *
1198 * @rx_dest_tag_hi_sel:
1199 * UDMAP receive flow destination tag high byte selector configuration to be
1200 * programmed into the rx_dest_tag_hi_sel field of the RFLOW_RFC register. See
1201 * the UDMAP section of the TRM for more information on this setting.
1202 *
1203 * @rx_dest_tag_lo_sel:
1204 * UDMAP receive flow destination tag low byte selector configuration to be
1205 * programmed into the rx_dest_tag_lo_sel field of the RFLOW_RFC register. See
1206 * the UDMAP section of the TRM for more information on this setting.
1207 *
1208 * @rx_fdq0_sz0_qnum:
1209 * UDMAP receive flow free descriptor queue 0 configuration to be programmed
1210 * into the rx_fdq0_sz0_qnum field of the flow's RFLOW_RFD register. See the
1211 * UDMAP section of the TRM for more information on this setting. The specified
1212 * free queue must be valid within the Navigator Subsystem and must be owned
1213 * by the host, or a subordinate of the host, requesting allocation and
1214 * configuration of the receive flow.
1215 *
1216 * @rx_fdq1_qnum:
1217 * UDMAP receive flow free descriptor queue 1 configuration to be programmed
1218 * into the rx_fdq1_qnum field of the flow's RFLOW_RFD register. See the
1219 * UDMAP section of the TRM for more information on this setting. The specified
1220 * free queue must be valid within the Navigator Subsystem and must be owned
1221 * by the host, or a subordinate of the host, requesting allocation and
1222 * configuration of the receive flow.
1223 *
1224 * @rx_fdq2_qnum:
1225 * UDMAP receive flow free descriptor queue 2 configuration to be programmed
1226 * into the rx_fdq2_qnum field of the flow's RFLOW_RFE register. See the
1227 * UDMAP section of the TRM for more information on this setting. The specified
1228 * free queue must be valid within the Navigator Subsystem and must be owned
1229 * by the host, or a subordinate of the host, requesting allocation and
1230 * configuration of the receive flow.
1231 *
1232 * @rx_fdq3_qnum:
1233 * UDMAP receive flow free descriptor queue 3 configuration to be programmed
1234 * into the rx_fdq3_qnum field of the flow's RFLOW_RFE register. See the
1235 * UDMAP section of the TRM for more information on this setting. The specified
1236 * free queue must be valid within the Navigator Subsystem and must be owned
1237 * by the host, or a subordinate of the host, requesting allocation and
1238 * configuration of the receive flow.
1239 *
1240 * @rx_ps_location:
1241 * UDMAP receive flow PS words location configuration to be programmed into the
1242 * rx_ps_location field of the flow's RFLOW_RFA register.
1243 */
1244struct ti_sci_msg_rm_udmap_flow_cfg_req {
1245 struct ti_sci_msg_hdr hdr;
1246 u32 valid_params;
1247 u16 nav_id;
1248 u16 flow_index;
1249 u8 rx_einfo_present;
1250 u8 rx_psinfo_present;
1251 u8 rx_error_handling;
1252 u8 rx_desc_type;
1253 u16 rx_sop_offset;
1254 u16 rx_dest_qnum;
1255 u8 rx_src_tag_hi;
1256 u8 rx_src_tag_lo;
1257 u8 rx_dest_tag_hi;
1258 u8 rx_dest_tag_lo;
1259 u8 rx_src_tag_hi_sel;
1260 u8 rx_src_tag_lo_sel;
1261 u8 rx_dest_tag_hi_sel;
1262 u8 rx_dest_tag_lo_sel;
1263 u16 rx_fdq0_sz0_qnum;
1264 u16 rx_fdq1_qnum;
1265 u16 rx_fdq2_qnum;
1266 u16 rx_fdq3_qnum;
1267 u8 rx_ps_location;
1268} __packed;
1269
1270/**
1271 * struct ti_sci_msg_req_proc_request - Request a processor
1272 * @hdr: Generic Header
1273 * @processor_id: ID of processor being requested
1274 *
1275 * Request type is TI_SCI_MSG_PROC_REQUEST, response is a generic ACK/NACK
1276 * message.
1277 */
1278struct ti_sci_msg_req_proc_request {
1279 struct ti_sci_msg_hdr hdr;
1280 u8 processor_id;
1281} __packed;
1282
1283/**
1284 * struct ti_sci_msg_req_proc_release - Release a processor
1285 * @hdr: Generic Header
1286 * @processor_id: ID of processor being released
1287 *
1288 * Request type is TI_SCI_MSG_PROC_RELEASE, response is a generic ACK/NACK
1289 * message.
1290 */
1291struct ti_sci_msg_req_proc_release {
1292 struct ti_sci_msg_hdr hdr;
1293 u8 processor_id;
1294} __packed;
1295
1296/**
1297 * struct ti_sci_msg_req_proc_handover - Handover a processor to a host
1298 * @hdr: Generic Header
1299 * @processor_id: ID of processor being handed over
1300 * @host_id: Host ID the control needs to be transferred to
1301 *
1302 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1303 * message.
1304 */
1305struct ti_sci_msg_req_proc_handover {
1306 struct ti_sci_msg_hdr hdr;
1307 u8 processor_id;
1308 u8 host_id;
1309} __packed;
1310
1311/* Boot Vector masks */
1312#define TI_SCI_ADDR_LOW_MASK GENMASK_ULL(31, 0)
1313#define TI_SCI_ADDR_HIGH_MASK GENMASK_ULL(63, 32)
1314#define TI_SCI_ADDR_HIGH_SHIFT 32
1315
1316/**
1317 * struct ti_sci_msg_req_set_config - Set Processor boot configuration
1318 * @hdr: Generic Header
1319 * @processor_id: ID of processor being configured
1320 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
1321 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
1322 * @config_flags_set: Optional Processor specific Config Flags to set.
1323 * Setting a bit here implies the corresponding mode
1324 * will be set
1325 * @config_flags_clear: Optional Processor specific Config Flags to clear.
1326 * Setting a bit here implies the corresponding mode
1327 * will be cleared
1328 *
1329 * Request type is TI_SCI_MSG_PROC_HANDOVER, response is a generic ACK/NACK
1330 * message.
1331 */
1332struct ti_sci_msg_req_set_config {
1333 struct ti_sci_msg_hdr hdr;
1334 u8 processor_id;
1335 u32 bootvector_low;
1336 u32 bootvector_high;
1337 u32 config_flags_set;
1338 u32 config_flags_clear;
1339} __packed;
1340
1341/**
1342 * struct ti_sci_msg_req_set_ctrl - Set Processor boot control flags
1343 * @hdr: Generic Header
1344 * @processor_id: ID of processor being configured
1345 * @control_flags_set: Optional Processor specific Control Flags to set.
1346 * Setting a bit here implies the corresponding mode
1347 * will be set
1348 * @control_flags_clear:Optional Processor specific Control Flags to clear.
1349 * Setting a bit here implies the corresponding mode
1350 * will be cleared
1351 *
1352 * Request type is TI_SCI_MSG_SET_CTRL, response is a generic ACK/NACK
1353 * message.
1354 */
1355struct ti_sci_msg_req_set_ctrl {
1356 struct ti_sci_msg_hdr hdr;
1357 u8 processor_id;
1358 u32 control_flags_set;
1359 u32 control_flags_clear;
1360} __packed;
1361
1362/**
1363 * struct ti_sci_msg_req_get_status - Processor boot status request
1364 * @hdr: Generic Header
1365 * @processor_id: ID of processor whose status is being requested
1366 *
1367 * Request type is TI_SCI_MSG_GET_STATUS, response is an appropriate
1368 * message, or NACK in case of inability to satisfy request.
1369 */
1370struct ti_sci_msg_req_get_status {
1371 struct ti_sci_msg_hdr hdr;
1372 u8 processor_id;
1373} __packed;
1374
1375/**
1376 * struct ti_sci_msg_resp_get_status - Processor boot status response
1377 * @hdr: Generic Header
1378 * @processor_id: ID of processor whose status is returned
1379 * @bootvector_low: Lower 32 bit address (Little Endian) of boot vector
1380 * @bootvector_high: Higher 32 bit address (Little Endian) of boot vector
1381 * @config_flags: Optional Processor specific Config Flags set currently
1382 * @control_flags: Optional Processor specific Control Flags set currently
1383 * @status_flags: Optional Processor specific Status Flags set currently
1384 *
1385 * Response structure to a TI_SCI_MSG_GET_STATUS request.
1386 */
1387struct ti_sci_msg_resp_get_status {
1388 struct ti_sci_msg_hdr hdr;
1389 u8 processor_id;
1390 u32 bootvector_low;
1391 u32 bootvector_high;
1392 u32 config_flags;
1393 u32 control_flags;
1394 u32 status_flags;
1395} __packed;
1396
1397#endif /* __TI_SCI_H */