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1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/err.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/regulator/of_regulator.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/driver.h>
14#include <linux/regulator/machine.h>
15#include <linux/regulator/pfuze100.h>
16#include <linux/i2c.h>
17#include <linux/slab.h>
18#include <linux/regmap.h>
19
20#define PFUZE_FLAG_DISABLE_SW BIT(1)
21
22#define PFUZE_NUMREGS 128
23#define PFUZE100_VOL_OFFSET 0
24#define PFUZE100_STANDBY_OFFSET 1
25#define PFUZE100_MODE_OFFSET 3
26#define PFUZE100_CONF_OFFSET 4
27
28#define PFUZE100_DEVICEID 0x0
29#define PFUZE100_REVID 0x3
30#define PFUZE100_FABID 0x4
31
32#define PFUZE100_COINVOL 0x1a
33#define PFUZE100_SW1ABVOL 0x20
34#define PFUZE100_SW1ABMODE 0x23
35#define PFUZE100_SW1CVOL 0x2e
36#define PFUZE100_SW1CMODE 0x31
37#define PFUZE100_SW2VOL 0x35
38#define PFUZE100_SW2MODE 0x38
39#define PFUZE100_SW3AVOL 0x3c
40#define PFUZE100_SW3AMODE 0x3f
41#define PFUZE100_SW3BVOL 0x43
42#define PFUZE100_SW3BMODE 0x46
43#define PFUZE100_SW4VOL 0x4a
44#define PFUZE100_SW4MODE 0x4d
45#define PFUZE100_SWBSTCON1 0x66
46#define PFUZE100_VREFDDRCON 0x6a
47#define PFUZE100_VSNVSVOL 0x6b
48#define PFUZE100_VGEN1VOL 0x6c
49#define PFUZE100_VGEN2VOL 0x6d
50#define PFUZE100_VGEN3VOL 0x6e
51#define PFUZE100_VGEN4VOL 0x6f
52#define PFUZE100_VGEN5VOL 0x70
53#define PFUZE100_VGEN6VOL 0x71
54
55#define PFUZE100_SWxMODE_MASK 0xf
56#define PFUZE100_SWxMODE_APS_APS 0x8
57#define PFUZE100_SWxMODE_APS_OFF 0x4
58
59#define PFUZE100_VGENxLPWR BIT(6)
60#define PFUZE100_VGENxSTBY BIT(5)
61
62enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
63
64struct pfuze_regulator {
65 struct regulator_desc desc;
66 unsigned char stby_reg;
67 unsigned char stby_mask;
68 bool sw_reg;
69};
70
71struct pfuze_chip {
72 int chip_id;
73 int flags;
74 struct regmap *regmap;
75 struct device *dev;
76 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
77 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
78 struct pfuze_regulator *pfuze_regulators;
79};
80
81static const int pfuze100_swbst[] = {
82 5000000, 5050000, 5100000, 5150000,
83};
84
85static const int pfuze100_vsnvs[] = {
86 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
87};
88
89static const int pfuze100_coin[] = {
90 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
91};
92
93static const int pfuze3000_sw1a[] = {
94 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
95 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
96 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
97 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
98};
99
100static const int pfuze3000_sw2lo[] = {
101 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
102};
103
104static const int pfuze3000_sw2hi[] = {
105 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
106};
107
108static const struct i2c_device_id pfuze_device_id[] = {
109 {.name = "pfuze100", .driver_data = PFUZE100},
110 {.name = "pfuze200", .driver_data = PFUZE200},
111 {.name = "pfuze3000", .driver_data = PFUZE3000},
112 {.name = "pfuze3001", .driver_data = PFUZE3001},
113 { }
114};
115MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
116
117static const struct of_device_id pfuze_dt_ids[] = {
118 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
119 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
120 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
121 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
122 { }
123};
124MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
125
126static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
127{
128 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
129 int id = rdev_get_id(rdev);
130 bool reg_has_ramp_delay;
131 unsigned int ramp_bits = 0;
132 int ret;
133
134 switch (pfuze100->chip_id) {
135 case PFUZE3001:
136 /* no dynamic voltage scaling for PF3001 */
137 reg_has_ramp_delay = false;
138 break;
139 case PFUZE3000:
140 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
141 break;
142 case PFUZE200:
143 reg_has_ramp_delay = (id < PFUZE200_SWBST);
144 break;
145 case PFUZE100:
146 default:
147 reg_has_ramp_delay = (id < PFUZE100_SWBST);
148 break;
149 }
150
151 if (reg_has_ramp_delay) {
152 if (ramp_delay > 0) {
153 ramp_delay = 12500 / ramp_delay;
154 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
155 }
156
157 ret = regmap_update_bits(pfuze100->regmap,
158 rdev->desc->vsel_reg + 4,
159 0xc0, ramp_bits << 6);
160 if (ret < 0)
161 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
162 } else {
163 ret = -EACCES;
164 }
165
166 return ret;
167}
168
169static const struct regulator_ops pfuze100_ldo_regulator_ops = {
170 .enable = regulator_enable_regmap,
171 .disable = regulator_disable_regmap,
172 .is_enabled = regulator_is_enabled_regmap,
173 .list_voltage = regulator_list_voltage_linear,
174 .set_voltage_sel = regulator_set_voltage_sel_regmap,
175 .get_voltage_sel = regulator_get_voltage_sel_regmap,
176};
177
178static const struct regulator_ops pfuze100_fixed_regulator_ops = {
179 .enable = regulator_enable_regmap,
180 .disable = regulator_disable_regmap,
181 .is_enabled = regulator_is_enabled_regmap,
182 .list_voltage = regulator_list_voltage_linear,
183};
184
185static const struct regulator_ops pfuze100_sw_regulator_ops = {
186 .list_voltage = regulator_list_voltage_linear,
187 .set_voltage_sel = regulator_set_voltage_sel_regmap,
188 .get_voltage_sel = regulator_get_voltage_sel_regmap,
189 .set_voltage_time_sel = regulator_set_voltage_time_sel,
190 .set_ramp_delay = pfuze100_set_ramp_delay,
191};
192
193static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
194 .enable = regulator_enable_regmap,
195 .disable = regulator_disable_regmap,
196 .is_enabled = regulator_is_enabled_regmap,
197 .list_voltage = regulator_list_voltage_linear,
198 .set_voltage_sel = regulator_set_voltage_sel_regmap,
199 .get_voltage_sel = regulator_get_voltage_sel_regmap,
200 .set_voltage_time_sel = regulator_set_voltage_time_sel,
201 .set_ramp_delay = pfuze100_set_ramp_delay,
202};
203
204static const struct regulator_ops pfuze100_swb_regulator_ops = {
205 .enable = regulator_enable_regmap,
206 .disable = regulator_disable_regmap,
207 .is_enabled = regulator_is_enabled_regmap,
208 .list_voltage = regulator_list_voltage_table,
209 .map_voltage = regulator_map_voltage_ascend,
210 .set_voltage_sel = regulator_set_voltage_sel_regmap,
211 .get_voltage_sel = regulator_get_voltage_sel_regmap,
212
213};
214
215static const struct regulator_ops pfuze3000_sw_regulator_ops = {
216 .enable = regulator_enable_regmap,
217 .disable = regulator_disable_regmap,
218 .is_enabled = regulator_is_enabled_regmap,
219 .list_voltage = regulator_list_voltage_table,
220 .map_voltage = regulator_map_voltage_ascend,
221 .set_voltage_sel = regulator_set_voltage_sel_regmap,
222 .get_voltage_sel = regulator_get_voltage_sel_regmap,
223 .set_voltage_time_sel = regulator_set_voltage_time_sel,
224 .set_ramp_delay = pfuze100_set_ramp_delay,
225
226};
227
228#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
229 [_chip ## _ ## _name] = { \
230 .desc = { \
231 .name = #_name, \
232 .n_voltages = 1, \
233 .ops = &pfuze100_fixed_regulator_ops, \
234 .type = REGULATOR_VOLTAGE, \
235 .id = _chip ## _ ## _name, \
236 .owner = THIS_MODULE, \
237 .min_uV = (voltage), \
238 .enable_reg = (base), \
239 .enable_mask = 0x10, \
240 }, \
241 }
242
243#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
244 [_chip ## _ ## _name] = { \
245 .desc = { \
246 .name = #_name,\
247 .n_voltages = ((max) - (min)) / (step) + 1, \
248 .ops = &pfuze100_sw_regulator_ops, \
249 .type = REGULATOR_VOLTAGE, \
250 .id = _chip ## _ ## _name, \
251 .owner = THIS_MODULE, \
252 .min_uV = (min), \
253 .uV_step = (step), \
254 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
255 .vsel_mask = 0x3f, \
256 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
257 .enable_mask = 0xf, \
258 }, \
259 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
260 .stby_mask = 0x3f, \
261 .sw_reg = true, \
262 }
263
264#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
265 [_chip ## _ ## _name] = { \
266 .desc = { \
267 .name = #_name, \
268 .n_voltages = ARRAY_SIZE(voltages), \
269 .ops = &pfuze100_swb_regulator_ops, \
270 .type = REGULATOR_VOLTAGE, \
271 .id = _chip ## _ ## _name, \
272 .owner = THIS_MODULE, \
273 .volt_table = voltages, \
274 .vsel_reg = (base), \
275 .vsel_mask = (mask), \
276 .enable_reg = (base), \
277 .enable_mask = 0x48, \
278 }, \
279 }
280
281#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
282 [_chip ## _ ## _name] = { \
283 .desc = { \
284 .name = #_name, \
285 .n_voltages = ((max) - (min)) / (step) + 1, \
286 .ops = &pfuze100_ldo_regulator_ops, \
287 .type = REGULATOR_VOLTAGE, \
288 .id = _chip ## _ ## _name, \
289 .owner = THIS_MODULE, \
290 .min_uV = (min), \
291 .uV_step = (step), \
292 .vsel_reg = (base), \
293 .vsel_mask = 0xf, \
294 .enable_reg = (base), \
295 .enable_mask = 0x10, \
296 }, \
297 .stby_reg = (base), \
298 .stby_mask = 0x20, \
299 }
300
301#define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
302 [_chip ## _ ## _name] = { \
303 .desc = { \
304 .name = #_name, \
305 .n_voltages = ARRAY_SIZE(voltages), \
306 .ops = &pfuze100_swb_regulator_ops, \
307 .type = REGULATOR_VOLTAGE, \
308 .id = _chip ## _ ## _name, \
309 .owner = THIS_MODULE, \
310 .volt_table = voltages, \
311 .vsel_reg = (base), \
312 .vsel_mask = (mask), \
313 .enable_reg = (base), \
314 .enable_mask = 0x8, \
315 }, \
316 }
317
318#define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
319 .desc = { \
320 .name = #_name, \
321 .n_voltages = ((max) - (min)) / (step) + 1, \
322 .ops = &pfuze100_ldo_regulator_ops, \
323 .type = REGULATOR_VOLTAGE, \
324 .id = _chip ## _ ## _name, \
325 .owner = THIS_MODULE, \
326 .min_uV = (min), \
327 .uV_step = (step), \
328 .vsel_reg = (base), \
329 .vsel_mask = 0x3, \
330 .enable_reg = (base), \
331 .enable_mask = 0x10, \
332 }, \
333 .stby_reg = (base), \
334 .stby_mask = 0x20, \
335}
336
337/* No linar case for the some switches of PFUZE3000 */
338#define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
339 [_chip ## _ ## _name] = { \
340 .desc = { \
341 .name = #_name, \
342 .n_voltages = ARRAY_SIZE(voltages), \
343 .ops = &pfuze3000_sw_regulator_ops, \
344 .type = REGULATOR_VOLTAGE, \
345 .id = _chip ## _ ## _name, \
346 .owner = THIS_MODULE, \
347 .volt_table = voltages, \
348 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
349 .vsel_mask = (mask), \
350 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
351 .enable_mask = 0xf, \
352 .enable_val = 0x8, \
353 .enable_time = 500, \
354 }, \
355 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
356 .stby_mask = (mask), \
357 .sw_reg = true, \
358 }
359
360#define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
361 .desc = { \
362 .name = #_name,\
363 .n_voltages = ((max) - (min)) / (step) + 1, \
364 .ops = &pfuze100_sw_regulator_ops, \
365 .type = REGULATOR_VOLTAGE, \
366 .id = _chip ## _ ## _name, \
367 .owner = THIS_MODULE, \
368 .min_uV = (min), \
369 .uV_step = (step), \
370 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
371 .vsel_mask = 0xf, \
372 }, \
373 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
374 .stby_mask = 0xf, \
375}
376
377/* PFUZE100 */
378static struct pfuze_regulator pfuze100_regulators[] = {
379 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
380 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
381 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
382 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
383 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
384 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
385 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
386 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
387 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
388 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
389 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
390 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
391 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
392 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
393 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
394 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
395};
396
397static struct pfuze_regulator pfuze200_regulators[] = {
398 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
399 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
400 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
401 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
402 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
403 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
404 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
405 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
406 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
407 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
408 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
409 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
410 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
411 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
412};
413
414static struct pfuze_regulator pfuze3000_regulators[] = {
415 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
416 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
417 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
418 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
419 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
420 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
421 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
422 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
423 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
424 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
425 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
426 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
427 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
428};
429
430static struct pfuze_regulator pfuze3001_regulators[] = {
431 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
432 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
433 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
434 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
435 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
436 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
437 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
438 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
439 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
440 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
441};
442
443#ifdef CONFIG_OF
444/* PFUZE100 */
445static struct of_regulator_match pfuze100_matches[] = {
446 { .name = "sw1ab", },
447 { .name = "sw1c", },
448 { .name = "sw2", },
449 { .name = "sw3a", },
450 { .name = "sw3b", },
451 { .name = "sw4", },
452 { .name = "swbst", },
453 { .name = "vsnvs", },
454 { .name = "vrefddr", },
455 { .name = "vgen1", },
456 { .name = "vgen2", },
457 { .name = "vgen3", },
458 { .name = "vgen4", },
459 { .name = "vgen5", },
460 { .name = "vgen6", },
461 { .name = "coin", },
462};
463
464/* PFUZE200 */
465static struct of_regulator_match pfuze200_matches[] = {
466
467 { .name = "sw1ab", },
468 { .name = "sw2", },
469 { .name = "sw3a", },
470 { .name = "sw3b", },
471 { .name = "swbst", },
472 { .name = "vsnvs", },
473 { .name = "vrefddr", },
474 { .name = "vgen1", },
475 { .name = "vgen2", },
476 { .name = "vgen3", },
477 { .name = "vgen4", },
478 { .name = "vgen5", },
479 { .name = "vgen6", },
480 { .name = "coin", },
481};
482
483/* PFUZE3000 */
484static struct of_regulator_match pfuze3000_matches[] = {
485
486 { .name = "sw1a", },
487 { .name = "sw1b", },
488 { .name = "sw2", },
489 { .name = "sw3", },
490 { .name = "swbst", },
491 { .name = "vsnvs", },
492 { .name = "vrefddr", },
493 { .name = "vldo1", },
494 { .name = "vldo2", },
495 { .name = "vccsd", },
496 { .name = "v33", },
497 { .name = "vldo3", },
498 { .name = "vldo4", },
499};
500
501/* PFUZE3001 */
502static struct of_regulator_match pfuze3001_matches[] = {
503
504 { .name = "sw1", },
505 { .name = "sw2", },
506 { .name = "sw3", },
507 { .name = "vsnvs", },
508 { .name = "vldo1", },
509 { .name = "vldo2", },
510 { .name = "vccsd", },
511 { .name = "v33", },
512 { .name = "vldo3", },
513 { .name = "vldo4", },
514};
515
516static struct of_regulator_match *pfuze_matches;
517
518static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
519{
520 struct device *dev = chip->dev;
521 struct device_node *np, *parent;
522 int ret;
523
524 np = of_node_get(dev->of_node);
525 if (!np)
526 return -EINVAL;
527
528 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
529 chip->flags |= PFUZE_FLAG_DISABLE_SW;
530
531 parent = of_get_child_by_name(np, "regulators");
532 if (!parent) {
533 dev_err(dev, "regulators node not found\n");
534 return -EINVAL;
535 }
536
537 switch (chip->chip_id) {
538 case PFUZE3001:
539 pfuze_matches = pfuze3001_matches;
540 ret = of_regulator_match(dev, parent, pfuze3001_matches,
541 ARRAY_SIZE(pfuze3001_matches));
542 break;
543 case PFUZE3000:
544 pfuze_matches = pfuze3000_matches;
545 ret = of_regulator_match(dev, parent, pfuze3000_matches,
546 ARRAY_SIZE(pfuze3000_matches));
547 break;
548 case PFUZE200:
549 pfuze_matches = pfuze200_matches;
550 ret = of_regulator_match(dev, parent, pfuze200_matches,
551 ARRAY_SIZE(pfuze200_matches));
552 break;
553
554 case PFUZE100:
555 default:
556 pfuze_matches = pfuze100_matches;
557 ret = of_regulator_match(dev, parent, pfuze100_matches,
558 ARRAY_SIZE(pfuze100_matches));
559 break;
560 }
561
562 of_node_put(parent);
563 if (ret < 0) {
564 dev_err(dev, "Error parsing regulator init data: %d\n",
565 ret);
566 return ret;
567 }
568
569 return 0;
570}
571
572static inline struct regulator_init_data *match_init_data(int index)
573{
574 return pfuze_matches[index].init_data;
575}
576
577static inline struct device_node *match_of_node(int index)
578{
579 return pfuze_matches[index].of_node;
580}
581#else
582static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
583{
584 return 0;
585}
586
587static inline struct regulator_init_data *match_init_data(int index)
588{
589 return NULL;
590}
591
592static inline struct device_node *match_of_node(int index)
593{
594 return NULL;
595}
596#endif
597
598static struct pfuze_chip *syspm_pfuze_chip;
599
600static void pfuze_power_off_prepare(void)
601{
602 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
603
604 /* Switch from default mode: APS/APS to APS/Off */
605 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
606 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
607 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
608 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
609 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
610 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
611 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
612 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
613 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
614 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
615 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
616 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
617
618 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
619 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
620 PFUZE100_VGENxSTBY);
621 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
622 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
623 PFUZE100_VGENxSTBY);
624 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
625 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
626 PFUZE100_VGENxSTBY);
627 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
628 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
629 PFUZE100_VGENxSTBY);
630 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
631 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
632 PFUZE100_VGENxSTBY);
633 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
634 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
635 PFUZE100_VGENxSTBY);
636}
637
638static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
639{
640 if (pfuze_chip->chip_id != PFUZE100) {
641 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
642 return -ENODEV;
643 }
644
645 if (pm_power_off_prepare) {
646 dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
647 return -EBUSY;
648 }
649
650 if (syspm_pfuze_chip) {
651 dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
652 return -EBUSY;
653 }
654
655 syspm_pfuze_chip = pfuze_chip;
656 pm_power_off_prepare = pfuze_power_off_prepare;
657
658 return 0;
659}
660
661static int pfuze_identify(struct pfuze_chip *pfuze_chip)
662{
663 unsigned int value;
664 int ret;
665
666 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
667 if (ret)
668 return ret;
669
670 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
671 /*
672 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
673 * as ID=8 in PFUZE100
674 */
675 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
676 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
677 (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
678 (value != pfuze_chip->chip_id)) {
679 /* device id NOT match with your setting */
680 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
681 return -ENODEV;
682 }
683
684 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
685 if (ret)
686 return ret;
687 dev_info(pfuze_chip->dev,
688 "Full layer: %x, Metal layer: %x\n",
689 (value & 0xf0) >> 4, value & 0x0f);
690
691 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
692 if (ret)
693 return ret;
694 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
695 (value & 0xc) >> 2, value & 0x3);
696
697 return 0;
698}
699
700static const struct regmap_config pfuze_regmap_config = {
701 .reg_bits = 8,
702 .val_bits = 8,
703 .max_register = PFUZE_NUMREGS - 1,
704 .cache_type = REGCACHE_RBTREE,
705};
706
707static int pfuze100_regulator_probe(struct i2c_client *client,
708 const struct i2c_device_id *id)
709{
710 struct pfuze_chip *pfuze_chip;
711 struct pfuze_regulator_platform_data *pdata =
712 dev_get_platdata(&client->dev);
713 struct regulator_config config = { };
714 int i, ret;
715 const struct of_device_id *match;
716 u32 regulator_num;
717 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
718
719 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
720 GFP_KERNEL);
721 if (!pfuze_chip)
722 return -ENOMEM;
723
724 if (client->dev.of_node) {
725 match = of_match_device(of_match_ptr(pfuze_dt_ids),
726 &client->dev);
727 if (!match) {
728 dev_err(&client->dev, "Error: No device match found\n");
729 return -ENODEV;
730 }
731 pfuze_chip->chip_id = (int)(long)match->data;
732 } else if (id) {
733 pfuze_chip->chip_id = id->driver_data;
734 } else {
735 dev_err(&client->dev, "No dts match or id table match found\n");
736 return -ENODEV;
737 }
738
739 i2c_set_clientdata(client, pfuze_chip);
740 pfuze_chip->dev = &client->dev;
741
742 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
743 if (IS_ERR(pfuze_chip->regmap)) {
744 ret = PTR_ERR(pfuze_chip->regmap);
745 dev_err(&client->dev,
746 "regmap allocation failed with err %d\n", ret);
747 return ret;
748 }
749
750 ret = pfuze_identify(pfuze_chip);
751 if (ret) {
752 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
753 return ret;
754 }
755
756 /* use the right regulators after identify the right device */
757 switch (pfuze_chip->chip_id) {
758 case PFUZE3001:
759 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
760 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
761 sw_check_start = PFUZE3001_SW2;
762 sw_check_end = PFUZE3001_SW2;
763 sw_hi = 1 << 3;
764 break;
765 case PFUZE3000:
766 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
767 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
768 sw_check_start = PFUZE3000_SW2;
769 sw_check_end = PFUZE3000_SW2;
770 sw_hi = 1 << 3;
771 break;
772 case PFUZE200:
773 pfuze_chip->pfuze_regulators = pfuze200_regulators;
774 regulator_num = ARRAY_SIZE(pfuze200_regulators);
775 sw_check_start = PFUZE200_SW2;
776 sw_check_end = PFUZE200_SW3B;
777 break;
778 case PFUZE100:
779 default:
780 pfuze_chip->pfuze_regulators = pfuze100_regulators;
781 regulator_num = ARRAY_SIZE(pfuze100_regulators);
782 sw_check_start = PFUZE100_SW2;
783 sw_check_end = PFUZE100_SW4;
784 break;
785 }
786 dev_info(&client->dev, "pfuze%s found.\n",
787 (pfuze_chip->chip_id == PFUZE100) ? "100" :
788 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
789 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
790
791 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
792 sizeof(pfuze_chip->regulator_descs));
793
794 ret = pfuze_parse_regulators_dt(pfuze_chip);
795 if (ret)
796 return ret;
797
798 for (i = 0; i < regulator_num; i++) {
799 struct regulator_init_data *init_data;
800 struct regulator_desc *desc;
801 int val;
802
803 desc = &pfuze_chip->regulator_descs[i].desc;
804
805 if (pdata)
806 init_data = pdata->init_data[i];
807 else
808 init_data = match_init_data(i);
809
810 /* SW2~SW4 high bit check and modify the voltage value table */
811 if (i >= sw_check_start && i <= sw_check_end) {
812 ret = regmap_read(pfuze_chip->regmap,
813 desc->vsel_reg, &val);
814 if (ret) {
815 dev_err(&client->dev, "Fails to read from the register.\n");
816 return ret;
817 }
818
819 if (val & sw_hi) {
820 if (pfuze_chip->chip_id == PFUZE3000 ||
821 pfuze_chip->chip_id == PFUZE3001) {
822 desc->volt_table = pfuze3000_sw2hi;
823 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
824 } else {
825 desc->min_uV = 800000;
826 desc->uV_step = 50000;
827 desc->n_voltages = 51;
828 }
829 }
830 }
831
832 /*
833 * Allow SW regulators to turn off. Checking it trough a flag is
834 * a workaround to keep the backward compatibility with existing
835 * old dtb's which may relay on the fact that we didn't disable
836 * the switched regulator till yet.
837 */
838 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
839 if (pfuze_chip->regulator_descs[i].sw_reg) {
840 desc->ops = &pfuze100_sw_disable_regulator_ops;
841 desc->enable_val = 0x8;
842 desc->disable_val = 0x0;
843 desc->enable_time = 500;
844 }
845 }
846
847 config.dev = &client->dev;
848 config.init_data = init_data;
849 config.driver_data = pfuze_chip;
850 config.of_node = match_of_node(i);
851
852 pfuze_chip->regulators[i] =
853 devm_regulator_register(&client->dev, desc, &config);
854 if (IS_ERR(pfuze_chip->regulators[i])) {
855 dev_err(&client->dev, "register regulator%s failed\n",
856 pfuze_chip->pfuze_regulators[i].desc.name);
857 return PTR_ERR(pfuze_chip->regulators[i]);
858 }
859 }
860
861 if (of_property_read_bool(client->dev.of_node,
862 "fsl,pmic-stby-poweroff"))
863 return pfuze_power_off_prepare_init(pfuze_chip);
864
865 return 0;
866}
867
868static int pfuze100_regulator_remove(struct i2c_client *client)
869{
870 if (syspm_pfuze_chip) {
871 syspm_pfuze_chip = NULL;
872 pm_power_off_prepare = NULL;
873 }
874
875 return 0;
876}
877
878static struct i2c_driver pfuze_driver = {
879 .id_table = pfuze_device_id,
880 .driver = {
881 .name = "pfuze100-regulator",
882 .of_match_table = pfuze_dt_ids,
883 },
884 .probe = pfuze100_regulator_probe,
885 .remove = pfuze100_regulator_remove,
886};
887module_i2c_driver(pfuze_driver);
888
889MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
890MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
891MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
4
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/init.h>
8#include <linux/err.h>
9#include <linux/of.h>
10#include <linux/of_device.h>
11#include <linux/regulator/of_regulator.h>
12#include <linux/platform_device.h>
13#include <linux/regulator/driver.h>
14#include <linux/regulator/machine.h>
15#include <linux/regulator/pfuze100.h>
16#include <linux/i2c.h>
17#include <linux/slab.h>
18#include <linux/regmap.h>
19
20#define PFUZE_FLAG_DISABLE_SW BIT(1)
21
22#define PFUZE_NUMREGS 128
23#define PFUZE100_VOL_OFFSET 0
24#define PFUZE100_STANDBY_OFFSET 1
25#define PFUZE100_MODE_OFFSET 3
26#define PFUZE100_CONF_OFFSET 4
27
28#define PFUZE100_DEVICEID 0x0
29#define PFUZE100_REVID 0x3
30#define PFUZE100_FABID 0x4
31
32#define PFUZE100_COINVOL 0x1a
33#define PFUZE100_SW1ABVOL 0x20
34#define PFUZE100_SW1ABMODE 0x23
35#define PFUZE100_SW1CVOL 0x2e
36#define PFUZE100_SW1CMODE 0x31
37#define PFUZE100_SW2VOL 0x35
38#define PFUZE100_SW2MODE 0x38
39#define PFUZE100_SW3AVOL 0x3c
40#define PFUZE100_SW3AMODE 0x3f
41#define PFUZE100_SW3BVOL 0x43
42#define PFUZE100_SW3BMODE 0x46
43#define PFUZE100_SW4VOL 0x4a
44#define PFUZE100_SW4MODE 0x4d
45#define PFUZE100_SWBSTCON1 0x66
46#define PFUZE100_VREFDDRCON 0x6a
47#define PFUZE100_VSNVSVOL 0x6b
48#define PFUZE100_VGEN1VOL 0x6c
49#define PFUZE100_VGEN2VOL 0x6d
50#define PFUZE100_VGEN3VOL 0x6e
51#define PFUZE100_VGEN4VOL 0x6f
52#define PFUZE100_VGEN5VOL 0x70
53#define PFUZE100_VGEN6VOL 0x71
54
55#define PFUZE100_SWxMODE_MASK 0xf
56#define PFUZE100_SWxMODE_APS_APS 0x8
57#define PFUZE100_SWxMODE_APS_OFF 0x4
58
59#define PFUZE100_VGENxLPWR BIT(6)
60#define PFUZE100_VGENxSTBY BIT(5)
61
62enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
63
64struct pfuze_regulator {
65 struct regulator_desc desc;
66 unsigned char stby_reg;
67 unsigned char stby_mask;
68 bool sw_reg;
69};
70
71struct pfuze_chip {
72 int chip_id;
73 int flags;
74 struct regmap *regmap;
75 struct device *dev;
76 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
77 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
78 struct pfuze_regulator *pfuze_regulators;
79};
80
81static const int pfuze100_swbst[] = {
82 5000000, 5050000, 5100000, 5150000,
83};
84
85static const int pfuze100_vsnvs[] = {
86 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
87};
88
89static const int pfuze100_coin[] = {
90 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
91};
92
93static const int pfuze3000_sw1a[] = {
94 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
95 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
96 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
97 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
98};
99
100static const int pfuze3000_sw2lo[] = {
101 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
102};
103
104static const int pfuze3000_sw2hi[] = {
105 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
106};
107
108static const struct of_device_id pfuze_dt_ids[] = {
109 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
110 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
111 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
112 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
113 { }
114};
115MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
116
117static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
118{
119 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
120 int id = rdev_get_id(rdev);
121 bool reg_has_ramp_delay;
122 unsigned int ramp_bits = 0;
123 int ret;
124
125 switch (pfuze100->chip_id) {
126 case PFUZE3001:
127 /* no dynamic voltage scaling for PF3001 */
128 reg_has_ramp_delay = false;
129 break;
130 case PFUZE3000:
131 reg_has_ramp_delay = (id < PFUZE3000_SWBST);
132 break;
133 case PFUZE200:
134 reg_has_ramp_delay = (id < PFUZE200_SWBST);
135 break;
136 case PFUZE100:
137 default:
138 reg_has_ramp_delay = (id < PFUZE100_SWBST);
139 break;
140 }
141
142 if (reg_has_ramp_delay) {
143 if (ramp_delay > 0) {
144 ramp_delay = 12500 / ramp_delay;
145 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
146 }
147
148 ret = regmap_update_bits(pfuze100->regmap,
149 rdev->desc->vsel_reg + 4,
150 0xc0, ramp_bits << 6);
151 if (ret < 0)
152 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
153 } else {
154 ret = -EACCES;
155 }
156
157 return ret;
158}
159
160static const struct regulator_ops pfuze100_ldo_regulator_ops = {
161 .enable = regulator_enable_regmap,
162 .disable = regulator_disable_regmap,
163 .is_enabled = regulator_is_enabled_regmap,
164 .list_voltage = regulator_list_voltage_linear,
165 .set_voltage_sel = regulator_set_voltage_sel_regmap,
166 .get_voltage_sel = regulator_get_voltage_sel_regmap,
167};
168
169static const struct regulator_ops pfuze100_fixed_regulator_ops = {
170 .enable = regulator_enable_regmap,
171 .disable = regulator_disable_regmap,
172 .is_enabled = regulator_is_enabled_regmap,
173 .list_voltage = regulator_list_voltage_linear,
174};
175
176static const struct regulator_ops pfuze100_sw_regulator_ops = {
177 .list_voltage = regulator_list_voltage_linear,
178 .set_voltage_sel = regulator_set_voltage_sel_regmap,
179 .get_voltage_sel = regulator_get_voltage_sel_regmap,
180 .set_voltage_time_sel = regulator_set_voltage_time_sel,
181 .set_ramp_delay = pfuze100_set_ramp_delay,
182};
183
184static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
185 .enable = regulator_enable_regmap,
186 .disable = regulator_disable_regmap,
187 .is_enabled = regulator_is_enabled_regmap,
188 .list_voltage = regulator_list_voltage_linear,
189 .set_voltage_sel = regulator_set_voltage_sel_regmap,
190 .get_voltage_sel = regulator_get_voltage_sel_regmap,
191 .set_voltage_time_sel = regulator_set_voltage_time_sel,
192 .set_ramp_delay = pfuze100_set_ramp_delay,
193};
194
195static const struct regulator_ops pfuze100_swb_regulator_ops = {
196 .enable = regulator_enable_regmap,
197 .disable = regulator_disable_regmap,
198 .is_enabled = regulator_is_enabled_regmap,
199 .list_voltage = regulator_list_voltage_table,
200 .map_voltage = regulator_map_voltage_ascend,
201 .set_voltage_sel = regulator_set_voltage_sel_regmap,
202 .get_voltage_sel = regulator_get_voltage_sel_regmap,
203
204};
205
206static const struct regulator_ops pfuze3000_sw_regulator_ops = {
207 .enable = regulator_enable_regmap,
208 .disable = regulator_disable_regmap,
209 .is_enabled = regulator_is_enabled_regmap,
210 .list_voltage = regulator_list_voltage_table,
211 .map_voltage = regulator_map_voltage_ascend,
212 .set_voltage_sel = regulator_set_voltage_sel_regmap,
213 .get_voltage_sel = regulator_get_voltage_sel_regmap,
214 .set_voltage_time_sel = regulator_set_voltage_time_sel,
215 .set_ramp_delay = pfuze100_set_ramp_delay,
216
217};
218
219#define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
220 [_chip ## _ ## _name] = { \
221 .desc = { \
222 .name = #_name, \
223 .n_voltages = 1, \
224 .ops = &pfuze100_fixed_regulator_ops, \
225 .type = REGULATOR_VOLTAGE, \
226 .id = _chip ## _ ## _name, \
227 .owner = THIS_MODULE, \
228 .min_uV = (voltage), \
229 .enable_reg = (base), \
230 .enable_mask = 0x10, \
231 }, \
232 }
233
234#define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
235 [_chip ## _ ## _name] = { \
236 .desc = { \
237 .name = #_name,\
238 .n_voltages = ((max) - (min)) / (step) + 1, \
239 .ops = &pfuze100_sw_regulator_ops, \
240 .type = REGULATOR_VOLTAGE, \
241 .id = _chip ## _ ## _name, \
242 .owner = THIS_MODULE, \
243 .min_uV = (min), \
244 .uV_step = (step), \
245 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
246 .vsel_mask = 0x3f, \
247 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
248 .enable_mask = 0xf, \
249 }, \
250 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
251 .stby_mask = 0x3f, \
252 .sw_reg = true, \
253 }
254
255#define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
256 [_chip ## _ ## _name] = { \
257 .desc = { \
258 .name = #_name, \
259 .n_voltages = ARRAY_SIZE(voltages), \
260 .ops = &pfuze100_swb_regulator_ops, \
261 .type = REGULATOR_VOLTAGE, \
262 .id = _chip ## _ ## _name, \
263 .owner = THIS_MODULE, \
264 .volt_table = voltages, \
265 .vsel_reg = (base), \
266 .vsel_mask = (mask), \
267 .enable_reg = (base), \
268 .enable_mask = 0x48, \
269 }, \
270 }
271
272#define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
273 [_chip ## _ ## _name] = { \
274 .desc = { \
275 .name = #_name, \
276 .n_voltages = ((max) - (min)) / (step) + 1, \
277 .ops = &pfuze100_ldo_regulator_ops, \
278 .type = REGULATOR_VOLTAGE, \
279 .id = _chip ## _ ## _name, \
280 .owner = THIS_MODULE, \
281 .min_uV = (min), \
282 .uV_step = (step), \
283 .vsel_reg = (base), \
284 .vsel_mask = 0xf, \
285 .enable_reg = (base), \
286 .enable_mask = 0x10, \
287 }, \
288 .stby_reg = (base), \
289 .stby_mask = 0x20, \
290 }
291
292#define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
293 [_chip ## _ ## _name] = { \
294 .desc = { \
295 .name = #_name, \
296 .n_voltages = ARRAY_SIZE(voltages), \
297 .ops = &pfuze100_swb_regulator_ops, \
298 .type = REGULATOR_VOLTAGE, \
299 .id = _chip ## _ ## _name, \
300 .owner = THIS_MODULE, \
301 .volt_table = voltages, \
302 .vsel_reg = (base), \
303 .vsel_mask = (mask), \
304 .enable_reg = (base), \
305 .enable_mask = 0x8, \
306 }, \
307 }
308
309#define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
310 .desc = { \
311 .name = #_name, \
312 .n_voltages = ((max) - (min)) / (step) + 1, \
313 .ops = &pfuze100_ldo_regulator_ops, \
314 .type = REGULATOR_VOLTAGE, \
315 .id = _chip ## _ ## _name, \
316 .owner = THIS_MODULE, \
317 .min_uV = (min), \
318 .uV_step = (step), \
319 .vsel_reg = (base), \
320 .vsel_mask = 0x3, \
321 .enable_reg = (base), \
322 .enable_mask = 0x10, \
323 }, \
324 .stby_reg = (base), \
325 .stby_mask = 0x20, \
326}
327
328/* No linar case for the some switches of PFUZE3000 */
329#define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
330 [_chip ## _ ## _name] = { \
331 .desc = { \
332 .name = #_name, \
333 .n_voltages = ARRAY_SIZE(voltages), \
334 .ops = &pfuze3000_sw_regulator_ops, \
335 .type = REGULATOR_VOLTAGE, \
336 .id = _chip ## _ ## _name, \
337 .owner = THIS_MODULE, \
338 .volt_table = voltages, \
339 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
340 .vsel_mask = (mask), \
341 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
342 .enable_mask = 0xf, \
343 .enable_val = 0x8, \
344 .enable_time = 500, \
345 }, \
346 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
347 .stby_mask = (mask), \
348 .sw_reg = true, \
349 }
350
351#define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
352 .desc = { \
353 .name = #_name,\
354 .n_voltages = ((max) - (min)) / (step) + 1, \
355 .ops = &pfuze100_sw_regulator_ops, \
356 .type = REGULATOR_VOLTAGE, \
357 .id = _chip ## _ ## _name, \
358 .owner = THIS_MODULE, \
359 .min_uV = (min), \
360 .uV_step = (step), \
361 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
362 .vsel_mask = 0xf, \
363 }, \
364 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
365 .stby_mask = 0xf, \
366}
367
368/* PFUZE100 */
369static struct pfuze_regulator pfuze100_regulators[] = {
370 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
371 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
372 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
373 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
374 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
375 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
376 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
377 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
378 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
379 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
380 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
381 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
382 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
383 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
384 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
385 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
386};
387
388static struct pfuze_regulator pfuze200_regulators[] = {
389 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
390 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
391 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
392 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
393 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
394 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
395 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
396 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
397 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
398 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
399 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
400 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
401 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
402 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
403};
404
405static struct pfuze_regulator pfuze3000_regulators[] = {
406 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
407 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
408 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
409 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
410 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
411 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
412 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
413 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
414 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
415 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
416 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
417 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
418 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
419};
420
421static struct pfuze_regulator pfuze3001_regulators[] = {
422 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
423 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
424 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
425 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
426 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
427 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
428 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
429 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
430 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
431 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
432};
433
434/* PFUZE100 */
435static struct of_regulator_match pfuze100_matches[] = {
436 { .name = "sw1ab", },
437 { .name = "sw1c", },
438 { .name = "sw2", },
439 { .name = "sw3a", },
440 { .name = "sw3b", },
441 { .name = "sw4", },
442 { .name = "swbst", },
443 { .name = "vsnvs", },
444 { .name = "vrefddr", },
445 { .name = "vgen1", },
446 { .name = "vgen2", },
447 { .name = "vgen3", },
448 { .name = "vgen4", },
449 { .name = "vgen5", },
450 { .name = "vgen6", },
451 { .name = "coin", },
452};
453
454/* PFUZE200 */
455static struct of_regulator_match pfuze200_matches[] = {
456
457 { .name = "sw1ab", },
458 { .name = "sw2", },
459 { .name = "sw3a", },
460 { .name = "sw3b", },
461 { .name = "swbst", },
462 { .name = "vsnvs", },
463 { .name = "vrefddr", },
464 { .name = "vgen1", },
465 { .name = "vgen2", },
466 { .name = "vgen3", },
467 { .name = "vgen4", },
468 { .name = "vgen5", },
469 { .name = "vgen6", },
470 { .name = "coin", },
471};
472
473/* PFUZE3000 */
474static struct of_regulator_match pfuze3000_matches[] = {
475
476 { .name = "sw1a", },
477 { .name = "sw1b", },
478 { .name = "sw2", },
479 { .name = "sw3", },
480 { .name = "swbst", },
481 { .name = "vsnvs", },
482 { .name = "vrefddr", },
483 { .name = "vldo1", },
484 { .name = "vldo2", },
485 { .name = "vccsd", },
486 { .name = "v33", },
487 { .name = "vldo3", },
488 { .name = "vldo4", },
489};
490
491/* PFUZE3001 */
492static struct of_regulator_match pfuze3001_matches[] = {
493
494 { .name = "sw1", },
495 { .name = "sw2", },
496 { .name = "sw3", },
497 { .name = "vsnvs", },
498 { .name = "vldo1", },
499 { .name = "vldo2", },
500 { .name = "vccsd", },
501 { .name = "v33", },
502 { .name = "vldo3", },
503 { .name = "vldo4", },
504};
505
506static struct of_regulator_match *pfuze_matches;
507
508static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
509{
510 struct device *dev = chip->dev;
511 struct device_node *np, *parent;
512 int ret;
513
514 np = of_node_get(dev->of_node);
515 if (!np)
516 return -EINVAL;
517
518 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
519 chip->flags |= PFUZE_FLAG_DISABLE_SW;
520
521 parent = of_get_child_by_name(np, "regulators");
522 if (!parent) {
523 dev_err(dev, "regulators node not found\n");
524 return -EINVAL;
525 }
526
527 switch (chip->chip_id) {
528 case PFUZE3001:
529 pfuze_matches = pfuze3001_matches;
530 ret = of_regulator_match(dev, parent, pfuze3001_matches,
531 ARRAY_SIZE(pfuze3001_matches));
532 break;
533 case PFUZE3000:
534 pfuze_matches = pfuze3000_matches;
535 ret = of_regulator_match(dev, parent, pfuze3000_matches,
536 ARRAY_SIZE(pfuze3000_matches));
537 break;
538 case PFUZE200:
539 pfuze_matches = pfuze200_matches;
540 ret = of_regulator_match(dev, parent, pfuze200_matches,
541 ARRAY_SIZE(pfuze200_matches));
542 break;
543
544 case PFUZE100:
545 default:
546 pfuze_matches = pfuze100_matches;
547 ret = of_regulator_match(dev, parent, pfuze100_matches,
548 ARRAY_SIZE(pfuze100_matches));
549 break;
550 }
551
552 of_node_put(parent);
553 if (ret < 0) {
554 dev_err(dev, "Error parsing regulator init data: %d\n",
555 ret);
556 return ret;
557 }
558
559 return 0;
560}
561
562static inline struct regulator_init_data *match_init_data(int index)
563{
564 return pfuze_matches[index].init_data;
565}
566
567static inline struct device_node *match_of_node(int index)
568{
569 return pfuze_matches[index].of_node;
570}
571
572static struct pfuze_chip *syspm_pfuze_chip;
573
574static void pfuze_power_off_prepare(void)
575{
576 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
577
578 /* Switch from default mode: APS/APS to APS/Off */
579 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
580 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
581 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
582 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
583 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
584 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
585 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
586 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
587 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
588 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
589 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
590 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
591
592 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
593 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
594 PFUZE100_VGENxSTBY);
595 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
596 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
597 PFUZE100_VGENxSTBY);
598 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
599 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
600 PFUZE100_VGENxSTBY);
601 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
602 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
603 PFUZE100_VGENxSTBY);
604 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
605 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
606 PFUZE100_VGENxSTBY);
607 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
608 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
609 PFUZE100_VGENxSTBY);
610}
611
612static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
613{
614 if (pfuze_chip->chip_id != PFUZE100) {
615 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
616 return -ENODEV;
617 }
618
619 if (pm_power_off_prepare) {
620 dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
621 return -EBUSY;
622 }
623
624 if (syspm_pfuze_chip) {
625 dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
626 return -EBUSY;
627 }
628
629 syspm_pfuze_chip = pfuze_chip;
630 pm_power_off_prepare = pfuze_power_off_prepare;
631
632 return 0;
633}
634
635static int pfuze_identify(struct pfuze_chip *pfuze_chip)
636{
637 unsigned int value;
638 int ret;
639
640 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
641 if (ret)
642 return ret;
643
644 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
645 /*
646 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
647 * as ID=8 in PFUZE100
648 */
649 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
650 } else if ((value & 0x0f) != pfuze_chip->chip_id &&
651 (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
652 (value != pfuze_chip->chip_id)) {
653 /* device id NOT match with your setting */
654 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
655 return -ENODEV;
656 }
657
658 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
659 if (ret)
660 return ret;
661 dev_info(pfuze_chip->dev,
662 "Full layer: %x, Metal layer: %x\n",
663 (value & 0xf0) >> 4, value & 0x0f);
664
665 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
666 if (ret)
667 return ret;
668 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
669 (value & 0xc) >> 2, value & 0x3);
670
671 return 0;
672}
673
674static const struct regmap_config pfuze_regmap_config = {
675 .reg_bits = 8,
676 .val_bits = 8,
677 .max_register = PFUZE_NUMREGS - 1,
678 .cache_type = REGCACHE_RBTREE,
679};
680
681static int pfuze100_regulator_probe(struct i2c_client *client,
682 const struct i2c_device_id *id)
683{
684 struct pfuze_chip *pfuze_chip;
685 struct regulator_config config = { };
686 int i, ret;
687 const struct of_device_id *match;
688 u32 regulator_num;
689 u32 sw_check_start, sw_check_end, sw_hi = 0x40;
690
691 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
692 GFP_KERNEL);
693 if (!pfuze_chip)
694 return -ENOMEM;
695
696 if (client->dev.of_node) {
697 match = of_match_device(of_match_ptr(pfuze_dt_ids),
698 &client->dev);
699 if (!match) {
700 dev_err(&client->dev, "Error: No device match found\n");
701 return -ENODEV;
702 }
703 pfuze_chip->chip_id = (int)(long)match->data;
704 } else if (id) {
705 pfuze_chip->chip_id = id->driver_data;
706 } else {
707 dev_err(&client->dev, "No dts match or id table match found\n");
708 return -ENODEV;
709 }
710
711 i2c_set_clientdata(client, pfuze_chip);
712 pfuze_chip->dev = &client->dev;
713
714 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
715 if (IS_ERR(pfuze_chip->regmap)) {
716 ret = PTR_ERR(pfuze_chip->regmap);
717 dev_err(&client->dev,
718 "regmap allocation failed with err %d\n", ret);
719 return ret;
720 }
721
722 ret = pfuze_identify(pfuze_chip);
723 if (ret) {
724 dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
725 return ret;
726 }
727
728 /* use the right regulators after identify the right device */
729 switch (pfuze_chip->chip_id) {
730 case PFUZE3001:
731 pfuze_chip->pfuze_regulators = pfuze3001_regulators;
732 regulator_num = ARRAY_SIZE(pfuze3001_regulators);
733 sw_check_start = PFUZE3001_SW2;
734 sw_check_end = PFUZE3001_SW2;
735 sw_hi = 1 << 3;
736 break;
737 case PFUZE3000:
738 pfuze_chip->pfuze_regulators = pfuze3000_regulators;
739 regulator_num = ARRAY_SIZE(pfuze3000_regulators);
740 sw_check_start = PFUZE3000_SW2;
741 sw_check_end = PFUZE3000_SW2;
742 sw_hi = 1 << 3;
743 break;
744 case PFUZE200:
745 pfuze_chip->pfuze_regulators = pfuze200_regulators;
746 regulator_num = ARRAY_SIZE(pfuze200_regulators);
747 sw_check_start = PFUZE200_SW2;
748 sw_check_end = PFUZE200_SW3B;
749 break;
750 case PFUZE100:
751 default:
752 pfuze_chip->pfuze_regulators = pfuze100_regulators;
753 regulator_num = ARRAY_SIZE(pfuze100_regulators);
754 sw_check_start = PFUZE100_SW2;
755 sw_check_end = PFUZE100_SW4;
756 break;
757 }
758 dev_info(&client->dev, "pfuze%s found.\n",
759 (pfuze_chip->chip_id == PFUZE100) ? "100" :
760 (((pfuze_chip->chip_id == PFUZE200) ? "200" :
761 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
762
763 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
764 sizeof(pfuze_chip->regulator_descs));
765
766 ret = pfuze_parse_regulators_dt(pfuze_chip);
767 if (ret)
768 return ret;
769
770 for (i = 0; i < regulator_num; i++) {
771 struct regulator_init_data *init_data;
772 struct regulator_desc *desc;
773 int val;
774
775 desc = &pfuze_chip->regulator_descs[i].desc;
776
777 init_data = match_init_data(i);
778
779 /* SW2~SW4 high bit check and modify the voltage value table */
780 if (i >= sw_check_start && i <= sw_check_end) {
781 ret = regmap_read(pfuze_chip->regmap,
782 desc->vsel_reg, &val);
783 if (ret) {
784 dev_err(&client->dev, "Fails to read from the register.\n");
785 return ret;
786 }
787
788 if (val & sw_hi) {
789 if (pfuze_chip->chip_id == PFUZE3000 ||
790 pfuze_chip->chip_id == PFUZE3001) {
791 desc->volt_table = pfuze3000_sw2hi;
792 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
793 } else {
794 desc->min_uV = 800000;
795 desc->uV_step = 50000;
796 desc->n_voltages = 51;
797 }
798 }
799 }
800
801 /*
802 * Allow SW regulators to turn off. Checking it trough a flag is
803 * a workaround to keep the backward compatibility with existing
804 * old dtb's which may relay on the fact that we didn't disable
805 * the switched regulator till yet.
806 */
807 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
808 if (pfuze_chip->chip_id == PFUZE100 ||
809 pfuze_chip->chip_id == PFUZE200) {
810 if (pfuze_chip->regulator_descs[i].sw_reg) {
811 desc->ops = &pfuze100_sw_disable_regulator_ops;
812 desc->enable_val = 0x8;
813 desc->disable_val = 0x0;
814 desc->enable_time = 500;
815 }
816 }
817 }
818
819 config.dev = &client->dev;
820 config.init_data = init_data;
821 config.driver_data = pfuze_chip;
822 config.of_node = match_of_node(i);
823
824 pfuze_chip->regulators[i] =
825 devm_regulator_register(&client->dev, desc, &config);
826 if (IS_ERR(pfuze_chip->regulators[i])) {
827 dev_err(&client->dev, "register regulator%s failed\n",
828 pfuze_chip->pfuze_regulators[i].desc.name);
829 return PTR_ERR(pfuze_chip->regulators[i]);
830 }
831 }
832
833 if (of_property_read_bool(client->dev.of_node,
834 "fsl,pmic-stby-poweroff"))
835 return pfuze_power_off_prepare_init(pfuze_chip);
836
837 return 0;
838}
839
840static int pfuze100_regulator_remove(struct i2c_client *client)
841{
842 if (syspm_pfuze_chip) {
843 syspm_pfuze_chip = NULL;
844 pm_power_off_prepare = NULL;
845 }
846
847 return 0;
848}
849
850static struct i2c_driver pfuze_driver = {
851 .driver = {
852 .name = "pfuze100-regulator",
853 .of_match_table = pfuze_dt_ids,
854 },
855 .probe = pfuze100_regulator_probe,
856 .remove = pfuze100_regulator_remove,
857};
858module_i2c_driver(pfuze_driver);
859
860MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
861MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
862MODULE_LICENSE("GPL v2");