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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19#include <linux/phy/phy.h>
20
21#include "pcie-designware.h"
22
23#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
24
25/* External local bus interface registers */
26#define PLR_OFFSET 0x700
27#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
28#define FAST_LINK_MODE BIT(7)
29#define LINK_CAPABLE_MASK GENMASK(21, 16)
30#define LINK_CAPABLE_X1 BIT(16)
31
32#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
33#define NUM_OF_LANES_MASK GENMASK(12, 8)
34#define NUM_OF_LANES_X1 BIT(8)
35#define DIRECT_SPEED_CHANGE BIT(17)
36
37#define TYPE1_HDR_OFFSET 0x0
38#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
39#define PCI_IO_EN BIT(0)
40#define PCI_MEM_SPACE_EN BIT(1)
41#define PCI_BUS_MASTER_EN BIT(2)
42
43#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
44#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
45
46#define PCIE_CAP_OFFSET 0x70
47#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
48#define PCIE_CAP_MAX_PAYLOAD_MASK GENMASK(7, 5)
49#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
50#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
51#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
52
53/* PCIe specific config registers */
54#define PCIE_CFG0 0x0
55#define APP_LTSSM_ENABLE BIT(7)
56
57#define PCIE_CFG_STATUS12 0x30
58#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
59#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
60#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
61
62#define PCIE_CFG_STATUS17 0x44
63#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
64
65#define WAIT_LINKUP_TIMEOUT 4000
66#define PORT_CLK_RATE 100000000UL
67#define MAX_PAYLOAD_SIZE 256
68#define MAX_READ_REQ_SIZE 256
69#define PCIE_RESET_DELAY 500
70#define PCIE_SHARED_RESET 1
71#define PCIE_NORMAL_RESET 0
72
73enum pcie_data_rate {
74 PCIE_GEN1,
75 PCIE_GEN2,
76 PCIE_GEN3,
77 PCIE_GEN4
78};
79
80struct meson_pcie_mem_res {
81 void __iomem *elbi_base;
82 void __iomem *cfg_base;
83};
84
85struct meson_pcie_clk_res {
86 struct clk *clk;
87 struct clk *port_clk;
88 struct clk *general_clk;
89};
90
91struct meson_pcie_rc_reset {
92 struct reset_control *port;
93 struct reset_control *apb;
94};
95
96struct meson_pcie {
97 struct dw_pcie pci;
98 struct meson_pcie_mem_res mem_res;
99 struct meson_pcie_clk_res clk_res;
100 struct meson_pcie_rc_reset mrst;
101 struct gpio_desc *reset_gpio;
102 struct phy *phy;
103};
104
105static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
106 const char *id,
107 u32 reset_type)
108{
109 struct device *dev = mp->pci.dev;
110 struct reset_control *reset;
111
112 if (reset_type == PCIE_SHARED_RESET)
113 reset = devm_reset_control_get_shared(dev, id);
114 else
115 reset = devm_reset_control_get(dev, id);
116
117 return reset;
118}
119
120static int meson_pcie_get_resets(struct meson_pcie *mp)
121{
122 struct meson_pcie_rc_reset *mrst = &mp->mrst;
123
124 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
125 if (IS_ERR(mrst->port))
126 return PTR_ERR(mrst->port);
127 reset_control_deassert(mrst->port);
128
129 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
130 if (IS_ERR(mrst->apb))
131 return PTR_ERR(mrst->apb);
132 reset_control_deassert(mrst->apb);
133
134 return 0;
135}
136
137static void __iomem *meson_pcie_get_mem(struct platform_device *pdev,
138 struct meson_pcie *mp,
139 const char *id)
140{
141 struct device *dev = mp->pci.dev;
142 struct resource *res;
143
144 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, id);
145
146 return devm_ioremap_resource(dev, res);
147}
148
149static int meson_pcie_get_mems(struct platform_device *pdev,
150 struct meson_pcie *mp)
151{
152 mp->mem_res.elbi_base = meson_pcie_get_mem(pdev, mp, "elbi");
153 if (IS_ERR(mp->mem_res.elbi_base))
154 return PTR_ERR(mp->mem_res.elbi_base);
155
156 mp->mem_res.cfg_base = meson_pcie_get_mem(pdev, mp, "cfg");
157 if (IS_ERR(mp->mem_res.cfg_base))
158 return PTR_ERR(mp->mem_res.cfg_base);
159
160 return 0;
161}
162
163static int meson_pcie_power_on(struct meson_pcie *mp)
164{
165 int ret = 0;
166
167 ret = phy_init(mp->phy);
168 if (ret)
169 return ret;
170
171 ret = phy_power_on(mp->phy);
172 if (ret) {
173 phy_exit(mp->phy);
174 return ret;
175 }
176
177 return 0;
178}
179
180static void meson_pcie_power_off(struct meson_pcie *mp)
181{
182 phy_power_off(mp->phy);
183 phy_exit(mp->phy);
184}
185
186static int meson_pcie_reset(struct meson_pcie *mp)
187{
188 struct meson_pcie_rc_reset *mrst = &mp->mrst;
189 int ret = 0;
190
191 ret = phy_reset(mp->phy);
192 if (ret)
193 return ret;
194
195 reset_control_assert(mrst->port);
196 reset_control_assert(mrst->apb);
197 udelay(PCIE_RESET_DELAY);
198 reset_control_deassert(mrst->port);
199 reset_control_deassert(mrst->apb);
200 udelay(PCIE_RESET_DELAY);
201
202 return 0;
203}
204
205static inline struct clk *meson_pcie_probe_clock(struct device *dev,
206 const char *id, u64 rate)
207{
208 struct clk *clk;
209 int ret;
210
211 clk = devm_clk_get(dev, id);
212 if (IS_ERR(clk))
213 return clk;
214
215 if (rate) {
216 ret = clk_set_rate(clk, rate);
217 if (ret) {
218 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
219 return ERR_PTR(ret);
220 }
221 }
222
223 ret = clk_prepare_enable(clk);
224 if (ret) {
225 dev_err(dev, "couldn't enable clk\n");
226 return ERR_PTR(ret);
227 }
228
229 devm_add_action_or_reset(dev,
230 (void (*) (void *))clk_disable_unprepare,
231 clk);
232
233 return clk;
234}
235
236static int meson_pcie_probe_clocks(struct meson_pcie *mp)
237{
238 struct device *dev = mp->pci.dev;
239 struct meson_pcie_clk_res *res = &mp->clk_res;
240
241 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
242 if (IS_ERR(res->port_clk))
243 return PTR_ERR(res->port_clk);
244
245 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
246 if (IS_ERR(res->general_clk))
247 return PTR_ERR(res->general_clk);
248
249 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
250 if (IS_ERR(res->clk))
251 return PTR_ERR(res->clk);
252
253 return 0;
254}
255
256static inline void meson_elb_writel(struct meson_pcie *mp, u32 val, u32 reg)
257{
258 writel(val, mp->mem_res.elbi_base + reg);
259}
260
261static inline u32 meson_elb_readl(struct meson_pcie *mp, u32 reg)
262{
263 return readl(mp->mem_res.elbi_base + reg);
264}
265
266static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
267{
268 return readl(mp->mem_res.cfg_base + reg);
269}
270
271static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
272{
273 writel(val, mp->mem_res.cfg_base + reg);
274}
275
276static void meson_pcie_assert_reset(struct meson_pcie *mp)
277{
278 gpiod_set_value_cansleep(mp->reset_gpio, 1);
279 udelay(500);
280 gpiod_set_value_cansleep(mp->reset_gpio, 0);
281}
282
283static void meson_pcie_init_dw(struct meson_pcie *mp)
284{
285 u32 val;
286
287 val = meson_cfg_readl(mp, PCIE_CFG0);
288 val |= APP_LTSSM_ENABLE;
289 meson_cfg_writel(mp, val, PCIE_CFG0);
290
291 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
292 val &= ~(LINK_CAPABLE_MASK | FAST_LINK_MODE);
293 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
294
295 val = meson_elb_readl(mp, PCIE_PORT_LINK_CTRL_OFF);
296 val |= LINK_CAPABLE_X1;
297 meson_elb_writel(mp, val, PCIE_PORT_LINK_CTRL_OFF);
298
299 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
300 val &= ~NUM_OF_LANES_MASK;
301 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
302
303 val = meson_elb_readl(mp, PCIE_GEN2_CTRL_OFF);
304 val |= NUM_OF_LANES_X1 | DIRECT_SPEED_CHANGE;
305 meson_elb_writel(mp, val, PCIE_GEN2_CTRL_OFF);
306
307 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR0);
308 meson_elb_writel(mp, 0x0, PCIE_BASE_ADDR1);
309}
310
311static int meson_size_to_payload(struct meson_pcie *mp, int size)
312{
313 struct device *dev = mp->pci.dev;
314
315 /*
316 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
317 * So if input size is not 2^order alignment or less than 2^7 or bigger
318 * than 2^12, just set to default size 2^(1+7).
319 */
320 if (!is_power_of_2(size) || size < 128 || size > 4096) {
321 dev_warn(dev, "payload size %d, set to default 256\n", size);
322 return 1;
323 }
324
325 return fls(size) - 8;
326}
327
328static void meson_set_max_payload(struct meson_pcie *mp, int size)
329{
330 u32 val;
331 int max_payload_size = meson_size_to_payload(mp, size);
332
333 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
334 val &= ~PCIE_CAP_MAX_PAYLOAD_MASK;
335 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
336
337 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
338 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
339 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
340}
341
342static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
343{
344 u32 val;
345 int max_rd_req_size = meson_size_to_payload(mp, size);
346
347 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
348 val &= ~PCIE_CAP_MAX_READ_REQ_MASK;
349 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
350
351 val = meson_elb_readl(mp, PCIE_DEV_CTRL_DEV_STUS);
352 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
353 meson_elb_writel(mp, val, PCIE_DEV_CTRL_DEV_STUS);
354}
355
356static inline void meson_enable_memory_space(struct meson_pcie *mp)
357{
358 /* Set the RC Bus Master, Memory Space and I/O Space enables */
359 meson_elb_writel(mp, PCI_IO_EN | PCI_MEM_SPACE_EN | PCI_BUS_MASTER_EN,
360 PCIE_STATUS_COMMAND);
361}
362
363static int meson_pcie_establish_link(struct meson_pcie *mp)
364{
365 struct dw_pcie *pci = &mp->pci;
366 struct pcie_port *pp = &pci->pp;
367
368 meson_pcie_init_dw(mp);
369 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
370 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
371
372 dw_pcie_setup_rc(pp);
373 meson_enable_memory_space(mp);
374
375 meson_pcie_assert_reset(mp);
376
377 return dw_pcie_wait_for_link(pci);
378}
379
380static void meson_pcie_enable_interrupts(struct meson_pcie *mp)
381{
382 if (IS_ENABLED(CONFIG_PCI_MSI))
383 dw_pcie_msi_init(&mp->pci.pp);
384}
385
386static int meson_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
387 u32 *val)
388{
389 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
390 int ret;
391
392 ret = dw_pcie_read(pci->dbi_base + where, size, val);
393 if (ret != PCIBIOS_SUCCESSFUL)
394 return ret;
395
396 /*
397 * There is a bug in the MESON AXG PCIe controller whereby software
398 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
399 * the return value in the config accessors.
400 */
401 if (where == PCI_CLASS_REVISION && size == 4)
402 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
403 else if (where == PCI_CLASS_DEVICE && size == 2)
404 *val = PCI_CLASS_BRIDGE_PCI;
405 else if (where == PCI_CLASS_DEVICE && size == 1)
406 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
407 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
408 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
409
410 return PCIBIOS_SUCCESSFUL;
411}
412
413static int meson_pcie_wr_own_conf(struct pcie_port *pp, int where,
414 int size, u32 val)
415{
416 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
417
418 return dw_pcie_write(pci->dbi_base + where, size, val);
419}
420
421static int meson_pcie_link_up(struct dw_pcie *pci)
422{
423 struct meson_pcie *mp = to_meson_pcie(pci);
424 struct device *dev = pci->dev;
425 u32 speed_okay = 0;
426 u32 cnt = 0;
427 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
428
429 do {
430 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
431 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
432 smlh_up = IS_SMLH_LINK_UP(state12);
433 rdlh_up = IS_RDLH_LINK_UP(state12);
434 ltssm_up = IS_LTSSM_UP(state12);
435
436 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
437 speed_okay = 1;
438
439 if (smlh_up)
440 dev_dbg(dev, "smlh_link_up is on\n");
441 if (rdlh_up)
442 dev_dbg(dev, "rdlh_link_up is on\n");
443 if (ltssm_up)
444 dev_dbg(dev, "ltssm_up is on\n");
445 if (speed_okay)
446 dev_dbg(dev, "speed_okay\n");
447
448 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
449 return 1;
450
451 cnt++;
452
453 udelay(10);
454 } while (cnt < WAIT_LINKUP_TIMEOUT);
455
456 dev_err(dev, "error: wait linkup timeout\n");
457 return 0;
458}
459
460static int meson_pcie_host_init(struct pcie_port *pp)
461{
462 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
463 struct meson_pcie *mp = to_meson_pcie(pci);
464 int ret;
465
466 ret = meson_pcie_establish_link(mp);
467 if (ret)
468 return ret;
469
470 meson_pcie_enable_interrupts(mp);
471
472 return 0;
473}
474
475static const struct dw_pcie_host_ops meson_pcie_host_ops = {
476 .rd_own_conf = meson_pcie_rd_own_conf,
477 .wr_own_conf = meson_pcie_wr_own_conf,
478 .host_init = meson_pcie_host_init,
479};
480
481static int meson_add_pcie_port(struct meson_pcie *mp,
482 struct platform_device *pdev)
483{
484 struct dw_pcie *pci = &mp->pci;
485 struct pcie_port *pp = &pci->pp;
486 struct device *dev = &pdev->dev;
487 int ret;
488
489 if (IS_ENABLED(CONFIG_PCI_MSI)) {
490 pp->msi_irq = platform_get_irq(pdev, 0);
491 if (pp->msi_irq < 0)
492 return pp->msi_irq;
493 }
494
495 pp->ops = &meson_pcie_host_ops;
496 pci->dbi_base = mp->mem_res.elbi_base;
497
498 ret = dw_pcie_host_init(pp);
499 if (ret) {
500 dev_err(dev, "failed to initialize host\n");
501 return ret;
502 }
503
504 return 0;
505}
506
507static const struct dw_pcie_ops dw_pcie_ops = {
508 .link_up = meson_pcie_link_up,
509};
510
511static int meson_pcie_probe(struct platform_device *pdev)
512{
513 struct device *dev = &pdev->dev;
514 struct dw_pcie *pci;
515 struct meson_pcie *mp;
516 int ret;
517
518 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
519 if (!mp)
520 return -ENOMEM;
521
522 pci = &mp->pci;
523 pci->dev = dev;
524 pci->ops = &dw_pcie_ops;
525
526 mp->phy = devm_phy_get(dev, "pcie");
527 if (IS_ERR(mp->phy)) {
528 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
529 return PTR_ERR(mp->phy);
530 }
531
532 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
533 if (IS_ERR(mp->reset_gpio)) {
534 dev_err(dev, "get reset gpio failed\n");
535 return PTR_ERR(mp->reset_gpio);
536 }
537
538 ret = meson_pcie_get_resets(mp);
539 if (ret) {
540 dev_err(dev, "get reset resource failed, %d\n", ret);
541 return ret;
542 }
543
544 ret = meson_pcie_get_mems(pdev, mp);
545 if (ret) {
546 dev_err(dev, "get memory resource failed, %d\n", ret);
547 return ret;
548 }
549
550 ret = meson_pcie_power_on(mp);
551 if (ret) {
552 dev_err(dev, "phy power on failed, %d\n", ret);
553 return ret;
554 }
555
556 ret = meson_pcie_reset(mp);
557 if (ret) {
558 dev_err(dev, "reset failed, %d\n", ret);
559 goto err_phy;
560 }
561
562 ret = meson_pcie_probe_clocks(mp);
563 if (ret) {
564 dev_err(dev, "init clock resources failed, %d\n", ret);
565 goto err_phy;
566 }
567
568 platform_set_drvdata(pdev, mp);
569
570 ret = meson_add_pcie_port(mp, pdev);
571 if (ret < 0) {
572 dev_err(dev, "Add PCIe port failed, %d\n", ret);
573 goto err_phy;
574 }
575
576 return 0;
577
578err_phy:
579 meson_pcie_power_off(mp);
580 return ret;
581}
582
583static const struct of_device_id meson_pcie_of_match[] = {
584 {
585 .compatible = "amlogic,axg-pcie",
586 },
587 {
588 .compatible = "amlogic,g12a-pcie",
589 },
590 {},
591};
592
593static struct platform_driver meson_pcie_driver = {
594 .probe = meson_pcie_probe,
595 .driver = {
596 .name = "meson-pcie",
597 .of_match_table = meson_pcie_of_match,
598 },
599};
600
601builtin_platform_driver(meson_pcie_driver);
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCIe host controller driver for Amlogic MESON SoCs
4 *
5 * Copyright (c) 2018 Amlogic, inc.
6 * Author: Yue Wang <yue.wang@amlogic.com>
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/gpio/consumer.h>
12#include <linux/of_device.h>
13#include <linux/of_gpio.h>
14#include <linux/pci.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/resource.h>
18#include <linux/types.h>
19#include <linux/phy/phy.h>
20#include <linux/module.h>
21
22#include "pcie-designware.h"
23
24#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
25
26#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
27#define PCIE_CAP_MAX_READ_REQ_SIZE(x) ((x) << 12)
28
29/* PCIe specific config registers */
30#define PCIE_CFG0 0x0
31#define APP_LTSSM_ENABLE BIT(7)
32
33#define PCIE_CFG_STATUS12 0x30
34#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
35#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
36#define IS_LTSSM_UP(x) ((((x) >> 10) & 0x1f) == 0x11)
37
38#define PCIE_CFG_STATUS17 0x44
39#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
40
41#define WAIT_LINKUP_TIMEOUT 4000
42#define PORT_CLK_RATE 100000000UL
43#define MAX_PAYLOAD_SIZE 256
44#define MAX_READ_REQ_SIZE 256
45#define PCIE_RESET_DELAY 500
46#define PCIE_SHARED_RESET 1
47#define PCIE_NORMAL_RESET 0
48
49enum pcie_data_rate {
50 PCIE_GEN1,
51 PCIE_GEN2,
52 PCIE_GEN3,
53 PCIE_GEN4
54};
55
56struct meson_pcie_clk_res {
57 struct clk *clk;
58 struct clk *port_clk;
59 struct clk *general_clk;
60};
61
62struct meson_pcie_rc_reset {
63 struct reset_control *port;
64 struct reset_control *apb;
65};
66
67struct meson_pcie {
68 struct dw_pcie pci;
69 void __iomem *cfg_base;
70 struct meson_pcie_clk_res clk_res;
71 struct meson_pcie_rc_reset mrst;
72 struct gpio_desc *reset_gpio;
73 struct phy *phy;
74};
75
76static struct reset_control *meson_pcie_get_reset(struct meson_pcie *mp,
77 const char *id,
78 u32 reset_type)
79{
80 struct device *dev = mp->pci.dev;
81 struct reset_control *reset;
82
83 if (reset_type == PCIE_SHARED_RESET)
84 reset = devm_reset_control_get_shared(dev, id);
85 else
86 reset = devm_reset_control_get(dev, id);
87
88 return reset;
89}
90
91static int meson_pcie_get_resets(struct meson_pcie *mp)
92{
93 struct meson_pcie_rc_reset *mrst = &mp->mrst;
94
95 mrst->port = meson_pcie_get_reset(mp, "port", PCIE_NORMAL_RESET);
96 if (IS_ERR(mrst->port))
97 return PTR_ERR(mrst->port);
98 reset_control_deassert(mrst->port);
99
100 mrst->apb = meson_pcie_get_reset(mp, "apb", PCIE_SHARED_RESET);
101 if (IS_ERR(mrst->apb))
102 return PTR_ERR(mrst->apb);
103 reset_control_deassert(mrst->apb);
104
105 return 0;
106}
107
108static int meson_pcie_get_mems(struct platform_device *pdev,
109 struct meson_pcie *mp)
110{
111 struct dw_pcie *pci = &mp->pci;
112
113 pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "elbi");
114 if (IS_ERR(pci->dbi_base))
115 return PTR_ERR(pci->dbi_base);
116
117 mp->cfg_base = devm_platform_ioremap_resource_byname(pdev, "cfg");
118 if (IS_ERR(mp->cfg_base))
119 return PTR_ERR(mp->cfg_base);
120
121 return 0;
122}
123
124static int meson_pcie_power_on(struct meson_pcie *mp)
125{
126 int ret = 0;
127
128 ret = phy_init(mp->phy);
129 if (ret)
130 return ret;
131
132 ret = phy_power_on(mp->phy);
133 if (ret) {
134 phy_exit(mp->phy);
135 return ret;
136 }
137
138 return 0;
139}
140
141static void meson_pcie_power_off(struct meson_pcie *mp)
142{
143 phy_power_off(mp->phy);
144 phy_exit(mp->phy);
145}
146
147static int meson_pcie_reset(struct meson_pcie *mp)
148{
149 struct meson_pcie_rc_reset *mrst = &mp->mrst;
150 int ret = 0;
151
152 ret = phy_reset(mp->phy);
153 if (ret)
154 return ret;
155
156 reset_control_assert(mrst->port);
157 reset_control_assert(mrst->apb);
158 udelay(PCIE_RESET_DELAY);
159 reset_control_deassert(mrst->port);
160 reset_control_deassert(mrst->apb);
161 udelay(PCIE_RESET_DELAY);
162
163 return 0;
164}
165
166static inline struct clk *meson_pcie_probe_clock(struct device *dev,
167 const char *id, u64 rate)
168{
169 struct clk *clk;
170 int ret;
171
172 clk = devm_clk_get(dev, id);
173 if (IS_ERR(clk))
174 return clk;
175
176 if (rate) {
177 ret = clk_set_rate(clk, rate);
178 if (ret) {
179 dev_err(dev, "set clk rate failed, ret = %d\n", ret);
180 return ERR_PTR(ret);
181 }
182 }
183
184 ret = clk_prepare_enable(clk);
185 if (ret) {
186 dev_err(dev, "couldn't enable clk\n");
187 return ERR_PTR(ret);
188 }
189
190 devm_add_action_or_reset(dev,
191 (void (*) (void *))clk_disable_unprepare,
192 clk);
193
194 return clk;
195}
196
197static int meson_pcie_probe_clocks(struct meson_pcie *mp)
198{
199 struct device *dev = mp->pci.dev;
200 struct meson_pcie_clk_res *res = &mp->clk_res;
201
202 res->port_clk = meson_pcie_probe_clock(dev, "port", PORT_CLK_RATE);
203 if (IS_ERR(res->port_clk))
204 return PTR_ERR(res->port_clk);
205
206 res->general_clk = meson_pcie_probe_clock(dev, "general", 0);
207 if (IS_ERR(res->general_clk))
208 return PTR_ERR(res->general_clk);
209
210 res->clk = meson_pcie_probe_clock(dev, "pclk", 0);
211 if (IS_ERR(res->clk))
212 return PTR_ERR(res->clk);
213
214 return 0;
215}
216
217static inline u32 meson_cfg_readl(struct meson_pcie *mp, u32 reg)
218{
219 return readl(mp->cfg_base + reg);
220}
221
222static inline void meson_cfg_writel(struct meson_pcie *mp, u32 val, u32 reg)
223{
224 writel(val, mp->cfg_base + reg);
225}
226
227static void meson_pcie_assert_reset(struct meson_pcie *mp)
228{
229 gpiod_set_value_cansleep(mp->reset_gpio, 1);
230 udelay(500);
231 gpiod_set_value_cansleep(mp->reset_gpio, 0);
232}
233
234static void meson_pcie_ltssm_enable(struct meson_pcie *mp)
235{
236 u32 val;
237
238 val = meson_cfg_readl(mp, PCIE_CFG0);
239 val |= APP_LTSSM_ENABLE;
240 meson_cfg_writel(mp, val, PCIE_CFG0);
241}
242
243static int meson_size_to_payload(struct meson_pcie *mp, int size)
244{
245 struct device *dev = mp->pci.dev;
246
247 /*
248 * dwc supports 2^(val+7) payload size, which val is 0~5 default to 1.
249 * So if input size is not 2^order alignment or less than 2^7 or bigger
250 * than 2^12, just set to default size 2^(1+7).
251 */
252 if (!is_power_of_2(size) || size < 128 || size > 4096) {
253 dev_warn(dev, "payload size %d, set to default 256\n", size);
254 return 1;
255 }
256
257 return fls(size) - 8;
258}
259
260static void meson_set_max_payload(struct meson_pcie *mp, int size)
261{
262 struct dw_pcie *pci = &mp->pci;
263 u32 val;
264 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
265 int max_payload_size = meson_size_to_payload(mp, size);
266
267 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
268 val &= ~PCI_EXP_DEVCTL_PAYLOAD;
269 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
270
271 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
272 val |= PCIE_CAP_MAX_PAYLOAD_SIZE(max_payload_size);
273 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
274}
275
276static void meson_set_max_rd_req_size(struct meson_pcie *mp, int size)
277{
278 struct dw_pcie *pci = &mp->pci;
279 u32 val;
280 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
281 int max_rd_req_size = meson_size_to_payload(mp, size);
282
283 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
284 val &= ~PCI_EXP_DEVCTL_READRQ;
285 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
286
287 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_DEVCTL);
288 val |= PCIE_CAP_MAX_READ_REQ_SIZE(max_rd_req_size);
289 dw_pcie_writel_dbi(pci, offset + PCI_EXP_DEVCTL, val);
290}
291
292static int meson_pcie_start_link(struct dw_pcie *pci)
293{
294 struct meson_pcie *mp = to_meson_pcie(pci);
295
296 meson_pcie_ltssm_enable(mp);
297 meson_pcie_assert_reset(mp);
298
299 return 0;
300}
301
302static int meson_pcie_rd_own_conf(struct pci_bus *bus, u32 devfn,
303 int where, int size, u32 *val)
304{
305 int ret;
306
307 ret = pci_generic_config_read(bus, devfn, where, size, val);
308 if (ret != PCIBIOS_SUCCESSFUL)
309 return ret;
310
311 /*
312 * There is a bug in the MESON AXG PCIe controller whereby software
313 * cannot program the PCI_CLASS_DEVICE register, so we must fabricate
314 * the return value in the config accessors.
315 */
316 if (where == PCI_CLASS_REVISION && size == 4)
317 *val = (PCI_CLASS_BRIDGE_PCI << 16) | (*val & 0xffff);
318 else if (where == PCI_CLASS_DEVICE && size == 2)
319 *val = PCI_CLASS_BRIDGE_PCI;
320 else if (where == PCI_CLASS_DEVICE && size == 1)
321 *val = PCI_CLASS_BRIDGE_PCI & 0xff;
322 else if (where == PCI_CLASS_DEVICE + 1 && size == 1)
323 *val = (PCI_CLASS_BRIDGE_PCI >> 8) & 0xff;
324
325 return PCIBIOS_SUCCESSFUL;
326}
327
328static struct pci_ops meson_pci_ops = {
329 .map_bus = dw_pcie_own_conf_map_bus,
330 .read = meson_pcie_rd_own_conf,
331 .write = pci_generic_config_write,
332};
333
334static int meson_pcie_link_up(struct dw_pcie *pci)
335{
336 struct meson_pcie *mp = to_meson_pcie(pci);
337 struct device *dev = pci->dev;
338 u32 speed_okay = 0;
339 u32 cnt = 0;
340 u32 state12, state17, smlh_up, ltssm_up, rdlh_up;
341
342 do {
343 state12 = meson_cfg_readl(mp, PCIE_CFG_STATUS12);
344 state17 = meson_cfg_readl(mp, PCIE_CFG_STATUS17);
345 smlh_up = IS_SMLH_LINK_UP(state12);
346 rdlh_up = IS_RDLH_LINK_UP(state12);
347 ltssm_up = IS_LTSSM_UP(state12);
348
349 if (PM_CURRENT_STATE(state17) < PCIE_GEN3)
350 speed_okay = 1;
351
352 if (smlh_up)
353 dev_dbg(dev, "smlh_link_up is on\n");
354 if (rdlh_up)
355 dev_dbg(dev, "rdlh_link_up is on\n");
356 if (ltssm_up)
357 dev_dbg(dev, "ltssm_up is on\n");
358 if (speed_okay)
359 dev_dbg(dev, "speed_okay\n");
360
361 if (smlh_up && rdlh_up && ltssm_up && speed_okay)
362 return 1;
363
364 cnt++;
365
366 udelay(10);
367 } while (cnt < WAIT_LINKUP_TIMEOUT);
368
369 dev_err(dev, "error: wait linkup timeout\n");
370 return 0;
371}
372
373static int meson_pcie_host_init(struct pcie_port *pp)
374{
375 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
376 struct meson_pcie *mp = to_meson_pcie(pci);
377
378 pp->bridge->ops = &meson_pci_ops;
379
380 meson_set_max_payload(mp, MAX_PAYLOAD_SIZE);
381 meson_set_max_rd_req_size(mp, MAX_READ_REQ_SIZE);
382
383 return 0;
384}
385
386static const struct dw_pcie_host_ops meson_pcie_host_ops = {
387 .host_init = meson_pcie_host_init,
388};
389
390static const struct dw_pcie_ops dw_pcie_ops = {
391 .link_up = meson_pcie_link_up,
392 .start_link = meson_pcie_start_link,
393};
394
395static int meson_pcie_probe(struct platform_device *pdev)
396{
397 struct device *dev = &pdev->dev;
398 struct dw_pcie *pci;
399 struct meson_pcie *mp;
400 int ret;
401
402 mp = devm_kzalloc(dev, sizeof(*mp), GFP_KERNEL);
403 if (!mp)
404 return -ENOMEM;
405
406 pci = &mp->pci;
407 pci->dev = dev;
408 pci->ops = &dw_pcie_ops;
409 pci->pp.ops = &meson_pcie_host_ops;
410 pci->num_lanes = 1;
411
412 mp->phy = devm_phy_get(dev, "pcie");
413 if (IS_ERR(mp->phy)) {
414 dev_err(dev, "get phy failed, %ld\n", PTR_ERR(mp->phy));
415 return PTR_ERR(mp->phy);
416 }
417
418 mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
419 if (IS_ERR(mp->reset_gpio)) {
420 dev_err(dev, "get reset gpio failed\n");
421 return PTR_ERR(mp->reset_gpio);
422 }
423
424 ret = meson_pcie_get_resets(mp);
425 if (ret) {
426 dev_err(dev, "get reset resource failed, %d\n", ret);
427 return ret;
428 }
429
430 ret = meson_pcie_get_mems(pdev, mp);
431 if (ret) {
432 dev_err(dev, "get memory resource failed, %d\n", ret);
433 return ret;
434 }
435
436 ret = meson_pcie_power_on(mp);
437 if (ret) {
438 dev_err(dev, "phy power on failed, %d\n", ret);
439 return ret;
440 }
441
442 ret = meson_pcie_reset(mp);
443 if (ret) {
444 dev_err(dev, "reset failed, %d\n", ret);
445 goto err_phy;
446 }
447
448 ret = meson_pcie_probe_clocks(mp);
449 if (ret) {
450 dev_err(dev, "init clock resources failed, %d\n", ret);
451 goto err_phy;
452 }
453
454 platform_set_drvdata(pdev, mp);
455
456 ret = dw_pcie_host_init(&pci->pp);
457 if (ret < 0) {
458 dev_err(dev, "Add PCIe port failed, %d\n", ret);
459 goto err_phy;
460 }
461
462 return 0;
463
464err_phy:
465 meson_pcie_power_off(mp);
466 return ret;
467}
468
469static const struct of_device_id meson_pcie_of_match[] = {
470 {
471 .compatible = "amlogic,axg-pcie",
472 },
473 {
474 .compatible = "amlogic,g12a-pcie",
475 },
476 {},
477};
478MODULE_DEVICE_TABLE(of, meson_pcie_of_match);
479
480static struct platform_driver meson_pcie_driver = {
481 .probe = meson_pcie_probe,
482 .driver = {
483 .name = "meson-pcie",
484 .of_match_table = meson_pcie_of_match,
485 },
486};
487
488module_platform_driver(meson_pcie_driver);
489
490MODULE_AUTHOR("Yue Wang <yue.wang@amlogic.com>");
491MODULE_DESCRIPTION("Amlogic PCIe Controller driver");
492MODULE_LICENSE("GPL v2");