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1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "display/intel_display.h"
31
32#include "gt/intel_engine_types.h"
33#include "gt/intel_context_types.h"
34#include "gt/intel_sseu.h"
35
36struct drm_printer;
37struct drm_i915_private;
38
39/* Keep in gen based order, and chronological order within a gen */
40enum intel_platform {
41 INTEL_PLATFORM_UNINITIALIZED = 0,
42 /* gen2 */
43 INTEL_I830,
44 INTEL_I845G,
45 INTEL_I85X,
46 INTEL_I865G,
47 /* gen3 */
48 INTEL_I915G,
49 INTEL_I915GM,
50 INTEL_I945G,
51 INTEL_I945GM,
52 INTEL_G33,
53 INTEL_PINEVIEW,
54 /* gen4 */
55 INTEL_I965G,
56 INTEL_I965GM,
57 INTEL_G45,
58 INTEL_GM45,
59 /* gen5 */
60 INTEL_IRONLAKE,
61 /* gen6 */
62 INTEL_SANDYBRIDGE,
63 /* gen7 */
64 INTEL_IVYBRIDGE,
65 INTEL_VALLEYVIEW,
66 INTEL_HASWELL,
67 /* gen8 */
68 INTEL_BROADWELL,
69 INTEL_CHERRYVIEW,
70 /* gen9 */
71 INTEL_SKYLAKE,
72 INTEL_BROXTON,
73 INTEL_KABYLAKE,
74 INTEL_GEMINILAKE,
75 INTEL_COFFEELAKE,
76 INTEL_COMETLAKE,
77 /* gen10 */
78 INTEL_CANNONLAKE,
79 /* gen11 */
80 INTEL_ICELAKE,
81 INTEL_ELKHARTLAKE,
82 /* gen12 */
83 INTEL_TIGERLAKE,
84 INTEL_ROCKETLAKE,
85 INTEL_DG1,
86 INTEL_MAX_PLATFORMS
87};
88
89/*
90 * Subplatform bits share the same namespace per parent platform. In other words
91 * it is fine for the same bit to be used on multiple parent platforms.
92 */
93
94#define INTEL_SUBPLATFORM_BITS (3)
95
96/* HSW/BDW/SKL/KBL/CFL */
97#define INTEL_SUBPLATFORM_ULT (0)
98#define INTEL_SUBPLATFORM_ULX (1)
99
100/* CNL/ICL */
101#define INTEL_SUBPLATFORM_PORTF (0)
102
103enum intel_ppgtt_type {
104 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
105 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
106 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
107};
108
109#define DEV_INFO_FOR_EACH_FLAG(func) \
110 func(is_mobile); \
111 func(is_lp); \
112 func(require_force_probe); \
113 func(is_dgfx); \
114 /* Keep has_* in alphabetical order */ \
115 func(has_64bit_reloc); \
116 func(gpu_reset_clobbers_display); \
117 func(has_reset_engine); \
118 func(has_fpga_dbg); \
119 func(has_global_mocs); \
120 func(has_gt_uc); \
121 func(has_l3_dpf); \
122 func(has_llc); \
123 func(has_logical_ring_contexts); \
124 func(has_logical_ring_elsq); \
125 func(has_logical_ring_preemption); \
126 func(has_master_unit_irq); \
127 func(has_pooled_eu); \
128 func(has_rc6); \
129 func(has_rc6p); \
130 func(has_rps); \
131 func(has_runtime_pm); \
132 func(has_snoop); \
133 func(has_coherent_ggtt); \
134 func(unfenced_needs_alignment); \
135 func(hws_needs_physical);
136
137#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
138 /* Keep in alphabetical order */ \
139 func(cursor_needs_physical); \
140 func(has_csr); \
141 func(has_ddi); \
142 func(has_dp_mst); \
143 func(has_dsb); \
144 func(has_dsc); \
145 func(has_fbc); \
146 func(has_gmch); \
147 func(has_hdcp); \
148 func(has_hotplug); \
149 func(has_ipc); \
150 func(has_modular_fia); \
151 func(has_overlay); \
152 func(has_psr); \
153 func(has_psr_hw_tracking); \
154 func(overlay_needs_physical); \
155 func(supports_tv);
156
157struct intel_device_info {
158 u16 gen_mask;
159
160 u8 gen;
161 u8 gt; /* GT number, 0 if undefined */
162 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
163
164 enum intel_platform platform;
165
166 unsigned int dma_mask_size; /* available DMA address bits */
167
168 enum intel_ppgtt_type ppgtt_type;
169 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
170
171 unsigned int page_sizes; /* page sizes supported by the HW */
172
173 u32 memory_regions; /* regions supported by the HW */
174
175 u32 display_mmio_offset;
176
177 u8 pipe_mask;
178 u8 cpu_transcoder_mask;
179
180 u8 abox_mask;
181
182#define DEFINE_FLAG(name) u8 name:1
183 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
184#undef DEFINE_FLAG
185
186 struct {
187#define DEFINE_FLAG(name) u8 name:1
188 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
189#undef DEFINE_FLAG
190 } display;
191
192 u16 ddb_size; /* in blocks */
193 u8 num_supported_dbuf_slices; /* number of DBuf slices */
194
195 /* Register offsets for the various display pipes and transcoders */
196 int pipe_offsets[I915_MAX_TRANSCODERS];
197 int trans_offsets[I915_MAX_TRANSCODERS];
198 int cursor_offsets[I915_MAX_PIPES];
199
200 struct color_luts {
201 u32 degamma_lut_size;
202 u32 gamma_lut_size;
203 u32 degamma_lut_tests;
204 u32 gamma_lut_tests;
205 } color;
206};
207
208struct intel_runtime_info {
209 /*
210 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
211 * into single runtime conditionals, and also to provide groundwork
212 * for future per platform, or per SKU build optimizations.
213 *
214 * Array can be extended when necessary if the corresponding
215 * BUILD_BUG_ON is hit.
216 */
217 u32 platform_mask[2];
218
219 u16 device_id;
220
221 u8 num_sprites[I915_MAX_PIPES];
222 u8 num_scalers[I915_MAX_PIPES];
223
224 u32 rawclk_freq;
225
226 u32 cs_timestamp_frequency_hz;
227 u32 cs_timestamp_period_ns;
228};
229
230struct intel_driver_caps {
231 unsigned int scheduler;
232 bool has_logical_contexts:1;
233};
234
235const char *intel_platform_name(enum intel_platform platform);
236
237void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
238void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
239
240void intel_device_info_print_static(const struct intel_device_info *info,
241 struct drm_printer *p);
242void intel_device_info_print_runtime(const struct intel_runtime_info *info,
243 struct drm_printer *p);
244
245void intel_driver_caps_print(const struct intel_driver_caps *caps,
246 struct drm_printer *p);
247
248#endif
1/*
2 * Copyright © 2014-2017 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#ifndef _INTEL_DEVICE_INFO_H_
26#define _INTEL_DEVICE_INFO_H_
27
28#include <uapi/drm/i915_drm.h>
29
30#include "intel_step.h"
31
32#include "display/intel_display.h"
33
34#include "gt/intel_engine_types.h"
35#include "gt/intel_context_types.h"
36#include "gt/intel_sseu.h"
37
38struct drm_printer;
39struct drm_i915_private;
40
41/* Keep in gen based order, and chronological order within a gen */
42enum intel_platform {
43 INTEL_PLATFORM_UNINITIALIZED = 0,
44 /* gen2 */
45 INTEL_I830,
46 INTEL_I845G,
47 INTEL_I85X,
48 INTEL_I865G,
49 /* gen3 */
50 INTEL_I915G,
51 INTEL_I915GM,
52 INTEL_I945G,
53 INTEL_I945GM,
54 INTEL_G33,
55 INTEL_PINEVIEW,
56 /* gen4 */
57 INTEL_I965G,
58 INTEL_I965GM,
59 INTEL_G45,
60 INTEL_GM45,
61 /* gen5 */
62 INTEL_IRONLAKE,
63 /* gen6 */
64 INTEL_SANDYBRIDGE,
65 /* gen7 */
66 INTEL_IVYBRIDGE,
67 INTEL_VALLEYVIEW,
68 INTEL_HASWELL,
69 /* gen8 */
70 INTEL_BROADWELL,
71 INTEL_CHERRYVIEW,
72 /* gen9 */
73 INTEL_SKYLAKE,
74 INTEL_BROXTON,
75 INTEL_KABYLAKE,
76 INTEL_GEMINILAKE,
77 INTEL_COFFEELAKE,
78 INTEL_COMETLAKE,
79 /* gen10 */
80 INTEL_CANNONLAKE,
81 /* gen11 */
82 INTEL_ICELAKE,
83 INTEL_ELKHARTLAKE,
84 INTEL_JASPERLAKE,
85 /* gen12 */
86 INTEL_TIGERLAKE,
87 INTEL_ROCKETLAKE,
88 INTEL_DG1,
89 INTEL_ALDERLAKE_S,
90 INTEL_ALDERLAKE_P,
91 INTEL_MAX_PLATFORMS
92};
93
94/*
95 * Subplatform bits share the same namespace per parent platform. In other words
96 * it is fine for the same bit to be used on multiple parent platforms.
97 */
98
99#define INTEL_SUBPLATFORM_BITS (2)
100#define INTEL_SUBPLATFORM_MASK (BIT(INTEL_SUBPLATFORM_BITS) - 1)
101
102/* HSW/BDW/SKL/KBL/CFL */
103#define INTEL_SUBPLATFORM_ULT (0)
104#define INTEL_SUBPLATFORM_ULX (1)
105
106/* CNL/ICL */
107#define INTEL_SUBPLATFORM_PORTF (0)
108
109enum intel_ppgtt_type {
110 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
111 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
112 INTEL_PPGTT_FULL = I915_GEM_PPGTT_FULL,
113};
114
115#define DEV_INFO_FOR_EACH_FLAG(func) \
116 func(is_mobile); \
117 func(is_lp); \
118 func(require_force_probe); \
119 func(is_dgfx); \
120 /* Keep has_* in alphabetical order */ \
121 func(has_64bit_reloc); \
122 func(gpu_reset_clobbers_display); \
123 func(has_reset_engine); \
124 func(has_global_mocs); \
125 func(has_gt_uc); \
126 func(has_l3_dpf); \
127 func(has_llc); \
128 func(has_logical_ring_contexts); \
129 func(has_logical_ring_elsq); \
130 func(has_master_unit_irq); \
131 func(has_pooled_eu); \
132 func(has_rc6); \
133 func(has_rc6p); \
134 func(has_rps); \
135 func(has_runtime_pm); \
136 func(has_snoop); \
137 func(has_coherent_ggtt); \
138 func(unfenced_needs_alignment); \
139 func(hws_needs_physical);
140
141#define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \
142 /* Keep in alphabetical order */ \
143 func(cursor_needs_physical); \
144 func(has_dmc); \
145 func(has_ddi); \
146 func(has_dp_mst); \
147 func(has_dsb); \
148 func(has_dsc); \
149 func(has_fbc); \
150 func(has_fpga_dbg); \
151 func(has_gmch); \
152 func(has_hdcp); \
153 func(has_hotplug); \
154 func(has_hti); \
155 func(has_ipc); \
156 func(has_modular_fia); \
157 func(has_overlay); \
158 func(has_psr); \
159 func(has_psr_hw_tracking); \
160 func(overlay_needs_physical); \
161 func(supports_tv);
162
163struct intel_device_info {
164 u8 graphics_ver;
165 u8 media_ver;
166
167 u8 gt; /* GT number, 0 if undefined */
168 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
169
170 enum intel_platform platform;
171
172 unsigned int dma_mask_size; /* available DMA address bits */
173
174 enum intel_ppgtt_type ppgtt_type;
175 unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
176
177 unsigned int page_sizes; /* page sizes supported by the HW */
178
179 u32 memory_regions; /* regions supported by the HW */
180
181 u32 display_mmio_offset;
182
183 u8 pipe_mask;
184 u8 cpu_transcoder_mask;
185
186 u8 abox_mask;
187
188 u8 has_cdclk_crawl; /* does support CDCLK crawling */
189
190#define DEFINE_FLAG(name) u8 name:1
191 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
192#undef DEFINE_FLAG
193
194 struct {
195 u8 ver;
196
197#define DEFINE_FLAG(name) u8 name:1
198 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
199#undef DEFINE_FLAG
200 } display;
201
202 struct {
203 u16 size; /* in blocks */
204 u8 slice_mask;
205 } dbuf;
206
207 /* Register offsets for the various display pipes and transcoders */
208 int pipe_offsets[I915_MAX_TRANSCODERS];
209 int trans_offsets[I915_MAX_TRANSCODERS];
210 int cursor_offsets[I915_MAX_PIPES];
211
212 struct color_luts {
213 u32 degamma_lut_size;
214 u32 gamma_lut_size;
215 u32 degamma_lut_tests;
216 u32 gamma_lut_tests;
217 } color;
218};
219
220struct intel_runtime_info {
221 /*
222 * Platform mask is used for optimizing or-ed IS_PLATFORM calls into
223 * into single runtime conditionals, and also to provide groundwork
224 * for future per platform, or per SKU build optimizations.
225 *
226 * Array can be extended when necessary if the corresponding
227 * BUILD_BUG_ON is hit.
228 */
229 u32 platform_mask[2];
230
231 u16 device_id;
232
233 u8 num_sprites[I915_MAX_PIPES];
234 u8 num_scalers[I915_MAX_PIPES];
235
236 u32 rawclk_freq;
237
238 struct intel_step_info step;
239};
240
241struct intel_driver_caps {
242 unsigned int scheduler;
243 bool has_logical_contexts:1;
244};
245
246const char *intel_platform_name(enum intel_platform platform);
247
248void intel_device_info_subplatform_init(struct drm_i915_private *dev_priv);
249void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
250
251void intel_device_info_print_static(const struct intel_device_info *info,
252 struct drm_printer *p);
253void intel_device_info_print_runtime(const struct intel_runtime_info *info,
254 struct drm_printer *p);
255
256void intel_driver_caps_print(const struct intel_driver_caps *caps,
257 struct drm_printer *p);
258
259#endif