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1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/pci.h>
25#include "amdgpu.h"
26#include "amdgpu_atomfirmware.h"
27#include "gmc_v10_0.h"
28
29#include "hdp/hdp_5_0_0_offset.h"
30#include "hdp/hdp_5_0_0_sh_mask.h"
31#include "gc/gc_10_1_0_sh_mask.h"
32#include "mmhub/mmhub_2_0_0_sh_mask.h"
33#include "athub/athub_2_0_0_sh_mask.h"
34#include "athub/athub_2_0_0_offset.h"
35#include "dcn/dcn_2_0_0_offset.h"
36#include "dcn/dcn_2_0_0_sh_mask.h"
37#include "oss/osssys_5_0_0_offset.h"
38#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
39#include "navi10_enum.h"
40
41#include "soc15.h"
42#include "soc15d.h"
43#include "soc15_common.h"
44
45#include "nbio_v2_3.h"
46
47#include "gfxhub_v2_0.h"
48#include "gfxhub_v2_1.h"
49#include "mmhub_v2_0.h"
50#include "athub_v2_0.h"
51#include "athub_v2_1.h"
52
53#if 0
54static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
55{
56 /* TODO add golden setting for hdp */
57};
58#endif
59
60static int
61gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
62 struct amdgpu_irq_src *src, unsigned type,
63 enum amdgpu_interrupt_state state)
64{
65 struct amdgpu_vmhub *hub;
66 u32 tmp, reg, bits[AMDGPU_MAX_VMHUBS], i;
67
68 bits[AMDGPU_GFXHUB_0] = GCVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
69 GCVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
70 GCVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
71 GCVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
72 GCVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
73 GCVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
74 GCVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
75
76 bits[AMDGPU_MMHUB_0] = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
77 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
78 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
79 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
80 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
81 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
82 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
83
84 switch (state) {
85 case AMDGPU_IRQ_STATE_DISABLE:
86 /* MM HUB */
87 hub = &adev->vmhub[AMDGPU_MMHUB_0];
88 for (i = 0; i < 16; i++) {
89 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
90 tmp = RREG32(reg);
91 tmp &= ~bits[AMDGPU_MMHUB_0];
92 WREG32(reg, tmp);
93 }
94
95 /* GFX HUB */
96 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
97 for (i = 0; i < 16; i++) {
98 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
99 tmp = RREG32(reg);
100 tmp &= ~bits[AMDGPU_GFXHUB_0];
101 WREG32(reg, tmp);
102 }
103 break;
104 case AMDGPU_IRQ_STATE_ENABLE:
105 /* MM HUB */
106 hub = &adev->vmhub[AMDGPU_MMHUB_0];
107 for (i = 0; i < 16; i++) {
108 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
109 tmp = RREG32(reg);
110 tmp |= bits[AMDGPU_MMHUB_0];
111 WREG32(reg, tmp);
112 }
113
114 /* GFX HUB */
115 hub = &adev->vmhub[AMDGPU_GFXHUB_0];
116 for (i = 0; i < 16; i++) {
117 reg = hub->vm_context0_cntl + hub->ctx_distance * i;
118 tmp = RREG32(reg);
119 tmp |= bits[AMDGPU_GFXHUB_0];
120 WREG32(reg, tmp);
121 }
122 break;
123 default:
124 break;
125 }
126
127 return 0;
128}
129
130static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
131 struct amdgpu_irq_src *source,
132 struct amdgpu_iv_entry *entry)
133{
134 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
135 uint32_t status = 0;
136 u64 addr;
137
138 addr = (u64)entry->src_data[0] << 12;
139 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
140
141 if (!amdgpu_sriov_vf(adev)) {
142 /*
143 * Issue a dummy read to wait for the status register to
144 * be updated to avoid reading an incorrect value due to
145 * the new fast GRBM interface.
146 */
147 if (entry->vmid_src == AMDGPU_GFXHUB_0)
148 RREG32(hub->vm_l2_pro_fault_status);
149
150 status = RREG32(hub->vm_l2_pro_fault_status);
151 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
152 }
153
154 if (printk_ratelimit()) {
155 struct amdgpu_task_info task_info;
156
157 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
158 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
159
160 dev_err(adev->dev,
161 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
162 "for process %s pid %d thread %s pid %d)\n",
163 entry->vmid_src ? "mmhub" : "gfxhub",
164 entry->src_id, entry->ring_id, entry->vmid,
165 entry->pasid, task_info.process_name, task_info.tgid,
166 task_info.task_name, task_info.pid);
167 dev_err(adev->dev, " in page starting at address 0x%016llx from client %d\n",
168 addr, entry->client_id);
169 if (!amdgpu_sriov_vf(adev)) {
170 dev_err(adev->dev,
171 "GCVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
172 status);
173 dev_err(adev->dev, "\t Faulty UTCL2 client ID: 0x%lx\n",
174 REG_GET_FIELD(status,
175 GCVM_L2_PROTECTION_FAULT_STATUS, CID));
176 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
177 REG_GET_FIELD(status,
178 GCVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
179 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
180 REG_GET_FIELD(status,
181 GCVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
182 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
183 REG_GET_FIELD(status,
184 GCVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
185 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
186 REG_GET_FIELD(status,
187 GCVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
188 dev_err(adev->dev, "\t RW: 0x%lx\n",
189 REG_GET_FIELD(status,
190 GCVM_L2_PROTECTION_FAULT_STATUS, RW));
191 }
192 }
193
194 return 0;
195}
196
197static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
198 .set = gmc_v10_0_vm_fault_interrupt_state,
199 .process = gmc_v10_0_process_interrupt,
200};
201
202static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
203{
204 adev->gmc.vm_fault.num_types = 1;
205 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
206}
207
208static uint32_t gmc_v10_0_get_invalidate_req(unsigned int vmid,
209 uint32_t flush_type)
210{
211 u32 req = 0;
212
213 /* invalidate using legacy mode on vmid*/
214 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
215 PER_VMID_INVALIDATE_REQ, 1 << vmid);
216 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
217 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
218 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
219 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
220 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
221 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
222 req = REG_SET_FIELD(req, GCVM_INVALIDATE_ENG0_REQ,
223 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
224
225 return req;
226}
227
228/**
229 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
230 *
231 * @adev: amdgpu_device pointer
232 * @vmhub: vmhub type
233 *
234 */
235static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
236 uint32_t vmhub)
237{
238 return ((vmhub == AMDGPU_MMHUB_0 ||
239 vmhub == AMDGPU_MMHUB_1) &&
240 (!amdgpu_sriov_vf(adev)));
241}
242
243static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
244 struct amdgpu_device *adev,
245 uint8_t vmid, uint16_t *p_pasid)
246{
247 uint32_t value;
248
249 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
250 + vmid);
251 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
252
253 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
254}
255
256/*
257 * GART
258 * VMID 0 is the physical GPU addresses as used by the kernel.
259 * VMIDs 1-15 are used for userspace clients and are handled
260 * by the amdgpu vm/hsa code.
261 */
262
263static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
264 unsigned int vmhub, uint32_t flush_type)
265{
266 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
267 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
268 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
269 u32 tmp;
270 /* Use register 17 for GART */
271 const unsigned eng = 17;
272 unsigned int i;
273
274 spin_lock(&adev->gmc.invalidate_lock);
275 /*
276 * It may lose gpuvm invalidate acknowldege state across power-gating
277 * off cycle, add semaphore acquire before invalidation and semaphore
278 * release after invalidation to avoid entering power gated state
279 * to WA the Issue
280 */
281
282 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
283 if (use_semaphore) {
284 for (i = 0; i < adev->usec_timeout; i++) {
285 /* a read return value of 1 means semaphore acuqire */
286 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_sem +
287 hub->eng_distance * eng);
288 if (tmp & 0x1)
289 break;
290 udelay(1);
291 }
292
293 if (i >= adev->usec_timeout)
294 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
295 }
296
297 WREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng, inv_req);
298
299 /*
300 * Issue a dummy read to wait for the ACK register to be cleared
301 * to avoid a false ACK due to the new fast GRBM interface.
302 */
303 if (vmhub == AMDGPU_GFXHUB_0)
304 RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
305
306 /* Wait for ACK with a delay.*/
307 for (i = 0; i < adev->usec_timeout; i++) {
308 tmp = RREG32_NO_KIQ(hub->vm_inv_eng0_ack +
309 hub->eng_distance * eng);
310 tmp &= 1 << vmid;
311 if (tmp)
312 break;
313
314 udelay(1);
315 }
316
317 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
318 if (use_semaphore)
319 /*
320 * add semaphore release after invalidation,
321 * write with 0 means semaphore release
322 */
323 WREG32_NO_KIQ(hub->vm_inv_eng0_sem +
324 hub->eng_distance * eng, 0);
325
326 spin_unlock(&adev->gmc.invalidate_lock);
327
328 if (i < adev->usec_timeout)
329 return;
330
331 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
332}
333
334/**
335 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
336 *
337 * @adev: amdgpu_device pointer
338 * @vmid: vm instance to flush
339 *
340 * Flush the TLB for the requested page table.
341 */
342static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
343 uint32_t vmhub, uint32_t flush_type)
344{
345 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
346 struct dma_fence *fence;
347 struct amdgpu_job *job;
348
349 int r;
350
351 /* flush hdp cache */
352 adev->nbio.funcs->hdp_flush(adev, NULL);
353
354 /* For SRIOV run time, driver shouldn't access the register through MMIO
355 * Directly use kiq to do the vm invalidation instead
356 */
357 if (adev->gfx.kiq.ring.sched.ready &&
358 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
359 !adev->in_gpu_reset) {
360
361 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
362 const unsigned eng = 17;
363 u32 inv_req = gmc_v10_0_get_invalidate_req(vmid, flush_type);
364 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
365 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
366
367 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
368 1 << vmid);
369 return;
370 }
371
372 mutex_lock(&adev->mman.gtt_window_lock);
373
374 if (vmhub == AMDGPU_MMHUB_0) {
375 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
376 mutex_unlock(&adev->mman.gtt_window_lock);
377 return;
378 }
379
380 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
381
382 if (!adev->mman.buffer_funcs_enabled ||
383 !adev->ib_pool_ready ||
384 adev->in_gpu_reset ||
385 ring->sched.ready == false) {
386 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
387 mutex_unlock(&adev->mman.gtt_window_lock);
388 return;
389 }
390
391 /* The SDMA on Navi has a bug which can theoretically result in memory
392 * corruption if an invalidation happens at the same time as an VA
393 * translation. Avoid this by doing the invalidation from the SDMA
394 * itself.
395 */
396 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
397 &job);
398 if (r)
399 goto error_alloc;
400
401 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
402 job->vm_needs_flush = true;
403 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
404 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
405 r = amdgpu_job_submit(job, &adev->mman.entity,
406 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
407 if (r)
408 goto error_submit;
409
410 mutex_unlock(&adev->mman.gtt_window_lock);
411
412 dma_fence_wait(fence, false);
413 dma_fence_put(fence);
414
415 return;
416
417error_submit:
418 amdgpu_job_free(job);
419
420error_alloc:
421 mutex_unlock(&adev->mman.gtt_window_lock);
422 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
423}
424
425/**
426 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
427 *
428 * @adev: amdgpu_device pointer
429 * @pasid: pasid to be flush
430 *
431 * Flush the TLB for the requested pasid.
432 */
433static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
434 uint16_t pasid, uint32_t flush_type,
435 bool all_hub)
436{
437 int vmid, i;
438 signed long r;
439 uint32_t seq;
440 uint16_t queried_pasid;
441 bool ret;
442 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
443 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
444
445 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
446 spin_lock(&adev->gfx.kiq.ring_lock);
447 /* 2 dwords flush + 8 dwords fence */
448 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
449 kiq->pmf->kiq_invalidate_tlbs(ring,
450 pasid, flush_type, all_hub);
451 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
452 if (r) {
453 amdgpu_ring_undo(ring);
454 spin_unlock(&adev->gfx.kiq.ring_lock);
455 return -ETIME;
456 }
457
458 amdgpu_ring_commit(ring);
459 spin_unlock(&adev->gfx.kiq.ring_lock);
460 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
461 if (r < 1) {
462 DRM_ERROR("wait for kiq fence error: %ld.\n", r);
463 return -ETIME;
464 }
465
466 return 0;
467 }
468
469 for (vmid = 1; vmid < 16; vmid++) {
470
471 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
472 &queried_pasid);
473 if (ret && queried_pasid == pasid) {
474 if (all_hub) {
475 for (i = 0; i < adev->num_vmhubs; i++)
476 gmc_v10_0_flush_gpu_tlb(adev, vmid,
477 i, flush_type);
478 } else {
479 gmc_v10_0_flush_gpu_tlb(adev, vmid,
480 AMDGPU_GFXHUB_0, flush_type);
481 }
482 break;
483 }
484 }
485
486 return 0;
487}
488
489static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
490 unsigned vmid, uint64_t pd_addr)
491{
492 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
493 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
494 uint32_t req = gmc_v10_0_get_invalidate_req(vmid, 0);
495 unsigned eng = ring->vm_inv_eng;
496
497 /*
498 * It may lose gpuvm invalidate acknowldege state across power-gating
499 * off cycle, add semaphore acquire before invalidation and semaphore
500 * release after invalidation to avoid entering power gated state
501 * to WA the Issue
502 */
503
504 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
505 if (use_semaphore)
506 /* a read return value of 1 means semaphore acuqire */
507 amdgpu_ring_emit_reg_wait(ring,
508 hub->vm_inv_eng0_sem +
509 hub->eng_distance * eng, 0x1, 0x1);
510
511 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
512 (hub->ctx_addr_distance * vmid),
513 lower_32_bits(pd_addr));
514
515 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
516 (hub->ctx_addr_distance * vmid),
517 upper_32_bits(pd_addr));
518
519 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
520 hub->eng_distance * eng,
521 hub->vm_inv_eng0_ack +
522 hub->eng_distance * eng,
523 req, 1 << vmid);
524
525 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
526 if (use_semaphore)
527 /*
528 * add semaphore release after invalidation,
529 * write with 0 means semaphore release
530 */
531 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
532 hub->eng_distance * eng, 0);
533
534 return pd_addr;
535}
536
537static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
538 unsigned pasid)
539{
540 struct amdgpu_device *adev = ring->adev;
541 uint32_t reg;
542
543 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
544 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
545 else
546 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
547
548 amdgpu_ring_emit_wreg(ring, reg, pasid);
549}
550
551/*
552 * PTE format on NAVI 10:
553 * 63:59 reserved
554 * 58:57 reserved
555 * 56 F
556 * 55 L
557 * 54 reserved
558 * 53:52 SW
559 * 51 T
560 * 50:48 mtype
561 * 47:12 4k physical page base address
562 * 11:7 fragment
563 * 6 write
564 * 5 read
565 * 4 exe
566 * 3 Z
567 * 2 snooped
568 * 1 system
569 * 0 valid
570 *
571 * PDE format on NAVI 10:
572 * 63:59 block fragment size
573 * 58:55 reserved
574 * 54 P
575 * 53:48 reserved
576 * 47:6 physical base address of PD or PTE
577 * 5:3 reserved
578 * 2 C
579 * 1 system
580 * 0 valid
581 */
582
583static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
584{
585 switch (flags) {
586 case AMDGPU_VM_MTYPE_DEFAULT:
587 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
588 case AMDGPU_VM_MTYPE_NC:
589 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
590 case AMDGPU_VM_MTYPE_WC:
591 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
592 case AMDGPU_VM_MTYPE_CC:
593 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
594 case AMDGPU_VM_MTYPE_UC:
595 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
596 default:
597 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
598 }
599}
600
601static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
602 uint64_t *addr, uint64_t *flags)
603{
604 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
605 *addr = adev->vm_manager.vram_base_offset + *addr -
606 adev->gmc.vram_start;
607 BUG_ON(*addr & 0xFFFF00000000003FULL);
608
609 if (!adev->gmc.translate_further)
610 return;
611
612 if (level == AMDGPU_VM_PDB1) {
613 /* Set the block fragment size */
614 if (!(*flags & AMDGPU_PDE_PTE))
615 *flags |= AMDGPU_PDE_BFS(0x9);
616
617 } else if (level == AMDGPU_VM_PDB0) {
618 if (*flags & AMDGPU_PDE_PTE)
619 *flags &= ~AMDGPU_PDE_PTE;
620 else
621 *flags |= AMDGPU_PTE_TF;
622 }
623}
624
625static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
626 struct amdgpu_bo_va_mapping *mapping,
627 uint64_t *flags)
628{
629 *flags &= ~AMDGPU_PTE_EXECUTABLE;
630 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
631
632 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
633 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
634
635 if (mapping->flags & AMDGPU_PTE_PRT) {
636 *flags |= AMDGPU_PTE_PRT;
637 *flags |= AMDGPU_PTE_SNOOPED;
638 *flags |= AMDGPU_PTE_LOG;
639 *flags |= AMDGPU_PTE_SYSTEM;
640 *flags &= ~AMDGPU_PTE_VALID;
641 }
642}
643
644static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
645 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
646 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
647 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
648 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
649 .map_mtype = gmc_v10_0_map_mtype,
650 .get_vm_pde = gmc_v10_0_get_vm_pde,
651 .get_vm_pte = gmc_v10_0_get_vm_pte
652};
653
654static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
655{
656 if (adev->gmc.gmc_funcs == NULL)
657 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
658}
659
660static int gmc_v10_0_early_init(void *handle)
661{
662 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
663
664 gmc_v10_0_set_gmc_funcs(adev);
665 gmc_v10_0_set_irq_funcs(adev);
666
667 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
668 adev->gmc.shared_aperture_end =
669 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
670 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
671 adev->gmc.private_aperture_end =
672 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
673
674 return 0;
675}
676
677static int gmc_v10_0_late_init(void *handle)
678{
679 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
680 int r;
681
682 amdgpu_bo_late_init(adev);
683
684 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
685 if (r)
686 return r;
687
688 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
689}
690
691static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
692 struct amdgpu_gmc *mc)
693{
694 u64 base = 0;
695
696 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
697 adev->asic_type == CHIP_NAVY_FLOUNDER)
698 base = gfxhub_v2_1_get_fb_location(adev);
699 else
700 base = gfxhub_v2_0_get_fb_location(adev);
701
702 /* add the xgmi offset of the physical node */
703 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
704
705 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
706 amdgpu_gmc_gart_location(adev, mc);
707
708 /* base offset of vram pages */
709 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
710 adev->asic_type == CHIP_NAVY_FLOUNDER)
711 adev->vm_manager.vram_base_offset = gfxhub_v2_1_get_mc_fb_offset(adev);
712 else
713 adev->vm_manager.vram_base_offset = gfxhub_v2_0_get_mc_fb_offset(adev);
714
715 /* add the xgmi offset of the physical node */
716 adev->vm_manager.vram_base_offset +=
717 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
718}
719
720/**
721 * gmc_v10_0_mc_init - initialize the memory controller driver params
722 *
723 * @adev: amdgpu_device pointer
724 *
725 * Look up the amount of vram, vram width, and decide how to place
726 * vram and gart within the GPU's physical address space.
727 * Returns 0 for success.
728 */
729static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
730{
731 int r;
732
733 /* size in MB on si */
734 adev->gmc.mc_vram_size =
735 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
736 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
737
738 if (!(adev->flags & AMD_IS_APU)) {
739 r = amdgpu_device_resize_fb_bar(adev);
740 if (r)
741 return r;
742 }
743 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
744 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
745
746 /* In case the PCI BAR is larger than the actual amount of vram */
747 adev->gmc.visible_vram_size = adev->gmc.aper_size;
748 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
749 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
750
751 /* set the gart size */
752 if (amdgpu_gart_size == -1) {
753 switch (adev->asic_type) {
754 case CHIP_NAVI10:
755 case CHIP_NAVI14:
756 case CHIP_NAVI12:
757 case CHIP_SIENNA_CICHLID:
758 case CHIP_NAVY_FLOUNDER:
759 default:
760 adev->gmc.gart_size = 512ULL << 20;
761 break;
762 }
763 } else
764 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
765
766 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
767
768 return 0;
769}
770
771static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
772{
773 int r;
774
775 if (adev->gart.bo) {
776 WARN(1, "NAVI10 PCIE GART already initialized\n");
777 return 0;
778 }
779
780 /* Initialize common gart structure */
781 r = amdgpu_gart_init(adev);
782 if (r)
783 return r;
784
785 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
786 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
787 AMDGPU_PTE_EXECUTABLE;
788
789 return amdgpu_gart_table_vram_alloc(adev);
790}
791
792static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
793{
794 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
795 unsigned size;
796
797 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
798 size = 9 * 1024 * 1024; /* reserve 8MB for vga emulator and 1 MB for FB */
799 } else {
800 u32 viewport;
801 u32 pitch;
802
803 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
804 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
805 size = (REG_GET_FIELD(viewport,
806 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
807 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
808 4);
809 }
810 /* return 0 if the pre-OS buffer uses up most of vram */
811 if ((adev->gmc.real_vram_size - size) < (8 * 1024 * 1024)) {
812 DRM_ERROR("Warning: pre-OS buffer uses most of vram, \
813 be aware of gart table overwrite\n");
814 return 0;
815 }
816
817 return size;
818}
819
820
821
822static int gmc_v10_0_sw_init(void *handle)
823{
824 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
825 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
826
827 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
828 adev->asic_type == CHIP_NAVY_FLOUNDER)
829 gfxhub_v2_1_init(adev);
830 else
831 gfxhub_v2_0_init(adev);
832
833 mmhub_v2_0_init(adev);
834
835 spin_lock_init(&adev->gmc.invalidate_lock);
836
837 if (adev->asic_type == CHIP_SIENNA_CICHLID && amdgpu_emu_mode == 1) {
838 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
839 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
840 } else {
841 r = amdgpu_atomfirmware_get_vram_info(adev,
842 &vram_width, &vram_type, &vram_vendor);
843 adev->gmc.vram_width = vram_width;
844
845 adev->gmc.vram_type = vram_type;
846 adev->gmc.vram_vendor = vram_vendor;
847 }
848
849 switch (adev->asic_type) {
850 case CHIP_NAVI10:
851 case CHIP_NAVI14:
852 case CHIP_NAVI12:
853 case CHIP_SIENNA_CICHLID:
854 case CHIP_NAVY_FLOUNDER:
855 adev->num_vmhubs = 2;
856 /*
857 * To fulfill 4-level page support,
858 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
859 * block size 512 (9bit)
860 */
861 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
862 break;
863 default:
864 break;
865 }
866
867 /* This interrupt is VMC page fault.*/
868 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
869 VMC_1_0__SRCID__VM_FAULT,
870 &adev->gmc.vm_fault);
871
872 if (r)
873 return r;
874
875 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
876 UTCL2_1_0__SRCID__FAULT,
877 &adev->gmc.vm_fault);
878 if (r)
879 return r;
880
881 /*
882 * Set the internal MC address mask This is the max address of the GPU's
883 * internal address space.
884 */
885 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
886
887 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
888 if (r) {
889 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
890 return r;
891 }
892
893 if (adev->gmc.xgmi.supported) {
894 r = gfxhub_v2_1_get_xgmi_info(adev);
895 if (r)
896 return r;
897 }
898
899 r = gmc_v10_0_mc_init(adev);
900 if (r)
901 return r;
902
903 adev->gmc.stolen_size = gmc_v10_0_get_vbios_fb_size(adev);
904
905 /* Memory manager */
906 r = amdgpu_bo_init(adev);
907 if (r)
908 return r;
909
910 r = gmc_v10_0_gart_init(adev);
911 if (r)
912 return r;
913
914 /*
915 * number of VMs
916 * VMID 0 is reserved for System
917 * amdgpu graphics/compute will use VMIDs 1-7
918 * amdkfd will use VMIDs 8-15
919 */
920 adev->vm_manager.first_kfd_vmid = 8;
921
922 amdgpu_vm_manager_init(adev);
923
924 return 0;
925}
926
927/**
928 * gmc_v8_0_gart_fini - vm fini callback
929 *
930 * @adev: amdgpu_device pointer
931 *
932 * Tears down the driver GART/VM setup (CIK).
933 */
934static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
935{
936 amdgpu_gart_table_vram_free(adev);
937 amdgpu_gart_fini(adev);
938}
939
940static int gmc_v10_0_sw_fini(void *handle)
941{
942 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
943
944 amdgpu_vm_manager_fini(adev);
945 gmc_v10_0_gart_fini(adev);
946 amdgpu_gem_force_release(adev);
947 amdgpu_bo_fini(adev);
948
949 return 0;
950}
951
952static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
953{
954 switch (adev->asic_type) {
955 case CHIP_NAVI10:
956 case CHIP_NAVI14:
957 case CHIP_NAVI12:
958 case CHIP_SIENNA_CICHLID:
959 case CHIP_NAVY_FLOUNDER:
960 break;
961 default:
962 break;
963 }
964}
965
966/**
967 * gmc_v10_0_gart_enable - gart enable
968 *
969 * @adev: amdgpu_device pointer
970 */
971static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
972{
973 int r;
974 bool value;
975 u32 tmp;
976
977 if (adev->gart.bo == NULL) {
978 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
979 return -EINVAL;
980 }
981
982 r = amdgpu_gart_table_vram_pin(adev);
983 if (r)
984 return r;
985
986 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
987 adev->asic_type == CHIP_NAVY_FLOUNDER)
988 r = gfxhub_v2_1_gart_enable(adev);
989 else
990 r = gfxhub_v2_0_gart_enable(adev);
991 if (r)
992 return r;
993
994 r = mmhub_v2_0_gart_enable(adev);
995 if (r)
996 return r;
997
998 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
999 tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
1000 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
1001
1002 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
1003 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
1004
1005 /* Flush HDP after it is initialized */
1006 adev->nbio.funcs->hdp_flush(adev, NULL);
1007
1008 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1009 false : true;
1010
1011 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
1012 adev->asic_type == CHIP_NAVY_FLOUNDER)
1013 gfxhub_v2_1_set_fault_enable_default(adev, value);
1014 else
1015 gfxhub_v2_0_set_fault_enable_default(adev, value);
1016 mmhub_v2_0_set_fault_enable_default(adev, value);
1017 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1018 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1019
1020 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1021 (unsigned)(adev->gmc.gart_size >> 20),
1022 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1023
1024 adev->gart.ready = true;
1025
1026 return 0;
1027}
1028
1029static int gmc_v10_0_hw_init(void *handle)
1030{
1031 int r;
1032 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033
1034 /* The sequence of these two function calls matters.*/
1035 gmc_v10_0_init_golden_registers(adev);
1036
1037 r = gmc_v10_0_gart_enable(adev);
1038 if (r)
1039 return r;
1040
1041 return 0;
1042}
1043
1044/**
1045 * gmc_v10_0_gart_disable - gart disable
1046 *
1047 * @adev: amdgpu_device pointer
1048 *
1049 * This disables all VM page table.
1050 */
1051static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1052{
1053 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
1054 adev->asic_type == CHIP_NAVY_FLOUNDER)
1055 gfxhub_v2_1_gart_disable(adev);
1056 else
1057 gfxhub_v2_0_gart_disable(adev);
1058 mmhub_v2_0_gart_disable(adev);
1059 amdgpu_gart_table_vram_unpin(adev);
1060}
1061
1062static int gmc_v10_0_hw_fini(void *handle)
1063{
1064 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1065
1066 if (amdgpu_sriov_vf(adev)) {
1067 /* full access mode, so don't touch any GMC register */
1068 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1069 return 0;
1070 }
1071
1072 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1073 gmc_v10_0_gart_disable(adev);
1074
1075 return 0;
1076}
1077
1078static int gmc_v10_0_suspend(void *handle)
1079{
1080 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1081
1082 gmc_v10_0_hw_fini(adev);
1083
1084 return 0;
1085}
1086
1087static int gmc_v10_0_resume(void *handle)
1088{
1089 int r;
1090 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1091
1092 r = gmc_v10_0_hw_init(adev);
1093 if (r)
1094 return r;
1095
1096 amdgpu_vmid_reset_all(adev);
1097
1098 return 0;
1099}
1100
1101static bool gmc_v10_0_is_idle(void *handle)
1102{
1103 /* MC is always ready in GMC v10.*/
1104 return true;
1105}
1106
1107static int gmc_v10_0_wait_for_idle(void *handle)
1108{
1109 /* There is no need to wait for MC idle in GMC v10.*/
1110 return 0;
1111}
1112
1113static int gmc_v10_0_soft_reset(void *handle)
1114{
1115 return 0;
1116}
1117
1118static int gmc_v10_0_set_clockgating_state(void *handle,
1119 enum amd_clockgating_state state)
1120{
1121 int r;
1122 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1123
1124 r = mmhub_v2_0_set_clockgating(adev, state);
1125 if (r)
1126 return r;
1127
1128 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
1129 adev->asic_type == CHIP_NAVY_FLOUNDER)
1130 return athub_v2_1_set_clockgating(adev, state);
1131 else
1132 return athub_v2_0_set_clockgating(adev, state);
1133}
1134
1135static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1136{
1137 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1138
1139 mmhub_v2_0_get_clockgating(adev, flags);
1140
1141 if (adev->asic_type == CHIP_SIENNA_CICHLID ||
1142 adev->asic_type == CHIP_NAVY_FLOUNDER)
1143 athub_v2_1_get_clockgating(adev, flags);
1144 else
1145 athub_v2_0_get_clockgating(adev, flags);
1146}
1147
1148static int gmc_v10_0_set_powergating_state(void *handle,
1149 enum amd_powergating_state state)
1150{
1151 return 0;
1152}
1153
1154const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1155 .name = "gmc_v10_0",
1156 .early_init = gmc_v10_0_early_init,
1157 .late_init = gmc_v10_0_late_init,
1158 .sw_init = gmc_v10_0_sw_init,
1159 .sw_fini = gmc_v10_0_sw_fini,
1160 .hw_init = gmc_v10_0_hw_init,
1161 .hw_fini = gmc_v10_0_hw_fini,
1162 .suspend = gmc_v10_0_suspend,
1163 .resume = gmc_v10_0_resume,
1164 .is_idle = gmc_v10_0_is_idle,
1165 .wait_for_idle = gmc_v10_0_wait_for_idle,
1166 .soft_reset = gmc_v10_0_soft_reset,
1167 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1168 .set_powergating_state = gmc_v10_0_set_powergating_state,
1169 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1170};
1171
1172const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1173{
1174 .type = AMD_IP_BLOCK_TYPE_GMC,
1175 .major = 10,
1176 .minor = 0,
1177 .rev = 0,
1178 .funcs = &gmc_v10_0_ip_funcs,
1179};
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/pci.h>
25#include "amdgpu.h"
26#include "amdgpu_atomfirmware.h"
27#include "gmc_v10_0.h"
28#include "umc_v8_7.h"
29
30#include "athub/athub_2_0_0_sh_mask.h"
31#include "athub/athub_2_0_0_offset.h"
32#include "dcn/dcn_2_0_0_offset.h"
33#include "dcn/dcn_2_0_0_sh_mask.h"
34#include "oss/osssys_5_0_0_offset.h"
35#include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
36#include "navi10_enum.h"
37
38#include "soc15.h"
39#include "soc15d.h"
40#include "soc15_common.h"
41
42#include "nbio_v2_3.h"
43
44#include "gfxhub_v2_0.h"
45#include "gfxhub_v2_1.h"
46#include "mmhub_v2_0.h"
47#include "mmhub_v2_3.h"
48#include "athub_v2_0.h"
49#include "athub_v2_1.h"
50
51#if 0
52static const struct soc15_reg_golden golden_settings_navi10_hdp[] =
53{
54 /* TODO add golden setting for hdp */
55};
56#endif
57
58static int gmc_v10_0_ecc_interrupt_state(struct amdgpu_device *adev,
59 struct amdgpu_irq_src *src,
60 unsigned type,
61 enum amdgpu_interrupt_state state)
62{
63 return 0;
64}
65
66static int
67gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
68 struct amdgpu_irq_src *src, unsigned type,
69 enum amdgpu_interrupt_state state)
70{
71 switch (state) {
72 case AMDGPU_IRQ_STATE_DISABLE:
73 /* MM HUB */
74 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, false);
75 /* GFX HUB */
76 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, false);
77 break;
78 case AMDGPU_IRQ_STATE_ENABLE:
79 /* MM HUB */
80 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_MMHUB_0, true);
81 /* GFX HUB */
82 amdgpu_gmc_set_vm_fault_masks(adev, AMDGPU_GFXHUB_0, true);
83 break;
84 default:
85 break;
86 }
87
88 return 0;
89}
90
91static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
92 struct amdgpu_irq_src *source,
93 struct amdgpu_iv_entry *entry)
94{
95 bool retry_fault = !!(entry->src_data[1] & 0x80);
96 struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
97 struct amdgpu_task_info task_info;
98 uint32_t status = 0;
99 u64 addr;
100
101 addr = (u64)entry->src_data[0] << 12;
102 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
103
104 if (retry_fault) {
105 /* Returning 1 here also prevents sending the IV to the KFD */
106
107 /* Process it onyl if it's the first fault for this address */
108 if (entry->ih != &adev->irq.ih_soft &&
109 amdgpu_gmc_filter_faults(adev, addr, entry->pasid,
110 entry->timestamp))
111 return 1;
112
113 /* Delegate it to a different ring if the hardware hasn't
114 * already done it.
115 */
116 if (entry->ih == &adev->irq.ih) {
117 amdgpu_irq_delegate(adev, entry, 8);
118 return 1;
119 }
120
121 /* Try to handle the recoverable page faults by filling page
122 * tables
123 */
124 if (amdgpu_vm_handle_fault(adev, entry->pasid, addr))
125 return 1;
126 }
127
128 if (!amdgpu_sriov_vf(adev)) {
129 /*
130 * Issue a dummy read to wait for the status register to
131 * be updated to avoid reading an incorrect value due to
132 * the new fast GRBM interface.
133 */
134 if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
135 (adev->asic_type < CHIP_SIENNA_CICHLID))
136 RREG32(hub->vm_l2_pro_fault_status);
137
138 status = RREG32(hub->vm_l2_pro_fault_status);
139 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
140 }
141
142 if (!printk_ratelimit())
143 return 0;
144
145 memset(&task_info, 0, sizeof(struct amdgpu_task_info));
146 amdgpu_vm_get_task_info(adev, entry->pasid, &task_info);
147
148 dev_err(adev->dev,
149 "[%s] page fault (src_id:%u ring:%u vmid:%u pasid:%u, "
150 "for process %s pid %d thread %s pid %d)\n",
151 entry->vmid_src ? "mmhub" : "gfxhub",
152 entry->src_id, entry->ring_id, entry->vmid,
153 entry->pasid, task_info.process_name, task_info.tgid,
154 task_info.task_name, task_info.pid);
155 dev_err(adev->dev, " in page starting at address 0x%016llx from client 0x%x (%s)\n",
156 addr, entry->client_id,
157 soc15_ih_clientid_name[entry->client_id]);
158
159 if (!amdgpu_sriov_vf(adev))
160 hub->vmhub_funcs->print_l2_protection_fault_status(adev,
161 status);
162
163 return 0;
164}
165
166static const struct amdgpu_irq_src_funcs gmc_v10_0_irq_funcs = {
167 .set = gmc_v10_0_vm_fault_interrupt_state,
168 .process = gmc_v10_0_process_interrupt,
169};
170
171static const struct amdgpu_irq_src_funcs gmc_v10_0_ecc_funcs = {
172 .set = gmc_v10_0_ecc_interrupt_state,
173 .process = amdgpu_umc_process_ecc_irq,
174};
175
176static void gmc_v10_0_set_irq_funcs(struct amdgpu_device *adev)
177{
178 adev->gmc.vm_fault.num_types = 1;
179 adev->gmc.vm_fault.funcs = &gmc_v10_0_irq_funcs;
180
181 if (!amdgpu_sriov_vf(adev)) {
182 adev->gmc.ecc_irq.num_types = 1;
183 adev->gmc.ecc_irq.funcs = &gmc_v10_0_ecc_funcs;
184 }
185}
186
187/**
188 * gmc_v10_0_use_invalidate_semaphore - judge whether to use semaphore
189 *
190 * @adev: amdgpu_device pointer
191 * @vmhub: vmhub type
192 *
193 */
194static bool gmc_v10_0_use_invalidate_semaphore(struct amdgpu_device *adev,
195 uint32_t vmhub)
196{
197 return ((vmhub == AMDGPU_MMHUB_0 ||
198 vmhub == AMDGPU_MMHUB_1) &&
199 (!amdgpu_sriov_vf(adev)));
200}
201
202static bool gmc_v10_0_get_atc_vmid_pasid_mapping_info(
203 struct amdgpu_device *adev,
204 uint8_t vmid, uint16_t *p_pasid)
205{
206 uint32_t value;
207
208 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
209 + vmid);
210 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
211
212 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
213}
214
215/*
216 * GART
217 * VMID 0 is the physical GPU addresses as used by the kernel.
218 * VMIDs 1-15 are used for userspace clients and are handled
219 * by the amdgpu vm/hsa code.
220 */
221
222static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
223 unsigned int vmhub, uint32_t flush_type)
224{
225 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(adev, vmhub);
226 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
227 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
228 u32 tmp;
229 /* Use register 17 for GART */
230 const unsigned eng = 17;
231 unsigned int i;
232 unsigned char hub_ip = 0;
233
234 hub_ip = (vmhub == AMDGPU_GFXHUB_0) ?
235 GC_HWIP : MMHUB_HWIP;
236
237 spin_lock(&adev->gmc.invalidate_lock);
238 /*
239 * It may lose gpuvm invalidate acknowldege state across power-gating
240 * off cycle, add semaphore acquire before invalidation and semaphore
241 * release after invalidation to avoid entering power gated state
242 * to WA the Issue
243 */
244
245 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
246 if (use_semaphore) {
247 for (i = 0; i < adev->usec_timeout; i++) {
248 /* a read return value of 1 means semaphore acuqire */
249 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
250 hub->eng_distance * eng, hub_ip);
251
252 if (tmp & 0x1)
253 break;
254 udelay(1);
255 }
256
257 if (i >= adev->usec_timeout)
258 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
259 }
260
261 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
262 hub->eng_distance * eng,
263 inv_req, hub_ip);
264
265 /*
266 * Issue a dummy read to wait for the ACK register to be cleared
267 * to avoid a false ACK due to the new fast GRBM interface.
268 */
269 if ((vmhub == AMDGPU_GFXHUB_0) &&
270 (adev->asic_type < CHIP_SIENNA_CICHLID))
271 RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_req +
272 hub->eng_distance * eng, hub_ip);
273
274 /* Wait for ACK with a delay.*/
275 for (i = 0; i < adev->usec_timeout; i++) {
276 tmp = RREG32_RLC_NO_KIQ(hub->vm_inv_eng0_ack +
277 hub->eng_distance * eng, hub_ip);
278
279 tmp &= 1 << vmid;
280 if (tmp)
281 break;
282
283 udelay(1);
284 }
285
286 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
287 if (use_semaphore)
288 /*
289 * add semaphore release after invalidation,
290 * write with 0 means semaphore release
291 */
292 WREG32_RLC_NO_KIQ(hub->vm_inv_eng0_sem +
293 hub->eng_distance * eng, 0, hub_ip);
294
295 spin_unlock(&adev->gmc.invalidate_lock);
296
297 if (i < adev->usec_timeout)
298 return;
299
300 DRM_ERROR("Timeout waiting for VM flush hub: %d!\n", vmhub);
301}
302
303/**
304 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
305 *
306 * @adev: amdgpu_device pointer
307 * @vmid: vm instance to flush
308 * @vmhub: vmhub type
309 * @flush_type: the flush type
310 *
311 * Flush the TLB for the requested page table.
312 */
313static void gmc_v10_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
314 uint32_t vmhub, uint32_t flush_type)
315{
316 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
317 struct dma_fence *fence;
318 struct amdgpu_job *job;
319
320 int r;
321
322 /* flush hdp cache */
323 adev->hdp.funcs->flush_hdp(adev, NULL);
324
325 /* For SRIOV run time, driver shouldn't access the register through MMIO
326 * Directly use kiq to do the vm invalidation instead
327 */
328 if (adev->gfx.kiq.ring.sched.ready &&
329 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev)) &&
330 down_read_trylock(&adev->reset_sem)) {
331 struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
332 const unsigned eng = 17;
333 u32 inv_req = hub->vmhub_funcs->get_invalidate_req(vmid, flush_type);
334 u32 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
335 u32 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
336
337 amdgpu_virt_kiq_reg_write_reg_wait(adev, req, ack, inv_req,
338 1 << vmid);
339
340 up_read(&adev->reset_sem);
341 return;
342 }
343
344 mutex_lock(&adev->mman.gtt_window_lock);
345
346 if (vmhub == AMDGPU_MMHUB_0) {
347 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
348 mutex_unlock(&adev->mman.gtt_window_lock);
349 return;
350 }
351
352 BUG_ON(vmhub != AMDGPU_GFXHUB_0);
353
354 if (!adev->mman.buffer_funcs_enabled ||
355 !adev->ib_pool_ready ||
356 amdgpu_in_reset(adev) ||
357 ring->sched.ready == false) {
358 gmc_v10_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
359 mutex_unlock(&adev->mman.gtt_window_lock);
360 return;
361 }
362
363 /* The SDMA on Navi has a bug which can theoretically result in memory
364 * corruption if an invalidation happens at the same time as an VA
365 * translation. Avoid this by doing the invalidation from the SDMA
366 * itself.
367 */
368 r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
369 &job);
370 if (r)
371 goto error_alloc;
372
373 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
374 job->vm_needs_flush = true;
375 job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
376 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
377 r = amdgpu_job_submit(job, &adev->mman.entity,
378 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
379 if (r)
380 goto error_submit;
381
382 mutex_unlock(&adev->mman.gtt_window_lock);
383
384 dma_fence_wait(fence, false);
385 dma_fence_put(fence);
386
387 return;
388
389error_submit:
390 amdgpu_job_free(job);
391
392error_alloc:
393 mutex_unlock(&adev->mman.gtt_window_lock);
394 DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
395}
396
397/**
398 * gmc_v10_0_flush_gpu_tlb_pasid - tlb flush via pasid
399 *
400 * @adev: amdgpu_device pointer
401 * @pasid: pasid to be flush
402 * @flush_type: the flush type
403 * @all_hub: Used with PACKET3_INVALIDATE_TLBS_ALL_HUB()
404 *
405 * Flush the TLB for the requested pasid.
406 */
407static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
408 uint16_t pasid, uint32_t flush_type,
409 bool all_hub)
410{
411 int vmid, i;
412 signed long r;
413 uint32_t seq;
414 uint16_t queried_pasid;
415 bool ret;
416 struct amdgpu_ring *ring = &adev->gfx.kiq.ring;
417 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
418
419 if (amdgpu_emu_mode == 0 && ring->sched.ready) {
420 spin_lock(&adev->gfx.kiq.ring_lock);
421 /* 2 dwords flush + 8 dwords fence */
422 amdgpu_ring_alloc(ring, kiq->pmf->invalidate_tlbs_size + 8);
423 kiq->pmf->kiq_invalidate_tlbs(ring,
424 pasid, flush_type, all_hub);
425 r = amdgpu_fence_emit_polling(ring, &seq, MAX_KIQ_REG_WAIT);
426 if (r) {
427 amdgpu_ring_undo(ring);
428 spin_unlock(&adev->gfx.kiq.ring_lock);
429 return -ETIME;
430 }
431
432 amdgpu_ring_commit(ring);
433 spin_unlock(&adev->gfx.kiq.ring_lock);
434 r = amdgpu_fence_wait_polling(ring, seq, adev->usec_timeout);
435 if (r < 1) {
436 dev_err(adev->dev, "wait for kiq fence error: %ld.\n", r);
437 return -ETIME;
438 }
439
440 return 0;
441 }
442
443 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
444
445 ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
446 &queried_pasid);
447 if (ret && queried_pasid == pasid) {
448 if (all_hub) {
449 for (i = 0; i < adev->num_vmhubs; i++)
450 gmc_v10_0_flush_gpu_tlb(adev, vmid,
451 i, flush_type);
452 } else {
453 gmc_v10_0_flush_gpu_tlb(adev, vmid,
454 AMDGPU_GFXHUB_0, flush_type);
455 }
456 break;
457 }
458 }
459
460 return 0;
461}
462
463static uint64_t gmc_v10_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
464 unsigned vmid, uint64_t pd_addr)
465{
466 bool use_semaphore = gmc_v10_0_use_invalidate_semaphore(ring->adev, ring->funcs->vmhub);
467 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
468 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
469 unsigned eng = ring->vm_inv_eng;
470
471 /*
472 * It may lose gpuvm invalidate acknowldege state across power-gating
473 * off cycle, add semaphore acquire before invalidation and semaphore
474 * release after invalidation to avoid entering power gated state
475 * to WA the Issue
476 */
477
478 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
479 if (use_semaphore)
480 /* a read return value of 1 means semaphore acuqire */
481 amdgpu_ring_emit_reg_wait(ring,
482 hub->vm_inv_eng0_sem +
483 hub->eng_distance * eng, 0x1, 0x1);
484
485 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
486 (hub->ctx_addr_distance * vmid),
487 lower_32_bits(pd_addr));
488
489 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
490 (hub->ctx_addr_distance * vmid),
491 upper_32_bits(pd_addr));
492
493 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
494 hub->eng_distance * eng,
495 hub->vm_inv_eng0_ack +
496 hub->eng_distance * eng,
497 req, 1 << vmid);
498
499 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
500 if (use_semaphore)
501 /*
502 * add semaphore release after invalidation,
503 * write with 0 means semaphore release
504 */
505 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
506 hub->eng_distance * eng, 0);
507
508 return pd_addr;
509}
510
511static void gmc_v10_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned vmid,
512 unsigned pasid)
513{
514 struct amdgpu_device *adev = ring->adev;
515 uint32_t reg;
516
517 if (ring->funcs->vmhub == AMDGPU_GFXHUB_0)
518 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
519 else
520 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
521
522 amdgpu_ring_emit_wreg(ring, reg, pasid);
523}
524
525/*
526 * PTE format on NAVI 10:
527 * 63:59 reserved
528 * 58 reserved and for sienna_cichlid is used for MALL noalloc
529 * 57 reserved
530 * 56 F
531 * 55 L
532 * 54 reserved
533 * 53:52 SW
534 * 51 T
535 * 50:48 mtype
536 * 47:12 4k physical page base address
537 * 11:7 fragment
538 * 6 write
539 * 5 read
540 * 4 exe
541 * 3 Z
542 * 2 snooped
543 * 1 system
544 * 0 valid
545 *
546 * PDE format on NAVI 10:
547 * 63:59 block fragment size
548 * 58:55 reserved
549 * 54 P
550 * 53:48 reserved
551 * 47:6 physical base address of PD or PTE
552 * 5:3 reserved
553 * 2 C
554 * 1 system
555 * 0 valid
556 */
557
558static uint64_t gmc_v10_0_map_mtype(struct amdgpu_device *adev, uint32_t flags)
559{
560 switch (flags) {
561 case AMDGPU_VM_MTYPE_DEFAULT:
562 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
563 case AMDGPU_VM_MTYPE_NC:
564 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
565 case AMDGPU_VM_MTYPE_WC:
566 return AMDGPU_PTE_MTYPE_NV10(MTYPE_WC);
567 case AMDGPU_VM_MTYPE_CC:
568 return AMDGPU_PTE_MTYPE_NV10(MTYPE_CC);
569 case AMDGPU_VM_MTYPE_UC:
570 return AMDGPU_PTE_MTYPE_NV10(MTYPE_UC);
571 default:
572 return AMDGPU_PTE_MTYPE_NV10(MTYPE_NC);
573 }
574}
575
576static void gmc_v10_0_get_vm_pde(struct amdgpu_device *adev, int level,
577 uint64_t *addr, uint64_t *flags)
578{
579 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
580 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
581 BUG_ON(*addr & 0xFFFF00000000003FULL);
582
583 if (!adev->gmc.translate_further)
584 return;
585
586 if (level == AMDGPU_VM_PDB1) {
587 /* Set the block fragment size */
588 if (!(*flags & AMDGPU_PDE_PTE))
589 *flags |= AMDGPU_PDE_BFS(0x9);
590
591 } else if (level == AMDGPU_VM_PDB0) {
592 if (*flags & AMDGPU_PDE_PTE)
593 *flags &= ~AMDGPU_PDE_PTE;
594 else
595 *flags |= AMDGPU_PTE_TF;
596 }
597}
598
599static void gmc_v10_0_get_vm_pte(struct amdgpu_device *adev,
600 struct amdgpu_bo_va_mapping *mapping,
601 uint64_t *flags)
602{
603 *flags &= ~AMDGPU_PTE_EXECUTABLE;
604 *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
605
606 *flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
607 *flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
608
609 if (mapping->flags & AMDGPU_PTE_PRT) {
610 *flags |= AMDGPU_PTE_PRT;
611 *flags |= AMDGPU_PTE_SNOOPED;
612 *flags |= AMDGPU_PTE_LOG;
613 *flags |= AMDGPU_PTE_SYSTEM;
614 *flags &= ~AMDGPU_PTE_VALID;
615 }
616}
617
618static unsigned gmc_v10_0_get_vbios_fb_size(struct amdgpu_device *adev)
619{
620 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
621 unsigned size;
622
623 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
624 size = AMDGPU_VBIOS_VGA_ALLOCATION;
625 } else {
626 u32 viewport;
627 u32 pitch;
628
629 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
630 pitch = RREG32_SOC15(DCE, 0, mmHUBPREQ0_DCSURF_SURFACE_PITCH);
631 size = (REG_GET_FIELD(viewport,
632 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
633 REG_GET_FIELD(pitch, HUBPREQ0_DCSURF_SURFACE_PITCH, PITCH) *
634 4);
635 }
636
637 return size;
638}
639
640static const struct amdgpu_gmc_funcs gmc_v10_0_gmc_funcs = {
641 .flush_gpu_tlb = gmc_v10_0_flush_gpu_tlb,
642 .flush_gpu_tlb_pasid = gmc_v10_0_flush_gpu_tlb_pasid,
643 .emit_flush_gpu_tlb = gmc_v10_0_emit_flush_gpu_tlb,
644 .emit_pasid_mapping = gmc_v10_0_emit_pasid_mapping,
645 .map_mtype = gmc_v10_0_map_mtype,
646 .get_vm_pde = gmc_v10_0_get_vm_pde,
647 .get_vm_pte = gmc_v10_0_get_vm_pte,
648 .get_vbios_fb_size = gmc_v10_0_get_vbios_fb_size,
649};
650
651static void gmc_v10_0_set_gmc_funcs(struct amdgpu_device *adev)
652{
653 if (adev->gmc.gmc_funcs == NULL)
654 adev->gmc.gmc_funcs = &gmc_v10_0_gmc_funcs;
655}
656
657static void gmc_v10_0_set_umc_funcs(struct amdgpu_device *adev)
658{
659 switch (adev->asic_type) {
660 case CHIP_SIENNA_CICHLID:
661 adev->umc.max_ras_err_cnt_per_query = UMC_V8_7_TOTAL_CHANNEL_NUM;
662 adev->umc.channel_inst_num = UMC_V8_7_CHANNEL_INSTANCE_NUM;
663 adev->umc.umc_inst_num = UMC_V8_7_UMC_INSTANCE_NUM;
664 adev->umc.channel_offs = UMC_V8_7_PER_CHANNEL_OFFSET_SIENNA;
665 adev->umc.channel_idx_tbl = &umc_v8_7_channel_idx_tbl[0][0];
666 adev->umc.ras_funcs = &umc_v8_7_ras_funcs;
667 break;
668 default:
669 break;
670 }
671}
672
673
674static void gmc_v10_0_set_mmhub_funcs(struct amdgpu_device *adev)
675{
676 switch (adev->asic_type) {
677 case CHIP_VANGOGH:
678 case CHIP_YELLOW_CARP:
679 adev->mmhub.funcs = &mmhub_v2_3_funcs;
680 break;
681 default:
682 adev->mmhub.funcs = &mmhub_v2_0_funcs;
683 break;
684 }
685}
686
687static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev)
688{
689 switch (adev->asic_type) {
690 case CHIP_SIENNA_CICHLID:
691 case CHIP_NAVY_FLOUNDER:
692 case CHIP_VANGOGH:
693 case CHIP_DIMGREY_CAVEFISH:
694 case CHIP_BEIGE_GOBY:
695 case CHIP_YELLOW_CARP:
696 adev->gfxhub.funcs = &gfxhub_v2_1_funcs;
697 break;
698 default:
699 adev->gfxhub.funcs = &gfxhub_v2_0_funcs;
700 break;
701 }
702}
703
704
705static int gmc_v10_0_early_init(void *handle)
706{
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708
709 gmc_v10_0_set_mmhub_funcs(adev);
710 gmc_v10_0_set_gfxhub_funcs(adev);
711 gmc_v10_0_set_gmc_funcs(adev);
712 gmc_v10_0_set_irq_funcs(adev);
713 gmc_v10_0_set_umc_funcs(adev);
714
715 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
716 adev->gmc.shared_aperture_end =
717 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
718 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
719 adev->gmc.private_aperture_end =
720 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
721
722 return 0;
723}
724
725static int gmc_v10_0_late_init(void *handle)
726{
727 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
728 int r;
729
730 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
731 if (r)
732 return r;
733
734 r = amdgpu_gmc_ras_late_init(adev);
735 if (r)
736 return r;
737
738 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
739}
740
741static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
742 struct amdgpu_gmc *mc)
743{
744 u64 base = 0;
745
746 base = adev->gfxhub.funcs->get_fb_location(adev);
747
748 /* add the xgmi offset of the physical node */
749 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
750
751 amdgpu_gmc_vram_location(adev, &adev->gmc, base);
752 amdgpu_gmc_gart_location(adev, mc);
753 amdgpu_gmc_agp_location(adev, mc);
754
755 /* base offset of vram pages */
756 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
757
758 /* add the xgmi offset of the physical node */
759 adev->vm_manager.vram_base_offset +=
760 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
761}
762
763/**
764 * gmc_v10_0_mc_init - initialize the memory controller driver params
765 *
766 * @adev: amdgpu_device pointer
767 *
768 * Look up the amount of vram, vram width, and decide how to place
769 * vram and gart within the GPU's physical address space.
770 * Returns 0 for success.
771 */
772static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
773{
774 int r;
775
776 /* size in MB on si */
777 adev->gmc.mc_vram_size =
778 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
779 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
780
781 if (!(adev->flags & AMD_IS_APU)) {
782 r = amdgpu_device_resize_fb_bar(adev);
783 if (r)
784 return r;
785 }
786 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
787 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
788
789#ifdef CONFIG_X86_64
790 if (adev->flags & AMD_IS_APU) {
791 adev->gmc.aper_base = adev->gfxhub.funcs->get_mc_fb_offset(adev);
792 adev->gmc.aper_size = adev->gmc.real_vram_size;
793 }
794#endif
795
796 /* In case the PCI BAR is larger than the actual amount of vram */
797 adev->gmc.visible_vram_size = adev->gmc.aper_size;
798 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
799 adev->gmc.visible_vram_size = adev->gmc.real_vram_size;
800
801 /* set the gart size */
802 if (amdgpu_gart_size == -1) {
803 switch (adev->asic_type) {
804 case CHIP_NAVI10:
805 case CHIP_NAVI14:
806 case CHIP_NAVI12:
807 case CHIP_SIENNA_CICHLID:
808 case CHIP_NAVY_FLOUNDER:
809 case CHIP_VANGOGH:
810 case CHIP_DIMGREY_CAVEFISH:
811 case CHIP_BEIGE_GOBY:
812 case CHIP_YELLOW_CARP:
813 default:
814 adev->gmc.gart_size = 512ULL << 20;
815 break;
816 }
817 } else
818 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
819
820 gmc_v10_0_vram_gtt_location(adev, &adev->gmc);
821
822 return 0;
823}
824
825static int gmc_v10_0_gart_init(struct amdgpu_device *adev)
826{
827 int r;
828
829 if (adev->gart.bo) {
830 WARN(1, "NAVI10 PCIE GART already initialized\n");
831 return 0;
832 }
833
834 /* Initialize common gart structure */
835 r = amdgpu_gart_init(adev);
836 if (r)
837 return r;
838
839 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
840 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(MTYPE_UC) |
841 AMDGPU_PTE_EXECUTABLE;
842
843 return amdgpu_gart_table_vram_alloc(adev);
844}
845
846static int gmc_v10_0_sw_init(void *handle)
847{
848 int r, vram_width = 0, vram_type = 0, vram_vendor = 0;
849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
850
851 adev->gfxhub.funcs->init(adev);
852
853 adev->mmhub.funcs->init(adev);
854
855 spin_lock_init(&adev->gmc.invalidate_lock);
856
857 if ((adev->flags & AMD_IS_APU) && amdgpu_emu_mode == 1) {
858 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
859 adev->gmc.vram_width = 64;
860 } else if (amdgpu_emu_mode == 1) {
861 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_GDDR6;
862 adev->gmc.vram_width = 1 * 128; /* numchan * chansize */
863 } else {
864 r = amdgpu_atomfirmware_get_vram_info(adev,
865 &vram_width, &vram_type, &vram_vendor);
866 adev->gmc.vram_width = vram_width;
867
868 adev->gmc.vram_type = vram_type;
869 adev->gmc.vram_vendor = vram_vendor;
870 }
871
872 switch (adev->asic_type) {
873 case CHIP_NAVI10:
874 case CHIP_NAVI14:
875 case CHIP_NAVI12:
876 case CHIP_SIENNA_CICHLID:
877 case CHIP_NAVY_FLOUNDER:
878 case CHIP_VANGOGH:
879 case CHIP_DIMGREY_CAVEFISH:
880 case CHIP_BEIGE_GOBY:
881 case CHIP_YELLOW_CARP:
882 adev->num_vmhubs = 2;
883 /*
884 * To fulfill 4-level page support,
885 * vm size is 256TB (48bit), maximum size of Navi10/Navi14/Navi12,
886 * block size 512 (9bit)
887 */
888 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
889 break;
890 default:
891 break;
892 }
893
894 /* This interrupt is VMC page fault.*/
895 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC,
896 VMC_1_0__SRCID__VM_FAULT,
897 &adev->gmc.vm_fault);
898
899 if (r)
900 return r;
901
902 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2,
903 UTCL2_1_0__SRCID__FAULT,
904 &adev->gmc.vm_fault);
905 if (r)
906 return r;
907
908 if (!amdgpu_sriov_vf(adev)) {
909 /* interrupt sent to DF. */
910 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
911 &adev->gmc.ecc_irq);
912 if (r)
913 return r;
914 }
915
916 /*
917 * Set the internal MC address mask This is the max address of the GPU's
918 * internal address space.
919 */
920 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
921
922 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(44));
923 if (r) {
924 printk(KERN_WARNING "amdgpu: No suitable DMA available.\n");
925 return r;
926 }
927
928 if (adev->gmc.xgmi.supported) {
929 r = adev->gfxhub.funcs->get_xgmi_info(adev);
930 if (r)
931 return r;
932 }
933
934 r = gmc_v10_0_mc_init(adev);
935 if (r)
936 return r;
937
938 amdgpu_gmc_get_vbios_allocations(adev);
939 amdgpu_gmc_get_reserved_allocation(adev);
940
941 /* Memory manager */
942 r = amdgpu_bo_init(adev);
943 if (r)
944 return r;
945
946 r = gmc_v10_0_gart_init(adev);
947 if (r)
948 return r;
949
950 /*
951 * number of VMs
952 * VMID 0 is reserved for System
953 * amdgpu graphics/compute will use VMIDs 1-7
954 * amdkfd will use VMIDs 8-15
955 */
956 adev->vm_manager.first_kfd_vmid = 8;
957
958 amdgpu_vm_manager_init(adev);
959
960 return 0;
961}
962
963/**
964 * gmc_v10_0_gart_fini - vm fini callback
965 *
966 * @adev: amdgpu_device pointer
967 *
968 * Tears down the driver GART/VM setup (CIK).
969 */
970static void gmc_v10_0_gart_fini(struct amdgpu_device *adev)
971{
972 amdgpu_gart_table_vram_free(adev);
973}
974
975static int gmc_v10_0_sw_fini(void *handle)
976{
977 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
978
979 amdgpu_vm_manager_fini(adev);
980 gmc_v10_0_gart_fini(adev);
981 amdgpu_gem_force_release(adev);
982 amdgpu_bo_fini(adev);
983
984 return 0;
985}
986
987static void gmc_v10_0_init_golden_registers(struct amdgpu_device *adev)
988{
989 switch (adev->asic_type) {
990 case CHIP_NAVI10:
991 case CHIP_NAVI14:
992 case CHIP_NAVI12:
993 case CHIP_SIENNA_CICHLID:
994 case CHIP_NAVY_FLOUNDER:
995 case CHIP_VANGOGH:
996 case CHIP_DIMGREY_CAVEFISH:
997 case CHIP_BEIGE_GOBY:
998 case CHIP_YELLOW_CARP:
999 break;
1000 default:
1001 break;
1002 }
1003}
1004
1005/**
1006 * gmc_v10_0_gart_enable - gart enable
1007 *
1008 * @adev: amdgpu_device pointer
1009 */
1010static int gmc_v10_0_gart_enable(struct amdgpu_device *adev)
1011{
1012 int r;
1013 bool value;
1014
1015 if (adev->gart.bo == NULL) {
1016 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
1017 return -EINVAL;
1018 }
1019
1020 r = amdgpu_gart_table_vram_pin(adev);
1021 if (r)
1022 return r;
1023
1024 r = adev->gfxhub.funcs->gart_enable(adev);
1025 if (r)
1026 return r;
1027
1028 r = adev->mmhub.funcs->gart_enable(adev);
1029 if (r)
1030 return r;
1031
1032 adev->hdp.funcs->init_registers(adev);
1033
1034 /* Flush HDP after it is initialized */
1035 adev->hdp.funcs->flush_hdp(adev, NULL);
1036
1037 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
1038 false : true;
1039
1040 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
1041 adev->mmhub.funcs->set_fault_enable_default(adev, value);
1042 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_MMHUB_0, 0);
1043 gmc_v10_0_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB_0, 0);
1044
1045 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1046 (unsigned)(adev->gmc.gart_size >> 20),
1047 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
1048
1049 adev->gart.ready = true;
1050
1051 return 0;
1052}
1053
1054static int gmc_v10_0_hw_init(void *handle)
1055{
1056 int r;
1057 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1058
1059 /* The sequence of these two function calls matters.*/
1060 gmc_v10_0_init_golden_registers(adev);
1061
1062 /*
1063 * harvestable groups in gc_utcl2 need to be programmed before any GFX block
1064 * register setup within GMC, or else system hang when harvesting SA.
1065 */
1066 if (adev->gfxhub.funcs && adev->gfxhub.funcs->utcl2_harvest)
1067 adev->gfxhub.funcs->utcl2_harvest(adev);
1068
1069 r = gmc_v10_0_gart_enable(adev);
1070 if (r)
1071 return r;
1072
1073 if (adev->umc.funcs && adev->umc.funcs->init_registers)
1074 adev->umc.funcs->init_registers(adev);
1075
1076 return 0;
1077}
1078
1079/**
1080 * gmc_v10_0_gart_disable - gart disable
1081 *
1082 * @adev: amdgpu_device pointer
1083 *
1084 * This disables all VM page table.
1085 */
1086static void gmc_v10_0_gart_disable(struct amdgpu_device *adev)
1087{
1088 adev->gfxhub.funcs->gart_disable(adev);
1089 adev->mmhub.funcs->gart_disable(adev);
1090 amdgpu_gart_table_vram_unpin(adev);
1091}
1092
1093static int gmc_v10_0_hw_fini(void *handle)
1094{
1095 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1096
1097 gmc_v10_0_gart_disable(adev);
1098
1099 if (amdgpu_sriov_vf(adev)) {
1100 /* full access mode, so don't touch any GMC register */
1101 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
1102 return 0;
1103 }
1104
1105 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
1106 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
1107
1108 return 0;
1109}
1110
1111static int gmc_v10_0_suspend(void *handle)
1112{
1113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1114
1115 gmc_v10_0_hw_fini(adev);
1116
1117 return 0;
1118}
1119
1120static int gmc_v10_0_resume(void *handle)
1121{
1122 int r;
1123 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1124
1125 r = gmc_v10_0_hw_init(adev);
1126 if (r)
1127 return r;
1128
1129 amdgpu_vmid_reset_all(adev);
1130
1131 return 0;
1132}
1133
1134static bool gmc_v10_0_is_idle(void *handle)
1135{
1136 /* MC is always ready in GMC v10.*/
1137 return true;
1138}
1139
1140static int gmc_v10_0_wait_for_idle(void *handle)
1141{
1142 /* There is no need to wait for MC idle in GMC v10.*/
1143 return 0;
1144}
1145
1146static int gmc_v10_0_soft_reset(void *handle)
1147{
1148 return 0;
1149}
1150
1151static int gmc_v10_0_set_clockgating_state(void *handle,
1152 enum amd_clockgating_state state)
1153{
1154 int r;
1155 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1156
1157 r = adev->mmhub.funcs->set_clockgating(adev, state);
1158 if (r)
1159 return r;
1160
1161 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1162 adev->asic_type <= CHIP_YELLOW_CARP)
1163 return athub_v2_1_set_clockgating(adev, state);
1164 else
1165 return athub_v2_0_set_clockgating(adev, state);
1166}
1167
1168static void gmc_v10_0_get_clockgating_state(void *handle, u32 *flags)
1169{
1170 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1171
1172 adev->mmhub.funcs->get_clockgating(adev, flags);
1173
1174 if (adev->asic_type >= CHIP_SIENNA_CICHLID &&
1175 adev->asic_type <= CHIP_YELLOW_CARP)
1176 athub_v2_1_get_clockgating(adev, flags);
1177 else
1178 athub_v2_0_get_clockgating(adev, flags);
1179}
1180
1181static int gmc_v10_0_set_powergating_state(void *handle,
1182 enum amd_powergating_state state)
1183{
1184 return 0;
1185}
1186
1187const struct amd_ip_funcs gmc_v10_0_ip_funcs = {
1188 .name = "gmc_v10_0",
1189 .early_init = gmc_v10_0_early_init,
1190 .late_init = gmc_v10_0_late_init,
1191 .sw_init = gmc_v10_0_sw_init,
1192 .sw_fini = gmc_v10_0_sw_fini,
1193 .hw_init = gmc_v10_0_hw_init,
1194 .hw_fini = gmc_v10_0_hw_fini,
1195 .suspend = gmc_v10_0_suspend,
1196 .resume = gmc_v10_0_resume,
1197 .is_idle = gmc_v10_0_is_idle,
1198 .wait_for_idle = gmc_v10_0_wait_for_idle,
1199 .soft_reset = gmc_v10_0_soft_reset,
1200 .set_clockgating_state = gmc_v10_0_set_clockgating_state,
1201 .set_powergating_state = gmc_v10_0_set_powergating_state,
1202 .get_clockgating_state = gmc_v10_0_get_clockgating_state,
1203};
1204
1205const struct amdgpu_ip_block_version gmc_v10_0_ip_block =
1206{
1207 .type = AMD_IP_BLOCK_TYPE_GMC,
1208 .major = 10,
1209 .minor = 0,
1210 .rev = 0,
1211 .funcs = &gmc_v10_0_ip_funcs,
1212};