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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26
27/* max number of IP instances */
28#define AMDGPU_MAX_SDMA_INSTANCES 8
29
30enum amdgpu_sdma_irq {
31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
32 AMDGPU_SDMA_IRQ_INSTANCE1,
33 AMDGPU_SDMA_IRQ_INSTANCE2,
34 AMDGPU_SDMA_IRQ_INSTANCE3,
35 AMDGPU_SDMA_IRQ_INSTANCE4,
36 AMDGPU_SDMA_IRQ_INSTANCE5,
37 AMDGPU_SDMA_IRQ_INSTANCE6,
38 AMDGPU_SDMA_IRQ_INSTANCE7,
39 AMDGPU_SDMA_IRQ_LAST
40};
41
42struct amdgpu_sdma_instance {
43 /* SDMA firmware */
44 const struct firmware *fw;
45 uint32_t fw_version;
46 uint32_t feature_version;
47
48 struct amdgpu_ring ring;
49 struct amdgpu_ring page;
50 bool burst_nop;
51};
52
53struct amdgpu_sdma_ras_funcs {
54 int (*ras_late_init)(struct amdgpu_device *adev,
55 void *ras_ih_info);
56 void (*ras_fini)(struct amdgpu_device *adev);
57 int (*query_ras_error_count)(struct amdgpu_device *adev,
58 uint32_t instance, void *ras_error_status);
59 void (*reset_ras_error_count)(struct amdgpu_device *adev);
60};
61
62struct amdgpu_sdma {
63 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
64 struct amdgpu_irq_src trap_irq;
65 struct amdgpu_irq_src illegal_inst_irq;
66 struct amdgpu_irq_src ecc_irq;
67 int num_instances;
68 uint32_t srbm_soft_reset;
69 bool has_page_queue;
70 struct ras_common_if *ras_if;
71 const struct amdgpu_sdma_ras_funcs *funcs;
72};
73
74/*
75 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
76 * But currently, we use sdma to move data.
77 */
78struct amdgpu_buffer_funcs {
79 /* maximum bytes in a single operation */
80 uint32_t copy_max_bytes;
81
82 /* number of dw to reserve per operation */
83 unsigned copy_num_dw;
84
85 /* used for buffer migration */
86 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
87 /* src addr in bytes */
88 uint64_t src_offset,
89 /* dst addr in bytes */
90 uint64_t dst_offset,
91 /* number of byte to transfer */
92 uint32_t byte_count,
93 bool tmz);
94
95 /* maximum bytes in a single operation */
96 uint32_t fill_max_bytes;
97
98 /* number of dw to reserve per operation */
99 unsigned fill_num_dw;
100
101 /* used for buffer clearing */
102 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
103 /* value to write to memory */
104 uint32_t src_data,
105 /* dst addr in bytes */
106 uint64_t dst_offset,
107 /* number of byte to fill */
108 uint32_t byte_count);
109};
110
111#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
112#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
113
114struct amdgpu_sdma_instance *
115amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
116int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
117uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
118int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
119 void *ras_ih_info);
120void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
121int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
122 void *err_data,
123 struct amdgpu_iv_entry *entry);
124int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
125 struct amdgpu_irq_src *source,
126 struct amdgpu_iv_entry *entry);
127#endif
1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __AMDGPU_SDMA_H__
25#define __AMDGPU_SDMA_H__
26
27/* max number of IP instances */
28#define AMDGPU_MAX_SDMA_INSTANCES 8
29
30enum amdgpu_sdma_irq {
31 AMDGPU_SDMA_IRQ_INSTANCE0 = 0,
32 AMDGPU_SDMA_IRQ_INSTANCE1,
33 AMDGPU_SDMA_IRQ_INSTANCE2,
34 AMDGPU_SDMA_IRQ_INSTANCE3,
35 AMDGPU_SDMA_IRQ_INSTANCE4,
36 AMDGPU_SDMA_IRQ_INSTANCE5,
37 AMDGPU_SDMA_IRQ_INSTANCE6,
38 AMDGPU_SDMA_IRQ_INSTANCE7,
39 AMDGPU_SDMA_IRQ_LAST
40};
41
42struct amdgpu_sdma_instance {
43 /* SDMA firmware */
44 const struct firmware *fw;
45 uint32_t fw_version;
46 uint32_t feature_version;
47
48 struct amdgpu_ring ring;
49 struct amdgpu_ring page;
50 bool burst_nop;
51};
52
53struct amdgpu_sdma_ras_funcs {
54 int (*ras_late_init)(struct amdgpu_device *adev,
55 void *ras_ih_info);
56 void (*ras_fini)(struct amdgpu_device *adev);
57 int (*query_ras_error_count)(struct amdgpu_device *adev,
58 uint32_t instance, void *ras_error_status);
59 void (*reset_ras_error_count)(struct amdgpu_device *adev);
60};
61
62struct amdgpu_sdma {
63 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
64 struct amdgpu_irq_src trap_irq;
65 struct amdgpu_irq_src illegal_inst_irq;
66 struct amdgpu_irq_src ecc_irq;
67 struct amdgpu_irq_src vm_hole_irq;
68 struct amdgpu_irq_src doorbell_invalid_irq;
69 struct amdgpu_irq_src pool_timeout_irq;
70 struct amdgpu_irq_src srbm_write_irq;
71
72 int num_instances;
73 uint32_t srbm_soft_reset;
74 bool has_page_queue;
75 struct ras_common_if *ras_if;
76 const struct amdgpu_sdma_ras_funcs *funcs;
77};
78
79/*
80 * Provided by hw blocks that can move/clear data. e.g., gfx or sdma
81 * But currently, we use sdma to move data.
82 */
83struct amdgpu_buffer_funcs {
84 /* maximum bytes in a single operation */
85 uint32_t copy_max_bytes;
86
87 /* number of dw to reserve per operation */
88 unsigned copy_num_dw;
89
90 /* used for buffer migration */
91 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
92 /* src addr in bytes */
93 uint64_t src_offset,
94 /* dst addr in bytes */
95 uint64_t dst_offset,
96 /* number of byte to transfer */
97 uint32_t byte_count,
98 bool tmz);
99
100 /* maximum bytes in a single operation */
101 uint32_t fill_max_bytes;
102
103 /* number of dw to reserve per operation */
104 unsigned fill_num_dw;
105
106 /* used for buffer clearing */
107 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
108 /* value to write to memory */
109 uint32_t src_data,
110 /* dst addr in bytes */
111 uint64_t dst_offset,
112 /* number of byte to fill */
113 uint32_t byte_count);
114};
115
116#define amdgpu_emit_copy_buffer(adev, ib, s, d, b, t) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b), (t))
117#define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
118
119struct amdgpu_sdma_instance *
120amdgpu_sdma_get_instance_from_ring(struct amdgpu_ring *ring);
121int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
122uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
123int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
124 void *ras_ih_info);
125void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
126int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
127 void *err_data,
128 struct amdgpu_iv_entry *entry);
129int amdgpu_sdma_process_ecc_irq(struct amdgpu_device *adev,
130 struct amdgpu_irq_src *source,
131 struct amdgpu_iv_entry *entry);
132#endif