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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include "amdgpu.h"
30#include <drm/drm_debugfs.h>
31#include <drm/amdgpu_drm.h>
32#include "amdgpu_sched.h"
33#include "amdgpu_uvd.h"
34#include "amdgpu_vce.h"
35#include "atom.h"
36
37#include <linux/vga_switcheroo.h>
38#include <linux/slab.h>
39#include <linux/uaccess.h>
40#include <linux/pci.h>
41#include <linux/pm_runtime.h>
42#include "amdgpu_amdkfd.h"
43#include "amdgpu_gem.h"
44#include "amdgpu_display.h"
45#include "amdgpu_ras.h"
46
47void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
48{
49 struct amdgpu_gpu_instance *gpu_instance;
50 int i;
51
52 mutex_lock(&mgpu_info.mutex);
53
54 for (i = 0; i < mgpu_info.num_gpu; i++) {
55 gpu_instance = &(mgpu_info.gpu_ins[i]);
56 if (gpu_instance->adev == adev) {
57 mgpu_info.gpu_ins[i] =
58 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
59 mgpu_info.num_gpu--;
60 if (adev->flags & AMD_IS_APU)
61 mgpu_info.num_apu--;
62 else
63 mgpu_info.num_dgpu--;
64 break;
65 }
66 }
67
68 mutex_unlock(&mgpu_info.mutex);
69}
70
71/**
72 * amdgpu_driver_unload_kms - Main unload function for KMS.
73 *
74 * @dev: drm dev pointer
75 *
76 * This is the main unload function for KMS (all asics).
77 * Returns 0 on success.
78 */
79void amdgpu_driver_unload_kms(struct drm_device *dev)
80{
81 struct amdgpu_device *adev = dev->dev_private;
82
83 if (adev == NULL)
84 return;
85
86 amdgpu_unregister_gpu_instance(adev);
87
88 if (adev->rmmio == NULL)
89 goto done_free;
90
91 if (adev->runpm) {
92 pm_runtime_get_sync(dev->dev);
93 pm_runtime_forbid(dev->dev);
94 }
95
96 amdgpu_acpi_fini(adev);
97
98 amdgpu_device_fini(adev);
99
100done_free:
101 kfree(adev);
102 dev->dev_private = NULL;
103}
104
105void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
106{
107 struct amdgpu_gpu_instance *gpu_instance;
108
109 mutex_lock(&mgpu_info.mutex);
110
111 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
112 DRM_ERROR("Cannot register more gpu instance\n");
113 mutex_unlock(&mgpu_info.mutex);
114 return;
115 }
116
117 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
118 gpu_instance->adev = adev;
119 gpu_instance->mgpu_fan_enabled = 0;
120
121 mgpu_info.num_gpu++;
122 if (adev->flags & AMD_IS_APU)
123 mgpu_info.num_apu++;
124 else
125 mgpu_info.num_dgpu++;
126
127 mutex_unlock(&mgpu_info.mutex);
128}
129
130/**
131 * amdgpu_driver_load_kms - Main load function for KMS.
132 *
133 * @dev: drm dev pointer
134 * @flags: device flags
135 *
136 * This is the main load function for KMS (all asics).
137 * Returns 0 on success, error on failure.
138 */
139int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags)
140{
141 struct amdgpu_device *adev;
142 int r, acpi_status;
143
144 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL);
145 if (adev == NULL) {
146 return -ENOMEM;
147 }
148 dev->dev_private = (void *)adev;
149
150 if (amdgpu_has_atpx() &&
151 (amdgpu_is_atpx_hybrid() ||
152 amdgpu_has_atpx_dgpu_power_cntl()) &&
153 ((flags & AMD_IS_APU) == 0) &&
154 !pci_is_thunderbolt_attached(dev->pdev))
155 flags |= AMD_IS_PX;
156
157 /* amdgpu_device_init should report only fatal error
158 * like memory allocation failure or iomapping failure,
159 * or memory manager initialization failure, it must
160 * properly initialize the GPU MC controller and permit
161 * VRAM allocation
162 */
163 r = amdgpu_device_init(adev, dev, dev->pdev, flags);
164 if (r) {
165 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
166 goto out;
167 }
168
169 if (amdgpu_device_supports_boco(dev) &&
170 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
171 adev->runpm = true;
172 } else if (amdgpu_device_supports_baco(dev) &&
173 (amdgpu_runtime_pm != 0)) {
174 switch (adev->asic_type) {
175#ifdef CONFIG_DRM_AMDGPU_CIK
176 case CHIP_BONAIRE:
177 case CHIP_HAWAII:
178#endif
179 case CHIP_VEGA20:
180 case CHIP_ARCTURUS:
181 case CHIP_SIENNA_CICHLID:
182 case CHIP_NAVY_FLOUNDER:
183 /* enable runpm if runpm=1 */
184 if (amdgpu_runtime_pm > 0)
185 adev->runpm = true;
186 break;
187 case CHIP_VEGA10:
188 /* turn runpm on if noretry=0 */
189 if (!amdgpu_noretry)
190 adev->runpm = true;
191 break;
192 default:
193 /* enable runpm on VI+ */
194 adev->runpm = true;
195 break;
196 }
197 }
198
199 /* Call ACPI methods: require modeset init
200 * but failure is not fatal
201 */
202
203 acpi_status = amdgpu_acpi_init(adev);
204 if (acpi_status)
205 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
206
207 if (adev->runpm) {
208 /* only need to skip on ATPX */
209 if (amdgpu_device_supports_boco(dev) &&
210 !amdgpu_is_atpx_hybrid())
211 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
212 pm_runtime_use_autosuspend(dev->dev);
213 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
214 pm_runtime_allow(dev->dev);
215 pm_runtime_mark_last_busy(dev->dev);
216 pm_runtime_put_autosuspend(dev->dev);
217 }
218
219out:
220 if (r) {
221 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
222 if (adev->rmmio && adev->runpm)
223 pm_runtime_put_noidle(dev->dev);
224 amdgpu_driver_unload_kms(dev);
225 }
226
227 return r;
228}
229
230static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
231 struct drm_amdgpu_query_fw *query_fw,
232 struct amdgpu_device *adev)
233{
234 switch (query_fw->fw_type) {
235 case AMDGPU_INFO_FW_VCE:
236 fw_info->ver = adev->vce.fw_version;
237 fw_info->feature = adev->vce.fb_version;
238 break;
239 case AMDGPU_INFO_FW_UVD:
240 fw_info->ver = adev->uvd.fw_version;
241 fw_info->feature = 0;
242 break;
243 case AMDGPU_INFO_FW_VCN:
244 fw_info->ver = adev->vcn.fw_version;
245 fw_info->feature = 0;
246 break;
247 case AMDGPU_INFO_FW_GMC:
248 fw_info->ver = adev->gmc.fw_version;
249 fw_info->feature = 0;
250 break;
251 case AMDGPU_INFO_FW_GFX_ME:
252 fw_info->ver = adev->gfx.me_fw_version;
253 fw_info->feature = adev->gfx.me_feature_version;
254 break;
255 case AMDGPU_INFO_FW_GFX_PFP:
256 fw_info->ver = adev->gfx.pfp_fw_version;
257 fw_info->feature = adev->gfx.pfp_feature_version;
258 break;
259 case AMDGPU_INFO_FW_GFX_CE:
260 fw_info->ver = adev->gfx.ce_fw_version;
261 fw_info->feature = adev->gfx.ce_feature_version;
262 break;
263 case AMDGPU_INFO_FW_GFX_RLC:
264 fw_info->ver = adev->gfx.rlc_fw_version;
265 fw_info->feature = adev->gfx.rlc_feature_version;
266 break;
267 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
268 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
269 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
270 break;
271 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
272 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
273 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
274 break;
275 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
276 fw_info->ver = adev->gfx.rlc_srls_fw_version;
277 fw_info->feature = adev->gfx.rlc_srls_feature_version;
278 break;
279 case AMDGPU_INFO_FW_GFX_MEC:
280 if (query_fw->index == 0) {
281 fw_info->ver = adev->gfx.mec_fw_version;
282 fw_info->feature = adev->gfx.mec_feature_version;
283 } else if (query_fw->index == 1) {
284 fw_info->ver = adev->gfx.mec2_fw_version;
285 fw_info->feature = adev->gfx.mec2_feature_version;
286 } else
287 return -EINVAL;
288 break;
289 case AMDGPU_INFO_FW_SMC:
290 fw_info->ver = adev->pm.fw_version;
291 fw_info->feature = 0;
292 break;
293 case AMDGPU_INFO_FW_TA:
294 if (query_fw->index > 1)
295 return -EINVAL;
296 if (query_fw->index == 0) {
297 fw_info->ver = adev->psp.ta_fw_version;
298 fw_info->feature = adev->psp.ta_xgmi_ucode_version;
299 } else {
300 fw_info->ver = adev->psp.ta_fw_version;
301 fw_info->feature = adev->psp.ta_ras_ucode_version;
302 }
303 break;
304 case AMDGPU_INFO_FW_SDMA:
305 if (query_fw->index >= adev->sdma.num_instances)
306 return -EINVAL;
307 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
308 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
309 break;
310 case AMDGPU_INFO_FW_SOS:
311 fw_info->ver = adev->psp.sos_fw_version;
312 fw_info->feature = adev->psp.sos_feature_version;
313 break;
314 case AMDGPU_INFO_FW_ASD:
315 fw_info->ver = adev->psp.asd_fw_version;
316 fw_info->feature = adev->psp.asd_feature_version;
317 break;
318 case AMDGPU_INFO_FW_DMCU:
319 fw_info->ver = adev->dm.dmcu_fw_version;
320 fw_info->feature = 0;
321 break;
322 case AMDGPU_INFO_FW_DMCUB:
323 fw_info->ver = adev->dm.dmcub_fw_version;
324 fw_info->feature = 0;
325 break;
326 default:
327 return -EINVAL;
328 }
329 return 0;
330}
331
332static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
333 struct drm_amdgpu_info *info,
334 struct drm_amdgpu_info_hw_ip *result)
335{
336 uint32_t ib_start_alignment = 0;
337 uint32_t ib_size_alignment = 0;
338 enum amd_ip_block_type type;
339 unsigned int num_rings = 0;
340 unsigned int i, j;
341
342 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
343 return -EINVAL;
344
345 switch (info->query_hw_ip.type) {
346 case AMDGPU_HW_IP_GFX:
347 type = AMD_IP_BLOCK_TYPE_GFX;
348 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
349 if (adev->gfx.gfx_ring[i].sched.ready)
350 ++num_rings;
351 ib_start_alignment = 32;
352 ib_size_alignment = 32;
353 break;
354 case AMDGPU_HW_IP_COMPUTE:
355 type = AMD_IP_BLOCK_TYPE_GFX;
356 for (i = 0; i < adev->gfx.num_compute_rings; i++)
357 if (adev->gfx.compute_ring[i].sched.ready)
358 ++num_rings;
359 ib_start_alignment = 32;
360 ib_size_alignment = 32;
361 break;
362 case AMDGPU_HW_IP_DMA:
363 type = AMD_IP_BLOCK_TYPE_SDMA;
364 for (i = 0; i < adev->sdma.num_instances; i++)
365 if (adev->sdma.instance[i].ring.sched.ready)
366 ++num_rings;
367 ib_start_alignment = 256;
368 ib_size_alignment = 4;
369 break;
370 case AMDGPU_HW_IP_UVD:
371 type = AMD_IP_BLOCK_TYPE_UVD;
372 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
373 if (adev->uvd.harvest_config & (1 << i))
374 continue;
375
376 if (adev->uvd.inst[i].ring.sched.ready)
377 ++num_rings;
378 }
379 ib_start_alignment = 64;
380 ib_size_alignment = 64;
381 break;
382 case AMDGPU_HW_IP_VCE:
383 type = AMD_IP_BLOCK_TYPE_VCE;
384 for (i = 0; i < adev->vce.num_rings; i++)
385 if (adev->vce.ring[i].sched.ready)
386 ++num_rings;
387 ib_start_alignment = 4;
388 ib_size_alignment = 1;
389 break;
390 case AMDGPU_HW_IP_UVD_ENC:
391 type = AMD_IP_BLOCK_TYPE_UVD;
392 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
393 if (adev->uvd.harvest_config & (1 << i))
394 continue;
395
396 for (j = 0; j < adev->uvd.num_enc_rings; j++)
397 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
398 ++num_rings;
399 }
400 ib_start_alignment = 64;
401 ib_size_alignment = 64;
402 break;
403 case AMDGPU_HW_IP_VCN_DEC:
404 type = AMD_IP_BLOCK_TYPE_VCN;
405 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
406 if (adev->uvd.harvest_config & (1 << i))
407 continue;
408
409 if (adev->vcn.inst[i].ring_dec.sched.ready)
410 ++num_rings;
411 }
412 ib_start_alignment = 16;
413 ib_size_alignment = 16;
414 break;
415 case AMDGPU_HW_IP_VCN_ENC:
416 type = AMD_IP_BLOCK_TYPE_VCN;
417 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
418 if (adev->uvd.harvest_config & (1 << i))
419 continue;
420
421 for (j = 0; j < adev->vcn.num_enc_rings; j++)
422 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
423 ++num_rings;
424 }
425 ib_start_alignment = 64;
426 ib_size_alignment = 1;
427 break;
428 case AMDGPU_HW_IP_VCN_JPEG:
429 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
430 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
431
432 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
433 if (adev->jpeg.harvest_config & (1 << i))
434 continue;
435
436 if (adev->jpeg.inst[i].ring_dec.sched.ready)
437 ++num_rings;
438 }
439 ib_start_alignment = 16;
440 ib_size_alignment = 16;
441 break;
442 default:
443 return -EINVAL;
444 }
445
446 for (i = 0; i < adev->num_ip_blocks; i++)
447 if (adev->ip_blocks[i].version->type == type &&
448 adev->ip_blocks[i].status.valid)
449 break;
450
451 if (i == adev->num_ip_blocks)
452 return 0;
453
454 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
455 num_rings);
456
457 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
458 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
459 result->capabilities_flags = 0;
460 result->available_rings = (1 << num_rings) - 1;
461 result->ib_start_alignment = ib_start_alignment;
462 result->ib_size_alignment = ib_size_alignment;
463 return 0;
464}
465
466/*
467 * Userspace get information ioctl
468 */
469/**
470 * amdgpu_info_ioctl - answer a device specific request.
471 *
472 * @adev: amdgpu device pointer
473 * @data: request object
474 * @filp: drm filp
475 *
476 * This function is used to pass device specific parameters to the userspace
477 * drivers. Examples include: pci device id, pipeline parms, tiling params,
478 * etc. (all asics).
479 * Returns 0 on success, -EINVAL on failure.
480 */
481static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
482{
483 struct amdgpu_device *adev = dev->dev_private;
484 struct drm_amdgpu_info *info = data;
485 struct amdgpu_mode_info *minfo = &adev->mode_info;
486 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
487 uint32_t size = info->return_size;
488 struct drm_crtc *crtc;
489 uint32_t ui32 = 0;
490 uint64_t ui64 = 0;
491 int i, found;
492 int ui32_size = sizeof(ui32);
493
494 if (!info->return_size || !info->return_pointer)
495 return -EINVAL;
496
497 switch (info->query) {
498 case AMDGPU_INFO_ACCEL_WORKING:
499 ui32 = adev->accel_working;
500 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
501 case AMDGPU_INFO_CRTC_FROM_ID:
502 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
503 crtc = (struct drm_crtc *)minfo->crtcs[i];
504 if (crtc && crtc->base.id == info->mode_crtc.id) {
505 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
506 ui32 = amdgpu_crtc->crtc_id;
507 found = 1;
508 break;
509 }
510 }
511 if (!found) {
512 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
513 return -EINVAL;
514 }
515 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
516 case AMDGPU_INFO_HW_IP_INFO: {
517 struct drm_amdgpu_info_hw_ip ip = {};
518 int ret;
519
520 ret = amdgpu_hw_ip_info(adev, info, &ip);
521 if (ret)
522 return ret;
523
524 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
525 return ret ? -EFAULT : 0;
526 }
527 case AMDGPU_INFO_HW_IP_COUNT: {
528 enum amd_ip_block_type type;
529 uint32_t count = 0;
530
531 switch (info->query_hw_ip.type) {
532 case AMDGPU_HW_IP_GFX:
533 type = AMD_IP_BLOCK_TYPE_GFX;
534 break;
535 case AMDGPU_HW_IP_COMPUTE:
536 type = AMD_IP_BLOCK_TYPE_GFX;
537 break;
538 case AMDGPU_HW_IP_DMA:
539 type = AMD_IP_BLOCK_TYPE_SDMA;
540 break;
541 case AMDGPU_HW_IP_UVD:
542 type = AMD_IP_BLOCK_TYPE_UVD;
543 break;
544 case AMDGPU_HW_IP_VCE:
545 type = AMD_IP_BLOCK_TYPE_VCE;
546 break;
547 case AMDGPU_HW_IP_UVD_ENC:
548 type = AMD_IP_BLOCK_TYPE_UVD;
549 break;
550 case AMDGPU_HW_IP_VCN_DEC:
551 case AMDGPU_HW_IP_VCN_ENC:
552 type = AMD_IP_BLOCK_TYPE_VCN;
553 break;
554 case AMDGPU_HW_IP_VCN_JPEG:
555 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
556 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
557 break;
558 default:
559 return -EINVAL;
560 }
561
562 for (i = 0; i < adev->num_ip_blocks; i++)
563 if (adev->ip_blocks[i].version->type == type &&
564 adev->ip_blocks[i].status.valid &&
565 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
566 count++;
567
568 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
569 }
570 case AMDGPU_INFO_TIMESTAMP:
571 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
572 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
573 case AMDGPU_INFO_FW_VERSION: {
574 struct drm_amdgpu_info_firmware fw_info;
575 int ret;
576
577 /* We only support one instance of each IP block right now. */
578 if (info->query_fw.ip_instance != 0)
579 return -EINVAL;
580
581 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
582 if (ret)
583 return ret;
584
585 return copy_to_user(out, &fw_info,
586 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
587 }
588 case AMDGPU_INFO_NUM_BYTES_MOVED:
589 ui64 = atomic64_read(&adev->num_bytes_moved);
590 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
591 case AMDGPU_INFO_NUM_EVICTIONS:
592 ui64 = atomic64_read(&adev->num_evictions);
593 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
594 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
595 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
596 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
597 case AMDGPU_INFO_VRAM_USAGE:
598 ui64 = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
599 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
600 case AMDGPU_INFO_VIS_VRAM_USAGE:
601 ui64 = amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
602 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
603 case AMDGPU_INFO_GTT_USAGE:
604 ui64 = amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
605 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
606 case AMDGPU_INFO_GDS_CONFIG: {
607 struct drm_amdgpu_info_gds gds_info;
608
609 memset(&gds_info, 0, sizeof(gds_info));
610 gds_info.compute_partition_size = adev->gds.gds_size;
611 gds_info.gds_total_size = adev->gds.gds_size;
612 gds_info.gws_per_compute_partition = adev->gds.gws_size;
613 gds_info.oa_per_compute_partition = adev->gds.oa_size;
614 return copy_to_user(out, &gds_info,
615 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
616 }
617 case AMDGPU_INFO_VRAM_GTT: {
618 struct drm_amdgpu_info_vram_gtt vram_gtt;
619
620 vram_gtt.vram_size = adev->gmc.real_vram_size -
621 atomic64_read(&adev->vram_pin_size) -
622 AMDGPU_VM_RESERVED_VRAM;
623 vram_gtt.vram_cpu_accessible_size =
624 min(adev->gmc.visible_vram_size -
625 atomic64_read(&adev->visible_pin_size),
626 vram_gtt.vram_size);
627 vram_gtt.gtt_size = adev->mman.bdev.man[TTM_PL_TT].size;
628 vram_gtt.gtt_size *= PAGE_SIZE;
629 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
630 return copy_to_user(out, &vram_gtt,
631 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
632 }
633 case AMDGPU_INFO_MEMORY: {
634 struct drm_amdgpu_memory_info mem;
635
636 memset(&mem, 0, sizeof(mem));
637 mem.vram.total_heap_size = adev->gmc.real_vram_size;
638 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
639 atomic64_read(&adev->vram_pin_size) -
640 AMDGPU_VM_RESERVED_VRAM;
641 mem.vram.heap_usage =
642 amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
643 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
644
645 mem.cpu_accessible_vram.total_heap_size =
646 adev->gmc.visible_vram_size;
647 mem.cpu_accessible_vram.usable_heap_size =
648 min(adev->gmc.visible_vram_size -
649 atomic64_read(&adev->visible_pin_size),
650 mem.vram.usable_heap_size);
651 mem.cpu_accessible_vram.heap_usage =
652 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
653 mem.cpu_accessible_vram.max_allocation =
654 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
655
656 mem.gtt.total_heap_size = adev->mman.bdev.man[TTM_PL_TT].size;
657 mem.gtt.total_heap_size *= PAGE_SIZE;
658 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
659 atomic64_read(&adev->gart_pin_size);
660 mem.gtt.heap_usage =
661 amdgpu_gtt_mgr_usage(&adev->mman.bdev.man[TTM_PL_TT]);
662 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
663
664 return copy_to_user(out, &mem,
665 min((size_t)size, sizeof(mem)))
666 ? -EFAULT : 0;
667 }
668 case AMDGPU_INFO_READ_MMR_REG: {
669 unsigned n, alloc_size;
670 uint32_t *regs;
671 unsigned se_num = (info->read_mmr_reg.instance >>
672 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
673 AMDGPU_INFO_MMR_SE_INDEX_MASK;
674 unsigned sh_num = (info->read_mmr_reg.instance >>
675 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
676 AMDGPU_INFO_MMR_SH_INDEX_MASK;
677
678 /* set full masks if the userspace set all bits
679 * in the bitfields */
680 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
681 se_num = 0xffffffff;
682 else if (se_num >= AMDGPU_GFX_MAX_SE)
683 return -EINVAL;
684 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
685 sh_num = 0xffffffff;
686 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
687 return -EINVAL;
688
689 if (info->read_mmr_reg.count > 128)
690 return -EINVAL;
691
692 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
693 if (!regs)
694 return -ENOMEM;
695 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
696
697 amdgpu_gfx_off_ctrl(adev, false);
698 for (i = 0; i < info->read_mmr_reg.count; i++) {
699 if (amdgpu_asic_read_register(adev, se_num, sh_num,
700 info->read_mmr_reg.dword_offset + i,
701 ®s[i])) {
702 DRM_DEBUG_KMS("unallowed offset %#x\n",
703 info->read_mmr_reg.dword_offset + i);
704 kfree(regs);
705 amdgpu_gfx_off_ctrl(adev, true);
706 return -EFAULT;
707 }
708 }
709 amdgpu_gfx_off_ctrl(adev, true);
710 n = copy_to_user(out, regs, min(size, alloc_size));
711 kfree(regs);
712 return n ? -EFAULT : 0;
713 }
714 case AMDGPU_INFO_DEV_INFO: {
715 struct drm_amdgpu_info_device dev_info;
716 uint64_t vm_size;
717
718 memset(&dev_info, 0, sizeof(dev_info));
719 dev_info.device_id = dev->pdev->device;
720 dev_info.chip_rev = adev->rev_id;
721 dev_info.external_rev = adev->external_rev_id;
722 dev_info.pci_rev = dev->pdev->revision;
723 dev_info.family = adev->family;
724 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines;
725 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
726 /* return all clocks in KHz */
727 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
728 if (adev->pm.dpm_enabled) {
729 dev_info.max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
730 dev_info.max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
731 } else {
732 dev_info.max_engine_clock = adev->clock.default_sclk * 10;
733 dev_info.max_memory_clock = adev->clock.default_mclk * 10;
734 }
735 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
736 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se *
737 adev->gfx.config.max_shader_engines;
738 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
739 dev_info._pad = 0;
740 dev_info.ids_flags = 0;
741 if (adev->flags & AMD_IS_APU)
742 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
743 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
744 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
745
746 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
747 vm_size -= AMDGPU_VA_RESERVED_SIZE;
748
749 /* Older VCE FW versions are buggy and can handle only 40bits */
750 if (adev->vce.fw_version &&
751 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
752 vm_size = min(vm_size, 1ULL << 40);
753
754 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
755 dev_info.virtual_address_max =
756 min(vm_size, AMDGPU_GMC_HOLE_START);
757
758 if (vm_size > AMDGPU_GMC_HOLE_START) {
759 dev_info.high_va_offset = AMDGPU_GMC_HOLE_END;
760 dev_info.high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
761 }
762 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
763 dev_info.pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
764 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE;
765 dev_info.cu_active_number = adev->gfx.cu_info.number;
766 dev_info.cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
767 dev_info.ce_ram_size = adev->gfx.ce_ram_size;
768 memcpy(&dev_info.cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
769 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
770 memcpy(&dev_info.cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
771 sizeof(adev->gfx.cu_info.bitmap));
772 dev_info.vram_type = adev->gmc.vram_type;
773 dev_info.vram_bit_width = adev->gmc.vram_width;
774 dev_info.vce_harvest_config = adev->vce.harvest_config;
775 dev_info.gc_double_offchip_lds_buf =
776 adev->gfx.config.double_offchip_lds_buf;
777 dev_info.wave_front_size = adev->gfx.cu_info.wave_front_size;
778 dev_info.num_shader_visible_vgprs = adev->gfx.config.max_gprs;
779 dev_info.num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
780 dev_info.num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
781 dev_info.gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
782 dev_info.gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
783 dev_info.max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
784
785 if (adev->family >= AMDGPU_FAMILY_NV)
786 dev_info.pa_sc_tile_steering_override =
787 adev->gfx.config.pa_sc_tile_steering_override;
788
789 dev_info.tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
790
791 return copy_to_user(out, &dev_info,
792 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0;
793 }
794 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
795 unsigned i;
796 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
797 struct amd_vce_state *vce_state;
798
799 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
800 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
801 if (vce_state) {
802 vce_clk_table.entries[i].sclk = vce_state->sclk;
803 vce_clk_table.entries[i].mclk = vce_state->mclk;
804 vce_clk_table.entries[i].eclk = vce_state->evclk;
805 vce_clk_table.num_valid_entries++;
806 }
807 }
808
809 return copy_to_user(out, &vce_clk_table,
810 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
811 }
812 case AMDGPU_INFO_VBIOS: {
813 uint32_t bios_size = adev->bios_size;
814
815 switch (info->vbios_info.type) {
816 case AMDGPU_INFO_VBIOS_SIZE:
817 return copy_to_user(out, &bios_size,
818 min((size_t)size, sizeof(bios_size)))
819 ? -EFAULT : 0;
820 case AMDGPU_INFO_VBIOS_IMAGE: {
821 uint8_t *bios;
822 uint32_t bios_offset = info->vbios_info.offset;
823
824 if (bios_offset >= bios_size)
825 return -EINVAL;
826
827 bios = adev->bios + bios_offset;
828 return copy_to_user(out, bios,
829 min((size_t)size, (size_t)(bios_size - bios_offset)))
830 ? -EFAULT : 0;
831 }
832 default:
833 DRM_DEBUG_KMS("Invalid request %d\n",
834 info->vbios_info.type);
835 return -EINVAL;
836 }
837 }
838 case AMDGPU_INFO_NUM_HANDLES: {
839 struct drm_amdgpu_info_num_handles handle;
840
841 switch (info->query_hw_ip.type) {
842 case AMDGPU_HW_IP_UVD:
843 /* Starting Polaris, we support unlimited UVD handles */
844 if (adev->asic_type < CHIP_POLARIS10) {
845 handle.uvd_max_handles = adev->uvd.max_handles;
846 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
847
848 return copy_to_user(out, &handle,
849 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
850 } else {
851 return -ENODATA;
852 }
853
854 break;
855 default:
856 return -EINVAL;
857 }
858 }
859 case AMDGPU_INFO_SENSOR: {
860 if (!adev->pm.dpm_enabled)
861 return -ENOENT;
862
863 switch (info->sensor_info.type) {
864 case AMDGPU_INFO_SENSOR_GFX_SCLK:
865 /* get sclk in Mhz */
866 if (amdgpu_dpm_read_sensor(adev,
867 AMDGPU_PP_SENSOR_GFX_SCLK,
868 (void *)&ui32, &ui32_size)) {
869 return -EINVAL;
870 }
871 ui32 /= 100;
872 break;
873 case AMDGPU_INFO_SENSOR_GFX_MCLK:
874 /* get mclk in Mhz */
875 if (amdgpu_dpm_read_sensor(adev,
876 AMDGPU_PP_SENSOR_GFX_MCLK,
877 (void *)&ui32, &ui32_size)) {
878 return -EINVAL;
879 }
880 ui32 /= 100;
881 break;
882 case AMDGPU_INFO_SENSOR_GPU_TEMP:
883 /* get temperature in millidegrees C */
884 if (amdgpu_dpm_read_sensor(adev,
885 AMDGPU_PP_SENSOR_GPU_TEMP,
886 (void *)&ui32, &ui32_size)) {
887 return -EINVAL;
888 }
889 break;
890 case AMDGPU_INFO_SENSOR_GPU_LOAD:
891 /* get GPU load */
892 if (amdgpu_dpm_read_sensor(adev,
893 AMDGPU_PP_SENSOR_GPU_LOAD,
894 (void *)&ui32, &ui32_size)) {
895 return -EINVAL;
896 }
897 break;
898 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
899 /* get average GPU power */
900 if (amdgpu_dpm_read_sensor(adev,
901 AMDGPU_PP_SENSOR_GPU_POWER,
902 (void *)&ui32, &ui32_size)) {
903 return -EINVAL;
904 }
905 ui32 >>= 8;
906 break;
907 case AMDGPU_INFO_SENSOR_VDDNB:
908 /* get VDDNB in millivolts */
909 if (amdgpu_dpm_read_sensor(adev,
910 AMDGPU_PP_SENSOR_VDDNB,
911 (void *)&ui32, &ui32_size)) {
912 return -EINVAL;
913 }
914 break;
915 case AMDGPU_INFO_SENSOR_VDDGFX:
916 /* get VDDGFX in millivolts */
917 if (amdgpu_dpm_read_sensor(adev,
918 AMDGPU_PP_SENSOR_VDDGFX,
919 (void *)&ui32, &ui32_size)) {
920 return -EINVAL;
921 }
922 break;
923 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
924 /* get stable pstate sclk in Mhz */
925 if (amdgpu_dpm_read_sensor(adev,
926 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
927 (void *)&ui32, &ui32_size)) {
928 return -EINVAL;
929 }
930 ui32 /= 100;
931 break;
932 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
933 /* get stable pstate mclk in Mhz */
934 if (amdgpu_dpm_read_sensor(adev,
935 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
936 (void *)&ui32, &ui32_size)) {
937 return -EINVAL;
938 }
939 ui32 /= 100;
940 break;
941 default:
942 DRM_DEBUG_KMS("Invalid request %d\n",
943 info->sensor_info.type);
944 return -EINVAL;
945 }
946 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
947 }
948 case AMDGPU_INFO_VRAM_LOST_COUNTER:
949 ui32 = atomic_read(&adev->vram_lost_counter);
950 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
951 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
952 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
953 uint64_t ras_mask;
954
955 if (!ras)
956 return -EINVAL;
957 ras_mask = (uint64_t)ras->supported << 32 | ras->features;
958
959 return copy_to_user(out, &ras_mask,
960 min_t(u64, size, sizeof(ras_mask))) ?
961 -EFAULT : 0;
962 }
963 default:
964 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
965 return -EINVAL;
966 }
967 return 0;
968}
969
970
971/*
972 * Outdated mess for old drm with Xorg being in charge (void function now).
973 */
974/**
975 * amdgpu_driver_lastclose_kms - drm callback for last close
976 *
977 * @dev: drm dev pointer
978 *
979 * Switch vga_switcheroo state after last close (all asics).
980 */
981void amdgpu_driver_lastclose_kms(struct drm_device *dev)
982{
983 drm_fb_helper_lastclose(dev);
984 vga_switcheroo_process_delayed_switch();
985}
986
987/**
988 * amdgpu_driver_open_kms - drm callback for open
989 *
990 * @dev: drm dev pointer
991 * @file_priv: drm file
992 *
993 * On device open, init vm on cayman+ (all asics).
994 * Returns 0 on success, error on failure.
995 */
996int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
997{
998 struct amdgpu_device *adev = dev->dev_private;
999 struct amdgpu_fpriv *fpriv;
1000 int r, pasid;
1001
1002 /* Ensure IB tests are run on ring */
1003 flush_delayed_work(&adev->delayed_init_work);
1004
1005
1006 if (amdgpu_ras_intr_triggered()) {
1007 DRM_ERROR("RAS Intr triggered, device disabled!!");
1008 return -EHWPOISON;
1009 }
1010
1011 file_priv->driver_priv = NULL;
1012
1013 r = pm_runtime_get_sync(dev->dev);
1014 if (r < 0)
1015 goto pm_put;
1016
1017 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1018 if (unlikely(!fpriv)) {
1019 r = -ENOMEM;
1020 goto out_suspend;
1021 }
1022
1023 pasid = amdgpu_pasid_alloc(16);
1024 if (pasid < 0) {
1025 dev_warn(adev->dev, "No more PASIDs available!");
1026 pasid = 0;
1027 }
1028 r = amdgpu_vm_init(adev, &fpriv->vm, AMDGPU_VM_CONTEXT_GFX, pasid);
1029 if (r)
1030 goto error_pasid;
1031
1032 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1033 if (!fpriv->prt_va) {
1034 r = -ENOMEM;
1035 goto error_vm;
1036 }
1037
1038 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1039 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1040
1041 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1042 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1043 if (r)
1044 goto error_vm;
1045 }
1046
1047 mutex_init(&fpriv->bo_list_lock);
1048 idr_init(&fpriv->bo_list_handles);
1049
1050 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1051
1052 file_priv->driver_priv = fpriv;
1053 goto out_suspend;
1054
1055error_vm:
1056 amdgpu_vm_fini(adev, &fpriv->vm);
1057
1058error_pasid:
1059 if (pasid)
1060 amdgpu_pasid_free(pasid);
1061
1062 kfree(fpriv);
1063
1064out_suspend:
1065 pm_runtime_mark_last_busy(dev->dev);
1066pm_put:
1067 pm_runtime_put_autosuspend(dev->dev);
1068
1069 return r;
1070}
1071
1072/**
1073 * amdgpu_driver_postclose_kms - drm callback for post close
1074 *
1075 * @dev: drm dev pointer
1076 * @file_priv: drm file
1077 *
1078 * On device post close, tear down vm on cayman+ (all asics).
1079 */
1080void amdgpu_driver_postclose_kms(struct drm_device *dev,
1081 struct drm_file *file_priv)
1082{
1083 struct amdgpu_device *adev = dev->dev_private;
1084 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1085 struct amdgpu_bo_list *list;
1086 struct amdgpu_bo *pd;
1087 unsigned int pasid;
1088 int handle;
1089
1090 if (!fpriv)
1091 return;
1092
1093 pm_runtime_get_sync(dev->dev);
1094
1095 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1096 amdgpu_uvd_free_handles(adev, file_priv);
1097 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1098 amdgpu_vce_free_handles(adev, file_priv);
1099
1100 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1101
1102 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1103 /* TODO: how to handle reserve failure */
1104 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1105 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1106 fpriv->csa_va = NULL;
1107 amdgpu_bo_unreserve(adev->virt.csa_obj);
1108 }
1109
1110 pasid = fpriv->vm.pasid;
1111 pd = amdgpu_bo_ref(fpriv->vm.root.base.bo);
1112
1113 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1114 amdgpu_vm_fini(adev, &fpriv->vm);
1115
1116 if (pasid)
1117 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1118 amdgpu_bo_unref(&pd);
1119
1120 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1121 amdgpu_bo_list_put(list);
1122
1123 idr_destroy(&fpriv->bo_list_handles);
1124 mutex_destroy(&fpriv->bo_list_lock);
1125
1126 kfree(fpriv);
1127 file_priv->driver_priv = NULL;
1128
1129 pm_runtime_mark_last_busy(dev->dev);
1130 pm_runtime_put_autosuspend(dev->dev);
1131}
1132
1133/*
1134 * VBlank related functions.
1135 */
1136/**
1137 * amdgpu_get_vblank_counter_kms - get frame count
1138 *
1139 * @crtc: crtc to get the frame count from
1140 *
1141 * Gets the frame count on the requested crtc (all asics).
1142 * Returns frame count on success, -EINVAL on failure.
1143 */
1144u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1145{
1146 struct drm_device *dev = crtc->dev;
1147 unsigned int pipe = crtc->index;
1148 struct amdgpu_device *adev = dev->dev_private;
1149 int vpos, hpos, stat;
1150 u32 count;
1151
1152 if (pipe >= adev->mode_info.num_crtc) {
1153 DRM_ERROR("Invalid crtc %u\n", pipe);
1154 return -EINVAL;
1155 }
1156
1157 /* The hw increments its frame counter at start of vsync, not at start
1158 * of vblank, as is required by DRM core vblank counter handling.
1159 * Cook the hw count here to make it appear to the caller as if it
1160 * incremented at start of vblank. We measure distance to start of
1161 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1162 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1163 * result by 1 to give the proper appearance to caller.
1164 */
1165 if (adev->mode_info.crtcs[pipe]) {
1166 /* Repeat readout if needed to provide stable result if
1167 * we cross start of vsync during the queries.
1168 */
1169 do {
1170 count = amdgpu_display_vblank_get_counter(adev, pipe);
1171 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1172 * vpos as distance to start of vblank, instead of
1173 * regular vertical scanout pos.
1174 */
1175 stat = amdgpu_display_get_crtc_scanoutpos(
1176 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1177 &vpos, &hpos, NULL, NULL,
1178 &adev->mode_info.crtcs[pipe]->base.hwmode);
1179 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1180
1181 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1182 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1183 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1184 } else {
1185 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1186 pipe, vpos);
1187
1188 /* Bump counter if we are at >= leading edge of vblank,
1189 * but before vsync where vpos would turn negative and
1190 * the hw counter really increments.
1191 */
1192 if (vpos >= 0)
1193 count++;
1194 }
1195 } else {
1196 /* Fallback to use value as is. */
1197 count = amdgpu_display_vblank_get_counter(adev, pipe);
1198 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1199 }
1200
1201 return count;
1202}
1203
1204/**
1205 * amdgpu_enable_vblank_kms - enable vblank interrupt
1206 *
1207 * @crtc: crtc to enable vblank interrupt for
1208 *
1209 * Enable the interrupt on the requested crtc (all asics).
1210 * Returns 0 on success, -EINVAL on failure.
1211 */
1212int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1213{
1214 struct drm_device *dev = crtc->dev;
1215 unsigned int pipe = crtc->index;
1216 struct amdgpu_device *adev = dev->dev_private;
1217 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1218
1219 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1220}
1221
1222/**
1223 * amdgpu_disable_vblank_kms - disable vblank interrupt
1224 *
1225 * @crtc: crtc to disable vblank interrupt for
1226 *
1227 * Disable the interrupt on the requested crtc (all asics).
1228 */
1229void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1230{
1231 struct drm_device *dev = crtc->dev;
1232 unsigned int pipe = crtc->index;
1233 struct amdgpu_device *adev = dev->dev_private;
1234 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1235
1236 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1237}
1238
1239const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1240 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1241 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1242 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1243 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1244 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1245 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1246 /* KMS */
1247 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1248 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1249 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1250 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1251 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1252 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1253 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1254 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1255 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1256 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW)
1257};
1258const int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms);
1259
1260/*
1261 * Debugfs info
1262 */
1263#if defined(CONFIG_DEBUG_FS)
1264
1265static int amdgpu_debugfs_firmware_info(struct seq_file *m, void *data)
1266{
1267 struct drm_info_node *node = (struct drm_info_node *) m->private;
1268 struct drm_device *dev = node->minor->dev;
1269 struct amdgpu_device *adev = dev->dev_private;
1270 struct drm_amdgpu_info_firmware fw_info;
1271 struct drm_amdgpu_query_fw query_fw;
1272 struct atom_context *ctx = adev->mode_info.atom_context;
1273 int ret, i;
1274
1275 /* VCE */
1276 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1277 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1278 if (ret)
1279 return ret;
1280 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1281 fw_info.feature, fw_info.ver);
1282
1283 /* UVD */
1284 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1285 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1286 if (ret)
1287 return ret;
1288 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1289 fw_info.feature, fw_info.ver);
1290
1291 /* GMC */
1292 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1293 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1294 if (ret)
1295 return ret;
1296 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1297 fw_info.feature, fw_info.ver);
1298
1299 /* ME */
1300 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1301 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1302 if (ret)
1303 return ret;
1304 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1305 fw_info.feature, fw_info.ver);
1306
1307 /* PFP */
1308 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1309 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1310 if (ret)
1311 return ret;
1312 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1313 fw_info.feature, fw_info.ver);
1314
1315 /* CE */
1316 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1317 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1318 if (ret)
1319 return ret;
1320 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1321 fw_info.feature, fw_info.ver);
1322
1323 /* RLC */
1324 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1325 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1326 if (ret)
1327 return ret;
1328 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1329 fw_info.feature, fw_info.ver);
1330
1331 /* RLC SAVE RESTORE LIST CNTL */
1332 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1333 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1334 if (ret)
1335 return ret;
1336 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1337 fw_info.feature, fw_info.ver);
1338
1339 /* RLC SAVE RESTORE LIST GPM MEM */
1340 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1341 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1342 if (ret)
1343 return ret;
1344 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1345 fw_info.feature, fw_info.ver);
1346
1347 /* RLC SAVE RESTORE LIST SRM MEM */
1348 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1349 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1350 if (ret)
1351 return ret;
1352 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1353 fw_info.feature, fw_info.ver);
1354
1355 /* MEC */
1356 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1357 query_fw.index = 0;
1358 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1359 if (ret)
1360 return ret;
1361 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1362 fw_info.feature, fw_info.ver);
1363
1364 /* MEC2 */
1365 if (adev->gfx.mec2_fw) {
1366 query_fw.index = 1;
1367 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1368 if (ret)
1369 return ret;
1370 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1371 fw_info.feature, fw_info.ver);
1372 }
1373
1374 /* PSP SOS */
1375 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1376 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1377 if (ret)
1378 return ret;
1379 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1380 fw_info.feature, fw_info.ver);
1381
1382
1383 /* PSP ASD */
1384 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1385 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1386 if (ret)
1387 return ret;
1388 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1389 fw_info.feature, fw_info.ver);
1390
1391 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1392 for (i = 0; i < 2; i++) {
1393 query_fw.index = i;
1394 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1395 if (ret)
1396 continue;
1397 seq_printf(m, "TA %s feature version: %u, firmware version: 0x%08x\n",
1398 i ? "RAS" : "XGMI", fw_info.feature, fw_info.ver);
1399 }
1400
1401 /* SMC */
1402 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1403 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1404 if (ret)
1405 return ret;
1406 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1407 fw_info.feature, fw_info.ver);
1408
1409 /* SDMA */
1410 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1411 for (i = 0; i < adev->sdma.num_instances; i++) {
1412 query_fw.index = i;
1413 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1414 if (ret)
1415 return ret;
1416 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1417 i, fw_info.feature, fw_info.ver);
1418 }
1419
1420 /* VCN */
1421 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1422 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1423 if (ret)
1424 return ret;
1425 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1426 fw_info.feature, fw_info.ver);
1427
1428 /* DMCU */
1429 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1430 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1431 if (ret)
1432 return ret;
1433 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1434 fw_info.feature, fw_info.ver);
1435
1436 /* DMCUB */
1437 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1438 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1439 if (ret)
1440 return ret;
1441 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1442 fw_info.feature, fw_info.ver);
1443
1444
1445 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1446
1447 return 0;
1448}
1449
1450static const struct drm_info_list amdgpu_firmware_info_list[] = {
1451 {"amdgpu_firmware_info", amdgpu_debugfs_firmware_info, 0, NULL},
1452};
1453#endif
1454
1455int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1456{
1457#if defined(CONFIG_DEBUG_FS)
1458 return amdgpu_debugfs_add_files(adev, amdgpu_firmware_info_list,
1459 ARRAY_SIZE(amdgpu_firmware_info_list));
1460#else
1461 return 0;
1462#endif
1463}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include <drm/drm_drv.h>
32#include "amdgpu_uvd.h"
33#include "amdgpu_vce.h"
34#include "atom.h"
35
36#include <linux/vga_switcheroo.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39#include <linux/pci.h>
40#include <linux/pm_runtime.h>
41#include "amdgpu_amdkfd.h"
42#include "amdgpu_gem.h"
43#include "amdgpu_display.h"
44#include "amdgpu_ras.h"
45
46void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
47{
48 struct amdgpu_gpu_instance *gpu_instance;
49 int i;
50
51 mutex_lock(&mgpu_info.mutex);
52
53 for (i = 0; i < mgpu_info.num_gpu; i++) {
54 gpu_instance = &(mgpu_info.gpu_ins[i]);
55 if (gpu_instance->adev == adev) {
56 mgpu_info.gpu_ins[i] =
57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
58 mgpu_info.num_gpu--;
59 if (adev->flags & AMD_IS_APU)
60 mgpu_info.num_apu--;
61 else
62 mgpu_info.num_dgpu--;
63 break;
64 }
65 }
66
67 mutex_unlock(&mgpu_info.mutex);
68}
69
70/**
71 * amdgpu_driver_unload_kms - Main unload function for KMS.
72 *
73 * @dev: drm dev pointer
74 *
75 * This is the main unload function for KMS (all asics).
76 * Returns 0 on success.
77 */
78void amdgpu_driver_unload_kms(struct drm_device *dev)
79{
80 struct amdgpu_device *adev = drm_to_adev(dev);
81
82 if (adev == NULL)
83 return;
84
85 amdgpu_unregister_gpu_instance(adev);
86
87 if (adev->rmmio == NULL)
88 return;
89
90 if (adev->runpm) {
91 pm_runtime_get_sync(dev->dev);
92 pm_runtime_forbid(dev->dev);
93 }
94
95 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
96 DRM_WARN("smart shift update failed\n");
97
98 amdgpu_acpi_fini(adev);
99 amdgpu_device_fini_hw(adev);
100}
101
102void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
103{
104 struct amdgpu_gpu_instance *gpu_instance;
105
106 mutex_lock(&mgpu_info.mutex);
107
108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
109 DRM_ERROR("Cannot register more gpu instance\n");
110 mutex_unlock(&mgpu_info.mutex);
111 return;
112 }
113
114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
115 gpu_instance->adev = adev;
116 gpu_instance->mgpu_fan_enabled = 0;
117
118 mgpu_info.num_gpu++;
119 if (adev->flags & AMD_IS_APU)
120 mgpu_info.num_apu++;
121 else
122 mgpu_info.num_dgpu++;
123
124 mutex_unlock(&mgpu_info.mutex);
125}
126
127static void amdgpu_get_audio_func(struct amdgpu_device *adev)
128{
129 struct pci_dev *p = NULL;
130
131 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
132 adev->pdev->bus->number, 1);
133 if (p) {
134 pm_runtime_get_sync(&p->dev);
135
136 pm_runtime_mark_last_busy(&p->dev);
137 pm_runtime_put_autosuspend(&p->dev);
138
139 pci_dev_put(p);
140 }
141}
142
143/**
144 * amdgpu_driver_load_kms - Main load function for KMS.
145 *
146 * @adev: pointer to struct amdgpu_device
147 * @flags: device flags
148 *
149 * This is the main load function for KMS (all asics).
150 * Returns 0 on success, error on failure.
151 */
152int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
153{
154 struct drm_device *dev;
155 struct pci_dev *parent;
156 int r, acpi_status;
157
158 dev = adev_to_drm(adev);
159
160 if (amdgpu_has_atpx() &&
161 (amdgpu_is_atpx_hybrid() ||
162 amdgpu_has_atpx_dgpu_power_cntl()) &&
163 ((flags & AMD_IS_APU) == 0) &&
164 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
165 flags |= AMD_IS_PX;
166
167 parent = pci_upstream_bridge(adev->pdev);
168 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
169
170 /* amdgpu_device_init should report only fatal error
171 * like memory allocation failure or iomapping failure,
172 * or memory manager initialization failure, it must
173 * properly initialize the GPU MC controller and permit
174 * VRAM allocation
175 */
176 r = amdgpu_device_init(adev, flags);
177 if (r) {
178 dev_err(dev->dev, "Fatal error during GPU init\n");
179 goto out;
180 }
181
182 if (amdgpu_device_supports_px(dev) &&
183 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for atpx */
184 adev->runpm = true;
185 dev_info(adev->dev, "Using ATPX for runtime pm\n");
186 } else if (amdgpu_device_supports_boco(dev) &&
187 (amdgpu_runtime_pm != 0)) { /* enable runpm by default for boco */
188 adev->runpm = true;
189 dev_info(adev->dev, "Using BOCO for runtime pm\n");
190 } else if (amdgpu_device_supports_baco(dev) &&
191 (amdgpu_runtime_pm != 0)) {
192 switch (adev->asic_type) {
193 case CHIP_VEGA20:
194 case CHIP_ARCTURUS:
195 /* enable runpm if runpm=1 */
196 if (amdgpu_runtime_pm > 0)
197 adev->runpm = true;
198 break;
199 case CHIP_VEGA10:
200 /* turn runpm on if noretry=0 */
201 if (!adev->gmc.noretry)
202 adev->runpm = true;
203 break;
204 default:
205 /* enable runpm on CI+ */
206 adev->runpm = true;
207 break;
208 }
209 if (adev->runpm)
210 dev_info(adev->dev, "Using BACO for runtime pm\n");
211 }
212
213 /* Call ACPI methods: require modeset init
214 * but failure is not fatal
215 */
216
217 acpi_status = amdgpu_acpi_init(adev);
218 if (acpi_status)
219 dev_dbg(dev->dev, "Error during ACPI methods call\n");
220
221 if (adev->runpm) {
222 /* only need to skip on ATPX */
223 if (amdgpu_device_supports_px(dev))
224 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
225 /* we want direct complete for BOCO */
226 if (amdgpu_device_supports_boco(dev))
227 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
228 DPM_FLAG_SMART_SUSPEND |
229 DPM_FLAG_MAY_SKIP_RESUME);
230 pm_runtime_use_autosuspend(dev->dev);
231 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
232
233 pm_runtime_allow(dev->dev);
234
235 pm_runtime_mark_last_busy(dev->dev);
236 pm_runtime_put_autosuspend(dev->dev);
237
238 /*
239 * For runpm implemented via BACO, PMFW will handle the
240 * timing for BACO in and out:
241 * - put ASIC into BACO state only when both video and
242 * audio functions are in D3 state.
243 * - pull ASIC out of BACO state when either video or
244 * audio function is in D0 state.
245 * Also, at startup, PMFW assumes both functions are in
246 * D0 state.
247 *
248 * So if snd driver was loaded prior to amdgpu driver
249 * and audio function was put into D3 state, there will
250 * be no PMFW-aware D-state transition(D0->D3) on runpm
251 * suspend. Thus the BACO will be not correctly kicked in.
252 *
253 * Via amdgpu_get_audio_func(), the audio dev is put
254 * into D0 state. Then there will be a PMFW-aware D-state
255 * transition(D0->D3) on runpm suspend.
256 */
257 if (amdgpu_device_supports_baco(dev) &&
258 !(adev->flags & AMD_IS_APU) &&
259 (adev->asic_type >= CHIP_NAVI10))
260 amdgpu_get_audio_func(adev);
261 }
262
263 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
264 DRM_WARN("smart shift update failed\n");
265
266out:
267 if (r) {
268 /* balance pm_runtime_get_sync in amdgpu_driver_unload_kms */
269 if (adev->rmmio && adev->runpm)
270 pm_runtime_put_noidle(dev->dev);
271 amdgpu_driver_unload_kms(dev);
272 }
273
274 return r;
275}
276
277static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
278 struct drm_amdgpu_query_fw *query_fw,
279 struct amdgpu_device *adev)
280{
281 switch (query_fw->fw_type) {
282 case AMDGPU_INFO_FW_VCE:
283 fw_info->ver = adev->vce.fw_version;
284 fw_info->feature = adev->vce.fb_version;
285 break;
286 case AMDGPU_INFO_FW_UVD:
287 fw_info->ver = adev->uvd.fw_version;
288 fw_info->feature = 0;
289 break;
290 case AMDGPU_INFO_FW_VCN:
291 fw_info->ver = adev->vcn.fw_version;
292 fw_info->feature = 0;
293 break;
294 case AMDGPU_INFO_FW_GMC:
295 fw_info->ver = adev->gmc.fw_version;
296 fw_info->feature = 0;
297 break;
298 case AMDGPU_INFO_FW_GFX_ME:
299 fw_info->ver = adev->gfx.me_fw_version;
300 fw_info->feature = adev->gfx.me_feature_version;
301 break;
302 case AMDGPU_INFO_FW_GFX_PFP:
303 fw_info->ver = adev->gfx.pfp_fw_version;
304 fw_info->feature = adev->gfx.pfp_feature_version;
305 break;
306 case AMDGPU_INFO_FW_GFX_CE:
307 fw_info->ver = adev->gfx.ce_fw_version;
308 fw_info->feature = adev->gfx.ce_feature_version;
309 break;
310 case AMDGPU_INFO_FW_GFX_RLC:
311 fw_info->ver = adev->gfx.rlc_fw_version;
312 fw_info->feature = adev->gfx.rlc_feature_version;
313 break;
314 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
315 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
316 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
317 break;
318 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
319 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
320 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
321 break;
322 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
323 fw_info->ver = adev->gfx.rlc_srls_fw_version;
324 fw_info->feature = adev->gfx.rlc_srls_feature_version;
325 break;
326 case AMDGPU_INFO_FW_GFX_MEC:
327 if (query_fw->index == 0) {
328 fw_info->ver = adev->gfx.mec_fw_version;
329 fw_info->feature = adev->gfx.mec_feature_version;
330 } else if (query_fw->index == 1) {
331 fw_info->ver = adev->gfx.mec2_fw_version;
332 fw_info->feature = adev->gfx.mec2_feature_version;
333 } else
334 return -EINVAL;
335 break;
336 case AMDGPU_INFO_FW_SMC:
337 fw_info->ver = adev->pm.fw_version;
338 fw_info->feature = 0;
339 break;
340 case AMDGPU_INFO_FW_TA:
341 switch (query_fw->index) {
342 case TA_FW_TYPE_PSP_XGMI:
343 fw_info->ver = adev->psp.ta_fw_version;
344 fw_info->feature = adev->psp.ta_xgmi_ucode_version;
345 break;
346 case TA_FW_TYPE_PSP_RAS:
347 fw_info->ver = adev->psp.ta_fw_version;
348 fw_info->feature = adev->psp.ta_ras_ucode_version;
349 break;
350 case TA_FW_TYPE_PSP_HDCP:
351 fw_info->ver = adev->psp.ta_fw_version;
352 fw_info->feature = adev->psp.ta_hdcp_ucode_version;
353 break;
354 case TA_FW_TYPE_PSP_DTM:
355 fw_info->ver = adev->psp.ta_fw_version;
356 fw_info->feature = adev->psp.ta_dtm_ucode_version;
357 break;
358 case TA_FW_TYPE_PSP_RAP:
359 fw_info->ver = adev->psp.ta_fw_version;
360 fw_info->feature = adev->psp.ta_rap_ucode_version;
361 break;
362 case TA_FW_TYPE_PSP_SECUREDISPLAY:
363 fw_info->ver = adev->psp.ta_fw_version;
364 fw_info->feature = adev->psp.ta_securedisplay_ucode_version;
365 break;
366 default:
367 return -EINVAL;
368 }
369 break;
370 case AMDGPU_INFO_FW_SDMA:
371 if (query_fw->index >= adev->sdma.num_instances)
372 return -EINVAL;
373 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
374 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
375 break;
376 case AMDGPU_INFO_FW_SOS:
377 fw_info->ver = adev->psp.sos_fw_version;
378 fw_info->feature = adev->psp.sos_feature_version;
379 break;
380 case AMDGPU_INFO_FW_ASD:
381 fw_info->ver = adev->psp.asd_fw_version;
382 fw_info->feature = adev->psp.asd_feature_version;
383 break;
384 case AMDGPU_INFO_FW_DMCU:
385 fw_info->ver = adev->dm.dmcu_fw_version;
386 fw_info->feature = 0;
387 break;
388 case AMDGPU_INFO_FW_DMCUB:
389 fw_info->ver = adev->dm.dmcub_fw_version;
390 fw_info->feature = 0;
391 break;
392 case AMDGPU_INFO_FW_TOC:
393 fw_info->ver = adev->psp.toc_fw_version;
394 fw_info->feature = adev->psp.toc_feature_version;
395 break;
396 default:
397 return -EINVAL;
398 }
399 return 0;
400}
401
402static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
403 struct drm_amdgpu_info *info,
404 struct drm_amdgpu_info_hw_ip *result)
405{
406 uint32_t ib_start_alignment = 0;
407 uint32_t ib_size_alignment = 0;
408 enum amd_ip_block_type type;
409 unsigned int num_rings = 0;
410 unsigned int i, j;
411
412 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
413 return -EINVAL;
414
415 switch (info->query_hw_ip.type) {
416 case AMDGPU_HW_IP_GFX:
417 type = AMD_IP_BLOCK_TYPE_GFX;
418 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
419 if (adev->gfx.gfx_ring[i].sched.ready)
420 ++num_rings;
421 ib_start_alignment = 32;
422 ib_size_alignment = 32;
423 break;
424 case AMDGPU_HW_IP_COMPUTE:
425 type = AMD_IP_BLOCK_TYPE_GFX;
426 for (i = 0; i < adev->gfx.num_compute_rings; i++)
427 if (adev->gfx.compute_ring[i].sched.ready)
428 ++num_rings;
429 ib_start_alignment = 32;
430 ib_size_alignment = 32;
431 break;
432 case AMDGPU_HW_IP_DMA:
433 type = AMD_IP_BLOCK_TYPE_SDMA;
434 for (i = 0; i < adev->sdma.num_instances; i++)
435 if (adev->sdma.instance[i].ring.sched.ready)
436 ++num_rings;
437 ib_start_alignment = 256;
438 ib_size_alignment = 4;
439 break;
440 case AMDGPU_HW_IP_UVD:
441 type = AMD_IP_BLOCK_TYPE_UVD;
442 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
443 if (adev->uvd.harvest_config & (1 << i))
444 continue;
445
446 if (adev->uvd.inst[i].ring.sched.ready)
447 ++num_rings;
448 }
449 ib_start_alignment = 64;
450 ib_size_alignment = 64;
451 break;
452 case AMDGPU_HW_IP_VCE:
453 type = AMD_IP_BLOCK_TYPE_VCE;
454 for (i = 0; i < adev->vce.num_rings; i++)
455 if (adev->vce.ring[i].sched.ready)
456 ++num_rings;
457 ib_start_alignment = 4;
458 ib_size_alignment = 1;
459 break;
460 case AMDGPU_HW_IP_UVD_ENC:
461 type = AMD_IP_BLOCK_TYPE_UVD;
462 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
463 if (adev->uvd.harvest_config & (1 << i))
464 continue;
465
466 for (j = 0; j < adev->uvd.num_enc_rings; j++)
467 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
468 ++num_rings;
469 }
470 ib_start_alignment = 64;
471 ib_size_alignment = 64;
472 break;
473 case AMDGPU_HW_IP_VCN_DEC:
474 type = AMD_IP_BLOCK_TYPE_VCN;
475 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
476 if (adev->uvd.harvest_config & (1 << i))
477 continue;
478
479 if (adev->vcn.inst[i].ring_dec.sched.ready)
480 ++num_rings;
481 }
482 ib_start_alignment = 16;
483 ib_size_alignment = 16;
484 break;
485 case AMDGPU_HW_IP_VCN_ENC:
486 type = AMD_IP_BLOCK_TYPE_VCN;
487 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
488 if (adev->uvd.harvest_config & (1 << i))
489 continue;
490
491 for (j = 0; j < adev->vcn.num_enc_rings; j++)
492 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
493 ++num_rings;
494 }
495 ib_start_alignment = 64;
496 ib_size_alignment = 1;
497 break;
498 case AMDGPU_HW_IP_VCN_JPEG:
499 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
500 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
501
502 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
503 if (adev->jpeg.harvest_config & (1 << i))
504 continue;
505
506 if (adev->jpeg.inst[i].ring_dec.sched.ready)
507 ++num_rings;
508 }
509 ib_start_alignment = 16;
510 ib_size_alignment = 16;
511 break;
512 default:
513 return -EINVAL;
514 }
515
516 for (i = 0; i < adev->num_ip_blocks; i++)
517 if (adev->ip_blocks[i].version->type == type &&
518 adev->ip_blocks[i].status.valid)
519 break;
520
521 if (i == adev->num_ip_blocks)
522 return 0;
523
524 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
525 num_rings);
526
527 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
528 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
529 result->capabilities_flags = 0;
530 result->available_rings = (1 << num_rings) - 1;
531 result->ib_start_alignment = ib_start_alignment;
532 result->ib_size_alignment = ib_size_alignment;
533 return 0;
534}
535
536/*
537 * Userspace get information ioctl
538 */
539/**
540 * amdgpu_info_ioctl - answer a device specific request.
541 *
542 * @dev: drm device pointer
543 * @data: request object
544 * @filp: drm filp
545 *
546 * This function is used to pass device specific parameters to the userspace
547 * drivers. Examples include: pci device id, pipeline parms, tiling params,
548 * etc. (all asics).
549 * Returns 0 on success, -EINVAL on failure.
550 */
551int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
552{
553 struct amdgpu_device *adev = drm_to_adev(dev);
554 struct drm_amdgpu_info *info = data;
555 struct amdgpu_mode_info *minfo = &adev->mode_info;
556 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
557 uint32_t size = info->return_size;
558 struct drm_crtc *crtc;
559 uint32_t ui32 = 0;
560 uint64_t ui64 = 0;
561 int i, found;
562 int ui32_size = sizeof(ui32);
563
564 if (!info->return_size || !info->return_pointer)
565 return -EINVAL;
566
567 switch (info->query) {
568 case AMDGPU_INFO_ACCEL_WORKING:
569 ui32 = adev->accel_working;
570 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
571 case AMDGPU_INFO_CRTC_FROM_ID:
572 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
573 crtc = (struct drm_crtc *)minfo->crtcs[i];
574 if (crtc && crtc->base.id == info->mode_crtc.id) {
575 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
576 ui32 = amdgpu_crtc->crtc_id;
577 found = 1;
578 break;
579 }
580 }
581 if (!found) {
582 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
583 return -EINVAL;
584 }
585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
586 case AMDGPU_INFO_HW_IP_INFO: {
587 struct drm_amdgpu_info_hw_ip ip = {};
588 int ret;
589
590 ret = amdgpu_hw_ip_info(adev, info, &ip);
591 if (ret)
592 return ret;
593
594 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
595 return ret ? -EFAULT : 0;
596 }
597 case AMDGPU_INFO_HW_IP_COUNT: {
598 enum amd_ip_block_type type;
599 uint32_t count = 0;
600
601 switch (info->query_hw_ip.type) {
602 case AMDGPU_HW_IP_GFX:
603 type = AMD_IP_BLOCK_TYPE_GFX;
604 break;
605 case AMDGPU_HW_IP_COMPUTE:
606 type = AMD_IP_BLOCK_TYPE_GFX;
607 break;
608 case AMDGPU_HW_IP_DMA:
609 type = AMD_IP_BLOCK_TYPE_SDMA;
610 break;
611 case AMDGPU_HW_IP_UVD:
612 type = AMD_IP_BLOCK_TYPE_UVD;
613 break;
614 case AMDGPU_HW_IP_VCE:
615 type = AMD_IP_BLOCK_TYPE_VCE;
616 break;
617 case AMDGPU_HW_IP_UVD_ENC:
618 type = AMD_IP_BLOCK_TYPE_UVD;
619 break;
620 case AMDGPU_HW_IP_VCN_DEC:
621 case AMDGPU_HW_IP_VCN_ENC:
622 type = AMD_IP_BLOCK_TYPE_VCN;
623 break;
624 case AMDGPU_HW_IP_VCN_JPEG:
625 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
626 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 for (i = 0; i < adev->num_ip_blocks; i++)
633 if (adev->ip_blocks[i].version->type == type &&
634 adev->ip_blocks[i].status.valid &&
635 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
636 count++;
637
638 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
639 }
640 case AMDGPU_INFO_TIMESTAMP:
641 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
643 case AMDGPU_INFO_FW_VERSION: {
644 struct drm_amdgpu_info_firmware fw_info;
645 int ret;
646
647 /* We only support one instance of each IP block right now. */
648 if (info->query_fw.ip_instance != 0)
649 return -EINVAL;
650
651 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
652 if (ret)
653 return ret;
654
655 return copy_to_user(out, &fw_info,
656 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
657 }
658 case AMDGPU_INFO_NUM_BYTES_MOVED:
659 ui64 = atomic64_read(&adev->num_bytes_moved);
660 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
661 case AMDGPU_INFO_NUM_EVICTIONS:
662 ui64 = atomic64_read(&adev->num_evictions);
663 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
664 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
665 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
666 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
667 case AMDGPU_INFO_VRAM_USAGE:
668 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
669 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
670 case AMDGPU_INFO_VIS_VRAM_USAGE:
671 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
672 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
673 case AMDGPU_INFO_GTT_USAGE:
674 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
675 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
676 case AMDGPU_INFO_GDS_CONFIG: {
677 struct drm_amdgpu_info_gds gds_info;
678
679 memset(&gds_info, 0, sizeof(gds_info));
680 gds_info.compute_partition_size = adev->gds.gds_size;
681 gds_info.gds_total_size = adev->gds.gds_size;
682 gds_info.gws_per_compute_partition = adev->gds.gws_size;
683 gds_info.oa_per_compute_partition = adev->gds.oa_size;
684 return copy_to_user(out, &gds_info,
685 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
686 }
687 case AMDGPU_INFO_VRAM_GTT: {
688 struct drm_amdgpu_info_vram_gtt vram_gtt;
689
690 vram_gtt.vram_size = adev->gmc.real_vram_size -
691 atomic64_read(&adev->vram_pin_size) -
692 AMDGPU_VM_RESERVED_VRAM;
693 vram_gtt.vram_cpu_accessible_size =
694 min(adev->gmc.visible_vram_size -
695 atomic64_read(&adev->visible_pin_size),
696 vram_gtt.vram_size);
697 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
698 vram_gtt.gtt_size *= PAGE_SIZE;
699 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
700 return copy_to_user(out, &vram_gtt,
701 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
702 }
703 case AMDGPU_INFO_MEMORY: {
704 struct drm_amdgpu_memory_info mem;
705 struct ttm_resource_manager *vram_man =
706 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
707 struct ttm_resource_manager *gtt_man =
708 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
709 memset(&mem, 0, sizeof(mem));
710 mem.vram.total_heap_size = adev->gmc.real_vram_size;
711 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
712 atomic64_read(&adev->vram_pin_size) -
713 AMDGPU_VM_RESERVED_VRAM;
714 mem.vram.heap_usage =
715 amdgpu_vram_mgr_usage(vram_man);
716 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
717
718 mem.cpu_accessible_vram.total_heap_size =
719 adev->gmc.visible_vram_size;
720 mem.cpu_accessible_vram.usable_heap_size =
721 min(adev->gmc.visible_vram_size -
722 atomic64_read(&adev->visible_pin_size),
723 mem.vram.usable_heap_size);
724 mem.cpu_accessible_vram.heap_usage =
725 amdgpu_vram_mgr_vis_usage(vram_man);
726 mem.cpu_accessible_vram.max_allocation =
727 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
728
729 mem.gtt.total_heap_size = gtt_man->size;
730 mem.gtt.total_heap_size *= PAGE_SIZE;
731 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
732 atomic64_read(&adev->gart_pin_size);
733 mem.gtt.heap_usage =
734 amdgpu_gtt_mgr_usage(gtt_man);
735 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
736
737 return copy_to_user(out, &mem,
738 min((size_t)size, sizeof(mem)))
739 ? -EFAULT : 0;
740 }
741 case AMDGPU_INFO_READ_MMR_REG: {
742 unsigned n, alloc_size;
743 uint32_t *regs;
744 unsigned se_num = (info->read_mmr_reg.instance >>
745 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
746 AMDGPU_INFO_MMR_SE_INDEX_MASK;
747 unsigned sh_num = (info->read_mmr_reg.instance >>
748 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
749 AMDGPU_INFO_MMR_SH_INDEX_MASK;
750
751 /* set full masks if the userspace set all bits
752 * in the bitfields */
753 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
754 se_num = 0xffffffff;
755 else if (se_num >= AMDGPU_GFX_MAX_SE)
756 return -EINVAL;
757 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
758 sh_num = 0xffffffff;
759 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
760 return -EINVAL;
761
762 if (info->read_mmr_reg.count > 128)
763 return -EINVAL;
764
765 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
766 if (!regs)
767 return -ENOMEM;
768 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
769
770 amdgpu_gfx_off_ctrl(adev, false);
771 for (i = 0; i < info->read_mmr_reg.count; i++) {
772 if (amdgpu_asic_read_register(adev, se_num, sh_num,
773 info->read_mmr_reg.dword_offset + i,
774 ®s[i])) {
775 DRM_DEBUG_KMS("unallowed offset %#x\n",
776 info->read_mmr_reg.dword_offset + i);
777 kfree(regs);
778 amdgpu_gfx_off_ctrl(adev, true);
779 return -EFAULT;
780 }
781 }
782 amdgpu_gfx_off_ctrl(adev, true);
783 n = copy_to_user(out, regs, min(size, alloc_size));
784 kfree(regs);
785 return n ? -EFAULT : 0;
786 }
787 case AMDGPU_INFO_DEV_INFO: {
788 struct drm_amdgpu_info_device *dev_info;
789 uint64_t vm_size;
790 int ret;
791
792 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
793 if (!dev_info)
794 return -ENOMEM;
795
796 dev_info->device_id = adev->pdev->device;
797 dev_info->chip_rev = adev->rev_id;
798 dev_info->external_rev = adev->external_rev_id;
799 dev_info->pci_rev = adev->pdev->revision;
800 dev_info->family = adev->family;
801 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
802 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
803 /* return all clocks in KHz */
804 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
805 if (adev->pm.dpm_enabled) {
806 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
807 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
808 } else {
809 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
810 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
811 }
812 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
813 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
814 adev->gfx.config.max_shader_engines;
815 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
816 dev_info->_pad = 0;
817 dev_info->ids_flags = 0;
818 if (adev->flags & AMD_IS_APU)
819 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
820 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
821 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
822 if (amdgpu_is_tmz(adev))
823 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
824
825 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
826 vm_size -= AMDGPU_VA_RESERVED_SIZE;
827
828 /* Older VCE FW versions are buggy and can handle only 40bits */
829 if (adev->vce.fw_version &&
830 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
831 vm_size = min(vm_size, 1ULL << 40);
832
833 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
834 dev_info->virtual_address_max =
835 min(vm_size, AMDGPU_GMC_HOLE_START);
836
837 if (vm_size > AMDGPU_GMC_HOLE_START) {
838 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
839 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
840 }
841 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
842 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
843 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
844 dev_info->cu_active_number = adev->gfx.cu_info.number;
845 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
846 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
847 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
848 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
849 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
850 sizeof(adev->gfx.cu_info.bitmap));
851 dev_info->vram_type = adev->gmc.vram_type;
852 dev_info->vram_bit_width = adev->gmc.vram_width;
853 dev_info->vce_harvest_config = adev->vce.harvest_config;
854 dev_info->gc_double_offchip_lds_buf =
855 adev->gfx.config.double_offchip_lds_buf;
856 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
857 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
858 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
859 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
860 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
861 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
862 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
863
864 if (adev->family >= AMDGPU_FAMILY_NV)
865 dev_info->pa_sc_tile_steering_override =
866 adev->gfx.config.pa_sc_tile_steering_override;
867
868 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
869
870 ret = copy_to_user(out, dev_info,
871 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
872 kfree(dev_info);
873 return ret;
874 }
875 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
876 unsigned i;
877 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
878 struct amd_vce_state *vce_state;
879
880 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
881 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
882 if (vce_state) {
883 vce_clk_table.entries[i].sclk = vce_state->sclk;
884 vce_clk_table.entries[i].mclk = vce_state->mclk;
885 vce_clk_table.entries[i].eclk = vce_state->evclk;
886 vce_clk_table.num_valid_entries++;
887 }
888 }
889
890 return copy_to_user(out, &vce_clk_table,
891 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
892 }
893 case AMDGPU_INFO_VBIOS: {
894 uint32_t bios_size = adev->bios_size;
895
896 switch (info->vbios_info.type) {
897 case AMDGPU_INFO_VBIOS_SIZE:
898 return copy_to_user(out, &bios_size,
899 min((size_t)size, sizeof(bios_size)))
900 ? -EFAULT : 0;
901 case AMDGPU_INFO_VBIOS_IMAGE: {
902 uint8_t *bios;
903 uint32_t bios_offset = info->vbios_info.offset;
904
905 if (bios_offset >= bios_size)
906 return -EINVAL;
907
908 bios = adev->bios + bios_offset;
909 return copy_to_user(out, bios,
910 min((size_t)size, (size_t)(bios_size - bios_offset)))
911 ? -EFAULT : 0;
912 }
913 case AMDGPU_INFO_VBIOS_INFO: {
914 struct drm_amdgpu_info_vbios vbios_info = {};
915 struct atom_context *atom_context;
916
917 atom_context = adev->mode_info.atom_context;
918 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
919 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
920 vbios_info.version = atom_context->version;
921 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
922 sizeof(atom_context->vbios_ver_str));
923 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
924
925 return copy_to_user(out, &vbios_info,
926 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
927 }
928 default:
929 DRM_DEBUG_KMS("Invalid request %d\n",
930 info->vbios_info.type);
931 return -EINVAL;
932 }
933 }
934 case AMDGPU_INFO_NUM_HANDLES: {
935 struct drm_amdgpu_info_num_handles handle;
936
937 switch (info->query_hw_ip.type) {
938 case AMDGPU_HW_IP_UVD:
939 /* Starting Polaris, we support unlimited UVD handles */
940 if (adev->asic_type < CHIP_POLARIS10) {
941 handle.uvd_max_handles = adev->uvd.max_handles;
942 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
943
944 return copy_to_user(out, &handle,
945 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
946 } else {
947 return -ENODATA;
948 }
949
950 break;
951 default:
952 return -EINVAL;
953 }
954 }
955 case AMDGPU_INFO_SENSOR: {
956 if (!adev->pm.dpm_enabled)
957 return -ENOENT;
958
959 switch (info->sensor_info.type) {
960 case AMDGPU_INFO_SENSOR_GFX_SCLK:
961 /* get sclk in Mhz */
962 if (amdgpu_dpm_read_sensor(adev,
963 AMDGPU_PP_SENSOR_GFX_SCLK,
964 (void *)&ui32, &ui32_size)) {
965 return -EINVAL;
966 }
967 ui32 /= 100;
968 break;
969 case AMDGPU_INFO_SENSOR_GFX_MCLK:
970 /* get mclk in Mhz */
971 if (amdgpu_dpm_read_sensor(adev,
972 AMDGPU_PP_SENSOR_GFX_MCLK,
973 (void *)&ui32, &ui32_size)) {
974 return -EINVAL;
975 }
976 ui32 /= 100;
977 break;
978 case AMDGPU_INFO_SENSOR_GPU_TEMP:
979 /* get temperature in millidegrees C */
980 if (amdgpu_dpm_read_sensor(adev,
981 AMDGPU_PP_SENSOR_GPU_TEMP,
982 (void *)&ui32, &ui32_size)) {
983 return -EINVAL;
984 }
985 break;
986 case AMDGPU_INFO_SENSOR_GPU_LOAD:
987 /* get GPU load */
988 if (amdgpu_dpm_read_sensor(adev,
989 AMDGPU_PP_SENSOR_GPU_LOAD,
990 (void *)&ui32, &ui32_size)) {
991 return -EINVAL;
992 }
993 break;
994 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
995 /* get average GPU power */
996 if (amdgpu_dpm_read_sensor(adev,
997 AMDGPU_PP_SENSOR_GPU_POWER,
998 (void *)&ui32, &ui32_size)) {
999 return -EINVAL;
1000 }
1001 ui32 >>= 8;
1002 break;
1003 case AMDGPU_INFO_SENSOR_VDDNB:
1004 /* get VDDNB in millivolts */
1005 if (amdgpu_dpm_read_sensor(adev,
1006 AMDGPU_PP_SENSOR_VDDNB,
1007 (void *)&ui32, &ui32_size)) {
1008 return -EINVAL;
1009 }
1010 break;
1011 case AMDGPU_INFO_SENSOR_VDDGFX:
1012 /* get VDDGFX in millivolts */
1013 if (amdgpu_dpm_read_sensor(adev,
1014 AMDGPU_PP_SENSOR_VDDGFX,
1015 (void *)&ui32, &ui32_size)) {
1016 return -EINVAL;
1017 }
1018 break;
1019 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1020 /* get stable pstate sclk in Mhz */
1021 if (amdgpu_dpm_read_sensor(adev,
1022 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1023 (void *)&ui32, &ui32_size)) {
1024 return -EINVAL;
1025 }
1026 ui32 /= 100;
1027 break;
1028 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1029 /* get stable pstate mclk in Mhz */
1030 if (amdgpu_dpm_read_sensor(adev,
1031 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1032 (void *)&ui32, &ui32_size)) {
1033 return -EINVAL;
1034 }
1035 ui32 /= 100;
1036 break;
1037 default:
1038 DRM_DEBUG_KMS("Invalid request %d\n",
1039 info->sensor_info.type);
1040 return -EINVAL;
1041 }
1042 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1043 }
1044 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1045 ui32 = atomic_read(&adev->vram_lost_counter);
1046 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1047 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1048 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1049 uint64_t ras_mask;
1050
1051 if (!ras)
1052 return -EINVAL;
1053 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1054
1055 return copy_to_user(out, &ras_mask,
1056 min_t(u64, size, sizeof(ras_mask))) ?
1057 -EFAULT : 0;
1058 }
1059 case AMDGPU_INFO_VIDEO_CAPS: {
1060 const struct amdgpu_video_codecs *codecs;
1061 struct drm_amdgpu_info_video_caps *caps;
1062 int r;
1063
1064 switch (info->video_cap.type) {
1065 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1066 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1067 if (r)
1068 return -EINVAL;
1069 break;
1070 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1071 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1072 if (r)
1073 return -EINVAL;
1074 break;
1075 default:
1076 DRM_DEBUG_KMS("Invalid request %d\n",
1077 info->video_cap.type);
1078 return -EINVAL;
1079 }
1080
1081 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1082 if (!caps)
1083 return -ENOMEM;
1084
1085 for (i = 0; i < codecs->codec_count; i++) {
1086 int idx = codecs->codec_array[i].codec_type;
1087
1088 switch (idx) {
1089 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1090 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1091 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1092 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1093 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1094 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1095 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1096 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1097 caps->codec_info[idx].valid = 1;
1098 caps->codec_info[idx].max_width =
1099 codecs->codec_array[i].max_width;
1100 caps->codec_info[idx].max_height =
1101 codecs->codec_array[i].max_height;
1102 caps->codec_info[idx].max_pixels_per_frame =
1103 codecs->codec_array[i].max_pixels_per_frame;
1104 caps->codec_info[idx].max_level =
1105 codecs->codec_array[i].max_level;
1106 break;
1107 default:
1108 break;
1109 }
1110 }
1111 r = copy_to_user(out, caps,
1112 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1113 kfree(caps);
1114 return r;
1115 }
1116 default:
1117 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1118 return -EINVAL;
1119 }
1120 return 0;
1121}
1122
1123
1124/*
1125 * Outdated mess for old drm with Xorg being in charge (void function now).
1126 */
1127/**
1128 * amdgpu_driver_lastclose_kms - drm callback for last close
1129 *
1130 * @dev: drm dev pointer
1131 *
1132 * Switch vga_switcheroo state after last close (all asics).
1133 */
1134void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1135{
1136 drm_fb_helper_lastclose(dev);
1137 vga_switcheroo_process_delayed_switch();
1138}
1139
1140/**
1141 * amdgpu_driver_open_kms - drm callback for open
1142 *
1143 * @dev: drm dev pointer
1144 * @file_priv: drm file
1145 *
1146 * On device open, init vm on cayman+ (all asics).
1147 * Returns 0 on success, error on failure.
1148 */
1149int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1150{
1151 struct amdgpu_device *adev = drm_to_adev(dev);
1152 struct amdgpu_fpriv *fpriv;
1153 int r, pasid;
1154
1155 /* Ensure IB tests are run on ring */
1156 flush_delayed_work(&adev->delayed_init_work);
1157
1158
1159 if (amdgpu_ras_intr_triggered()) {
1160 DRM_ERROR("RAS Intr triggered, device disabled!!");
1161 return -EHWPOISON;
1162 }
1163
1164 file_priv->driver_priv = NULL;
1165
1166 r = pm_runtime_get_sync(dev->dev);
1167 if (r < 0)
1168 goto pm_put;
1169
1170 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1171 if (unlikely(!fpriv)) {
1172 r = -ENOMEM;
1173 goto out_suspend;
1174 }
1175
1176 pasid = amdgpu_pasid_alloc(16);
1177 if (pasid < 0) {
1178 dev_warn(adev->dev, "No more PASIDs available!");
1179 pasid = 0;
1180 }
1181
1182 r = amdgpu_vm_init(adev, &fpriv->vm, pasid);
1183 if (r)
1184 goto error_pasid;
1185
1186 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1187 if (!fpriv->prt_va) {
1188 r = -ENOMEM;
1189 goto error_vm;
1190 }
1191
1192 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1193 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1194
1195 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1196 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1197 if (r)
1198 goto error_vm;
1199 }
1200
1201 mutex_init(&fpriv->bo_list_lock);
1202 idr_init(&fpriv->bo_list_handles);
1203
1204 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1205
1206 file_priv->driver_priv = fpriv;
1207 goto out_suspend;
1208
1209error_vm:
1210 amdgpu_vm_fini(adev, &fpriv->vm);
1211
1212error_pasid:
1213 if (pasid)
1214 amdgpu_pasid_free(pasid);
1215
1216 kfree(fpriv);
1217
1218out_suspend:
1219 pm_runtime_mark_last_busy(dev->dev);
1220pm_put:
1221 pm_runtime_put_autosuspend(dev->dev);
1222
1223 return r;
1224}
1225
1226/**
1227 * amdgpu_driver_postclose_kms - drm callback for post close
1228 *
1229 * @dev: drm dev pointer
1230 * @file_priv: drm file
1231 *
1232 * On device post close, tear down vm on cayman+ (all asics).
1233 */
1234void amdgpu_driver_postclose_kms(struct drm_device *dev,
1235 struct drm_file *file_priv)
1236{
1237 struct amdgpu_device *adev = drm_to_adev(dev);
1238 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1239 struct amdgpu_bo_list *list;
1240 struct amdgpu_bo *pd;
1241 u32 pasid;
1242 int handle;
1243
1244 if (!fpriv)
1245 return;
1246
1247 pm_runtime_get_sync(dev->dev);
1248
1249 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1250 amdgpu_uvd_free_handles(adev, file_priv);
1251 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1252 amdgpu_vce_free_handles(adev, file_priv);
1253
1254 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1255
1256 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1257 /* TODO: how to handle reserve failure */
1258 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1259 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1260 fpriv->csa_va = NULL;
1261 amdgpu_bo_unreserve(adev->virt.csa_obj);
1262 }
1263
1264 pasid = fpriv->vm.pasid;
1265 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1266
1267 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1268 amdgpu_vm_fini(adev, &fpriv->vm);
1269
1270 if (pasid)
1271 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1272 amdgpu_bo_unref(&pd);
1273
1274 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1275 amdgpu_bo_list_put(list);
1276
1277 idr_destroy(&fpriv->bo_list_handles);
1278 mutex_destroy(&fpriv->bo_list_lock);
1279
1280 kfree(fpriv);
1281 file_priv->driver_priv = NULL;
1282
1283 pm_runtime_mark_last_busy(dev->dev);
1284 pm_runtime_put_autosuspend(dev->dev);
1285}
1286
1287
1288void amdgpu_driver_release_kms(struct drm_device *dev)
1289{
1290 struct amdgpu_device *adev = drm_to_adev(dev);
1291
1292 amdgpu_device_fini_sw(adev);
1293 pci_set_drvdata(adev->pdev, NULL);
1294}
1295
1296/*
1297 * VBlank related functions.
1298 */
1299/**
1300 * amdgpu_get_vblank_counter_kms - get frame count
1301 *
1302 * @crtc: crtc to get the frame count from
1303 *
1304 * Gets the frame count on the requested crtc (all asics).
1305 * Returns frame count on success, -EINVAL on failure.
1306 */
1307u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1308{
1309 struct drm_device *dev = crtc->dev;
1310 unsigned int pipe = crtc->index;
1311 struct amdgpu_device *adev = drm_to_adev(dev);
1312 int vpos, hpos, stat;
1313 u32 count;
1314
1315 if (pipe >= adev->mode_info.num_crtc) {
1316 DRM_ERROR("Invalid crtc %u\n", pipe);
1317 return -EINVAL;
1318 }
1319
1320 /* The hw increments its frame counter at start of vsync, not at start
1321 * of vblank, as is required by DRM core vblank counter handling.
1322 * Cook the hw count here to make it appear to the caller as if it
1323 * incremented at start of vblank. We measure distance to start of
1324 * vblank in vpos. vpos therefore will be >= 0 between start of vblank
1325 * and start of vsync, so vpos >= 0 means to bump the hw frame counter
1326 * result by 1 to give the proper appearance to caller.
1327 */
1328 if (adev->mode_info.crtcs[pipe]) {
1329 /* Repeat readout if needed to provide stable result if
1330 * we cross start of vsync during the queries.
1331 */
1332 do {
1333 count = amdgpu_display_vblank_get_counter(adev, pipe);
1334 /* Ask amdgpu_display_get_crtc_scanoutpos to return
1335 * vpos as distance to start of vblank, instead of
1336 * regular vertical scanout pos.
1337 */
1338 stat = amdgpu_display_get_crtc_scanoutpos(
1339 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1340 &vpos, &hpos, NULL, NULL,
1341 &adev->mode_info.crtcs[pipe]->base.hwmode);
1342 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1343
1344 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1345 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1346 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1347 } else {
1348 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1349 pipe, vpos);
1350
1351 /* Bump counter if we are at >= leading edge of vblank,
1352 * but before vsync where vpos would turn negative and
1353 * the hw counter really increments.
1354 */
1355 if (vpos >= 0)
1356 count++;
1357 }
1358 } else {
1359 /* Fallback to use value as is. */
1360 count = amdgpu_display_vblank_get_counter(adev, pipe);
1361 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1362 }
1363
1364 return count;
1365}
1366
1367/**
1368 * amdgpu_enable_vblank_kms - enable vblank interrupt
1369 *
1370 * @crtc: crtc to enable vblank interrupt for
1371 *
1372 * Enable the interrupt on the requested crtc (all asics).
1373 * Returns 0 on success, -EINVAL on failure.
1374 */
1375int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1376{
1377 struct drm_device *dev = crtc->dev;
1378 unsigned int pipe = crtc->index;
1379 struct amdgpu_device *adev = drm_to_adev(dev);
1380 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1381
1382 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1383}
1384
1385/**
1386 * amdgpu_disable_vblank_kms - disable vblank interrupt
1387 *
1388 * @crtc: crtc to disable vblank interrupt for
1389 *
1390 * Disable the interrupt on the requested crtc (all asics).
1391 */
1392void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1393{
1394 struct drm_device *dev = crtc->dev;
1395 unsigned int pipe = crtc->index;
1396 struct amdgpu_device *adev = drm_to_adev(dev);
1397 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1398
1399 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1400}
1401
1402/*
1403 * Debugfs info
1404 */
1405#if defined(CONFIG_DEBUG_FS)
1406
1407static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1408{
1409 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1410 struct drm_amdgpu_info_firmware fw_info;
1411 struct drm_amdgpu_query_fw query_fw;
1412 struct atom_context *ctx = adev->mode_info.atom_context;
1413 int ret, i;
1414
1415 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1416#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1417 TA_FW_NAME(XGMI),
1418 TA_FW_NAME(RAS),
1419 TA_FW_NAME(HDCP),
1420 TA_FW_NAME(DTM),
1421 TA_FW_NAME(RAP),
1422 TA_FW_NAME(SECUREDISPLAY),
1423#undef TA_FW_NAME
1424 };
1425
1426 /* VCE */
1427 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1428 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1429 if (ret)
1430 return ret;
1431 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1432 fw_info.feature, fw_info.ver);
1433
1434 /* UVD */
1435 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1436 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1437 if (ret)
1438 return ret;
1439 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1440 fw_info.feature, fw_info.ver);
1441
1442 /* GMC */
1443 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1444 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1445 if (ret)
1446 return ret;
1447 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1448 fw_info.feature, fw_info.ver);
1449
1450 /* ME */
1451 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1452 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1453 if (ret)
1454 return ret;
1455 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1456 fw_info.feature, fw_info.ver);
1457
1458 /* PFP */
1459 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1460 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1461 if (ret)
1462 return ret;
1463 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1464 fw_info.feature, fw_info.ver);
1465
1466 /* CE */
1467 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1468 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1469 if (ret)
1470 return ret;
1471 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1472 fw_info.feature, fw_info.ver);
1473
1474 /* RLC */
1475 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1476 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1477 if (ret)
1478 return ret;
1479 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1480 fw_info.feature, fw_info.ver);
1481
1482 /* RLC SAVE RESTORE LIST CNTL */
1483 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1484 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1485 if (ret)
1486 return ret;
1487 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1488 fw_info.feature, fw_info.ver);
1489
1490 /* RLC SAVE RESTORE LIST GPM MEM */
1491 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1492 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1493 if (ret)
1494 return ret;
1495 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1496 fw_info.feature, fw_info.ver);
1497
1498 /* RLC SAVE RESTORE LIST SRM MEM */
1499 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1500 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1501 if (ret)
1502 return ret;
1503 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1504 fw_info.feature, fw_info.ver);
1505
1506 /* MEC */
1507 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1508 query_fw.index = 0;
1509 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1510 if (ret)
1511 return ret;
1512 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1513 fw_info.feature, fw_info.ver);
1514
1515 /* MEC2 */
1516 if (adev->gfx.mec2_fw) {
1517 query_fw.index = 1;
1518 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1519 if (ret)
1520 return ret;
1521 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1522 fw_info.feature, fw_info.ver);
1523 }
1524
1525 /* PSP SOS */
1526 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1527 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1528 if (ret)
1529 return ret;
1530 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1531 fw_info.feature, fw_info.ver);
1532
1533
1534 /* PSP ASD */
1535 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1536 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1537 if (ret)
1538 return ret;
1539 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1540 fw_info.feature, fw_info.ver);
1541
1542 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1543 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1544 query_fw.index = i;
1545 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1546 if (ret)
1547 continue;
1548
1549 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1550 ta_fw_name[i], fw_info.feature, fw_info.ver);
1551 }
1552
1553 /* SMC */
1554 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1555 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1556 if (ret)
1557 return ret;
1558 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1559 fw_info.feature, fw_info.ver);
1560
1561 /* SDMA */
1562 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1563 for (i = 0; i < adev->sdma.num_instances; i++) {
1564 query_fw.index = i;
1565 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1566 if (ret)
1567 return ret;
1568 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1569 i, fw_info.feature, fw_info.ver);
1570 }
1571
1572 /* VCN */
1573 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1574 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1575 if (ret)
1576 return ret;
1577 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1578 fw_info.feature, fw_info.ver);
1579
1580 /* DMCU */
1581 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1582 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1583 if (ret)
1584 return ret;
1585 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1586 fw_info.feature, fw_info.ver);
1587
1588 /* DMCUB */
1589 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1590 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1591 if (ret)
1592 return ret;
1593 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1594 fw_info.feature, fw_info.ver);
1595
1596 /* TOC */
1597 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1598 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1599 if (ret)
1600 return ret;
1601 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1602 fw_info.feature, fw_info.ver);
1603
1604 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1605
1606 return 0;
1607}
1608
1609DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1610
1611#endif
1612
1613void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1614{
1615#if defined(CONFIG_DEBUG_FS)
1616 struct drm_minor *minor = adev_to_drm(adev)->primary;
1617 struct dentry *root = minor->debugfs_root;
1618
1619 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1620 adev, &amdgpu_debugfs_firmware_info_fops);
1621
1622#endif
1623}