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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/arm/kernel/bios32.c
4 *
5 * PCI bios-type initialisation for PCI machines
6 *
7 * Bits taken from various places.
8 */
9#include <linux/export.h>
10#include <linux/kernel.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/init.h>
14#include <linux/io.h>
15
16#include <asm/mach-types.h>
17#include <asm/mach/map.h>
18#include <asm/mach/pci.h>
19
20static int debug_pci;
21
22/*
23 * We can't use pci_get_device() here since we are
24 * called from interrupt context.
25 */
26static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
27{
28 struct pci_dev *dev;
29
30 list_for_each_entry(dev, &bus->devices, bus_list) {
31 u16 status;
32
33 /*
34 * ignore host bridge - we handle
35 * that separately
36 */
37 if (dev->bus->number == 0 && dev->devfn == 0)
38 continue;
39
40 pci_read_config_word(dev, PCI_STATUS, &status);
41 if (status == 0xffff)
42 continue;
43
44 if ((status & status_mask) == 0)
45 continue;
46
47 /* clear the status errors */
48 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49
50 if (warn)
51 printk("(%s: %04X) ", pci_name(dev), status);
52 }
53
54 list_for_each_entry(dev, &bus->devices, bus_list)
55 if (dev->subordinate)
56 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
57}
58
59void pcibios_report_status(u_int status_mask, int warn)
60{
61 struct pci_bus *bus;
62
63 list_for_each_entry(bus, &pci_root_buses, node)
64 pcibios_bus_report_status(bus, status_mask, warn);
65}
66
67/*
68 * We don't use this to fix the device, but initialisation of it.
69 * It's not the correct use for this, but it works.
70 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
71 * the following area:
72 * 1. park on CPU
73 * 2. ISA bridge ping-pong
74 * 3. ISA bridge master handling of target RETRY
75 *
76 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
77 * live with bug 2.
78 */
79static void pci_fixup_83c553(struct pci_dev *dev)
80{
81 /*
82 * Set memory region to start at address 0, and enable IO
83 */
84 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
85 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
86
87 dev->resource[0].end -= dev->resource[0].start;
88 dev->resource[0].start = 0;
89
90 /*
91 * All memory requests from ISA to be channelled to PCI
92 */
93 pci_write_config_byte(dev, 0x48, 0xff);
94
95 /*
96 * Enable ping-pong on bus master to ISA bridge transactions.
97 * This improves the sound DMA substantially. The fixed
98 * priority arbiter also helps (see below).
99 */
100 pci_write_config_byte(dev, 0x42, 0x01);
101
102 /*
103 * Enable PCI retry
104 */
105 pci_write_config_byte(dev, 0x40, 0x22);
106
107 /*
108 * We used to set the arbiter to "park on last master" (bit
109 * 1 set), but unfortunately the CyberPro does not park the
110 * bus. We must therefore park on CPU. Unfortunately, this
111 * may trigger yet another bug in the 553.
112 */
113 pci_write_config_byte(dev, 0x83, 0x02);
114
115 /*
116 * Make the ISA DMA request lowest priority, and disable
117 * rotating priorities completely.
118 */
119 pci_write_config_byte(dev, 0x80, 0x11);
120 pci_write_config_byte(dev, 0x81, 0x00);
121
122 /*
123 * Route INTA input to IRQ 11, and set IRQ11 to be level
124 * sensitive.
125 */
126 pci_write_config_word(dev, 0x44, 0xb000);
127 outb(0x08, 0x4d1);
128}
129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
130
131static void pci_fixup_unassign(struct pci_dev *dev)
132{
133 dev->resource[0].end -= dev->resource[0].start;
134 dev->resource[0].start = 0;
135}
136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
137
138/*
139 * Prevent the PCI layer from seeing the resources allocated to this device
140 * if it is the host bridge by marking it as such. These resources are of
141 * no consequence to the PCI layer (they are handled elsewhere).
142 */
143static void pci_fixup_dec21285(struct pci_dev *dev)
144{
145 int i;
146
147 if (dev->devfn == 0) {
148 dev->class &= 0xff;
149 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
150 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
151 dev->resource[i].start = 0;
152 dev->resource[i].end = 0;
153 dev->resource[i].flags = 0;
154 }
155 }
156}
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
158
159/*
160 * PCI IDE controllers use non-standard I/O port decoding, respect it.
161 */
162static void pci_fixup_ide_bases(struct pci_dev *dev)
163{
164 struct resource *r;
165 int i;
166
167 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
168 return;
169
170 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
171 r = dev->resource + i;
172 if ((r->start & ~0x80) == 0x374) {
173 r->start |= 2;
174 r->end = r->start;
175 }
176 }
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
179
180/*
181 * Put the DEC21142 to sleep
182 */
183static void pci_fixup_dec21142(struct pci_dev *dev)
184{
185 pci_write_config_dword(dev, 0x40, 0x80000000);
186}
187DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
188
189/*
190 * The CY82C693 needs some rather major fixups to ensure that it does
191 * the right thing. Idea from the Alpha people, with a few additions.
192 *
193 * We ensure that the IDE base registers are set to 1f0/3f4 for the
194 * primary bus, and 170/374 for the secondary bus. Also, hide them
195 * from the PCI subsystem view as well so we won't try to perform
196 * our own auto-configuration on them.
197 *
198 * In addition, we ensure that the PCI IDE interrupts are routed to
199 * IRQ 14 and IRQ 15 respectively.
200 *
201 * The above gets us to a point where the IDE on this device is
202 * functional. However, The CY82C693U _does not work_ in bus
203 * master mode without locking the PCI bus solid.
204 */
205static void pci_fixup_cy82c693(struct pci_dev *dev)
206{
207 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
208 u32 base0, base1;
209
210 if (dev->class & 0x80) { /* primary */
211 base0 = 0x1f0;
212 base1 = 0x3f4;
213 } else { /* secondary */
214 base0 = 0x170;
215 base1 = 0x374;
216 }
217
218 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
219 base0 | PCI_BASE_ADDRESS_SPACE_IO);
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
221 base1 | PCI_BASE_ADDRESS_SPACE_IO);
222
223 dev->resource[0].start = 0;
224 dev->resource[0].end = 0;
225 dev->resource[0].flags = 0;
226
227 dev->resource[1].start = 0;
228 dev->resource[1].end = 0;
229 dev->resource[1].flags = 0;
230 } else if (PCI_FUNC(dev->devfn) == 0) {
231 /*
232 * Setup IDE IRQ routing.
233 */
234 pci_write_config_byte(dev, 0x4b, 14);
235 pci_write_config_byte(dev, 0x4c, 15);
236
237 /*
238 * Disable FREQACK handshake, enable USB.
239 */
240 pci_write_config_byte(dev, 0x4d, 0x41);
241
242 /*
243 * Enable PCI retry, and PCI post-write buffer.
244 */
245 pci_write_config_byte(dev, 0x44, 0x17);
246
247 /*
248 * Enable ISA master and DMA post write buffering.
249 */
250 pci_write_config_byte(dev, 0x45, 0x03);
251 }
252}
253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
254
255/*
256 * If the bus contains any of these devices, then we must not turn on
257 * parity checking of any kind. Currently this is CyberPro 20x0 only.
258 */
259static inline int pdev_bad_for_parity(struct pci_dev *dev)
260{
261 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
262 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
263 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
264 (dev->vendor == PCI_VENDOR_ID_ITE &&
265 dev->device == PCI_DEVICE_ID_ITE_8152));
266
267}
268
269/*
270 * pcibios_fixup_bus - Called after each bus is probed,
271 * but before its children are examined.
272 */
273void pcibios_fixup_bus(struct pci_bus *bus)
274{
275 struct pci_dev *dev;
276 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
277
278 /*
279 * Walk the devices on this bus, working out what we can
280 * and can't support.
281 */
282 list_for_each_entry(dev, &bus->devices, bus_list) {
283 u16 status;
284
285 pci_read_config_word(dev, PCI_STATUS, &status);
286
287 /*
288 * If any device on this bus does not support fast back
289 * to back transfers, then the bus as a whole is not able
290 * to support them. Having fast back to back transfers
291 * on saves us one PCI cycle per transaction.
292 */
293 if (!(status & PCI_STATUS_FAST_BACK))
294 features &= ~PCI_COMMAND_FAST_BACK;
295
296 if (pdev_bad_for_parity(dev))
297 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
298
299 switch (dev->class >> 8) {
300 case PCI_CLASS_BRIDGE_PCI:
301 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
302 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
303 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
304 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
305 break;
306
307 case PCI_CLASS_BRIDGE_CARDBUS:
308 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
309 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
310 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
311 break;
312 }
313 }
314
315 /*
316 * Now walk the devices again, this time setting them up.
317 */
318 list_for_each_entry(dev, &bus->devices, bus_list) {
319 u16 cmd;
320
321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
322 cmd |= features;
323 pci_write_config_word(dev, PCI_COMMAND, cmd);
324
325 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
326 L1_CACHE_BYTES >> 2);
327 }
328
329 /*
330 * Propagate the flags to the PCI bridge.
331 */
332 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
333 if (features & PCI_COMMAND_FAST_BACK)
334 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
335 if (features & PCI_COMMAND_PARITY)
336 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
337 }
338
339 /*
340 * Report what we did for this bus
341 */
342 pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
343 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
344}
345EXPORT_SYMBOL(pcibios_fixup_bus);
346
347/*
348 * Swizzle the device pin each time we cross a bridge. If a platform does
349 * not provide a swizzle function, we perform the standard PCI swizzling.
350 *
351 * The default swizzling walks up the bus tree one level at a time, applying
352 * the standard swizzle function at each step, stopping when it finds the PCI
353 * root bus. This will return the slot number of the bridge device on the
354 * root bus and the interrupt pin on that device which should correspond
355 * with the downstream device interrupt.
356 *
357 * Platforms may override this, in which case the slot and pin returned
358 * depend entirely on the platform code. However, please note that the
359 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
360 * PCI extenders, so it can not be ignored.
361 */
362static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
363{
364 struct pci_sys_data *sys = dev->sysdata;
365 int slot, oldpin = *pin;
366
367 if (sys->swizzle)
368 slot = sys->swizzle(dev, pin);
369 else
370 slot = pci_common_swizzle(dev, pin);
371
372 if (debug_pci)
373 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
374 pci_name(dev), oldpin, *pin, slot);
375
376 return slot;
377}
378
379/*
380 * Map a slot/pin to an IRQ.
381 */
382static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
383{
384 struct pci_sys_data *sys = dev->sysdata;
385 int irq = -1;
386
387 if (sys->map_irq)
388 irq = sys->map_irq(dev, slot, pin);
389
390 if (debug_pci)
391 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
392 pci_name(dev), slot, pin, irq);
393
394 return irq;
395}
396
397static int pcibios_init_resource(int busnr, struct pci_sys_data *sys,
398 int io_optional)
399{
400 int ret;
401 struct resource_entry *window;
402
403 if (list_empty(&sys->resources)) {
404 pci_add_resource_offset(&sys->resources,
405 &iomem_resource, sys->mem_offset);
406 }
407
408 /*
409 * If a platform says I/O port support is optional, we don't add
410 * the default I/O space. The platform is responsible for adding
411 * any I/O space it needs.
412 */
413 if (io_optional)
414 return 0;
415
416 resource_list_for_each_entry(window, &sys->resources)
417 if (resource_type(window->res) == IORESOURCE_IO)
418 return 0;
419
420 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
421 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
422 sys->io_res.flags = IORESOURCE_IO;
423 sys->io_res.name = sys->io_res_name;
424 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
425
426 ret = request_resource(&ioport_resource, &sys->io_res);
427 if (ret) {
428 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
429 return ret;
430 }
431 pci_add_resource_offset(&sys->resources, &sys->io_res,
432 sys->io_offset);
433
434 return 0;
435}
436
437static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
438 struct list_head *head)
439{
440 struct pci_sys_data *sys = NULL;
441 int ret;
442 int nr, busnr;
443
444 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
445 struct pci_host_bridge *bridge;
446
447 bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
448 if (WARN(!bridge, "PCI: unable to allocate bridge!"))
449 break;
450
451 sys = pci_host_bridge_priv(bridge);
452
453 sys->busnr = busnr;
454 sys->swizzle = hw->swizzle;
455 sys->map_irq = hw->map_irq;
456 INIT_LIST_HEAD(&sys->resources);
457
458 if (hw->private_data)
459 sys->private_data = hw->private_data[nr];
460
461 ret = hw->setup(nr, sys);
462
463 if (ret > 0) {
464
465 ret = pcibios_init_resource(nr, sys, hw->io_optional);
466 if (ret) {
467 pci_free_host_bridge(bridge);
468 break;
469 }
470
471 bridge->map_irq = pcibios_map_irq;
472 bridge->swizzle_irq = pcibios_swizzle;
473
474 if (hw->scan)
475 ret = hw->scan(nr, bridge);
476 else {
477 list_splice_init(&sys->resources,
478 &bridge->windows);
479 bridge->dev.parent = parent;
480 bridge->sysdata = sys;
481 bridge->busnr = sys->busnr;
482 bridge->ops = hw->ops;
483 bridge->msi = hw->msi_ctrl;
484 bridge->align_resource =
485 hw->align_resource;
486
487 ret = pci_scan_root_bus_bridge(bridge);
488 }
489
490 if (WARN(ret < 0, "PCI: unable to scan bus!")) {
491 pci_free_host_bridge(bridge);
492 break;
493 }
494
495 sys->bus = bridge->bus;
496
497 busnr = sys->bus->busn_res.end + 1;
498
499 list_add(&sys->node, head);
500 } else {
501 pci_free_host_bridge(bridge);
502 if (ret < 0)
503 break;
504 }
505 }
506}
507
508void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
509{
510 struct pci_sys_data *sys;
511 LIST_HEAD(head);
512
513 pci_add_flags(PCI_REASSIGN_ALL_BUS);
514 if (hw->preinit)
515 hw->preinit();
516 pcibios_init_hw(parent, hw, &head);
517 if (hw->postinit)
518 hw->postinit();
519
520 list_for_each_entry(sys, &head, node) {
521 struct pci_bus *bus = sys->bus;
522
523 /*
524 * We insert PCI resources into the iomem_resource and
525 * ioport_resource trees in either pci_bus_claim_resources()
526 * or pci_bus_assign_resources().
527 */
528 if (pci_has_flag(PCI_PROBE_ONLY)) {
529 pci_bus_claim_resources(bus);
530 } else {
531 struct pci_bus *child;
532
533 pci_bus_size_bridges(bus);
534 pci_bus_assign_resources(bus);
535
536 list_for_each_entry(child, &bus->children, node)
537 pcie_bus_configure_settings(child);
538 }
539
540 pci_bus_add_devices(bus);
541 }
542}
543
544#ifndef CONFIG_PCI_HOST_ITE8152
545void pcibios_set_master(struct pci_dev *dev)
546{
547 /* No special bus mastering setup handling */
548}
549#endif
550
551char * __init pcibios_setup(char *str)
552{
553 if (!strcmp(str, "debug")) {
554 debug_pci = 1;
555 return NULL;
556 }
557 return str;
558}
559
560/*
561 * From arch/i386/kernel/pci-i386.c:
562 *
563 * We need to avoid collisions with `mirrored' VGA ports
564 * and other strange ISA hardware, so we always want the
565 * addresses to be allocated in the 0x000-0x0ff region
566 * modulo 0x400.
567 *
568 * Why? Because some silly external IO cards only decode
569 * the low 10 bits of the IO address. The 0x00-0xff region
570 * is reserved for motherboard devices that decode all 16
571 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
572 * but we want to try to avoid allocating at 0x2900-0x2bff
573 * which might be mirrored at 0x0100-0x03ff..
574 */
575resource_size_t pcibios_align_resource(void *data, const struct resource *res,
576 resource_size_t size, resource_size_t align)
577{
578 struct pci_dev *dev = data;
579 resource_size_t start = res->start;
580 struct pci_host_bridge *host_bridge;
581
582 if (res->flags & IORESOURCE_IO && start & 0x300)
583 start = (start + 0x3ff) & ~0x3ff;
584
585 start = (start + align - 1) & ~(align - 1);
586
587 host_bridge = pci_find_host_bridge(dev->bus);
588
589 if (host_bridge->align_resource)
590 return host_bridge->align_resource(dev, res,
591 start, size, align);
592
593 return start;
594}
595
596void __init pci_map_io_early(unsigned long pfn)
597{
598 struct map_desc pci_io_desc = {
599 .virtual = PCI_IO_VIRT_BASE,
600 .type = MT_DEVICE,
601 .length = SZ_64K,
602 };
603
604 pci_io_desc.pfn = pfn;
605 iotable_init(&pci_io_desc, 1);
606}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * linux/arch/arm/kernel/bios32.c
4 *
5 * PCI bios-type initialisation for PCI machines
6 *
7 * Bits taken from various places.
8 */
9#include <linux/export.h>
10#include <linux/kernel.h>
11#include <linux/pci.h>
12#include <linux/slab.h>
13#include <linux/init.h>
14#include <linux/io.h>
15
16#include <asm/mach-types.h>
17#include <asm/mach/map.h>
18#include <asm/mach/pci.h>
19
20static int debug_pci;
21
22/*
23 * We can't use pci_get_device() here since we are
24 * called from interrupt context.
25 */
26static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
27{
28 struct pci_dev *dev;
29
30 list_for_each_entry(dev, &bus->devices, bus_list) {
31 u16 status;
32
33 /*
34 * ignore host bridge - we handle
35 * that separately
36 */
37 if (dev->bus->number == 0 && dev->devfn == 0)
38 continue;
39
40 pci_read_config_word(dev, PCI_STATUS, &status);
41 if (status == 0xffff)
42 continue;
43
44 if ((status & status_mask) == 0)
45 continue;
46
47 /* clear the status errors */
48 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
49
50 if (warn)
51 printk("(%s: %04X) ", pci_name(dev), status);
52 }
53
54 list_for_each_entry(dev, &bus->devices, bus_list)
55 if (dev->subordinate)
56 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
57}
58
59void pcibios_report_status(u_int status_mask, int warn)
60{
61 struct pci_bus *bus;
62
63 list_for_each_entry(bus, &pci_root_buses, node)
64 pcibios_bus_report_status(bus, status_mask, warn);
65}
66
67/*
68 * We don't use this to fix the device, but initialisation of it.
69 * It's not the correct use for this, but it works.
70 * Note that the arbiter/ISA bridge appears to be buggy, specifically in
71 * the following area:
72 * 1. park on CPU
73 * 2. ISA bridge ping-pong
74 * 3. ISA bridge master handling of target RETRY
75 *
76 * Bug 3 is responsible for the sound DMA grinding to a halt. We now
77 * live with bug 2.
78 */
79static void pci_fixup_83c553(struct pci_dev *dev)
80{
81 /*
82 * Set memory region to start at address 0, and enable IO
83 */
84 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
85 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
86
87 dev->resource[0].end -= dev->resource[0].start;
88 dev->resource[0].start = 0;
89
90 /*
91 * All memory requests from ISA to be channelled to PCI
92 */
93 pci_write_config_byte(dev, 0x48, 0xff);
94
95 /*
96 * Enable ping-pong on bus master to ISA bridge transactions.
97 * This improves the sound DMA substantially. The fixed
98 * priority arbiter also helps (see below).
99 */
100 pci_write_config_byte(dev, 0x42, 0x01);
101
102 /*
103 * Enable PCI retry
104 */
105 pci_write_config_byte(dev, 0x40, 0x22);
106
107 /*
108 * We used to set the arbiter to "park on last master" (bit
109 * 1 set), but unfortunately the CyberPro does not park the
110 * bus. We must therefore park on CPU. Unfortunately, this
111 * may trigger yet another bug in the 553.
112 */
113 pci_write_config_byte(dev, 0x83, 0x02);
114
115 /*
116 * Make the ISA DMA request lowest priority, and disable
117 * rotating priorities completely.
118 */
119 pci_write_config_byte(dev, 0x80, 0x11);
120 pci_write_config_byte(dev, 0x81, 0x00);
121
122 /*
123 * Route INTA input to IRQ 11, and set IRQ11 to be level
124 * sensitive.
125 */
126 pci_write_config_word(dev, 0x44, 0xb000);
127 outb(0x08, 0x4d1);
128}
129DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
130
131static void pci_fixup_unassign(struct pci_dev *dev)
132{
133 dev->resource[0].end -= dev->resource[0].start;
134 dev->resource[0].start = 0;
135}
136DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
137
138/*
139 * Prevent the PCI layer from seeing the resources allocated to this device
140 * if it is the host bridge by marking it as such. These resources are of
141 * no consequence to the PCI layer (they are handled elsewhere).
142 */
143static void pci_fixup_dec21285(struct pci_dev *dev)
144{
145 int i;
146
147 if (dev->devfn == 0) {
148 dev->class &= 0xff;
149 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
150 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
151 dev->resource[i].start = 0;
152 dev->resource[i].end = 0;
153 dev->resource[i].flags = 0;
154 }
155 }
156}
157DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
158
159/*
160 * PCI IDE controllers use non-standard I/O port decoding, respect it.
161 */
162static void pci_fixup_ide_bases(struct pci_dev *dev)
163{
164 struct resource *r;
165 int i;
166
167 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
168 return;
169
170 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
171 r = dev->resource + i;
172 if ((r->start & ~0x80) == 0x374) {
173 r->start |= 2;
174 r->end = r->start;
175 }
176 }
177}
178DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
179
180/*
181 * Put the DEC21142 to sleep
182 */
183static void pci_fixup_dec21142(struct pci_dev *dev)
184{
185 pci_write_config_dword(dev, 0x40, 0x80000000);
186}
187DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
188
189/*
190 * The CY82C693 needs some rather major fixups to ensure that it does
191 * the right thing. Idea from the Alpha people, with a few additions.
192 *
193 * We ensure that the IDE base registers are set to 1f0/3f4 for the
194 * primary bus, and 170/374 for the secondary bus. Also, hide them
195 * from the PCI subsystem view as well so we won't try to perform
196 * our own auto-configuration on them.
197 *
198 * In addition, we ensure that the PCI IDE interrupts are routed to
199 * IRQ 14 and IRQ 15 respectively.
200 *
201 * The above gets us to a point where the IDE on this device is
202 * functional. However, The CY82C693U _does not work_ in bus
203 * master mode without locking the PCI bus solid.
204 */
205static void pci_fixup_cy82c693(struct pci_dev *dev)
206{
207 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
208 u32 base0, base1;
209
210 if (dev->class & 0x80) { /* primary */
211 base0 = 0x1f0;
212 base1 = 0x3f4;
213 } else { /* secondary */
214 base0 = 0x170;
215 base1 = 0x374;
216 }
217
218 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
219 base0 | PCI_BASE_ADDRESS_SPACE_IO);
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
221 base1 | PCI_BASE_ADDRESS_SPACE_IO);
222
223 dev->resource[0].start = 0;
224 dev->resource[0].end = 0;
225 dev->resource[0].flags = 0;
226
227 dev->resource[1].start = 0;
228 dev->resource[1].end = 0;
229 dev->resource[1].flags = 0;
230 } else if (PCI_FUNC(dev->devfn) == 0) {
231 /*
232 * Setup IDE IRQ routing.
233 */
234 pci_write_config_byte(dev, 0x4b, 14);
235 pci_write_config_byte(dev, 0x4c, 15);
236
237 /*
238 * Disable FREQACK handshake, enable USB.
239 */
240 pci_write_config_byte(dev, 0x4d, 0x41);
241
242 /*
243 * Enable PCI retry, and PCI post-write buffer.
244 */
245 pci_write_config_byte(dev, 0x44, 0x17);
246
247 /*
248 * Enable ISA master and DMA post write buffering.
249 */
250 pci_write_config_byte(dev, 0x45, 0x03);
251 }
252}
253DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
254
255/*
256 * If the bus contains any of these devices, then we must not turn on
257 * parity checking of any kind. Currently this is CyberPro 20x0 only.
258 */
259static inline int pdev_bad_for_parity(struct pci_dev *dev)
260{
261 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
262 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
263 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
264 (dev->vendor == PCI_VENDOR_ID_ITE &&
265 dev->device == PCI_DEVICE_ID_ITE_8152));
266
267}
268
269/*
270 * pcibios_fixup_bus - Called after each bus is probed,
271 * but before its children are examined.
272 */
273void pcibios_fixup_bus(struct pci_bus *bus)
274{
275 struct pci_dev *dev;
276 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
277
278 /*
279 * Walk the devices on this bus, working out what we can
280 * and can't support.
281 */
282 list_for_each_entry(dev, &bus->devices, bus_list) {
283 u16 status;
284
285 pci_read_config_word(dev, PCI_STATUS, &status);
286
287 /*
288 * If any device on this bus does not support fast back
289 * to back transfers, then the bus as a whole is not able
290 * to support them. Having fast back to back transfers
291 * on saves us one PCI cycle per transaction.
292 */
293 if (!(status & PCI_STATUS_FAST_BACK))
294 features &= ~PCI_COMMAND_FAST_BACK;
295
296 if (pdev_bad_for_parity(dev))
297 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
298
299 switch (dev->class >> 8) {
300 case PCI_CLASS_BRIDGE_PCI:
301 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
302 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
303 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
304 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
305 break;
306
307 case PCI_CLASS_BRIDGE_CARDBUS:
308 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
309 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
310 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
311 break;
312 }
313 }
314
315 /*
316 * Now walk the devices again, this time setting them up.
317 */
318 list_for_each_entry(dev, &bus->devices, bus_list) {
319 u16 cmd;
320
321 pci_read_config_word(dev, PCI_COMMAND, &cmd);
322 cmd |= features;
323 pci_write_config_word(dev, PCI_COMMAND, cmd);
324
325 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
326 L1_CACHE_BYTES >> 2);
327 }
328
329 /*
330 * Propagate the flags to the PCI bridge.
331 */
332 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
333 if (features & PCI_COMMAND_FAST_BACK)
334 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
335 if (features & PCI_COMMAND_PARITY)
336 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
337 }
338
339 /*
340 * Report what we did for this bus
341 */
342 pr_info("PCI: bus%d: Fast back to back transfers %sabled\n",
343 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
344}
345EXPORT_SYMBOL(pcibios_fixup_bus);
346
347/*
348 * Swizzle the device pin each time we cross a bridge. If a platform does
349 * not provide a swizzle function, we perform the standard PCI swizzling.
350 *
351 * The default swizzling walks up the bus tree one level at a time, applying
352 * the standard swizzle function at each step, stopping when it finds the PCI
353 * root bus. This will return the slot number of the bridge device on the
354 * root bus and the interrupt pin on that device which should correspond
355 * with the downstream device interrupt.
356 *
357 * Platforms may override this, in which case the slot and pin returned
358 * depend entirely on the platform code. However, please note that the
359 * PCI standard swizzle is implemented on plug-in cards and Cardbus based
360 * PCI extenders, so it can not be ignored.
361 */
362static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
363{
364 struct pci_sys_data *sys = dev->sysdata;
365 int slot, oldpin = *pin;
366
367 if (sys->swizzle)
368 slot = sys->swizzle(dev, pin);
369 else
370 slot = pci_common_swizzle(dev, pin);
371
372 if (debug_pci)
373 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
374 pci_name(dev), oldpin, *pin, slot);
375
376 return slot;
377}
378
379/*
380 * Map a slot/pin to an IRQ.
381 */
382static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
383{
384 struct pci_sys_data *sys = dev->sysdata;
385 int irq = -1;
386
387 if (sys->map_irq)
388 irq = sys->map_irq(dev, slot, pin);
389
390 if (debug_pci)
391 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
392 pci_name(dev), slot, pin, irq);
393
394 return irq;
395}
396
397static int pcibios_init_resource(int busnr, struct pci_sys_data *sys)
398{
399 int ret;
400 struct resource_entry *window;
401
402 if (list_empty(&sys->resources)) {
403 pci_add_resource_offset(&sys->resources,
404 &iomem_resource, sys->mem_offset);
405 }
406
407 resource_list_for_each_entry(window, &sys->resources)
408 if (resource_type(window->res) == IORESOURCE_IO)
409 return 0;
410
411 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
412 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
413 sys->io_res.flags = IORESOURCE_IO;
414 sys->io_res.name = sys->io_res_name;
415 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
416
417 ret = request_resource(&ioport_resource, &sys->io_res);
418 if (ret) {
419 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
420 return ret;
421 }
422 pci_add_resource_offset(&sys->resources, &sys->io_res,
423 sys->io_offset);
424
425 return 0;
426}
427
428static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
429 struct list_head *head)
430{
431 struct pci_sys_data *sys = NULL;
432 int ret;
433 int nr, busnr;
434
435 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
436 struct pci_host_bridge *bridge;
437
438 bridge = pci_alloc_host_bridge(sizeof(struct pci_sys_data));
439 if (WARN(!bridge, "PCI: unable to allocate bridge!"))
440 break;
441
442 sys = pci_host_bridge_priv(bridge);
443
444 sys->busnr = busnr;
445 sys->swizzle = hw->swizzle;
446 sys->map_irq = hw->map_irq;
447 INIT_LIST_HEAD(&sys->resources);
448
449 if (hw->private_data)
450 sys->private_data = hw->private_data[nr];
451
452 ret = hw->setup(nr, sys);
453
454 if (ret > 0) {
455
456 ret = pcibios_init_resource(nr, sys);
457 if (ret) {
458 pci_free_host_bridge(bridge);
459 break;
460 }
461
462 bridge->map_irq = pcibios_map_irq;
463 bridge->swizzle_irq = pcibios_swizzle;
464
465 if (hw->scan)
466 ret = hw->scan(nr, bridge);
467 else {
468 list_splice_init(&sys->resources,
469 &bridge->windows);
470 bridge->dev.parent = parent;
471 bridge->sysdata = sys;
472 bridge->busnr = sys->busnr;
473 bridge->ops = hw->ops;
474
475 ret = pci_scan_root_bus_bridge(bridge);
476 }
477
478 if (WARN(ret < 0, "PCI: unable to scan bus!")) {
479 pci_free_host_bridge(bridge);
480 break;
481 }
482
483 sys->bus = bridge->bus;
484
485 busnr = sys->bus->busn_res.end + 1;
486
487 list_add(&sys->node, head);
488 } else {
489 pci_free_host_bridge(bridge);
490 if (ret < 0)
491 break;
492 }
493 }
494}
495
496void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
497{
498 struct pci_sys_data *sys;
499 LIST_HEAD(head);
500
501 pci_add_flags(PCI_REASSIGN_ALL_BUS);
502 if (hw->preinit)
503 hw->preinit();
504 pcibios_init_hw(parent, hw, &head);
505 if (hw->postinit)
506 hw->postinit();
507
508 list_for_each_entry(sys, &head, node) {
509 struct pci_bus *bus = sys->bus;
510
511 /*
512 * We insert PCI resources into the iomem_resource and
513 * ioport_resource trees in either pci_bus_claim_resources()
514 * or pci_bus_assign_resources().
515 */
516 if (pci_has_flag(PCI_PROBE_ONLY)) {
517 pci_bus_claim_resources(bus);
518 } else {
519 struct pci_bus *child;
520
521 pci_bus_size_bridges(bus);
522 pci_bus_assign_resources(bus);
523
524 list_for_each_entry(child, &bus->children, node)
525 pcie_bus_configure_settings(child);
526 }
527
528 pci_bus_add_devices(bus);
529 }
530}
531
532#ifndef CONFIG_PCI_HOST_ITE8152
533void pcibios_set_master(struct pci_dev *dev)
534{
535 /* No special bus mastering setup handling */
536}
537#endif
538
539char * __init pcibios_setup(char *str)
540{
541 if (!strcmp(str, "debug")) {
542 debug_pci = 1;
543 return NULL;
544 }
545 return str;
546}
547
548/*
549 * From arch/i386/kernel/pci-i386.c:
550 *
551 * We need to avoid collisions with `mirrored' VGA ports
552 * and other strange ISA hardware, so we always want the
553 * addresses to be allocated in the 0x000-0x0ff region
554 * modulo 0x400.
555 *
556 * Why? Because some silly external IO cards only decode
557 * the low 10 bits of the IO address. The 0x00-0xff region
558 * is reserved for motherboard devices that decode all 16
559 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
560 * but we want to try to avoid allocating at 0x2900-0x2bff
561 * which might be mirrored at 0x0100-0x03ff..
562 */
563resource_size_t pcibios_align_resource(void *data, const struct resource *res,
564 resource_size_t size, resource_size_t align)
565{
566 struct pci_dev *dev = data;
567 resource_size_t start = res->start;
568 struct pci_host_bridge *host_bridge;
569
570 if (res->flags & IORESOURCE_IO && start & 0x300)
571 start = (start + 0x3ff) & ~0x3ff;
572
573 start = (start + align - 1) & ~(align - 1);
574
575 host_bridge = pci_find_host_bridge(dev->bus);
576
577 if (host_bridge->align_resource)
578 return host_bridge->align_resource(dev, res,
579 start, size, align);
580
581 return start;
582}
583
584void __init pci_map_io_early(unsigned long pfn)
585{
586 struct map_desc pci_io_desc = {
587 .virtual = PCI_IO_VIRT_BASE,
588 .type = MT_DEVICE,
589 .length = SZ_64K,
590 };
591
592 pci_io_desc.pfn = pfn;
593 iotable_init(&pci_io_desc, 1);
594}