Loading...
Note: File does not exist in v4.6.
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Ice Lake PCH pinctrl/GPIO driver
4 *
5 * Copyright (C) 2018, Intel Corporation
6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7 * Mika Westerberg <mika.westerberg@linux.intel.com>
8 */
9
10#include <linux/acpi.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13
14#include <linux/pinctrl/pinctrl.h>
15
16#include "pinctrl-intel.h"
17
18#define ICL_PAD_OWN 0x020
19#define ICL_PADCFGLOCK 0x080
20#define ICL_HOSTSW_OWN 0x0b0
21#define ICL_GPI_IS 0x100
22#define ICL_GPI_IE 0x110
23
24#define ICL_GPP(r, s, e, g) \
25 { \
26 .reg_num = (r), \
27 .base = (s), \
28 .size = ((e) - (s) + 1), \
29 .gpio_base = (g), \
30 }
31
32#define ICL_COMMUNITY(b, s, e, g) \
33 { \
34 .barno = (b), \
35 .padown_offset = ICL_PAD_OWN, \
36 .padcfglock_offset = ICL_PADCFGLOCK, \
37 .hostown_offset = ICL_HOSTSW_OWN, \
38 .is_offset = ICL_GPI_IS, \
39 .ie_offset = ICL_GPI_IE, \
40 .pin_base = (s), \
41 .npins = ((e) - (s) + 1), \
42 .gpps = (g), \
43 .ngpps = ARRAY_SIZE(g), \
44 }
45
46/* Ice Lake-LP */
47static const struct pinctrl_pin_desc icllp_pins[] = {
48 /* GPP_G */
49 PINCTRL_PIN(0, "SD3_CMD"),
50 PINCTRL_PIN(1, "SD3_D0"),
51 PINCTRL_PIN(2, "SD3_D1"),
52 PINCTRL_PIN(3, "SD3_D2"),
53 PINCTRL_PIN(4, "SD3_D3"),
54 PINCTRL_PIN(5, "SD3_CDB"),
55 PINCTRL_PIN(6, "SD3_CLK"),
56 PINCTRL_PIN(7, "SD3_WP"),
57 /* GPP_B */
58 PINCTRL_PIN(8, "CORE_VID_0"),
59 PINCTRL_PIN(9, "CORE_VID_1"),
60 PINCTRL_PIN(10, "VRALERTB"),
61 PINCTRL_PIN(11, "CPU_GP_2"),
62 PINCTRL_PIN(12, "CPU_GP_3"),
63 PINCTRL_PIN(13, "ISH_I2C0_SDA"),
64 PINCTRL_PIN(14, "ISH_I2C0_SCL"),
65 PINCTRL_PIN(15, "ISH_I2C1_SDA"),
66 PINCTRL_PIN(16, "ISH_I2C1_SCL"),
67 PINCTRL_PIN(17, "I2C5_SDA"),
68 PINCTRL_PIN(18, "I2C5_SCL"),
69 PINCTRL_PIN(19, "PMCALERTB"),
70 PINCTRL_PIN(20, "SLP_S0B"),
71 PINCTRL_PIN(21, "PLTRSTB"),
72 PINCTRL_PIN(22, "SPKR"),
73 PINCTRL_PIN(23, "GSPI0_CS0B"),
74 PINCTRL_PIN(24, "GSPI0_CLK"),
75 PINCTRL_PIN(25, "GSPI0_MISO"),
76 PINCTRL_PIN(26, "GSPI0_MOSI"),
77 PINCTRL_PIN(27, "GSPI1_CS0B"),
78 PINCTRL_PIN(28, "GSPI1_CLK"),
79 PINCTRL_PIN(29, "GSPI1_MISO"),
80 PINCTRL_PIN(30, "GSPI1_MOSI"),
81 PINCTRL_PIN(31, "SML1ALERTB"),
82 PINCTRL_PIN(32, "GSPI0_CLK_LOOPBK"),
83 PINCTRL_PIN(33, "GSPI1_CLK_LOOPBK"),
84 /* GPP_A */
85 PINCTRL_PIN(34, "ESPI_IO_0"),
86 PINCTRL_PIN(35, "ESPI_IO_1"),
87 PINCTRL_PIN(36, "ESPI_IO_2"),
88 PINCTRL_PIN(37, "ESPI_IO_3"),
89 PINCTRL_PIN(38, "ESPI_CSB"),
90 PINCTRL_PIN(39, "ESPI_CLK"),
91 PINCTRL_PIN(40, "ESPI_RESETB"),
92 PINCTRL_PIN(41, "I2S2_SCLK"),
93 PINCTRL_PIN(42, "I2S2_SFRM"),
94 PINCTRL_PIN(43, "I2S2_TXD"),
95 PINCTRL_PIN(44, "I2S2_RXD"),
96 PINCTRL_PIN(45, "SATA_DEVSLP_2"),
97 PINCTRL_PIN(46, "SATAXPCIE_1"),
98 PINCTRL_PIN(47, "SATAXPCIE_2"),
99 PINCTRL_PIN(48, "USB2_OCB_1"),
100 PINCTRL_PIN(49, "USB2_OCB_2"),
101 PINCTRL_PIN(50, "USB2_OCB_3"),
102 PINCTRL_PIN(51, "DDSP_HPD_C"),
103 PINCTRL_PIN(52, "DDSP_HPD_B"),
104 PINCTRL_PIN(53, "DDSP_HPD_1"),
105 PINCTRL_PIN(54, "DDSP_HPD_2"),
106 PINCTRL_PIN(55, "I2S5_TXD"),
107 PINCTRL_PIN(56, "I2S5_RXD"),
108 PINCTRL_PIN(57, "I2S1_SCLK"),
109 PINCTRL_PIN(58, "ESPI_CLK_LOOPBK"),
110 /* GPP_H */
111 PINCTRL_PIN(59, "SD_1P8_SEL"),
112 PINCTRL_PIN(60, "SD_PWR_EN_B"),
113 PINCTRL_PIN(61, "GPPC_H_2"),
114 PINCTRL_PIN(62, "SX_EXIT_HOLDOFFB"),
115 PINCTRL_PIN(63, "I2C2_SDA"),
116 PINCTRL_PIN(64, "I2C2_SCL"),
117 PINCTRL_PIN(65, "I2C3_SDA"),
118 PINCTRL_PIN(66, "I2C3_SCL"),
119 PINCTRL_PIN(67, "I2C4_SDA"),
120 PINCTRL_PIN(68, "I2C4_SCL"),
121 PINCTRL_PIN(69, "SRCCLKREQB_4"),
122 PINCTRL_PIN(70, "SRCCLKREQB_5"),
123 PINCTRL_PIN(71, "M2_SKT2_CFG_0"),
124 PINCTRL_PIN(72, "M2_SKT2_CFG_1"),
125 PINCTRL_PIN(73, "M2_SKT2_CFG_2"),
126 PINCTRL_PIN(74, "M2_SKT2_CFG_3"),
127 PINCTRL_PIN(75, "DDPB_CTRLCLK"),
128 PINCTRL_PIN(76, "DDPB_CTRLDATA"),
129 PINCTRL_PIN(77, "CPU_VCCIO_PWR_GATEB"),
130 PINCTRL_PIN(78, "TIME_SYNC_0"),
131 PINCTRL_PIN(79, "IMGCLKOUT_1"),
132 PINCTRL_PIN(80, "IMGCLKOUT_2"),
133 PINCTRL_PIN(81, "IMGCLKOUT_3"),
134 PINCTRL_PIN(82, "IMGCLKOUT_4"),
135 /* GPP_D */
136 PINCTRL_PIN(83, "ISH_GP_0"),
137 PINCTRL_PIN(84, "ISH_GP_1"),
138 PINCTRL_PIN(85, "ISH_GP_2"),
139 PINCTRL_PIN(86, "ISH_GP_3"),
140 PINCTRL_PIN(87, "IMGCLKOUT_0"),
141 PINCTRL_PIN(88, "SRCCLKREQB_0"),
142 PINCTRL_PIN(89, "SRCCLKREQB_1"),
143 PINCTRL_PIN(90, "SRCCLKREQB_2"),
144 PINCTRL_PIN(91, "SRCCLKREQB_3"),
145 PINCTRL_PIN(92, "ISH_SPI_CSB"),
146 PINCTRL_PIN(93, "ISH_SPI_CLK"),
147 PINCTRL_PIN(94, "ISH_SPI_MISO"),
148 PINCTRL_PIN(95, "ISH_SPI_MOSI"),
149 PINCTRL_PIN(96, "ISH_UART0_RXD"),
150 PINCTRL_PIN(97, "ISH_UART0_TXD"),
151 PINCTRL_PIN(98, "ISH_UART0_RTSB"),
152 PINCTRL_PIN(99, "ISH_UART0_CTSB"),
153 PINCTRL_PIN(100, "ISH_GP_4"),
154 PINCTRL_PIN(101, "ISH_GP_5"),
155 PINCTRL_PIN(102, "I2S_MCLK"),
156 PINCTRL_PIN(103, "GSPI2_CLK_LOOPBK"),
157 /* GPP_F */
158 PINCTRL_PIN(104, "CNV_BRI_DT"),
159 PINCTRL_PIN(105, "CNV_BRI_RSP"),
160 PINCTRL_PIN(106, "CNV_RGI_DT"),
161 PINCTRL_PIN(107, "CNV_RGI_RSP"),
162 PINCTRL_PIN(108, "CNV_RF_RESET_B"),
163 PINCTRL_PIN(109, "EMMC_HIP_MON"),
164 PINCTRL_PIN(110, "CNV_PA_BLANKING"),
165 PINCTRL_PIN(111, "EMMC_CMD"),
166 PINCTRL_PIN(112, "EMMC_DATA0"),
167 PINCTRL_PIN(113, "EMMC_DATA1"),
168 PINCTRL_PIN(114, "EMMC_DATA2"),
169 PINCTRL_PIN(115, "EMMC_DATA3"),
170 PINCTRL_PIN(116, "EMMC_DATA4"),
171 PINCTRL_PIN(117, "EMMC_DATA5"),
172 PINCTRL_PIN(118, "EMMC_DATA6"),
173 PINCTRL_PIN(119, "EMMC_DATA7"),
174 PINCTRL_PIN(120, "EMMC_RCLK"),
175 PINCTRL_PIN(121, "EMMC_CLK"),
176 PINCTRL_PIN(122, "EMMC_RESETB"),
177 PINCTRL_PIN(123, "A4WP_PRESENT"),
178 /* vGPIO */
179 PINCTRL_PIN(124, "CNV_BTEN"),
180 PINCTRL_PIN(125, "CNV_WCEN"),
181 PINCTRL_PIN(126, "CNV_BT_HOST_WAKEB"),
182 PINCTRL_PIN(127, "CNV_BT_IF_SELECT"),
183 PINCTRL_PIN(128, "vCNV_BT_UART_TXD"),
184 PINCTRL_PIN(129, "vCNV_BT_UART_RXD"),
185 PINCTRL_PIN(130, "vCNV_BT_UART_CTS_B"),
186 PINCTRL_PIN(131, "vCNV_BT_UART_RTS_B"),
187 PINCTRL_PIN(132, "vCNV_MFUART1_TXD"),
188 PINCTRL_PIN(133, "vCNV_MFUART1_RXD"),
189 PINCTRL_PIN(134, "vCNV_MFUART1_CTS_B"),
190 PINCTRL_PIN(135, "vCNV_MFUART1_RTS_B"),
191 PINCTRL_PIN(136, "vUART0_TXD"),
192 PINCTRL_PIN(137, "vUART0_RXD"),
193 PINCTRL_PIN(138, "vUART0_CTS_B"),
194 PINCTRL_PIN(139, "vUART0_RTS_B"),
195 PINCTRL_PIN(140, "vISH_UART0_TXD"),
196 PINCTRL_PIN(141, "vISH_UART0_RXD"),
197 PINCTRL_PIN(142, "vISH_UART0_CTS_B"),
198 PINCTRL_PIN(143, "vISH_UART0_RTS_B"),
199 PINCTRL_PIN(144, "vCNV_BT_I2S_BCLK"),
200 PINCTRL_PIN(145, "vCNV_BT_I2S_WS_SYNC"),
201 PINCTRL_PIN(146, "vCNV_BT_I2S_SDO"),
202 PINCTRL_PIN(147, "vCNV_BT_I2S_SDI"),
203 PINCTRL_PIN(148, "vI2S2_SCLK"),
204 PINCTRL_PIN(149, "vI2S2_SFRM"),
205 PINCTRL_PIN(150, "vI2S2_TXD"),
206 PINCTRL_PIN(151, "vI2S2_RXD"),
207 PINCTRL_PIN(152, "vSD3_CD_B"),
208 /* GPP_C */
209 PINCTRL_PIN(153, "SMBCLK"),
210 PINCTRL_PIN(154, "SMBDATA"),
211 PINCTRL_PIN(155, "SMBALERTB"),
212 PINCTRL_PIN(156, "SML0CLK"),
213 PINCTRL_PIN(157, "SML0DATA"),
214 PINCTRL_PIN(158, "SML0ALERTB"),
215 PINCTRL_PIN(159, "SML1CLK"),
216 PINCTRL_PIN(160, "SML1DATA"),
217 PINCTRL_PIN(161, "UART0_RXD"),
218 PINCTRL_PIN(162, "UART0_TXD"),
219 PINCTRL_PIN(163, "UART0_RTSB"),
220 PINCTRL_PIN(164, "UART0_CTSB"),
221 PINCTRL_PIN(165, "UART1_RXD"),
222 PINCTRL_PIN(166, "UART1_TXD"),
223 PINCTRL_PIN(167, "UART1_RTSB"),
224 PINCTRL_PIN(168, "UART1_CTSB"),
225 PINCTRL_PIN(169, "I2C0_SDA"),
226 PINCTRL_PIN(170, "I2C0_SCL"),
227 PINCTRL_PIN(171, "I2C1_SDA"),
228 PINCTRL_PIN(172, "I2C1_SCL"),
229 PINCTRL_PIN(173, "UART2_RXD"),
230 PINCTRL_PIN(174, "UART2_TXD"),
231 PINCTRL_PIN(175, "UART2_RTSB"),
232 PINCTRL_PIN(176, "UART2_CTSB"),
233 /* HVCMOS */
234 PINCTRL_PIN(177, "L_BKLTEN"),
235 PINCTRL_PIN(178, "L_BKLTCTL"),
236 PINCTRL_PIN(179, "L_VDDEN"),
237 PINCTRL_PIN(180, "SYS_PWROK"),
238 PINCTRL_PIN(181, "SYS_RESETB"),
239 PINCTRL_PIN(182, "MLK_RSTB"),
240 /* GPP_E */
241 PINCTRL_PIN(183, "SATAXPCIE_0"),
242 PINCTRL_PIN(184, "SPI1_IO_2"),
243 PINCTRL_PIN(185, "SPI1_IO_3"),
244 PINCTRL_PIN(186, "CPU_GP_0"),
245 PINCTRL_PIN(187, "SATA_DEVSLP_0"),
246 PINCTRL_PIN(188, "SATA_DEVSLP_1"),
247 PINCTRL_PIN(189, "GPPC_E_6"),
248 PINCTRL_PIN(190, "CPU_GP_1"),
249 PINCTRL_PIN(191, "SATA_LEDB"),
250 PINCTRL_PIN(192, "USB2_OCB_0"),
251 PINCTRL_PIN(193, "SPI1_CSB"),
252 PINCTRL_PIN(194, "SPI1_CLK"),
253 PINCTRL_PIN(195, "SPI1_MISO_IO_1"),
254 PINCTRL_PIN(196, "SPI1_MOSI_IO_0"),
255 PINCTRL_PIN(197, "DDSP_HPD_A"),
256 PINCTRL_PIN(198, "ISH_GP_6"),
257 PINCTRL_PIN(199, "ISH_GP_7"),
258 PINCTRL_PIN(200, "DISP_MISC_4"),
259 PINCTRL_PIN(201, "DDP1_CTRLCLK"),
260 PINCTRL_PIN(202, "DDP1_CTRLDATA"),
261 PINCTRL_PIN(203, "DDP2_CTRLCLK"),
262 PINCTRL_PIN(204, "DDP2_CTRLDATA"),
263 PINCTRL_PIN(205, "DDPA_CTRLCLK"),
264 PINCTRL_PIN(206, "DDPA_CTRLDATA"),
265 /* JTAG */
266 PINCTRL_PIN(207, "JTAG_TDO"),
267 PINCTRL_PIN(208, "JTAGX"),
268 PINCTRL_PIN(209, "PRDYB"),
269 PINCTRL_PIN(210, "PREQB"),
270 PINCTRL_PIN(211, "CPU_TRSTB"),
271 PINCTRL_PIN(212, "JTAG_TDI"),
272 PINCTRL_PIN(213, "JTAG_TMS"),
273 PINCTRL_PIN(214, "JTAG_TCK"),
274 PINCTRL_PIN(215, "ITP_PMODE"),
275 /* GPP_R */
276 PINCTRL_PIN(216, "HDA_BCLK"),
277 PINCTRL_PIN(217, "HDA_SYNC"),
278 PINCTRL_PIN(218, "HDA_SDO"),
279 PINCTRL_PIN(219, "HDA_SDI_0"),
280 PINCTRL_PIN(220, "HDA_RSTB"),
281 PINCTRL_PIN(221, "HDA_SDI_1"),
282 PINCTRL_PIN(222, "I2S1_TXD"),
283 PINCTRL_PIN(223, "I2S1_RXD"),
284 /* GPP_S */
285 PINCTRL_PIN(224, "SNDW1_CLK"),
286 PINCTRL_PIN(225, "SNDW1_DATA"),
287 PINCTRL_PIN(226, "SNDW2_CLK"),
288 PINCTRL_PIN(227, "SNDW2_DATA"),
289 PINCTRL_PIN(228, "SNDW3_CLK"),
290 PINCTRL_PIN(229, "SNDW3_DATA"),
291 PINCTRL_PIN(230, "SNDW4_CLK"),
292 PINCTRL_PIN(231, "SNDW4_DATA"),
293 /* SPI */
294 PINCTRL_PIN(232, "SPI0_IO_2"),
295 PINCTRL_PIN(233, "SPI0_IO_3"),
296 PINCTRL_PIN(234, "SPI0_MOSI_IO_0"),
297 PINCTRL_PIN(235, "SPI0_MISO_IO_1"),
298 PINCTRL_PIN(236, "SPI0_TPM_CSB"),
299 PINCTRL_PIN(237, "SPI0_FLASH_0_CSB"),
300 PINCTRL_PIN(238, "SPI0_FLASH_1_CSB"),
301 PINCTRL_PIN(239, "SPI0_CLK"),
302 PINCTRL_PIN(240, "SPI0_CLK_LOOPBK"),
303};
304
305static const struct intel_padgroup icllp_community0_gpps[] = {
306 ICL_GPP(0, 0, 7, 0), /* GPP_G */
307 ICL_GPP(1, 8, 33, 32), /* GPP_B */
308 ICL_GPP(2, 34, 58, 64), /* GPP_A */
309};
310
311static const struct intel_padgroup icllp_community1_gpps[] = {
312 ICL_GPP(0, 59, 82, 96), /* GPP_H */
313 ICL_GPP(1, 83, 103, 128), /* GPP_D */
314 ICL_GPP(2, 104, 123, 160), /* GPP_F */
315 ICL_GPP(3, 124, 152, 192), /* vGPIO */
316};
317
318static const struct intel_padgroup icllp_community4_gpps[] = {
319 ICL_GPP(0, 153, 176, 224), /* GPP_C */
320 ICL_GPP(1, 177, 182, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */
321 ICL_GPP(2, 183, 206, 256), /* GPP_E */
322 ICL_GPP(3, 207, 215, INTEL_GPIO_BASE_NOMAP), /* JTAG */
323};
324
325static const struct intel_padgroup icllp_community5_gpps[] = {
326 ICL_GPP(0, 216, 223, 288), /* GPP_R */
327 ICL_GPP(1, 224, 231, 320), /* GPP_S */
328 ICL_GPP(2, 232, 240, INTEL_GPIO_BASE_NOMAP), /* SPI */
329};
330
331static const struct intel_community icllp_communities[] = {
332 ICL_COMMUNITY(0, 0, 58, icllp_community0_gpps),
333 ICL_COMMUNITY(1, 59, 152, icllp_community1_gpps),
334 ICL_COMMUNITY(2, 153, 215, icllp_community4_gpps),
335 ICL_COMMUNITY(3, 216, 240, icllp_community5_gpps),
336};
337
338static const unsigned int icllp_spi0_pins[] = { 22, 23, 24, 25, 26 };
339static const unsigned int icllp_spi0_modes[] = { 3, 1, 1, 1, 1 };
340static const unsigned int icllp_spi1_pins[] = { 27, 28, 29, 30, 31 };
341static const unsigned int icllp_spi1_modes[] = { 1, 1, 1, 1, 3 };
342static const unsigned int icllp_spi2_pins[] = { 92, 93, 94, 95, 98 };
343static const unsigned int icllp_spi2_modes[] = { 3, 3, 3, 3, 2 };
344
345static const unsigned int icllp_i2c0_pins[] = { 169, 170 };
346static const unsigned int icllp_i2c1_pins[] = { 171, 172 };
347static const unsigned int icllp_i2c2_pins[] = { 63, 64 };
348static const unsigned int icllp_i2c3_pins[] = { 65, 66 };
349static const unsigned int icllp_i2c4_pins[] = { 67, 68 };
350
351static const unsigned int icllp_uart0_pins[] = { 161, 162, 163, 164 };
352static const unsigned int icllp_uart1_pins[] = { 165, 166, 167, 168 };
353static const unsigned int icllp_uart2_pins[] = { 173, 174, 175, 176 };
354
355static const struct intel_pingroup icllp_groups[] = {
356 PIN_GROUP("spi0_grp", icllp_spi0_pins, icllp_spi0_modes),
357 PIN_GROUP("spi1_grp", icllp_spi1_pins, icllp_spi1_modes),
358 PIN_GROUP("spi2_grp", icllp_spi2_pins, icllp_spi2_modes),
359 PIN_GROUP("i2c0_grp", icllp_i2c0_pins, 1),
360 PIN_GROUP("i2c1_grp", icllp_i2c1_pins, 1),
361 PIN_GROUP("i2c2_grp", icllp_i2c2_pins, 1),
362 PIN_GROUP("i2c3_grp", icllp_i2c3_pins, 1),
363 PIN_GROUP("i2c4_grp", icllp_i2c4_pins, 1),
364 PIN_GROUP("uart0_grp", icllp_uart0_pins, 1),
365 PIN_GROUP("uart1_grp", icllp_uart1_pins, 1),
366 PIN_GROUP("uart2_grp", icllp_uart2_pins, 1),
367};
368
369static const char * const icllp_spi0_groups[] = { "spi0_grp" };
370static const char * const icllp_spi1_groups[] = { "spi1_grp" };
371static const char * const icllp_spi2_groups[] = { "spi2_grp" };
372static const char * const icllp_i2c0_groups[] = { "i2c0_grp" };
373static const char * const icllp_i2c1_groups[] = { "i2c1_grp" };
374static const char * const icllp_i2c2_groups[] = { "i2c2_grp" };
375static const char * const icllp_i2c3_groups[] = { "i2c3_grp" };
376static const char * const icllp_i2c4_groups[] = { "i2c4_grp" };
377static const char * const icllp_uart0_groups[] = { "uart0_grp" };
378static const char * const icllp_uart1_groups[] = { "uart1_grp" };
379static const char * const icllp_uart2_groups[] = { "uart2_grp" };
380
381static const struct intel_function icllp_functions[] = {
382 FUNCTION("spi0", icllp_spi0_groups),
383 FUNCTION("spi1", icllp_spi1_groups),
384 FUNCTION("spi2", icllp_spi2_groups),
385 FUNCTION("i2c0", icllp_i2c0_groups),
386 FUNCTION("i2c1", icllp_i2c1_groups),
387 FUNCTION("i2c2", icllp_i2c2_groups),
388 FUNCTION("i2c3", icllp_i2c3_groups),
389 FUNCTION("i2c4", icllp_i2c4_groups),
390 FUNCTION("uart0", icllp_uart0_groups),
391 FUNCTION("uart1", icllp_uart1_groups),
392 FUNCTION("uart2", icllp_uart2_groups),
393};
394
395static const struct intel_pinctrl_soc_data icllp_soc_data = {
396 .pins = icllp_pins,
397 .npins = ARRAY_SIZE(icllp_pins),
398 .groups = icllp_groups,
399 .ngroups = ARRAY_SIZE(icllp_groups),
400 .functions = icllp_functions,
401 .nfunctions = ARRAY_SIZE(icllp_functions),
402 .communities = icllp_communities,
403 .ncommunities = ARRAY_SIZE(icllp_communities),
404};
405
406static INTEL_PINCTRL_PM_OPS(icl_pinctrl_pm_ops);
407
408static const struct acpi_device_id icl_pinctrl_acpi_match[] = {
409 { "INT3455", (kernel_ulong_t)&icllp_soc_data },
410 { }
411};
412MODULE_DEVICE_TABLE(acpi, icl_pinctrl_acpi_match);
413
414static struct platform_driver icl_pinctrl_driver = {
415 .probe = intel_pinctrl_probe_by_hid,
416 .driver = {
417 .name = "icelake-pinctrl",
418 .acpi_match_table = icl_pinctrl_acpi_match,
419 .pm = &icl_pinctrl_pm_ops,
420 },
421};
422
423module_platform_driver(icl_pinctrl_driver);
424
425MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
426MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
427MODULE_DESCRIPTION("Intel Ice Lake PCH pinctrl/GPIO driver");
428MODULE_LICENSE("GPL v2");