1/*
  2 * JZ4780 NAND driver
  3 *
  4 * Copyright (c) 2015 Imagination Technologies
  5 * Author: Alex Smith <alex.smith@imgtec.com>
  6 *
  7 * This program is free software; you can redistribute it and/or modify it
  8 * under the terms of the GNU General Public License version 2 as published
  9 * by the Free Software Foundation.
 10 */
 11
 12#include <linux/delay.h>
 13#include <linux/init.h>
 14#include <linux/io.h>
 15#include <linux/list.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/of_address.h>
 19#include <linux/gpio/consumer.h>
 20#include <linux/of_mtd.h>
 21#include <linux/platform_device.h>
 22#include <linux/slab.h>
 23#include <linux/mtd/mtd.h>
 24#include <linux/mtd/nand.h>
 25#include <linux/mtd/partitions.h>
 26
 27#include <linux/jz4780-nemc.h>
 28
 29#include "jz4780_bch.h"
 30
 31#define DRV_NAME	"jz4780-nand"
 32
 33#define OFFSET_DATA	0x00000000
 34#define OFFSET_CMD	0x00400000
 35#define OFFSET_ADDR	0x00800000
 36
 37/* Command delay when there is no R/B pin. */
 38#define RB_DELAY_US	100
 39
 40struct jz4780_nand_cs {
 41	unsigned int bank;
 42	void __iomem *base;
 43};
 44
 45struct jz4780_nand_controller {
 46	struct device *dev;
 47	struct jz4780_bch *bch;
 48	struct nand_hw_control controller;
 49	unsigned int num_banks;
 50	struct list_head chips;
 51	int selected;
 52	struct jz4780_nand_cs cs[];
 53};
 54
 55struct jz4780_nand_chip {
 56	struct nand_chip chip;
 57	struct list_head chip_list;
 58
 59	struct nand_ecclayout ecclayout;
 60
 61	struct gpio_desc *busy_gpio;
 62	struct gpio_desc *wp_gpio;
 63	unsigned int reading: 1;
 64};
 65
 66static inline struct jz4780_nand_chip *to_jz4780_nand_chip(struct mtd_info *mtd)
 67{
 68	return container_of(mtd_to_nand(mtd), struct jz4780_nand_chip, chip);
 69}
 70
 71static inline struct jz4780_nand_controller *to_jz4780_nand_controller(struct nand_hw_control *ctrl)
 72{
 73	return container_of(ctrl, struct jz4780_nand_controller, controller);
 74}
 75
 76static void jz4780_nand_select_chip(struct mtd_info *mtd, int chipnr)
 77{
 78	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 79	struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
 80	struct jz4780_nand_cs *cs;
 81
 82	/* Ensure the currently selected chip is deasserted. */
 83	if (chipnr == -1 && nfc->selected >= 0) {
 84		cs = &nfc->cs[nfc->selected];
 85		jz4780_nemc_assert(nfc->dev, cs->bank, false);
 86	}
 87
 88	nfc->selected = chipnr;
 89}
 90
 91static void jz4780_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 92				 unsigned int ctrl)
 93{
 94	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
 95	struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
 96	struct jz4780_nand_cs *cs;
 97
 98	if (WARN_ON(nfc->selected < 0))
 99		return;
100
101	cs = &nfc->cs[nfc->selected];
102
103	jz4780_nemc_assert(nfc->dev, cs->bank, ctrl & NAND_NCE);
104
105	if (cmd == NAND_CMD_NONE)
106		return;
107
108	if (ctrl & NAND_ALE)
109		writeb(cmd, cs->base + OFFSET_ADDR);
110	else if (ctrl & NAND_CLE)
111		writeb(cmd, cs->base + OFFSET_CMD);
112}
113
114static int jz4780_nand_dev_ready(struct mtd_info *mtd)
115{
116	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
117
118	return !gpiod_get_value_cansleep(nand->busy_gpio);
119}
120
121static void jz4780_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
122{
123	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
124
125	nand->reading = (mode == NAND_ECC_READ);
126}
127
128static int jz4780_nand_ecc_calculate(struct mtd_info *mtd, const u8 *dat,
129				     u8 *ecc_code)
130{
131	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
132	struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
133	struct jz4780_bch_params params;
134
135	/*
136	 * Don't need to generate the ECC when reading, BCH does it for us as
137	 * part of decoding/correction.
138	 */
139	if (nand->reading)
140		return 0;
141
142	params.size = nand->chip.ecc.size;
143	params.bytes = nand->chip.ecc.bytes;
144	params.strength = nand->chip.ecc.strength;
145
146	return jz4780_bch_calculate(nfc->bch, &params, dat, ecc_code);
147}
148
149static int jz4780_nand_ecc_correct(struct mtd_info *mtd, u8 *dat,
150				   u8 *read_ecc, u8 *calc_ecc)
151{
152	struct jz4780_nand_chip *nand = to_jz4780_nand_chip(mtd);
153	struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(nand->chip.controller);
154	struct jz4780_bch_params params;
155
156	params.size = nand->chip.ecc.size;
157	params.bytes = nand->chip.ecc.bytes;
158	params.strength = nand->chip.ecc.strength;
159
160	return jz4780_bch_correct(nfc->bch, &params, dat, read_ecc);
161}
162
163static int jz4780_nand_init_ecc(struct jz4780_nand_chip *nand, struct device *dev)
164{
165	struct nand_chip *chip = &nand->chip;
166	struct mtd_info *mtd = nand_to_mtd(chip);
167	struct jz4780_nand_controller *nfc = to_jz4780_nand_controller(chip->controller);
168	struct nand_ecclayout *layout = &nand->ecclayout;
169	u32 start, i;
170
171	chip->ecc.bytes = fls((1 + 8) * chip->ecc.size)	*
172				(chip->ecc.strength / 8);
173
174	switch (chip->ecc.mode) {
175	case NAND_ECC_HW:
176		if (!nfc->bch) {
177			dev_err(dev, "HW BCH selected, but BCH controller not found\n");
178			return -ENODEV;
179		}
180
181		chip->ecc.hwctl = jz4780_nand_ecc_hwctl;
182		chip->ecc.calculate = jz4780_nand_ecc_calculate;
183		chip->ecc.correct = jz4780_nand_ecc_correct;
184		/* fall through */
185	case NAND_ECC_SOFT:
186	case NAND_ECC_SOFT_BCH:
187		dev_info(dev, "using %s (strength %d, size %d, bytes %d)\n",
188			(nfc->bch) ? "hardware BCH" : "software ECC",
189			chip->ecc.strength, chip->ecc.size, chip->ecc.bytes);
190		break;
191	case NAND_ECC_NONE:
192		dev_info(dev, "not using ECC\n");
193		break;
194	default:
195		dev_err(dev, "ECC mode %d not supported\n", chip->ecc.mode);
196		return -EINVAL;
197	}
198
199	/* The NAND core will generate the ECC layout for SW ECC */
200	if (chip->ecc.mode != NAND_ECC_HW)
201		return 0;
202
203	/* Generate ECC layout. ECC codes are right aligned in the OOB area. */
204	layout->eccbytes = mtd->writesize / chip->ecc.size * chip->ecc.bytes;
205
206	if (layout->eccbytes > mtd->oobsize - 2) {
207		dev_err(dev,
208			"invalid ECC config: required %d ECC bytes, but only %d are available",
209			layout->eccbytes, mtd->oobsize - 2);
210		return -EINVAL;
211	}
212
213	start = mtd->oobsize - layout->eccbytes;
214	for (i = 0; i < layout->eccbytes; i++)
215		layout->eccpos[i] = start + i;
216
217	layout->oobfree[0].offset = 2;
218	layout->oobfree[0].length = mtd->oobsize - layout->eccbytes - 2;
219
220	chip->ecc.layout = layout;
221	return 0;
222}
223
224static int jz4780_nand_init_chip(struct platform_device *pdev,
225				struct jz4780_nand_controller *nfc,
226				struct device_node *np,
227				unsigned int chipnr)
228{
229	struct device *dev = &pdev->dev;
230	struct jz4780_nand_chip *nand;
231	struct jz4780_nand_cs *cs;
232	struct resource *res;
233	struct nand_chip *chip;
234	struct mtd_info *mtd;
235	const __be32 *reg;
236	int ret = 0;
237
238	cs = &nfc->cs[chipnr];
239
240	reg = of_get_property(np, "reg", NULL);
241	if (!reg)
242		return -EINVAL;
243
244	cs->bank = be32_to_cpu(*reg);
245
246	jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
247
248	res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
249	cs->base = devm_ioremap_resource(dev, res);
250	if (IS_ERR(cs->base))
251		return PTR_ERR(cs->base);
252
253	nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
254	if (!nand)
255		return -ENOMEM;
256
257	nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
258
259	if (IS_ERR(nand->busy_gpio)) {
260		ret = PTR_ERR(nand->busy_gpio);
261		dev_err(dev, "failed to request busy GPIO: %d\n", ret);
262		return ret;
263	} else if (nand->busy_gpio) {
264		nand->chip.dev_ready = jz4780_nand_dev_ready;
265	}
266
267	nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
268
269	if (IS_ERR(nand->wp_gpio)) {
270		ret = PTR_ERR(nand->wp_gpio);
271		dev_err(dev, "failed to request WP GPIO: %d\n", ret);
272		return ret;
273	}
274
275	chip = &nand->chip;
276	mtd = nand_to_mtd(chip);
277	mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
278				   cs->bank);
279	if (!mtd->name)
280		return -ENOMEM;
281	mtd->dev.parent = dev;
282
283	chip->IO_ADDR_R = cs->base + OFFSET_DATA;
284	chip->IO_ADDR_W = cs->base + OFFSET_DATA;
285	chip->chip_delay = RB_DELAY_US;
286	chip->options = NAND_NO_SUBPAGE_WRITE;
287	chip->select_chip = jz4780_nand_select_chip;
288	chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
289	chip->ecc.mode = NAND_ECC_HW;
290	chip->controller = &nfc->controller;
291	nand_set_flash_node(chip, np);
292
293	ret = nand_scan_ident(mtd, 1, NULL);
294	if (ret)
295		return ret;
296
297	ret = jz4780_nand_init_ecc(nand, dev);
298	if (ret)
299		return ret;
300
301	ret = nand_scan_tail(mtd);
302	if (ret)
303		return ret;
304
305	ret = mtd_device_register(mtd, NULL, 0);
306	if (ret) {
307		nand_release(mtd);
308		return ret;
309	}
310
311	list_add_tail(&nand->chip_list, &nfc->chips);
312
313	return 0;
314}
315
316static void jz4780_nand_cleanup_chips(struct jz4780_nand_controller *nfc)
317{
318	struct jz4780_nand_chip *chip;
319
320	while (!list_empty(&nfc->chips)) {
321		chip = list_first_entry(&nfc->chips, struct jz4780_nand_chip, chip_list);
322		nand_release(nand_to_mtd(&chip->chip));
323		list_del(&chip->chip_list);
324	}
325}
326
327static int jz4780_nand_init_chips(struct jz4780_nand_controller *nfc,
328				  struct platform_device *pdev)
329{
330	struct device *dev = &pdev->dev;
331	struct device_node *np;
332	int i = 0;
333	int ret;
334	int num_chips = of_get_child_count(dev->of_node);
335
336	if (num_chips > nfc->num_banks) {
337		dev_err(dev, "found %d chips but only %d banks\n", num_chips, nfc->num_banks);
338		return -EINVAL;
339	}
340
341	for_each_child_of_node(dev->of_node, np) {
342		ret = jz4780_nand_init_chip(pdev, nfc, np, i);
343		if (ret) {
344			jz4780_nand_cleanup_chips(nfc);
345			return ret;
346		}
347
348		i++;
349	}
350
351	return 0;
352}
353
354static int jz4780_nand_probe(struct platform_device *pdev)
355{
356	struct device *dev = &pdev->dev;
357	unsigned int num_banks;
358	struct jz4780_nand_controller *nfc;
359	int ret;
360
361	num_banks = jz4780_nemc_num_banks(dev);
362	if (num_banks == 0) {
363		dev_err(dev, "no banks found\n");
364		return -ENODEV;
365	}
366
367	nfc = devm_kzalloc(dev, sizeof(*nfc) + (sizeof(nfc->cs[0]) * num_banks), GFP_KERNEL);
368	if (!nfc)
369		return -ENOMEM;
370
371	/*
372	 * Check for BCH HW before we call nand_scan_ident, to prevent us from
373	 * having to call it again if the BCH driver returns -EPROBE_DEFER.
374	 */
375	nfc->bch = of_jz4780_bch_get(dev->of_node);
376	if (IS_ERR(nfc->bch))
377		return PTR_ERR(nfc->bch);
378
379	nfc->dev = dev;
380	nfc->num_banks = num_banks;
381
382	spin_lock_init(&nfc->controller.lock);
383	INIT_LIST_HEAD(&nfc->chips);
384	init_waitqueue_head(&nfc->controller.wq);
385
386	ret = jz4780_nand_init_chips(nfc, pdev);
387	if (ret) {
388		if (nfc->bch)
389			jz4780_bch_release(nfc->bch);
390		return ret;
391	}
392
393	platform_set_drvdata(pdev, nfc);
394	return 0;
395}
396
397static int jz4780_nand_remove(struct platform_device *pdev)
398{
399	struct jz4780_nand_controller *nfc = platform_get_drvdata(pdev);
400
401	if (nfc->bch)
402		jz4780_bch_release(nfc->bch);
403
404	jz4780_nand_cleanup_chips(nfc);
405
406	return 0;
407}
408
409static const struct of_device_id jz4780_nand_dt_match[] = {
410	{ .compatible = "ingenic,jz4780-nand" },
411	{},
412};
413MODULE_DEVICE_TABLE(of, jz4780_nand_dt_match);
414
415static struct platform_driver jz4780_nand_driver = {
416	.probe		= jz4780_nand_probe,
417	.remove		= jz4780_nand_remove,
418	.driver	= {
419		.name	= DRV_NAME,
420		.of_match_table = of_match_ptr(jz4780_nand_dt_match),
421	},
422};
423module_platform_driver(jz4780_nand_driver);
424
425MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
426MODULE_AUTHOR("Harvey Hunt <harvey.hunt@imgtec.com>");
427MODULE_DESCRIPTION("Ingenic JZ4780 NAND driver");
428MODULE_LICENSE("GPL v2");