1/*
  2 * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
  3 * Copyright (C) 2012-2013 Xilinx, Inc.
  4 * Copyright (C) 2007-2009 PetaLogix
  5 * Copyright (C) 2006 Atmark Techno, Inc.
  6 *
  7 * This file is subject to the terms and conditions of the GNU General Public
  8 * License. See the file "COPYING" in the main directory of this archive
  9 * for more details.
 10 */
 11
 12#include <linux/irqdomain.h>
 13#include <linux/irq.h>
 14#include <linux/irqchip.h>
 15#include <linux/irqchip/chained_irq.h>
 16#include <linux/of_address.h>
 17#include <linux/io.h>
 18#include <linux/jump_label.h>
 19#include <linux/bug.h>
 20#include <linux/of_irq.h>
 21
 22/* No one else should require these constants, so define them locally here. */
 23#define ISR 0x00			/* Interrupt Status Register */
 24#define IPR 0x04			/* Interrupt Pending Register */
 25#define IER 0x08			/* Interrupt Enable Register */
 26#define IAR 0x0c			/* Interrupt Acknowledge Register */
 27#define SIE 0x10			/* Set Interrupt Enable bits */
 28#define CIE 0x14			/* Clear Interrupt Enable bits */
 29#define IVR 0x18			/* Interrupt Vector Register */
 30#define MER 0x1c			/* Master Enable Register */
 31
 32#define MER_ME (1<<0)
 33#define MER_HIE (1<<1)
 34
 35static DEFINE_STATIC_KEY_FALSE(xintc_is_be);
 36
 37struct xintc_irq_chip {
 38	void		__iomem *base;
 39	struct		irq_domain *root_domain;
 40	u32		intr_mask;
 41	u32		nr_irq;
 42};
 43
 44static struct xintc_irq_chip *primary_intc;
 45
 46static void xintc_write(struct xintc_irq_chip *irqc, int reg, u32 data)
 47{
 48	if (static_branch_unlikely(&xintc_is_be))
 49		iowrite32be(data, irqc->base + reg);
 50	else
 51		iowrite32(data, irqc->base + reg);
 52}
 53
 54static u32 xintc_read(struct xintc_irq_chip *irqc, int reg)
 55{
 56	if (static_branch_unlikely(&xintc_is_be))
 57		return ioread32be(irqc->base + reg);
 58	else
 59		return ioread32(irqc->base + reg);
 60}
 61
 62static void intc_enable_or_unmask(struct irq_data *d)
 63{
 64	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
 65	unsigned long mask = BIT(d->hwirq);
 66
 67	pr_debug("irq-xilinx: enable_or_unmask: %ld\n", d->hwirq);
 68
 69	/* ack level irqs because they can't be acked during
 70	 * ack function since the handle_level_irq function
 71	 * acks the irq before calling the interrupt handler
 72	 */
 73	if (irqd_is_level_type(d))
 74		xintc_write(irqc, IAR, mask);
 75
 76	xintc_write(irqc, SIE, mask);
 77}
 78
 79static void intc_disable_or_mask(struct irq_data *d)
 80{
 81	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
 82
 83	pr_debug("irq-xilinx: disable: %ld\n", d->hwirq);
 84	xintc_write(irqc, CIE, BIT(d->hwirq));
 85}
 86
 87static void intc_ack(struct irq_data *d)
 88{
 89	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
 90
 91	pr_debug("irq-xilinx: ack: %ld\n", d->hwirq);
 92	xintc_write(irqc, IAR, BIT(d->hwirq));
 93}
 94
 95static void intc_mask_ack(struct irq_data *d)
 96{
 97	struct xintc_irq_chip *irqc = irq_data_get_irq_chip_data(d);
 98	unsigned long mask = BIT(d->hwirq);
 99
100	pr_debug("irq-xilinx: disable_and_ack: %ld\n", d->hwirq);
101	xintc_write(irqc, CIE, mask);
102	xintc_write(irqc, IAR, mask);
103}
104
105static struct irq_chip intc_dev = {
106	.name = "Xilinx INTC",
107	.irq_unmask = intc_enable_or_unmask,
108	.irq_mask = intc_disable_or_mask,
109	.irq_ack = intc_ack,
110	.irq_mask_ack = intc_mask_ack,
111};
112
113static unsigned int xintc_get_irq_local(struct xintc_irq_chip *irqc)
114{
115	unsigned int irq = 0;
116	u32 hwirq;
117
118	hwirq = xintc_read(irqc, IVR);
119	if (hwirq != -1U)
120		irq = irq_find_mapping(irqc->root_domain, hwirq);
121
122	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
123
124	return irq;
125}
126
127unsigned int xintc_get_irq(void)
128{
129	unsigned int irq = -1;
130	u32 hwirq;
131
132	hwirq = xintc_read(primary_intc, IVR);
133	if (hwirq != -1U)
134		irq = irq_find_mapping(primary_intc->root_domain, hwirq);
135
136	pr_debug("irq-xilinx: hwirq=%d, irq=%d\n", hwirq, irq);
137
138	return irq;
139}
140
141static int xintc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
142{
143	struct xintc_irq_chip *irqc = d->host_data;
144
145	if (irqc->intr_mask & BIT(hw)) {
146		irq_set_chip_and_handler_name(irq, &intc_dev,
147					      handle_edge_irq, "edge");
148		irq_clear_status_flags(irq, IRQ_LEVEL);
149	} else {
150		irq_set_chip_and_handler_name(irq, &intc_dev,
151					      handle_level_irq, "level");
152		irq_set_status_flags(irq, IRQ_LEVEL);
153	}
154	irq_set_chip_data(irq, irqc);
155	return 0;
156}
157
158static const struct irq_domain_ops xintc_irq_domain_ops = {
159	.xlate = irq_domain_xlate_onetwocell,
160	.map = xintc_map,
161};
162
163static void xil_intc_irq_handler(struct irq_desc *desc)
164{
165	struct irq_chip *chip = irq_desc_get_chip(desc);
166	struct xintc_irq_chip *irqc;
167	u32 pending;
168
169	irqc = irq_data_get_irq_handler_data(&desc->irq_data);
170	chained_irq_enter(chip, desc);
171	do {
172		pending = xintc_get_irq_local(irqc);
173		if (pending == 0)
174			break;
175		generic_handle_irq(pending);
176	} while (true);
177	chained_irq_exit(chip, desc);
178}
179
180static int __init xilinx_intc_of_init(struct device_node *intc,
181					     struct device_node *parent)
182{
183	struct xintc_irq_chip *irqc;
184	int ret, irq;
185
186	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
187	if (!irqc)
188		return -ENOMEM;
189	irqc->base = of_iomap(intc, 0);
190	BUG_ON(!irqc->base);
191
192	ret = of_property_read_u32(intc, "xlnx,num-intr-inputs", &irqc->nr_irq);
193	if (ret < 0) {
194		pr_err("irq-xilinx: unable to read xlnx,num-intr-inputs\n");
195		goto error;
196	}
197
198	ret = of_property_read_u32(intc, "xlnx,kind-of-intr", &irqc->intr_mask);
199	if (ret < 0) {
200		pr_warn("irq-xilinx: unable to read xlnx,kind-of-intr\n");
201		irqc->intr_mask = 0;
202	}
203
204	if (irqc->intr_mask >> irqc->nr_irq)
205		pr_warn("irq-xilinx: mismatch in kind-of-intr param\n");
206
207	pr_info("irq-xilinx: %pOF: num_irq=%d, edge=0x%x\n",
208		intc, irqc->nr_irq, irqc->intr_mask);
209
210
211	/*
212	 * Disable all external interrupts until they are
213	 * explicity requested.
214	 */
215	xintc_write(irqc, IER, 0);
216
217	/* Acknowledge any pending interrupts just in case. */
218	xintc_write(irqc, IAR, 0xffffffff);
219
220	/* Turn on the Master Enable. */
221	xintc_write(irqc, MER, MER_HIE | MER_ME);
222	if (xintc_read(irqc, MER) != (MER_HIE | MER_ME)) {
223		static_branch_enable(&xintc_is_be);
224		xintc_write(irqc, MER, MER_HIE | MER_ME);
225	}
226
227	irqc->root_domain = irq_domain_add_linear(intc, irqc->nr_irq,
228						  &xintc_irq_domain_ops, irqc);
229	if (!irqc->root_domain) {
230		pr_err("irq-xilinx: Unable to create IRQ domain\n");
231		ret = -EINVAL;
232		goto error;
233	}
234
235	if (parent) {
236		irq = irq_of_parse_and_map(intc, 0);
237		if (irq) {
238			irq_set_chained_handler_and_data(irq,
239							 xil_intc_irq_handler,
240							 irqc);
241		} else {
242			pr_err("irq-xilinx: interrupts property not in DT\n");
243			ret = -EINVAL;
244			goto error;
245		}
246	} else {
247		primary_intc = irqc;
248		irq_set_default_host(primary_intc->root_domain);
249	}
250
251	return 0;
252
253error:
254	iounmap(irqc->base);
255	kfree(irqc);
256	return ret;
257
258}
259
260IRQCHIP_DECLARE(xilinx_intc_xps, "xlnx,xps-intc-1.00.a", xilinx_intc_of_init);
261IRQCHIP_DECLARE(xilinx_intc_opb, "xlnx,opb-intc-1.00.c", xilinx_intc_of_init);