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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Renesas INTC External IRQ Pin Driver
4 *
5 * Copyright (C) 2013 Magnus Damm
6 */
7
8#include <linux/init.h>
9#include <linux/of.h>
10#include <linux/platform_device.h>
11#include <linux/spinlock.h>
12#include <linux/interrupt.h>
13#include <linux/ioport.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/err.h>
18#include <linux/slab.h>
19#include <linux/module.h>
20#include <linux/of_device.h>
21#include <linux/pm_runtime.h>
22
23#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
24
25#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
26#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
27#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
28#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
29#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
30#define INTC_IRQPIN_REG_NR_MANDATORY 5
31#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
32#define INTC_IRQPIN_REG_NR 6
33
34/* INTC external IRQ PIN hardware register access:
35 *
36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
37 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
41 *
42 * (*) May be accessed by more than one driver instance - lock needed
43 * (**) Read-modify-write access by one driver instance - lock needed
44 * (***) Accessed by one driver instance only - no locking needed
45 */
46
47struct intc_irqpin_iomem {
48 void __iomem *iomem;
49 unsigned long (*read)(void __iomem *iomem);
50 void (*write)(void __iomem *iomem, unsigned long data);
51 int width;
52};
53
54struct intc_irqpin_irq {
55 int hw_irq;
56 int requested_irq;
57 int domain_irq;
58 struct intc_irqpin_priv *p;
59};
60
61struct intc_irqpin_priv {
62 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
63 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
64 unsigned int sense_bitfield_width;
65 struct platform_device *pdev;
66 struct irq_chip irq_chip;
67 struct irq_domain *irq_domain;
68 atomic_t wakeup_path;
69 unsigned shared_irqs:1;
70 u8 shared_irq_mask;
71};
72
73struct intc_irqpin_config {
74 unsigned int irlm_bit;
75 unsigned needs_irlm:1;
76};
77
78static unsigned long intc_irqpin_read32(void __iomem *iomem)
79{
80 return ioread32(iomem);
81}
82
83static unsigned long intc_irqpin_read8(void __iomem *iomem)
84{
85 return ioread8(iomem);
86}
87
88static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
89{
90 iowrite32(data, iomem);
91}
92
93static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
94{
95 iowrite8(data, iomem);
96}
97
98static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
99 int reg)
100{
101 struct intc_irqpin_iomem *i = &p->iomem[reg];
102
103 return i->read(i->iomem);
104}
105
106static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
107 int reg, unsigned long data)
108{
109 struct intc_irqpin_iomem *i = &p->iomem[reg];
110
111 i->write(i->iomem, data);
112}
113
114static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
115 int reg, int hw_irq)
116{
117 return BIT((p->iomem[reg].width - 1) - hw_irq);
118}
119
120static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
121 int reg, int hw_irq)
122{
123 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
124}
125
126static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
127
128static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
129 int reg, int shift,
130 int width, int value)
131{
132 unsigned long flags;
133 unsigned long tmp;
134
135 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
136
137 tmp = intc_irqpin_read(p, reg);
138 tmp &= ~(((1 << width) - 1) << shift);
139 tmp |= value << shift;
140 intc_irqpin_write(p, reg, tmp);
141
142 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
143}
144
145static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
146 int irq, int do_mask)
147{
148 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
149 int bitfield_width = 4;
150 int shift = 32 - (irq + 1) * bitfield_width;
151
152 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
153 shift, bitfield_width,
154 do_mask ? 0 : (1 << bitfield_width) - 1);
155}
156
157static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
158{
159 /* The SENSE register is assumed to be 32-bit. */
160 int bitfield_width = p->sense_bitfield_width;
161 int shift = 32 - (irq + 1) * bitfield_width;
162
163 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
164
165 if (value >= (1 << bitfield_width))
166 return -EINVAL;
167
168 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
169 bitfield_width, value);
170 return 0;
171}
172
173static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
174{
175 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
176 str, i->requested_irq, i->hw_irq, i->domain_irq);
177}
178
179static void intc_irqpin_irq_enable(struct irq_data *d)
180{
181 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
182 int hw_irq = irqd_to_hwirq(d);
183
184 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
185 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
186}
187
188static void intc_irqpin_irq_disable(struct irq_data *d)
189{
190 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
191 int hw_irq = irqd_to_hwirq(d);
192
193 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
194 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
195}
196
197static void intc_irqpin_shared_irq_enable(struct irq_data *d)
198{
199 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
200 int hw_irq = irqd_to_hwirq(d);
201
202 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
203 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
204
205 p->shared_irq_mask &= ~BIT(hw_irq);
206}
207
208static void intc_irqpin_shared_irq_disable(struct irq_data *d)
209{
210 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
211 int hw_irq = irqd_to_hwirq(d);
212
213 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
214 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
215
216 p->shared_irq_mask |= BIT(hw_irq);
217}
218
219static void intc_irqpin_irq_enable_force(struct irq_data *d)
220{
221 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
222 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
223
224 intc_irqpin_irq_enable(d);
225
226 /* enable interrupt through parent interrupt controller,
227 * assumes non-shared interrupt with 1:1 mapping
228 * needed for busted IRQs on some SoCs like sh73a0
229 */
230 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
231}
232
233static void intc_irqpin_irq_disable_force(struct irq_data *d)
234{
235 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
236 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
237
238 /* disable interrupt through parent interrupt controller,
239 * assumes non-shared interrupt with 1:1 mapping
240 * needed for busted IRQs on some SoCs like sh73a0
241 */
242 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
243 intc_irqpin_irq_disable(d);
244}
245
246#define INTC_IRQ_SENSE_VALID 0x10
247#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
248
249static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
250 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
251 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
252 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
253 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
254 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
255};
256
257static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
258{
259 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
260 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
261
262 if (!(value & INTC_IRQ_SENSE_VALID))
263 return -EINVAL;
264
265 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
266 value ^ INTC_IRQ_SENSE_VALID);
267}
268
269static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
270{
271 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
272 int hw_irq = irqd_to_hwirq(d);
273
274 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
275 if (on)
276 atomic_inc(&p->wakeup_path);
277 else
278 atomic_dec(&p->wakeup_path);
279
280 return 0;
281}
282
283static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
284{
285 struct intc_irqpin_irq *i = dev_id;
286 struct intc_irqpin_priv *p = i->p;
287 unsigned long bit;
288
289 intc_irqpin_dbg(i, "demux1");
290 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
291
292 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
293 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
294 intc_irqpin_dbg(i, "demux2");
295 generic_handle_irq(i->domain_irq);
296 return IRQ_HANDLED;
297 }
298 return IRQ_NONE;
299}
300
301static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
302{
303 struct intc_irqpin_priv *p = dev_id;
304 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
305 irqreturn_t status = IRQ_NONE;
306 int k;
307
308 for (k = 0; k < 8; k++) {
309 if (reg_source & BIT(7 - k)) {
310 if (BIT(k) & p->shared_irq_mask)
311 continue;
312
313 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
314 }
315 }
316
317 return status;
318}
319
320/*
321 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
322 * different category than their parents, so it won't report false recursion.
323 */
324static struct lock_class_key intc_irqpin_irq_lock_class;
325
326/* And this is for the request mutex */
327static struct lock_class_key intc_irqpin_irq_request_class;
328
329static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
330 irq_hw_number_t hw)
331{
332 struct intc_irqpin_priv *p = h->host_data;
333
334 p->irq[hw].domain_irq = virq;
335 p->irq[hw].hw_irq = hw;
336
337 intc_irqpin_dbg(&p->irq[hw], "map");
338 irq_set_chip_data(virq, h->host_data);
339 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
340 &intc_irqpin_irq_request_class);
341 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
342 return 0;
343}
344
345static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
346 .map = intc_irqpin_irq_domain_map,
347 .xlate = irq_domain_xlate_twocell,
348};
349
350static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
351 .irlm_bit = 23, /* ICR0.IRLM0 */
352 .needs_irlm = 1,
353};
354
355static const struct intc_irqpin_config intc_irqpin_rmobile = {
356 .needs_irlm = 0,
357};
358
359static const struct of_device_id intc_irqpin_dt_ids[] = {
360 { .compatible = "renesas,intc-irqpin", },
361 { .compatible = "renesas,intc-irqpin-r8a7778",
362 .data = &intc_irqpin_irlm_r8a777x },
363 { .compatible = "renesas,intc-irqpin-r8a7779",
364 .data = &intc_irqpin_irlm_r8a777x },
365 { .compatible = "renesas,intc-irqpin-r8a7740",
366 .data = &intc_irqpin_rmobile },
367 { .compatible = "renesas,intc-irqpin-sh73a0",
368 .data = &intc_irqpin_rmobile },
369 {},
370};
371MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
372
373static int intc_irqpin_probe(struct platform_device *pdev)
374{
375 const struct intc_irqpin_config *config;
376 struct device *dev = &pdev->dev;
377 struct intc_irqpin_priv *p;
378 struct intc_irqpin_iomem *i;
379 struct resource *io[INTC_IRQPIN_REG_NR];
380 struct resource *irq;
381 struct irq_chip *irq_chip;
382 void (*enable_fn)(struct irq_data *d);
383 void (*disable_fn)(struct irq_data *d);
384 const char *name = dev_name(dev);
385 bool control_parent;
386 unsigned int nirqs;
387 int ref_irq;
388 int ret;
389 int k;
390
391 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
392 if (!p)
393 return -ENOMEM;
394
395 /* deal with driver instance configuration */
396 of_property_read_u32(dev->of_node, "sense-bitfield-width",
397 &p->sense_bitfield_width);
398 control_parent = of_property_read_bool(dev->of_node, "control-parent");
399 if (!p->sense_bitfield_width)
400 p->sense_bitfield_width = 4; /* default to 4 bits */
401
402 p->pdev = pdev;
403 platform_set_drvdata(pdev, p);
404
405 config = of_device_get_match_data(dev);
406
407 pm_runtime_enable(dev);
408 pm_runtime_get_sync(dev);
409
410 /* get hold of register banks */
411 memset(io, 0, sizeof(io));
412 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
413 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
414 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
415 dev_err(dev, "not enough IOMEM resources\n");
416 ret = -EINVAL;
417 goto err0;
418 }
419 }
420
421 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
422 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
423 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
424 if (!irq)
425 break;
426
427 p->irq[k].p = p;
428 p->irq[k].requested_irq = irq->start;
429 }
430
431 nirqs = k;
432 if (nirqs < 1) {
433 dev_err(dev, "not enough IRQ resources\n");
434 ret = -EINVAL;
435 goto err0;
436 }
437
438 /* ioremap IOMEM and setup read/write callbacks */
439 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
440 i = &p->iomem[k];
441
442 /* handle optional registers */
443 if (!io[k])
444 continue;
445
446 switch (resource_size(io[k])) {
447 case 1:
448 i->width = 8;
449 i->read = intc_irqpin_read8;
450 i->write = intc_irqpin_write8;
451 break;
452 case 4:
453 i->width = 32;
454 i->read = intc_irqpin_read32;
455 i->write = intc_irqpin_write32;
456 break;
457 default:
458 dev_err(dev, "IOMEM size mismatch\n");
459 ret = -EINVAL;
460 goto err0;
461 }
462
463 i->iomem = devm_ioremap(dev, io[k]->start,
464 resource_size(io[k]));
465 if (!i->iomem) {
466 dev_err(dev, "failed to remap IOMEM\n");
467 ret = -ENXIO;
468 goto err0;
469 }
470 }
471
472 /* configure "individual IRQ mode" where needed */
473 if (config && config->needs_irlm) {
474 if (io[INTC_IRQPIN_REG_IRLM])
475 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
476 config->irlm_bit, 1, 1);
477 else
478 dev_warn(dev, "unable to select IRLM mode\n");
479 }
480
481 /* mask all interrupts using priority */
482 for (k = 0; k < nirqs; k++)
483 intc_irqpin_mask_unmask_prio(p, k, 1);
484
485 /* clear all pending interrupts */
486 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
487
488 /* scan for shared interrupt lines */
489 ref_irq = p->irq[0].requested_irq;
490 p->shared_irqs = 1;
491 for (k = 1; k < nirqs; k++) {
492 if (ref_irq != p->irq[k].requested_irq) {
493 p->shared_irqs = 0;
494 break;
495 }
496 }
497
498 /* use more severe masking method if requested */
499 if (control_parent) {
500 enable_fn = intc_irqpin_irq_enable_force;
501 disable_fn = intc_irqpin_irq_disable_force;
502 } else if (!p->shared_irqs) {
503 enable_fn = intc_irqpin_irq_enable;
504 disable_fn = intc_irqpin_irq_disable;
505 } else {
506 enable_fn = intc_irqpin_shared_irq_enable;
507 disable_fn = intc_irqpin_shared_irq_disable;
508 }
509
510 irq_chip = &p->irq_chip;
511 irq_chip->name = "intc-irqpin";
512 irq_chip->parent_device = dev;
513 irq_chip->irq_mask = disable_fn;
514 irq_chip->irq_unmask = enable_fn;
515 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
516 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
517 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
518
519 p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
520 &intc_irqpin_irq_domain_ops, p);
521 if (!p->irq_domain) {
522 ret = -ENXIO;
523 dev_err(dev, "cannot initialize irq domain\n");
524 goto err0;
525 }
526
527 if (p->shared_irqs) {
528 /* request one shared interrupt */
529 if (devm_request_irq(dev, p->irq[0].requested_irq,
530 intc_irqpin_shared_irq_handler,
531 IRQF_SHARED, name, p)) {
532 dev_err(dev, "failed to request low IRQ\n");
533 ret = -ENOENT;
534 goto err1;
535 }
536 } else {
537 /* request interrupts one by one */
538 for (k = 0; k < nirqs; k++) {
539 if (devm_request_irq(dev, p->irq[k].requested_irq,
540 intc_irqpin_irq_handler, 0, name,
541 &p->irq[k])) {
542 dev_err(dev, "failed to request low IRQ\n");
543 ret = -ENOENT;
544 goto err1;
545 }
546 }
547 }
548
549 /* unmask all interrupts on prio level */
550 for (k = 0; k < nirqs; k++)
551 intc_irqpin_mask_unmask_prio(p, k, 0);
552
553 dev_info(dev, "driving %d irqs\n", nirqs);
554
555 return 0;
556
557err1:
558 irq_domain_remove(p->irq_domain);
559err0:
560 pm_runtime_put(dev);
561 pm_runtime_disable(dev);
562 return ret;
563}
564
565static int intc_irqpin_remove(struct platform_device *pdev)
566{
567 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
568
569 irq_domain_remove(p->irq_domain);
570 pm_runtime_put(&pdev->dev);
571 pm_runtime_disable(&pdev->dev);
572 return 0;
573}
574
575static int __maybe_unused intc_irqpin_suspend(struct device *dev)
576{
577 struct intc_irqpin_priv *p = dev_get_drvdata(dev);
578
579 if (atomic_read(&p->wakeup_path))
580 device_set_wakeup_path(dev);
581
582 return 0;
583}
584
585static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
586
587static struct platform_driver intc_irqpin_device_driver = {
588 .probe = intc_irqpin_probe,
589 .remove = intc_irqpin_remove,
590 .driver = {
591 .name = "renesas_intc_irqpin",
592 .of_match_table = intc_irqpin_dt_ids,
593 .pm = &intc_irqpin_pm_ops,
594 }
595};
596
597static int __init intc_irqpin_init(void)
598{
599 return platform_driver_register(&intc_irqpin_device_driver);
600}
601postcore_initcall(intc_irqpin_init);
602
603static void __exit intc_irqpin_exit(void)
604{
605 platform_driver_unregister(&intc_irqpin_device_driver);
606}
607module_exit(intc_irqpin_exit);
608
609MODULE_AUTHOR("Magnus Damm");
610MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
611MODULE_LICENSE("GPL v2");
1/*
2 * Renesas INTC External IRQ Pin Driver
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/clk.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/platform_device.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26#include <linux/ioport.h>
27#include <linux/io.h>
28#include <linux/irq.h>
29#include <linux/irqdomain.h>
30#include <linux/err.h>
31#include <linux/slab.h>
32#include <linux/module.h>
33#include <linux/of_device.h>
34#include <linux/pm_runtime.h>
35
36#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
37
38#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
39#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
40#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
41#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
42#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
43#define INTC_IRQPIN_REG_NR_MANDATORY 5
44#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
45#define INTC_IRQPIN_REG_NR 6
46
47/* INTC external IRQ PIN hardware register access:
48 *
49 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
50 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
51 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
52 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
53 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
54 *
55 * (*) May be accessed by more than one driver instance - lock needed
56 * (**) Read-modify-write access by one driver instance - lock needed
57 * (***) Accessed by one driver instance only - no locking needed
58 */
59
60struct intc_irqpin_iomem {
61 void __iomem *iomem;
62 unsigned long (*read)(void __iomem *iomem);
63 void (*write)(void __iomem *iomem, unsigned long data);
64 int width;
65};
66
67struct intc_irqpin_irq {
68 int hw_irq;
69 int requested_irq;
70 int domain_irq;
71 struct intc_irqpin_priv *p;
72};
73
74struct intc_irqpin_priv {
75 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
76 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
77 unsigned int sense_bitfield_width;
78 struct platform_device *pdev;
79 struct irq_chip irq_chip;
80 struct irq_domain *irq_domain;
81 struct clk *clk;
82 unsigned shared_irqs:1;
83 unsigned needs_clk:1;
84 u8 shared_irq_mask;
85};
86
87struct intc_irqpin_config {
88 unsigned int irlm_bit;
89 unsigned needs_irlm:1;
90 unsigned needs_clk:1;
91};
92
93static unsigned long intc_irqpin_read32(void __iomem *iomem)
94{
95 return ioread32(iomem);
96}
97
98static unsigned long intc_irqpin_read8(void __iomem *iomem)
99{
100 return ioread8(iomem);
101}
102
103static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
104{
105 iowrite32(data, iomem);
106}
107
108static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
109{
110 iowrite8(data, iomem);
111}
112
113static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
114 int reg)
115{
116 struct intc_irqpin_iomem *i = &p->iomem[reg];
117
118 return i->read(i->iomem);
119}
120
121static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
122 int reg, unsigned long data)
123{
124 struct intc_irqpin_iomem *i = &p->iomem[reg];
125
126 i->write(i->iomem, data);
127}
128
129static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
130 int reg, int hw_irq)
131{
132 return BIT((p->iomem[reg].width - 1) - hw_irq);
133}
134
135static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
136 int reg, int hw_irq)
137{
138 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
139}
140
141static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
142
143static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
144 int reg, int shift,
145 int width, int value)
146{
147 unsigned long flags;
148 unsigned long tmp;
149
150 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
151
152 tmp = intc_irqpin_read(p, reg);
153 tmp &= ~(((1 << width) - 1) << shift);
154 tmp |= value << shift;
155 intc_irqpin_write(p, reg, tmp);
156
157 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
158}
159
160static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
161 int irq, int do_mask)
162{
163 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
164 int bitfield_width = 4;
165 int shift = 32 - (irq + 1) * bitfield_width;
166
167 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
168 shift, bitfield_width,
169 do_mask ? 0 : (1 << bitfield_width) - 1);
170}
171
172static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
173{
174 /* The SENSE register is assumed to be 32-bit. */
175 int bitfield_width = p->sense_bitfield_width;
176 int shift = 32 - (irq + 1) * bitfield_width;
177
178 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
179
180 if (value >= (1 << bitfield_width))
181 return -EINVAL;
182
183 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
184 bitfield_width, value);
185 return 0;
186}
187
188static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
189{
190 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
191 str, i->requested_irq, i->hw_irq, i->domain_irq);
192}
193
194static void intc_irqpin_irq_enable(struct irq_data *d)
195{
196 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
197 int hw_irq = irqd_to_hwirq(d);
198
199 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
200 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
201}
202
203static void intc_irqpin_irq_disable(struct irq_data *d)
204{
205 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
206 int hw_irq = irqd_to_hwirq(d);
207
208 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
209 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
210}
211
212static void intc_irqpin_shared_irq_enable(struct irq_data *d)
213{
214 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
215 int hw_irq = irqd_to_hwirq(d);
216
217 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
218 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
219
220 p->shared_irq_mask &= ~BIT(hw_irq);
221}
222
223static void intc_irqpin_shared_irq_disable(struct irq_data *d)
224{
225 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
226 int hw_irq = irqd_to_hwirq(d);
227
228 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
229 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
230
231 p->shared_irq_mask |= BIT(hw_irq);
232}
233
234static void intc_irqpin_irq_enable_force(struct irq_data *d)
235{
236 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
237 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
238
239 intc_irqpin_irq_enable(d);
240
241 /* enable interrupt through parent interrupt controller,
242 * assumes non-shared interrupt with 1:1 mapping
243 * needed for busted IRQs on some SoCs like sh73a0
244 */
245 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
246}
247
248static void intc_irqpin_irq_disable_force(struct irq_data *d)
249{
250 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
251 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
252
253 /* disable interrupt through parent interrupt controller,
254 * assumes non-shared interrupt with 1:1 mapping
255 * needed for busted IRQs on some SoCs like sh73a0
256 */
257 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
258 intc_irqpin_irq_disable(d);
259}
260
261#define INTC_IRQ_SENSE_VALID 0x10
262#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
263
264static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
265 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
266 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
267 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
268 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
269 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
270};
271
272static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
273{
274 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
275 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
276
277 if (!(value & INTC_IRQ_SENSE_VALID))
278 return -EINVAL;
279
280 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
281 value ^ INTC_IRQ_SENSE_VALID);
282}
283
284static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
285{
286 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
287 int hw_irq = irqd_to_hwirq(d);
288
289 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
290
291 if (!p->clk)
292 return 0;
293
294 if (on)
295 clk_enable(p->clk);
296 else
297 clk_disable(p->clk);
298
299 return 0;
300}
301
302static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
303{
304 struct intc_irqpin_irq *i = dev_id;
305 struct intc_irqpin_priv *p = i->p;
306 unsigned long bit;
307
308 intc_irqpin_dbg(i, "demux1");
309 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
310
311 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
312 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
313 intc_irqpin_dbg(i, "demux2");
314 generic_handle_irq(i->domain_irq);
315 return IRQ_HANDLED;
316 }
317 return IRQ_NONE;
318}
319
320static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
321{
322 struct intc_irqpin_priv *p = dev_id;
323 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
324 irqreturn_t status = IRQ_NONE;
325 int k;
326
327 for (k = 0; k < 8; k++) {
328 if (reg_source & BIT(7 - k)) {
329 if (BIT(k) & p->shared_irq_mask)
330 continue;
331
332 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
333 }
334 }
335
336 return status;
337}
338
339/*
340 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
341 * different category than their parents, so it won't report false recursion.
342 */
343static struct lock_class_key intc_irqpin_irq_lock_class;
344
345static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
346 irq_hw_number_t hw)
347{
348 struct intc_irqpin_priv *p = h->host_data;
349
350 p->irq[hw].domain_irq = virq;
351 p->irq[hw].hw_irq = hw;
352
353 intc_irqpin_dbg(&p->irq[hw], "map");
354 irq_set_chip_data(virq, h->host_data);
355 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class);
356 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
357 return 0;
358}
359
360static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
361 .map = intc_irqpin_irq_domain_map,
362 .xlate = irq_domain_xlate_twocell,
363};
364
365static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
366 .irlm_bit = 23, /* ICR0.IRLM0 */
367 .needs_irlm = 1,
368 .needs_clk = 0,
369};
370
371static const struct intc_irqpin_config intc_irqpin_rmobile = {
372 .needs_irlm = 0,
373 .needs_clk = 1,
374};
375
376static const struct of_device_id intc_irqpin_dt_ids[] = {
377 { .compatible = "renesas,intc-irqpin", },
378 { .compatible = "renesas,intc-irqpin-r8a7778",
379 .data = &intc_irqpin_irlm_r8a777x },
380 { .compatible = "renesas,intc-irqpin-r8a7779",
381 .data = &intc_irqpin_irlm_r8a777x },
382 { .compatible = "renesas,intc-irqpin-r8a7740",
383 .data = &intc_irqpin_rmobile },
384 { .compatible = "renesas,intc-irqpin-sh73a0",
385 .data = &intc_irqpin_rmobile },
386 {},
387};
388MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
389
390static int intc_irqpin_probe(struct platform_device *pdev)
391{
392 const struct intc_irqpin_config *config = NULL;
393 struct device *dev = &pdev->dev;
394 const struct of_device_id *of_id;
395 struct intc_irqpin_priv *p;
396 struct intc_irqpin_iomem *i;
397 struct resource *io[INTC_IRQPIN_REG_NR];
398 struct resource *irq;
399 struct irq_chip *irq_chip;
400 void (*enable_fn)(struct irq_data *d);
401 void (*disable_fn)(struct irq_data *d);
402 const char *name = dev_name(dev);
403 bool control_parent;
404 unsigned int nirqs;
405 int ref_irq;
406 int ret;
407 int k;
408
409 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
410 if (!p) {
411 dev_err(dev, "failed to allocate driver data\n");
412 return -ENOMEM;
413 }
414
415 /* deal with driver instance configuration */
416 of_property_read_u32(dev->of_node, "sense-bitfield-width",
417 &p->sense_bitfield_width);
418 control_parent = of_property_read_bool(dev->of_node, "control-parent");
419 if (!p->sense_bitfield_width)
420 p->sense_bitfield_width = 4; /* default to 4 bits */
421
422 p->pdev = pdev;
423 platform_set_drvdata(pdev, p);
424
425 of_id = of_match_device(intc_irqpin_dt_ids, dev);
426 if (of_id && of_id->data) {
427 config = of_id->data;
428 p->needs_clk = config->needs_clk;
429 }
430
431 p->clk = devm_clk_get(dev, NULL);
432 if (IS_ERR(p->clk)) {
433 if (p->needs_clk) {
434 dev_err(dev, "unable to get clock\n");
435 ret = PTR_ERR(p->clk);
436 goto err0;
437 }
438 p->clk = NULL;
439 }
440
441 pm_runtime_enable(dev);
442 pm_runtime_get_sync(dev);
443
444 /* get hold of register banks */
445 memset(io, 0, sizeof(io));
446 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
447 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
448 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
449 dev_err(dev, "not enough IOMEM resources\n");
450 ret = -EINVAL;
451 goto err0;
452 }
453 }
454
455 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
456 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
457 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
458 if (!irq)
459 break;
460
461 p->irq[k].p = p;
462 p->irq[k].requested_irq = irq->start;
463 }
464
465 nirqs = k;
466 if (nirqs < 1) {
467 dev_err(dev, "not enough IRQ resources\n");
468 ret = -EINVAL;
469 goto err0;
470 }
471
472 /* ioremap IOMEM and setup read/write callbacks */
473 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
474 i = &p->iomem[k];
475
476 /* handle optional registers */
477 if (!io[k])
478 continue;
479
480 switch (resource_size(io[k])) {
481 case 1:
482 i->width = 8;
483 i->read = intc_irqpin_read8;
484 i->write = intc_irqpin_write8;
485 break;
486 case 4:
487 i->width = 32;
488 i->read = intc_irqpin_read32;
489 i->write = intc_irqpin_write32;
490 break;
491 default:
492 dev_err(dev, "IOMEM size mismatch\n");
493 ret = -EINVAL;
494 goto err0;
495 }
496
497 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
498 resource_size(io[k]));
499 if (!i->iomem) {
500 dev_err(dev, "failed to remap IOMEM\n");
501 ret = -ENXIO;
502 goto err0;
503 }
504 }
505
506 /* configure "individual IRQ mode" where needed */
507 if (config && config->needs_irlm) {
508 if (io[INTC_IRQPIN_REG_IRLM])
509 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
510 config->irlm_bit, 1, 1);
511 else
512 dev_warn(dev, "unable to select IRLM mode\n");
513 }
514
515 /* mask all interrupts using priority */
516 for (k = 0; k < nirqs; k++)
517 intc_irqpin_mask_unmask_prio(p, k, 1);
518
519 /* clear all pending interrupts */
520 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
521
522 /* scan for shared interrupt lines */
523 ref_irq = p->irq[0].requested_irq;
524 p->shared_irqs = 1;
525 for (k = 1; k < nirqs; k++) {
526 if (ref_irq != p->irq[k].requested_irq) {
527 p->shared_irqs = 0;
528 break;
529 }
530 }
531
532 /* use more severe masking method if requested */
533 if (control_parent) {
534 enable_fn = intc_irqpin_irq_enable_force;
535 disable_fn = intc_irqpin_irq_disable_force;
536 } else if (!p->shared_irqs) {
537 enable_fn = intc_irqpin_irq_enable;
538 disable_fn = intc_irqpin_irq_disable;
539 } else {
540 enable_fn = intc_irqpin_shared_irq_enable;
541 disable_fn = intc_irqpin_shared_irq_disable;
542 }
543
544 irq_chip = &p->irq_chip;
545 irq_chip->name = name;
546 irq_chip->irq_mask = disable_fn;
547 irq_chip->irq_unmask = enable_fn;
548 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
549 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
550 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
551
552 p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
553 &intc_irqpin_irq_domain_ops, p);
554 if (!p->irq_domain) {
555 ret = -ENXIO;
556 dev_err(dev, "cannot initialize irq domain\n");
557 goto err0;
558 }
559
560 if (p->shared_irqs) {
561 /* request one shared interrupt */
562 if (devm_request_irq(dev, p->irq[0].requested_irq,
563 intc_irqpin_shared_irq_handler,
564 IRQF_SHARED, name, p)) {
565 dev_err(dev, "failed to request low IRQ\n");
566 ret = -ENOENT;
567 goto err1;
568 }
569 } else {
570 /* request interrupts one by one */
571 for (k = 0; k < nirqs; k++) {
572 if (devm_request_irq(dev, p->irq[k].requested_irq,
573 intc_irqpin_irq_handler, 0, name,
574 &p->irq[k])) {
575 dev_err(dev, "failed to request low IRQ\n");
576 ret = -ENOENT;
577 goto err1;
578 }
579 }
580 }
581
582 /* unmask all interrupts on prio level */
583 for (k = 0; k < nirqs; k++)
584 intc_irqpin_mask_unmask_prio(p, k, 0);
585
586 dev_info(dev, "driving %d irqs\n", nirqs);
587
588 return 0;
589
590err1:
591 irq_domain_remove(p->irq_domain);
592err0:
593 pm_runtime_put(dev);
594 pm_runtime_disable(dev);
595 return ret;
596}
597
598static int intc_irqpin_remove(struct platform_device *pdev)
599{
600 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
601
602 irq_domain_remove(p->irq_domain);
603 pm_runtime_put(&pdev->dev);
604 pm_runtime_disable(&pdev->dev);
605 return 0;
606}
607
608static struct platform_driver intc_irqpin_device_driver = {
609 .probe = intc_irqpin_probe,
610 .remove = intc_irqpin_remove,
611 .driver = {
612 .name = "renesas_intc_irqpin",
613 .of_match_table = intc_irqpin_dt_ids,
614 }
615};
616
617static int __init intc_irqpin_init(void)
618{
619 return platform_driver_register(&intc_irqpin_device_driver);
620}
621postcore_initcall(intc_irqpin_init);
622
623static void __exit intc_irqpin_exit(void)
624{
625 platform_driver_unregister(&intc_irqpin_device_driver);
626}
627module_exit(intc_irqpin_exit);
628
629MODULE_AUTHOR("Magnus Damm");
630MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
631MODULE_LICENSE("GPL v2");