Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 */
4
5#ifndef MSM_IOMMU_H
6#define MSM_IOMMU_H
7
8#include <linux/interrupt.h>
9#include <linux/iommu.h>
10#include <linux/clk.h>
11
12/* Sharability attributes of MSM IOMMU mappings */
13#define MSM_IOMMU_ATTR_NON_SH 0x0
14#define MSM_IOMMU_ATTR_SH 0x4
15
16/* Cacheability attributes of MSM IOMMU mappings */
17#define MSM_IOMMU_ATTR_NONCACHED 0x0
18#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
19#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
20#define MSM_IOMMU_ATTR_CACHED_WT 0x3
21
22/* Mask for the cache policy attribute */
23#define MSM_IOMMU_CP_MASK 0x03
24
25/* Maximum number of Machine IDs that we are allowing to be mapped to the same
26 * context bank. The number of MIDs mapped to the same CB does not affect
27 * performance, but there is a practical limit on how many distinct MIDs may
28 * be present. These mappings are typically determined at design time and are
29 * not expected to change at run time.
30 */
31#define MAX_NUM_MIDS 32
32
33/* Maximum number of context banks that can be present in IOMMU */
34#define IOMMU_MAX_CBS 128
35
36/**
37 * struct msm_iommu_dev - a single IOMMU hardware instance
38 * ncb Number of context banks present on this IOMMU HW instance
39 * dev: IOMMU device
40 * irq: Interrupt number
41 * clk: The bus clock for this IOMMU hardware instance
42 * pclk: The clock for the IOMMU bus interconnect
43 * dev_node: list head in qcom_iommu_device_list
44 * dom_node: list head for domain
45 * ctx_list: list of 'struct msm_iommu_ctx_dev'
46 * context_map: Bitmap to track allocated context banks
47 */
48struct msm_iommu_dev {
49 void __iomem *base;
50 int ncb;
51 struct device *dev;
52 int irq;
53 struct clk *clk;
54 struct clk *pclk;
55 struct list_head dev_node;
56 struct list_head dom_node;
57 struct list_head ctx_list;
58 DECLARE_BITMAP(context_map, IOMMU_MAX_CBS);
59
60 struct iommu_device iommu;
61};
62
63/**
64 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
65 * of_node node ptr of client device
66 * num Index of this context bank within the hardware
67 * mids List of Machine IDs that are to be mapped into this context
68 * bank, terminated by -1. The MID is a set of signals on the
69 * AXI bus that identifies the function associated with a specific
70 * memory request. (See ARM spec).
71 * num_mids Total number of mids
72 * node list head in ctx_list
73 */
74struct msm_iommu_ctx_dev {
75 struct device_node *of_node;
76 int num;
77 int mids[MAX_NUM_MIDS];
78 int num_mids;
79 struct list_head list;
80};
81
82/*
83 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
84 * interrupt is not supported in the API yet, but this will print an error
85 * message and dump useful IOMMU registers.
86 */
87irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
88
89#endif
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef MSM_IOMMU_H
19#define MSM_IOMMU_H
20
21#include <linux/interrupt.h>
22#include <linux/clk.h>
23
24/* Sharability attributes of MSM IOMMU mappings */
25#define MSM_IOMMU_ATTR_NON_SH 0x0
26#define MSM_IOMMU_ATTR_SH 0x4
27
28/* Cacheability attributes of MSM IOMMU mappings */
29#define MSM_IOMMU_ATTR_NONCACHED 0x0
30#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
31#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
32#define MSM_IOMMU_ATTR_CACHED_WT 0x3
33
34/* Mask for the cache policy attribute */
35#define MSM_IOMMU_CP_MASK 0x03
36
37/* Maximum number of Machine IDs that we are allowing to be mapped to the same
38 * context bank. The number of MIDs mapped to the same CB does not affect
39 * performance, but there is a practical limit on how many distinct MIDs may
40 * be present. These mappings are typically determined at design time and are
41 * not expected to change at run time.
42 */
43#define MAX_NUM_MIDS 32
44
45/**
46 * struct msm_iommu_dev - a single IOMMU hardware instance
47 * name Human-readable name given to this IOMMU HW instance
48 * ncb Number of context banks present on this IOMMU HW instance
49 */
50struct msm_iommu_dev {
51 const char *name;
52 int ncb;
53};
54
55/**
56 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
57 * name Human-readable name given to this context bank
58 * num Index of this context bank within the hardware
59 * mids List of Machine IDs that are to be mapped into this context
60 * bank, terminated by -1. The MID is a set of signals on the
61 * AXI bus that identifies the function associated with a specific
62 * memory request. (See ARM spec).
63 */
64struct msm_iommu_ctx_dev {
65 const char *name;
66 int num;
67 int mids[MAX_NUM_MIDS];
68};
69
70
71/**
72 * struct msm_iommu_drvdata - A single IOMMU hardware instance
73 * @base: IOMMU config port base address (VA)
74 * @ncb The number of contexts on this IOMMU
75 * @irq: Interrupt number
76 * @clk: The bus clock for this IOMMU hardware instance
77 * @pclk: The clock for the IOMMU bus interconnect
78 *
79 * A msm_iommu_drvdata holds the global driver data about a single piece
80 * of an IOMMU hardware instance.
81 */
82struct msm_iommu_drvdata {
83 void __iomem *base;
84 int irq;
85 int ncb;
86 struct clk *clk;
87 struct clk *pclk;
88};
89
90/**
91 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
92 * @num: Hardware context number of this context
93 * @pdev: Platform device associated wit this HW instance
94 * @attached_elm: List element for domains to track which devices are
95 * attached to them
96 *
97 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
98 * within each IOMMU hardware instance
99 */
100struct msm_iommu_ctx_drvdata {
101 int num;
102 struct platform_device *pdev;
103 struct list_head attached_elm;
104};
105
106/*
107 * Look up an IOMMU context device by its context name. NULL if none found.
108 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
109 * their platform devices.
110 */
111struct device *msm_iommu_get_ctx(const char *ctx_name);
112
113/*
114 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
115 * interrupt is not supported in the API yet, but this will print an error
116 * message and dump useful IOMMU registers.
117 */
118irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
119
120#endif