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1// SPDX-License-Identifier: GPL-2.0-only
2/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
3 *
4 * Author: Stepan Moskovchenko <stepanm@codeaurora.org>
5 */
6
7#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8#include <linux/kernel.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/errno.h>
12#include <linux/io.h>
13#include <linux/io-pgtable.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/spinlock.h>
17#include <linux/slab.h>
18#include <linux/iommu.h>
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/of_iommu.h>
22
23#include <asm/cacheflush.h>
24#include <linux/sizes.h>
25
26#include "msm_iommu_hw-8xxx.h"
27#include "msm_iommu.h"
28
29#define MRC(reg, processor, op1, crn, crm, op2) \
30__asm__ __volatile__ ( \
31" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
32: "=r" (reg))
33
34/* bitmap of the page sizes currently supported */
35#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
36
37static DEFINE_SPINLOCK(msm_iommu_lock);
38static LIST_HEAD(qcom_iommu_devices);
39static struct iommu_ops msm_iommu_ops;
40
41struct msm_priv {
42 struct list_head list_attached;
43 struct iommu_domain domain;
44 struct io_pgtable_cfg cfg;
45 struct io_pgtable_ops *iop;
46 struct device *dev;
47 spinlock_t pgtlock; /* pagetable lock */
48};
49
50static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
51{
52 return container_of(dom, struct msm_priv, domain);
53}
54
55static int __enable_clocks(struct msm_iommu_dev *iommu)
56{
57 int ret;
58
59 ret = clk_enable(iommu->pclk);
60 if (ret)
61 goto fail;
62
63 if (iommu->clk) {
64 ret = clk_enable(iommu->clk);
65 if (ret)
66 clk_disable(iommu->pclk);
67 }
68fail:
69 return ret;
70}
71
72static void __disable_clocks(struct msm_iommu_dev *iommu)
73{
74 if (iommu->clk)
75 clk_disable(iommu->clk);
76 clk_disable(iommu->pclk);
77}
78
79static void msm_iommu_reset(void __iomem *base, int ncb)
80{
81 int ctx;
82
83 SET_RPUE(base, 0);
84 SET_RPUEIE(base, 0);
85 SET_ESRRESTORE(base, 0);
86 SET_TBE(base, 0);
87 SET_CR(base, 0);
88 SET_SPDMBE(base, 0);
89 SET_TESTBUSCR(base, 0);
90 SET_TLBRSW(base, 0);
91 SET_GLOBAL_TLBIALL(base, 0);
92 SET_RPU_ACR(base, 0);
93 SET_TLBLKCRWE(base, 1);
94
95 for (ctx = 0; ctx < ncb; ctx++) {
96 SET_BPRCOSH(base, ctx, 0);
97 SET_BPRCISH(base, ctx, 0);
98 SET_BPRCNSH(base, ctx, 0);
99 SET_BPSHCFG(base, ctx, 0);
100 SET_BPMTCFG(base, ctx, 0);
101 SET_ACTLR(base, ctx, 0);
102 SET_SCTLR(base, ctx, 0);
103 SET_FSRRESTORE(base, ctx, 0);
104 SET_TTBR0(base, ctx, 0);
105 SET_TTBR1(base, ctx, 0);
106 SET_TTBCR(base, ctx, 0);
107 SET_BFBCR(base, ctx, 0);
108 SET_PAR(base, ctx, 0);
109 SET_FAR(base, ctx, 0);
110 SET_CTX_TLBIALL(base, ctx, 0);
111 SET_TLBFLPTER(base, ctx, 0);
112 SET_TLBSLPTER(base, ctx, 0);
113 SET_TLBLKCR(base, ctx, 0);
114 SET_CONTEXTIDR(base, ctx, 0);
115 }
116}
117
118static void __flush_iotlb(void *cookie)
119{
120 struct msm_priv *priv = cookie;
121 struct msm_iommu_dev *iommu = NULL;
122 struct msm_iommu_ctx_dev *master;
123 int ret = 0;
124
125 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
126 ret = __enable_clocks(iommu);
127 if (ret)
128 goto fail;
129
130 list_for_each_entry(master, &iommu->ctx_list, list)
131 SET_CTX_TLBIALL(iommu->base, master->num, 0);
132
133 __disable_clocks(iommu);
134 }
135fail:
136 return;
137}
138
139static void __flush_iotlb_range(unsigned long iova, size_t size,
140 size_t granule, bool leaf, void *cookie)
141{
142 struct msm_priv *priv = cookie;
143 struct msm_iommu_dev *iommu = NULL;
144 struct msm_iommu_ctx_dev *master;
145 int ret = 0;
146 int temp_size;
147
148 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
149 ret = __enable_clocks(iommu);
150 if (ret)
151 goto fail;
152
153 list_for_each_entry(master, &iommu->ctx_list, list) {
154 temp_size = size;
155 do {
156 iova &= TLBIVA_VA;
157 iova |= GET_CONTEXTIDR_ASID(iommu->base,
158 master->num);
159 SET_TLBIVA(iommu->base, master->num, iova);
160 iova += granule;
161 } while (temp_size -= granule);
162 }
163
164 __disable_clocks(iommu);
165 }
166
167fail:
168 return;
169}
170
171static void __flush_iotlb_walk(unsigned long iova, size_t size,
172 size_t granule, void *cookie)
173{
174 __flush_iotlb_range(iova, size, granule, false, cookie);
175}
176
177static void __flush_iotlb_leaf(unsigned long iova, size_t size,
178 size_t granule, void *cookie)
179{
180 __flush_iotlb_range(iova, size, granule, true, cookie);
181}
182
183static void __flush_iotlb_page(struct iommu_iotlb_gather *gather,
184 unsigned long iova, size_t granule, void *cookie)
185{
186 __flush_iotlb_range(iova, granule, granule, true, cookie);
187}
188
189static const struct iommu_flush_ops msm_iommu_flush_ops = {
190 .tlb_flush_all = __flush_iotlb,
191 .tlb_flush_walk = __flush_iotlb_walk,
192 .tlb_flush_leaf = __flush_iotlb_leaf,
193 .tlb_add_page = __flush_iotlb_page,
194};
195
196static int msm_iommu_alloc_ctx(unsigned long *map, int start, int end)
197{
198 int idx;
199
200 do {
201 idx = find_next_zero_bit(map, end, start);
202 if (idx == end)
203 return -ENOSPC;
204 } while (test_and_set_bit(idx, map));
205
206 return idx;
207}
208
209static void msm_iommu_free_ctx(unsigned long *map, int idx)
210{
211 clear_bit(idx, map);
212}
213
214static void config_mids(struct msm_iommu_dev *iommu,
215 struct msm_iommu_ctx_dev *master)
216{
217 int mid, ctx, i;
218
219 for (i = 0; i < master->num_mids; i++) {
220 mid = master->mids[i];
221 ctx = master->num;
222
223 SET_M2VCBR_N(iommu->base, mid, 0);
224 SET_CBACR_N(iommu->base, ctx, 0);
225
226 /* Set VMID = 0 */
227 SET_VMID(iommu->base, mid, 0);
228
229 /* Set the context number for that MID to this context */
230 SET_CBNDX(iommu->base, mid, ctx);
231
232 /* Set MID associated with this context bank to 0*/
233 SET_CBVMID(iommu->base, ctx, 0);
234
235 /* Set the ASID for TLB tagging for this context */
236 SET_CONTEXTIDR_ASID(iommu->base, ctx, ctx);
237
238 /* Set security bit override to be Non-secure */
239 SET_NSCFG(iommu->base, mid, 3);
240 }
241}
242
243static void __reset_context(void __iomem *base, int ctx)
244{
245 SET_BPRCOSH(base, ctx, 0);
246 SET_BPRCISH(base, ctx, 0);
247 SET_BPRCNSH(base, ctx, 0);
248 SET_BPSHCFG(base, ctx, 0);
249 SET_BPMTCFG(base, ctx, 0);
250 SET_ACTLR(base, ctx, 0);
251 SET_SCTLR(base, ctx, 0);
252 SET_FSRRESTORE(base, ctx, 0);
253 SET_TTBR0(base, ctx, 0);
254 SET_TTBR1(base, ctx, 0);
255 SET_TTBCR(base, ctx, 0);
256 SET_BFBCR(base, ctx, 0);
257 SET_PAR(base, ctx, 0);
258 SET_FAR(base, ctx, 0);
259 SET_CTX_TLBIALL(base, ctx, 0);
260 SET_TLBFLPTER(base, ctx, 0);
261 SET_TLBSLPTER(base, ctx, 0);
262 SET_TLBLKCR(base, ctx, 0);
263}
264
265static void __program_context(void __iomem *base, int ctx,
266 struct msm_priv *priv)
267{
268 __reset_context(base, ctx);
269
270 /* Turn on TEX Remap */
271 SET_TRE(base, ctx, 1);
272 SET_AFE(base, ctx, 1);
273
274 /* Set up HTW mode */
275 /* TLB miss configuration: perform HTW on miss */
276 SET_TLBMCFG(base, ctx, 0x3);
277
278 /* V2P configuration: HTW for access */
279 SET_V2PCFG(base, ctx, 0x3);
280
281 SET_TTBCR(base, ctx, priv->cfg.arm_v7s_cfg.tcr);
282 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr);
283 SET_TTBR1(base, ctx, 0);
284
285 /* Set prrr and nmrr */
286 SET_PRRR(base, ctx, priv->cfg.arm_v7s_cfg.prrr);
287 SET_NMRR(base, ctx, priv->cfg.arm_v7s_cfg.nmrr);
288
289 /* Invalidate the TLB for this context */
290 SET_CTX_TLBIALL(base, ctx, 0);
291
292 /* Set interrupt number to "secure" interrupt */
293 SET_IRPTNDX(base, ctx, 0);
294
295 /* Enable context fault interrupt */
296 SET_CFEIE(base, ctx, 1);
297
298 /* Stall access on a context fault and let the handler deal with it */
299 SET_CFCFG(base, ctx, 1);
300
301 /* Redirect all cacheable requests to L2 slave port. */
302 SET_RCISH(base, ctx, 1);
303 SET_RCOSH(base, ctx, 1);
304 SET_RCNSH(base, ctx, 1);
305
306 /* Turn on BFB prefetch */
307 SET_BFBDFE(base, ctx, 1);
308
309 /* Enable the MMU */
310 SET_M(base, ctx, 1);
311}
312
313static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
314{
315 struct msm_priv *priv;
316
317 if (type != IOMMU_DOMAIN_UNMANAGED)
318 return NULL;
319
320 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
321 if (!priv)
322 goto fail_nomem;
323
324 INIT_LIST_HEAD(&priv->list_attached);
325
326 priv->domain.geometry.aperture_start = 0;
327 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
328 priv->domain.geometry.force_aperture = true;
329
330 return &priv->domain;
331
332fail_nomem:
333 kfree(priv);
334 return NULL;
335}
336
337static void msm_iommu_domain_free(struct iommu_domain *domain)
338{
339 struct msm_priv *priv;
340 unsigned long flags;
341
342 spin_lock_irqsave(&msm_iommu_lock, flags);
343 priv = to_msm_priv(domain);
344 kfree(priv);
345 spin_unlock_irqrestore(&msm_iommu_lock, flags);
346}
347
348static int msm_iommu_domain_config(struct msm_priv *priv)
349{
350 spin_lock_init(&priv->pgtlock);
351
352 priv->cfg = (struct io_pgtable_cfg) {
353 .quirks = IO_PGTABLE_QUIRK_TLBI_ON_MAP,
354 .pgsize_bitmap = msm_iommu_ops.pgsize_bitmap,
355 .ias = 32,
356 .oas = 32,
357 .tlb = &msm_iommu_flush_ops,
358 .iommu_dev = priv->dev,
359 };
360
361 priv->iop = alloc_io_pgtable_ops(ARM_V7S, &priv->cfg, priv);
362 if (!priv->iop) {
363 dev_err(priv->dev, "Failed to allocate pgtable\n");
364 return -EINVAL;
365 }
366
367 msm_iommu_ops.pgsize_bitmap = priv->cfg.pgsize_bitmap;
368
369 return 0;
370}
371
372/* Must be called under msm_iommu_lock */
373static struct msm_iommu_dev *find_iommu_for_dev(struct device *dev)
374{
375 struct msm_iommu_dev *iommu, *ret = NULL;
376 struct msm_iommu_ctx_dev *master;
377
378 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
379 master = list_first_entry(&iommu->ctx_list,
380 struct msm_iommu_ctx_dev,
381 list);
382 if (master->of_node == dev->of_node) {
383 ret = iommu;
384 break;
385 }
386 }
387
388 return ret;
389}
390
391static struct iommu_device *msm_iommu_probe_device(struct device *dev)
392{
393 struct msm_iommu_dev *iommu;
394 unsigned long flags;
395
396 spin_lock_irqsave(&msm_iommu_lock, flags);
397 iommu = find_iommu_for_dev(dev);
398 spin_unlock_irqrestore(&msm_iommu_lock, flags);
399
400 if (!iommu)
401 return ERR_PTR(-ENODEV);
402
403 return &iommu->iommu;
404}
405
406static void msm_iommu_release_device(struct device *dev)
407{
408}
409
410static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
411{
412 int ret = 0;
413 unsigned long flags;
414 struct msm_iommu_dev *iommu;
415 struct msm_priv *priv = to_msm_priv(domain);
416 struct msm_iommu_ctx_dev *master;
417
418 priv->dev = dev;
419 msm_iommu_domain_config(priv);
420
421 spin_lock_irqsave(&msm_iommu_lock, flags);
422 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
423 master = list_first_entry(&iommu->ctx_list,
424 struct msm_iommu_ctx_dev,
425 list);
426 if (master->of_node == dev->of_node) {
427 ret = __enable_clocks(iommu);
428 if (ret)
429 goto fail;
430
431 list_for_each_entry(master, &iommu->ctx_list, list) {
432 if (master->num) {
433 dev_err(dev, "domain already attached");
434 ret = -EEXIST;
435 goto fail;
436 }
437 master->num =
438 msm_iommu_alloc_ctx(iommu->context_map,
439 0, iommu->ncb);
440 if (IS_ERR_VALUE(master->num)) {
441 ret = -ENODEV;
442 goto fail;
443 }
444 config_mids(iommu, master);
445 __program_context(iommu->base, master->num,
446 priv);
447 }
448 __disable_clocks(iommu);
449 list_add(&iommu->dom_node, &priv->list_attached);
450 }
451 }
452
453fail:
454 spin_unlock_irqrestore(&msm_iommu_lock, flags);
455
456 return ret;
457}
458
459static void msm_iommu_detach_dev(struct iommu_domain *domain,
460 struct device *dev)
461{
462 struct msm_priv *priv = to_msm_priv(domain);
463 unsigned long flags;
464 struct msm_iommu_dev *iommu;
465 struct msm_iommu_ctx_dev *master;
466 int ret;
467
468 free_io_pgtable_ops(priv->iop);
469
470 spin_lock_irqsave(&msm_iommu_lock, flags);
471 list_for_each_entry(iommu, &priv->list_attached, dom_node) {
472 ret = __enable_clocks(iommu);
473 if (ret)
474 goto fail;
475
476 list_for_each_entry(master, &iommu->ctx_list, list) {
477 msm_iommu_free_ctx(iommu->context_map, master->num);
478 __reset_context(iommu->base, master->num);
479 }
480 __disable_clocks(iommu);
481 }
482fail:
483 spin_unlock_irqrestore(&msm_iommu_lock, flags);
484}
485
486static int msm_iommu_map(struct iommu_domain *domain, unsigned long iova,
487 phys_addr_t pa, size_t len, int prot, gfp_t gfp)
488{
489 struct msm_priv *priv = to_msm_priv(domain);
490 unsigned long flags;
491 int ret;
492
493 spin_lock_irqsave(&priv->pgtlock, flags);
494 ret = priv->iop->map(priv->iop, iova, pa, len, prot, GFP_ATOMIC);
495 spin_unlock_irqrestore(&priv->pgtlock, flags);
496
497 return ret;
498}
499
500static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
501 size_t len, struct iommu_iotlb_gather *gather)
502{
503 struct msm_priv *priv = to_msm_priv(domain);
504 unsigned long flags;
505
506 spin_lock_irqsave(&priv->pgtlock, flags);
507 len = priv->iop->unmap(priv->iop, iova, len, gather);
508 spin_unlock_irqrestore(&priv->pgtlock, flags);
509
510 return len;
511}
512
513static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
514 dma_addr_t va)
515{
516 struct msm_priv *priv;
517 struct msm_iommu_dev *iommu;
518 struct msm_iommu_ctx_dev *master;
519 unsigned int par;
520 unsigned long flags;
521 phys_addr_t ret = 0;
522
523 spin_lock_irqsave(&msm_iommu_lock, flags);
524
525 priv = to_msm_priv(domain);
526 iommu = list_first_entry(&priv->list_attached,
527 struct msm_iommu_dev, dom_node);
528
529 if (list_empty(&iommu->ctx_list))
530 goto fail;
531
532 master = list_first_entry(&iommu->ctx_list,
533 struct msm_iommu_ctx_dev, list);
534 if (!master)
535 goto fail;
536
537 ret = __enable_clocks(iommu);
538 if (ret)
539 goto fail;
540
541 /* Invalidate context TLB */
542 SET_CTX_TLBIALL(iommu->base, master->num, 0);
543 SET_V2PPR(iommu->base, master->num, va & V2Pxx_VA);
544
545 par = GET_PAR(iommu->base, master->num);
546
547 /* We are dealing with a supersection */
548 if (GET_NOFAULT_SS(iommu->base, master->num))
549 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
550 else /* Upper 20 bits from PAR, lower 12 from VA */
551 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
552
553 if (GET_FAULT(iommu->base, master->num))
554 ret = 0;
555
556 __disable_clocks(iommu);
557fail:
558 spin_unlock_irqrestore(&msm_iommu_lock, flags);
559 return ret;
560}
561
562static bool msm_iommu_capable(enum iommu_cap cap)
563{
564 return false;
565}
566
567static void print_ctx_regs(void __iomem *base, int ctx)
568{
569 unsigned int fsr = GET_FSR(base, ctx);
570 pr_err("FAR = %08x PAR = %08x\n",
571 GET_FAR(base, ctx), GET_PAR(base, ctx));
572 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
573 (fsr & 0x02) ? "TF " : "",
574 (fsr & 0x04) ? "AFF " : "",
575 (fsr & 0x08) ? "APF " : "",
576 (fsr & 0x10) ? "TLBMF " : "",
577 (fsr & 0x20) ? "HTWDEEF " : "",
578 (fsr & 0x40) ? "HTWSEEF " : "",
579 (fsr & 0x80) ? "MHF " : "",
580 (fsr & 0x10000) ? "SL " : "",
581 (fsr & 0x40000000) ? "SS " : "",
582 (fsr & 0x80000000) ? "MULTI " : "");
583
584 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
585 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
586 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
587 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
588 pr_err("SCTLR = %08x ACTLR = %08x\n",
589 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
590}
591
592static void insert_iommu_master(struct device *dev,
593 struct msm_iommu_dev **iommu,
594 struct of_phandle_args *spec)
595{
596 struct msm_iommu_ctx_dev *master = dev_iommu_priv_get(dev);
597 int sid;
598
599 if (list_empty(&(*iommu)->ctx_list)) {
600 master = kzalloc(sizeof(*master), GFP_ATOMIC);
601 master->of_node = dev->of_node;
602 list_add(&master->list, &(*iommu)->ctx_list);
603 dev_iommu_priv_set(dev, master);
604 }
605
606 for (sid = 0; sid < master->num_mids; sid++)
607 if (master->mids[sid] == spec->args[0]) {
608 dev_warn(dev, "Stream ID 0x%hx repeated; ignoring\n",
609 sid);
610 return;
611 }
612
613 master->mids[master->num_mids++] = spec->args[0];
614}
615
616static int qcom_iommu_of_xlate(struct device *dev,
617 struct of_phandle_args *spec)
618{
619 struct msm_iommu_dev *iommu;
620 unsigned long flags;
621 int ret = 0;
622
623 spin_lock_irqsave(&msm_iommu_lock, flags);
624 list_for_each_entry(iommu, &qcom_iommu_devices, dev_node)
625 if (iommu->dev->of_node == spec->np)
626 break;
627
628 if (!iommu || iommu->dev->of_node != spec->np) {
629 ret = -ENODEV;
630 goto fail;
631 }
632
633 insert_iommu_master(dev, &iommu, spec);
634fail:
635 spin_unlock_irqrestore(&msm_iommu_lock, flags);
636
637 return ret;
638}
639
640irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
641{
642 struct msm_iommu_dev *iommu = dev_id;
643 unsigned int fsr;
644 int i, ret;
645
646 spin_lock(&msm_iommu_lock);
647
648 if (!iommu) {
649 pr_err("Invalid device ID in context interrupt handler\n");
650 goto fail;
651 }
652
653 pr_err("Unexpected IOMMU page fault!\n");
654 pr_err("base = %08x\n", (unsigned int)iommu->base);
655
656 ret = __enable_clocks(iommu);
657 if (ret)
658 goto fail;
659
660 for (i = 0; i < iommu->ncb; i++) {
661 fsr = GET_FSR(iommu->base, i);
662 if (fsr) {
663 pr_err("Fault occurred in context %d.\n", i);
664 pr_err("Interesting registers:\n");
665 print_ctx_regs(iommu->base, i);
666 SET_FSR(iommu->base, i, 0x4000000F);
667 }
668 }
669 __disable_clocks(iommu);
670fail:
671 spin_unlock(&msm_iommu_lock);
672 return 0;
673}
674
675static struct iommu_ops msm_iommu_ops = {
676 .capable = msm_iommu_capable,
677 .domain_alloc = msm_iommu_domain_alloc,
678 .domain_free = msm_iommu_domain_free,
679 .attach_dev = msm_iommu_attach_dev,
680 .detach_dev = msm_iommu_detach_dev,
681 .map = msm_iommu_map,
682 .unmap = msm_iommu_unmap,
683 /*
684 * Nothing is needed here, the barrier to guarantee
685 * completion of the tlb sync operation is implicitly
686 * taken care when the iommu client does a writel before
687 * kick starting the other master.
688 */
689 .iotlb_sync = NULL,
690 .iova_to_phys = msm_iommu_iova_to_phys,
691 .probe_device = msm_iommu_probe_device,
692 .release_device = msm_iommu_release_device,
693 .device_group = generic_device_group,
694 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
695 .of_xlate = qcom_iommu_of_xlate,
696};
697
698static int msm_iommu_probe(struct platform_device *pdev)
699{
700 struct resource *r;
701 resource_size_t ioaddr;
702 struct msm_iommu_dev *iommu;
703 int ret, par, val;
704
705 iommu = devm_kzalloc(&pdev->dev, sizeof(*iommu), GFP_KERNEL);
706 if (!iommu)
707 return -ENODEV;
708
709 iommu->dev = &pdev->dev;
710 INIT_LIST_HEAD(&iommu->ctx_list);
711
712 iommu->pclk = devm_clk_get(iommu->dev, "smmu_pclk");
713 if (IS_ERR(iommu->pclk)) {
714 dev_err(iommu->dev, "could not get smmu_pclk\n");
715 return PTR_ERR(iommu->pclk);
716 }
717
718 ret = clk_prepare(iommu->pclk);
719 if (ret) {
720 dev_err(iommu->dev, "could not prepare smmu_pclk\n");
721 return ret;
722 }
723
724 iommu->clk = devm_clk_get(iommu->dev, "iommu_clk");
725 if (IS_ERR(iommu->clk)) {
726 dev_err(iommu->dev, "could not get iommu_clk\n");
727 clk_unprepare(iommu->pclk);
728 return PTR_ERR(iommu->clk);
729 }
730
731 ret = clk_prepare(iommu->clk);
732 if (ret) {
733 dev_err(iommu->dev, "could not prepare iommu_clk\n");
734 clk_unprepare(iommu->pclk);
735 return ret;
736 }
737
738 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
739 iommu->base = devm_ioremap_resource(iommu->dev, r);
740 if (IS_ERR(iommu->base)) {
741 dev_err(iommu->dev, "could not get iommu base\n");
742 ret = PTR_ERR(iommu->base);
743 goto fail;
744 }
745 ioaddr = r->start;
746
747 iommu->irq = platform_get_irq(pdev, 0);
748 if (iommu->irq < 0) {
749 ret = -ENODEV;
750 goto fail;
751 }
752
753 ret = of_property_read_u32(iommu->dev->of_node, "qcom,ncb", &val);
754 if (ret) {
755 dev_err(iommu->dev, "could not get ncb\n");
756 goto fail;
757 }
758 iommu->ncb = val;
759
760 msm_iommu_reset(iommu->base, iommu->ncb);
761 SET_M(iommu->base, 0, 1);
762 SET_PAR(iommu->base, 0, 0);
763 SET_V2PCFG(iommu->base, 0, 1);
764 SET_V2PPR(iommu->base, 0, 0);
765 par = GET_PAR(iommu->base, 0);
766 SET_V2PCFG(iommu->base, 0, 0);
767 SET_M(iommu->base, 0, 0);
768
769 if (!par) {
770 pr_err("Invalid PAR value detected\n");
771 ret = -ENODEV;
772 goto fail;
773 }
774
775 ret = devm_request_threaded_irq(iommu->dev, iommu->irq, NULL,
776 msm_iommu_fault_handler,
777 IRQF_ONESHOT | IRQF_SHARED,
778 "msm_iommu_secure_irpt_handler",
779 iommu);
780 if (ret) {
781 pr_err("Request IRQ %d failed with ret=%d\n", iommu->irq, ret);
782 goto fail;
783 }
784
785 list_add(&iommu->dev_node, &qcom_iommu_devices);
786
787 ret = iommu_device_sysfs_add(&iommu->iommu, iommu->dev, NULL,
788 "msm-smmu.%pa", &ioaddr);
789 if (ret) {
790 pr_err("Could not add msm-smmu at %pa to sysfs\n", &ioaddr);
791 goto fail;
792 }
793
794 iommu_device_set_ops(&iommu->iommu, &msm_iommu_ops);
795 iommu_device_set_fwnode(&iommu->iommu, &pdev->dev.of_node->fwnode);
796
797 ret = iommu_device_register(&iommu->iommu);
798 if (ret) {
799 pr_err("Could not register msm-smmu at %pa\n", &ioaddr);
800 goto fail;
801 }
802
803 bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
804
805 pr_info("device mapped at %p, irq %d with %d ctx banks\n",
806 iommu->base, iommu->irq, iommu->ncb);
807
808 return ret;
809fail:
810 clk_unprepare(iommu->clk);
811 clk_unprepare(iommu->pclk);
812 return ret;
813}
814
815static const struct of_device_id msm_iommu_dt_match[] = {
816 { .compatible = "qcom,apq8064-iommu" },
817 {}
818};
819
820static int msm_iommu_remove(struct platform_device *pdev)
821{
822 struct msm_iommu_dev *iommu = platform_get_drvdata(pdev);
823
824 clk_unprepare(iommu->clk);
825 clk_unprepare(iommu->pclk);
826 return 0;
827}
828
829static struct platform_driver msm_iommu_driver = {
830 .driver = {
831 .name = "msm_iommu",
832 .of_match_table = msm_iommu_dt_match,
833 },
834 .probe = msm_iommu_probe,
835 .remove = msm_iommu_remove,
836};
837
838static int __init msm_iommu_driver_init(void)
839{
840 int ret;
841
842 ret = platform_driver_register(&msm_iommu_driver);
843 if (ret != 0)
844 pr_err("Failed to register IOMMU driver\n");
845
846 return ret;
847}
848subsys_initcall(msm_iommu_driver_init);
849
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/platform_device.h>
22#include <linux/errno.h>
23#include <linux/io.h>
24#include <linux/interrupt.h>
25#include <linux/list.h>
26#include <linux/spinlock.h>
27#include <linux/slab.h>
28#include <linux/iommu.h>
29#include <linux/clk.h>
30
31#include <asm/cacheflush.h>
32#include <asm/sizes.h>
33
34#include "msm_iommu_hw-8xxx.h"
35#include "msm_iommu.h"
36
37#define MRC(reg, processor, op1, crn, crm, op2) \
38__asm__ __volatile__ ( \
39" mrc " #processor "," #op1 ", %0," #crn "," #crm "," #op2 "\n" \
40: "=r" (reg))
41
42#define RCP15_PRRR(reg) MRC(reg, p15, 0, c10, c2, 0)
43#define RCP15_NMRR(reg) MRC(reg, p15, 0, c10, c2, 1)
44
45/* bitmap of the page sizes currently supported */
46#define MSM_IOMMU_PGSIZES (SZ_4K | SZ_64K | SZ_1M | SZ_16M)
47
48static int msm_iommu_tex_class[4];
49
50DEFINE_SPINLOCK(msm_iommu_lock);
51
52struct msm_priv {
53 unsigned long *pgtable;
54 struct list_head list_attached;
55 struct iommu_domain domain;
56};
57
58static struct msm_priv *to_msm_priv(struct iommu_domain *dom)
59{
60 return container_of(dom, struct msm_priv, domain);
61}
62
63static int __enable_clocks(struct msm_iommu_drvdata *drvdata)
64{
65 int ret;
66
67 ret = clk_enable(drvdata->pclk);
68 if (ret)
69 goto fail;
70
71 if (drvdata->clk) {
72 ret = clk_enable(drvdata->clk);
73 if (ret)
74 clk_disable(drvdata->pclk);
75 }
76fail:
77 return ret;
78}
79
80static void __disable_clocks(struct msm_iommu_drvdata *drvdata)
81{
82 clk_disable(drvdata->clk);
83 clk_disable(drvdata->pclk);
84}
85
86static int __flush_iotlb(struct iommu_domain *domain)
87{
88 struct msm_priv *priv = to_msm_priv(domain);
89 struct msm_iommu_drvdata *iommu_drvdata;
90 struct msm_iommu_ctx_drvdata *ctx_drvdata;
91 int ret = 0;
92#ifndef CONFIG_IOMMU_PGTABLES_L2
93 unsigned long *fl_table = priv->pgtable;
94 int i;
95
96 if (!list_empty(&priv->list_attached)) {
97 dmac_flush_range(fl_table, fl_table + SZ_16K);
98
99 for (i = 0; i < NUM_FL_PTE; i++)
100 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE) {
101 void *sl_table = __va(fl_table[i] &
102 FL_BASE_MASK);
103 dmac_flush_range(sl_table, sl_table + SZ_4K);
104 }
105 }
106#endif
107
108 list_for_each_entry(ctx_drvdata, &priv->list_attached, attached_elm) {
109
110 BUG_ON(!ctx_drvdata->pdev || !ctx_drvdata->pdev->dev.parent);
111
112 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
113 BUG_ON(!iommu_drvdata);
114
115 ret = __enable_clocks(iommu_drvdata);
116 if (ret)
117 goto fail;
118
119 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0);
120 __disable_clocks(iommu_drvdata);
121 }
122fail:
123 return ret;
124}
125
126static void __reset_context(void __iomem *base, int ctx)
127{
128 SET_BPRCOSH(base, ctx, 0);
129 SET_BPRCISH(base, ctx, 0);
130 SET_BPRCNSH(base, ctx, 0);
131 SET_BPSHCFG(base, ctx, 0);
132 SET_BPMTCFG(base, ctx, 0);
133 SET_ACTLR(base, ctx, 0);
134 SET_SCTLR(base, ctx, 0);
135 SET_FSRRESTORE(base, ctx, 0);
136 SET_TTBR0(base, ctx, 0);
137 SET_TTBR1(base, ctx, 0);
138 SET_TTBCR(base, ctx, 0);
139 SET_BFBCR(base, ctx, 0);
140 SET_PAR(base, ctx, 0);
141 SET_FAR(base, ctx, 0);
142 SET_CTX_TLBIALL(base, ctx, 0);
143 SET_TLBFLPTER(base, ctx, 0);
144 SET_TLBSLPTER(base, ctx, 0);
145 SET_TLBLKCR(base, ctx, 0);
146 SET_PRRR(base, ctx, 0);
147 SET_NMRR(base, ctx, 0);
148}
149
150static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
151{
152 unsigned int prrr, nmrr;
153 __reset_context(base, ctx);
154
155 /* Set up HTW mode */
156 /* TLB miss configuration: perform HTW on miss */
157 SET_TLBMCFG(base, ctx, 0x3);
158
159 /* V2P configuration: HTW for access */
160 SET_V2PCFG(base, ctx, 0x3);
161
162 SET_TTBCR(base, ctx, 0);
163 SET_TTBR0_PA(base, ctx, (pgtable >> 14));
164
165 /* Invalidate the TLB for this context */
166 SET_CTX_TLBIALL(base, ctx, 0);
167
168 /* Set interrupt number to "secure" interrupt */
169 SET_IRPTNDX(base, ctx, 0);
170
171 /* Enable context fault interrupt */
172 SET_CFEIE(base, ctx, 1);
173
174 /* Stall access on a context fault and let the handler deal with it */
175 SET_CFCFG(base, ctx, 1);
176
177 /* Redirect all cacheable requests to L2 slave port. */
178 SET_RCISH(base, ctx, 1);
179 SET_RCOSH(base, ctx, 1);
180 SET_RCNSH(base, ctx, 1);
181
182 /* Turn on TEX Remap */
183 SET_TRE(base, ctx, 1);
184
185 /* Set TEX remap attributes */
186 RCP15_PRRR(prrr);
187 RCP15_NMRR(nmrr);
188 SET_PRRR(base, ctx, prrr);
189 SET_NMRR(base, ctx, nmrr);
190
191 /* Turn on BFB prefetch */
192 SET_BFBDFE(base, ctx, 1);
193
194#ifdef CONFIG_IOMMU_PGTABLES_L2
195 /* Configure page tables as inner-cacheable and shareable to reduce
196 * the TLB miss penalty.
197 */
198 SET_TTBR0_SH(base, ctx, 1);
199 SET_TTBR1_SH(base, ctx, 1);
200
201 SET_TTBR0_NOS(base, ctx, 1);
202 SET_TTBR1_NOS(base, ctx, 1);
203
204 SET_TTBR0_IRGNH(base, ctx, 0); /* WB, WA */
205 SET_TTBR0_IRGNL(base, ctx, 1);
206
207 SET_TTBR1_IRGNH(base, ctx, 0); /* WB, WA */
208 SET_TTBR1_IRGNL(base, ctx, 1);
209
210 SET_TTBR0_ORGN(base, ctx, 1); /* WB, WA */
211 SET_TTBR1_ORGN(base, ctx, 1); /* WB, WA */
212#endif
213
214 /* Enable the MMU */
215 SET_M(base, ctx, 1);
216}
217
218static struct iommu_domain *msm_iommu_domain_alloc(unsigned type)
219{
220 struct msm_priv *priv;
221
222 if (type != IOMMU_DOMAIN_UNMANAGED)
223 return NULL;
224
225 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
226 if (!priv)
227 goto fail_nomem;
228
229 INIT_LIST_HEAD(&priv->list_attached);
230 priv->pgtable = (unsigned long *)__get_free_pages(GFP_KERNEL,
231 get_order(SZ_16K));
232
233 if (!priv->pgtable)
234 goto fail_nomem;
235
236 memset(priv->pgtable, 0, SZ_16K);
237
238 priv->domain.geometry.aperture_start = 0;
239 priv->domain.geometry.aperture_end = (1ULL << 32) - 1;
240 priv->domain.geometry.force_aperture = true;
241
242 return &priv->domain;
243
244fail_nomem:
245 kfree(priv);
246 return NULL;
247}
248
249static void msm_iommu_domain_free(struct iommu_domain *domain)
250{
251 struct msm_priv *priv;
252 unsigned long flags;
253 unsigned long *fl_table;
254 int i;
255
256 spin_lock_irqsave(&msm_iommu_lock, flags);
257 priv = to_msm_priv(domain);
258
259 fl_table = priv->pgtable;
260
261 for (i = 0; i < NUM_FL_PTE; i++)
262 if ((fl_table[i] & 0x03) == FL_TYPE_TABLE)
263 free_page((unsigned long) __va(((fl_table[i]) &
264 FL_BASE_MASK)));
265
266 free_pages((unsigned long)priv->pgtable, get_order(SZ_16K));
267 priv->pgtable = NULL;
268
269 kfree(priv);
270 spin_unlock_irqrestore(&msm_iommu_lock, flags);
271}
272
273static int msm_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
274{
275 struct msm_priv *priv;
276 struct msm_iommu_ctx_dev *ctx_dev;
277 struct msm_iommu_drvdata *iommu_drvdata;
278 struct msm_iommu_ctx_drvdata *ctx_drvdata;
279 struct msm_iommu_ctx_drvdata *tmp_drvdata;
280 int ret = 0;
281 unsigned long flags;
282
283 spin_lock_irqsave(&msm_iommu_lock, flags);
284
285 priv = to_msm_priv(domain);
286
287 if (!dev) {
288 ret = -EINVAL;
289 goto fail;
290 }
291
292 iommu_drvdata = dev_get_drvdata(dev->parent);
293 ctx_drvdata = dev_get_drvdata(dev);
294 ctx_dev = dev->platform_data;
295
296 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev) {
297 ret = -EINVAL;
298 goto fail;
299 }
300
301 if (!list_empty(&ctx_drvdata->attached_elm)) {
302 ret = -EBUSY;
303 goto fail;
304 }
305
306 list_for_each_entry(tmp_drvdata, &priv->list_attached, attached_elm)
307 if (tmp_drvdata == ctx_drvdata) {
308 ret = -EBUSY;
309 goto fail;
310 }
311
312 ret = __enable_clocks(iommu_drvdata);
313 if (ret)
314 goto fail;
315
316 __program_context(iommu_drvdata->base, ctx_dev->num,
317 __pa(priv->pgtable));
318
319 __disable_clocks(iommu_drvdata);
320 list_add(&(ctx_drvdata->attached_elm), &priv->list_attached);
321 ret = __flush_iotlb(domain);
322
323fail:
324 spin_unlock_irqrestore(&msm_iommu_lock, flags);
325 return ret;
326}
327
328static void msm_iommu_detach_dev(struct iommu_domain *domain,
329 struct device *dev)
330{
331 struct msm_priv *priv;
332 struct msm_iommu_ctx_dev *ctx_dev;
333 struct msm_iommu_drvdata *iommu_drvdata;
334 struct msm_iommu_ctx_drvdata *ctx_drvdata;
335 unsigned long flags;
336 int ret;
337
338 spin_lock_irqsave(&msm_iommu_lock, flags);
339 priv = to_msm_priv(domain);
340
341 if (!dev)
342 goto fail;
343
344 iommu_drvdata = dev_get_drvdata(dev->parent);
345 ctx_drvdata = dev_get_drvdata(dev);
346 ctx_dev = dev->platform_data;
347
348 if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
349 goto fail;
350
351 ret = __flush_iotlb(domain);
352 if (ret)
353 goto fail;
354
355 ret = __enable_clocks(iommu_drvdata);
356 if (ret)
357 goto fail;
358
359 __reset_context(iommu_drvdata->base, ctx_dev->num);
360 __disable_clocks(iommu_drvdata);
361 list_del_init(&ctx_drvdata->attached_elm);
362
363fail:
364 spin_unlock_irqrestore(&msm_iommu_lock, flags);
365}
366
367static int msm_iommu_map(struct iommu_domain *domain, unsigned long va,
368 phys_addr_t pa, size_t len, int prot)
369{
370 struct msm_priv *priv;
371 unsigned long flags;
372 unsigned long *fl_table;
373 unsigned long *fl_pte;
374 unsigned long fl_offset;
375 unsigned long *sl_table;
376 unsigned long *sl_pte;
377 unsigned long sl_offset;
378 unsigned int pgprot;
379 int ret = 0, tex, sh;
380
381 spin_lock_irqsave(&msm_iommu_lock, flags);
382
383 sh = (prot & MSM_IOMMU_ATTR_SH) ? 1 : 0;
384 tex = msm_iommu_tex_class[prot & MSM_IOMMU_CP_MASK];
385
386 if (tex < 0 || tex > NUM_TEX_CLASS - 1) {
387 ret = -EINVAL;
388 goto fail;
389 }
390
391 priv = to_msm_priv(domain);
392
393 fl_table = priv->pgtable;
394
395 if (len != SZ_16M && len != SZ_1M &&
396 len != SZ_64K && len != SZ_4K) {
397 pr_debug("Bad size: %d\n", len);
398 ret = -EINVAL;
399 goto fail;
400 }
401
402 if (!fl_table) {
403 pr_debug("Null page table\n");
404 ret = -EINVAL;
405 goto fail;
406 }
407
408 if (len == SZ_16M || len == SZ_1M) {
409 pgprot = sh ? FL_SHARED : 0;
410 pgprot |= tex & 0x01 ? FL_BUFFERABLE : 0;
411 pgprot |= tex & 0x02 ? FL_CACHEABLE : 0;
412 pgprot |= tex & 0x04 ? FL_TEX0 : 0;
413 } else {
414 pgprot = sh ? SL_SHARED : 0;
415 pgprot |= tex & 0x01 ? SL_BUFFERABLE : 0;
416 pgprot |= tex & 0x02 ? SL_CACHEABLE : 0;
417 pgprot |= tex & 0x04 ? SL_TEX0 : 0;
418 }
419
420 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
421 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
422
423 if (len == SZ_16M) {
424 int i = 0;
425 for (i = 0; i < 16; i++)
426 *(fl_pte+i) = (pa & 0xFF000000) | FL_SUPERSECTION |
427 FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
428 FL_SHARED | FL_NG | pgprot;
429 }
430
431 if (len == SZ_1M)
432 *fl_pte = (pa & 0xFFF00000) | FL_AP_READ | FL_AP_WRITE | FL_NG |
433 FL_TYPE_SECT | FL_SHARED | pgprot;
434
435 /* Need a 2nd level table */
436 if ((len == SZ_4K || len == SZ_64K) && (*fl_pte) == 0) {
437 unsigned long *sl;
438 sl = (unsigned long *) __get_free_pages(GFP_ATOMIC,
439 get_order(SZ_4K));
440
441 if (!sl) {
442 pr_debug("Could not allocate second level table\n");
443 ret = -ENOMEM;
444 goto fail;
445 }
446
447 memset(sl, 0, SZ_4K);
448 *fl_pte = ((((int)__pa(sl)) & FL_BASE_MASK) | FL_TYPE_TABLE);
449 }
450
451 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
452 sl_offset = SL_OFFSET(va);
453 sl_pte = sl_table + sl_offset;
454
455
456 if (len == SZ_4K)
457 *sl_pte = (pa & SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 | SL_NG |
458 SL_SHARED | SL_TYPE_SMALL | pgprot;
459
460 if (len == SZ_64K) {
461 int i;
462
463 for (i = 0; i < 16; i++)
464 *(sl_pte+i) = (pa & SL_BASE_MASK_LARGE) | SL_AP0 |
465 SL_NG | SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
466 }
467
468 ret = __flush_iotlb(domain);
469fail:
470 spin_unlock_irqrestore(&msm_iommu_lock, flags);
471 return ret;
472}
473
474static size_t msm_iommu_unmap(struct iommu_domain *domain, unsigned long va,
475 size_t len)
476{
477 struct msm_priv *priv;
478 unsigned long flags;
479 unsigned long *fl_table;
480 unsigned long *fl_pte;
481 unsigned long fl_offset;
482 unsigned long *sl_table;
483 unsigned long *sl_pte;
484 unsigned long sl_offset;
485 int i, ret = 0;
486
487 spin_lock_irqsave(&msm_iommu_lock, flags);
488
489 priv = to_msm_priv(domain);
490
491 fl_table = priv->pgtable;
492
493 if (len != SZ_16M && len != SZ_1M &&
494 len != SZ_64K && len != SZ_4K) {
495 pr_debug("Bad length: %d\n", len);
496 goto fail;
497 }
498
499 if (!fl_table) {
500 pr_debug("Null page table\n");
501 goto fail;
502 }
503
504 fl_offset = FL_OFFSET(va); /* Upper 12 bits */
505 fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
506
507 if (*fl_pte == 0) {
508 pr_debug("First level PTE is 0\n");
509 goto fail;
510 }
511
512 /* Unmap supersection */
513 if (len == SZ_16M)
514 for (i = 0; i < 16; i++)
515 *(fl_pte+i) = 0;
516
517 if (len == SZ_1M)
518 *fl_pte = 0;
519
520 sl_table = (unsigned long *) __va(((*fl_pte) & FL_BASE_MASK));
521 sl_offset = SL_OFFSET(va);
522 sl_pte = sl_table + sl_offset;
523
524 if (len == SZ_64K) {
525 for (i = 0; i < 16; i++)
526 *(sl_pte+i) = 0;
527 }
528
529 if (len == SZ_4K)
530 *sl_pte = 0;
531
532 if (len == SZ_4K || len == SZ_64K) {
533 int used = 0;
534
535 for (i = 0; i < NUM_SL_PTE; i++)
536 if (sl_table[i])
537 used = 1;
538 if (!used) {
539 free_page((unsigned long)sl_table);
540 *fl_pte = 0;
541 }
542 }
543
544 ret = __flush_iotlb(domain);
545
546fail:
547 spin_unlock_irqrestore(&msm_iommu_lock, flags);
548
549 /* the IOMMU API requires us to return how many bytes were unmapped */
550 len = ret ? 0 : len;
551 return len;
552}
553
554static phys_addr_t msm_iommu_iova_to_phys(struct iommu_domain *domain,
555 dma_addr_t va)
556{
557 struct msm_priv *priv;
558 struct msm_iommu_drvdata *iommu_drvdata;
559 struct msm_iommu_ctx_drvdata *ctx_drvdata;
560 unsigned int par;
561 unsigned long flags;
562 void __iomem *base;
563 phys_addr_t ret = 0;
564 int ctx;
565
566 spin_lock_irqsave(&msm_iommu_lock, flags);
567
568 priv = to_msm_priv(domain);
569 if (list_empty(&priv->list_attached))
570 goto fail;
571
572 ctx_drvdata = list_entry(priv->list_attached.next,
573 struct msm_iommu_ctx_drvdata, attached_elm);
574 iommu_drvdata = dev_get_drvdata(ctx_drvdata->pdev->dev.parent);
575
576 base = iommu_drvdata->base;
577 ctx = ctx_drvdata->num;
578
579 ret = __enable_clocks(iommu_drvdata);
580 if (ret)
581 goto fail;
582
583 /* Invalidate context TLB */
584 SET_CTX_TLBIALL(base, ctx, 0);
585 SET_V2PPR(base, ctx, va & V2Pxx_VA);
586
587 par = GET_PAR(base, ctx);
588
589 /* We are dealing with a supersection */
590 if (GET_NOFAULT_SS(base, ctx))
591 ret = (par & 0xFF000000) | (va & 0x00FFFFFF);
592 else /* Upper 20 bits from PAR, lower 12 from VA */
593 ret = (par & 0xFFFFF000) | (va & 0x00000FFF);
594
595 if (GET_FAULT(base, ctx))
596 ret = 0;
597
598 __disable_clocks(iommu_drvdata);
599fail:
600 spin_unlock_irqrestore(&msm_iommu_lock, flags);
601 return ret;
602}
603
604static bool msm_iommu_capable(enum iommu_cap cap)
605{
606 return false;
607}
608
609static void print_ctx_regs(void __iomem *base, int ctx)
610{
611 unsigned int fsr = GET_FSR(base, ctx);
612 pr_err("FAR = %08x PAR = %08x\n",
613 GET_FAR(base, ctx), GET_PAR(base, ctx));
614 pr_err("FSR = %08x [%s%s%s%s%s%s%s%s%s%s]\n", fsr,
615 (fsr & 0x02) ? "TF " : "",
616 (fsr & 0x04) ? "AFF " : "",
617 (fsr & 0x08) ? "APF " : "",
618 (fsr & 0x10) ? "TLBMF " : "",
619 (fsr & 0x20) ? "HTWDEEF " : "",
620 (fsr & 0x40) ? "HTWSEEF " : "",
621 (fsr & 0x80) ? "MHF " : "",
622 (fsr & 0x10000) ? "SL " : "",
623 (fsr & 0x40000000) ? "SS " : "",
624 (fsr & 0x80000000) ? "MULTI " : "");
625
626 pr_err("FSYNR0 = %08x FSYNR1 = %08x\n",
627 GET_FSYNR0(base, ctx), GET_FSYNR1(base, ctx));
628 pr_err("TTBR0 = %08x TTBR1 = %08x\n",
629 GET_TTBR0(base, ctx), GET_TTBR1(base, ctx));
630 pr_err("SCTLR = %08x ACTLR = %08x\n",
631 GET_SCTLR(base, ctx), GET_ACTLR(base, ctx));
632 pr_err("PRRR = %08x NMRR = %08x\n",
633 GET_PRRR(base, ctx), GET_NMRR(base, ctx));
634}
635
636irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
637{
638 struct msm_iommu_drvdata *drvdata = dev_id;
639 void __iomem *base;
640 unsigned int fsr;
641 int i, ret;
642
643 spin_lock(&msm_iommu_lock);
644
645 if (!drvdata) {
646 pr_err("Invalid device ID in context interrupt handler\n");
647 goto fail;
648 }
649
650 base = drvdata->base;
651
652 pr_err("Unexpected IOMMU page fault!\n");
653 pr_err("base = %08x\n", (unsigned int) base);
654
655 ret = __enable_clocks(drvdata);
656 if (ret)
657 goto fail;
658
659 for (i = 0; i < drvdata->ncb; i++) {
660 fsr = GET_FSR(base, i);
661 if (fsr) {
662 pr_err("Fault occurred in context %d.\n", i);
663 pr_err("Interesting registers:\n");
664 print_ctx_regs(base, i);
665 SET_FSR(base, i, 0x4000000F);
666 }
667 }
668 __disable_clocks(drvdata);
669fail:
670 spin_unlock(&msm_iommu_lock);
671 return 0;
672}
673
674static const struct iommu_ops msm_iommu_ops = {
675 .capable = msm_iommu_capable,
676 .domain_alloc = msm_iommu_domain_alloc,
677 .domain_free = msm_iommu_domain_free,
678 .attach_dev = msm_iommu_attach_dev,
679 .detach_dev = msm_iommu_detach_dev,
680 .map = msm_iommu_map,
681 .unmap = msm_iommu_unmap,
682 .map_sg = default_iommu_map_sg,
683 .iova_to_phys = msm_iommu_iova_to_phys,
684 .pgsize_bitmap = MSM_IOMMU_PGSIZES,
685};
686
687static int __init get_tex_class(int icp, int ocp, int mt, int nos)
688{
689 int i = 0;
690 unsigned int prrr = 0;
691 unsigned int nmrr = 0;
692 int c_icp, c_ocp, c_mt, c_nos;
693
694 RCP15_PRRR(prrr);
695 RCP15_NMRR(nmrr);
696
697 for (i = 0; i < NUM_TEX_CLASS; i++) {
698 c_nos = PRRR_NOS(prrr, i);
699 c_mt = PRRR_MT(prrr, i);
700 c_icp = NMRR_ICP(nmrr, i);
701 c_ocp = NMRR_OCP(nmrr, i);
702
703 if (icp == c_icp && ocp == c_ocp && c_mt == mt && c_nos == nos)
704 return i;
705 }
706
707 return -ENODEV;
708}
709
710static void __init setup_iommu_tex_classes(void)
711{
712 msm_iommu_tex_class[MSM_IOMMU_ATTR_NONCACHED] =
713 get_tex_class(CP_NONCACHED, CP_NONCACHED, MT_NORMAL, 1);
714
715 msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_WA] =
716 get_tex_class(CP_WB_WA, CP_WB_WA, MT_NORMAL, 1);
717
718 msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WB_NWA] =
719 get_tex_class(CP_WB_NWA, CP_WB_NWA, MT_NORMAL, 1);
720
721 msm_iommu_tex_class[MSM_IOMMU_ATTR_CACHED_WT] =
722 get_tex_class(CP_WT, CP_WT, MT_NORMAL, 1);
723}
724
725static int __init msm_iommu_init(void)
726{
727 setup_iommu_tex_classes();
728 bus_set_iommu(&platform_bus_type, &msm_iommu_ops);
729 return 0;
730}
731
732subsys_initcall(msm_iommu_init);
733
734MODULE_LICENSE("GPL v2");
735MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");